1 /*
2 * tiomap.c
3 *
4 * DSP-BIOS Bridge driver support functions for TI OMAP processors.
5 *
6 * Processor Manager Driver for TI OMAP3430 EVM.
7 *
8 * Copyright (C) 2005-2006 Texas Instruments, Inc.
9 *
10 * This package is free software; you can redistribute it and/or modify
11 * it under the terms of the GNU General Public License version 2 as
12 * published by the Free Software Foundation.
13 *
14 * THIS PACKAGE IS PROVIDED ``AS IS'' AND WITHOUT ANY EXPRESS OR
15 * IMPLIED WARRANTIES, INCLUDING, WITHOUT LIMITATION, THE IMPLIED
16 * WARRANTIES OF MERCHANTIBILITY AND FITNESS FOR A PARTICULAR PURPOSE.
17 */
18
19 #include <plat/dsp.h>
20
21 #include <linux/types.h>
22 /* ----------------------------------- Host OS */
23 #include <dspbridge/host_os.h>
24 #include <linux/mm.h>
25 #include <linux/mmzone.h>
26
27 /* ----------------------------------- DSP/BIOS Bridge */
28 #include <dspbridge/dbdefs.h>
29
30 /* ----------------------------------- Trace & Debug */
31 #include <dspbridge/dbc.h>
32
33 /* ----------------------------------- OS Adaptation Layer */
34 #include <dspbridge/drv.h>
35 #include <dspbridge/sync.h>
36
37 /* ------------------------------------ Hardware Abstraction Layer */
38 #include <hw_defs.h>
39 #include <hw_mmu.h>
40
41 /* ----------------------------------- Link Driver */
42 #include <dspbridge/dspdefs.h>
43 #include <dspbridge/dspchnl.h>
44 #include <dspbridge/dspdeh.h>
45 #include <dspbridge/dspio.h>
46 #include <dspbridge/dspmsg.h>
47 #include <dspbridge/pwr.h>
48 #include <dspbridge/io_sm.h>
49
50 /* ----------------------------------- Platform Manager */
51 #include <dspbridge/dev.h>
52 #include <dspbridge/dspapi.h>
53 #include <dspbridge/dmm.h>
54 #include <dspbridge/wdt.h>
55
56 /* ----------------------------------- Local */
57 #include "_tiomap.h"
58 #include "_tiomap_pwr.h"
59 #include "tiomap_io.h"
60
61 /* Offset in shared mem to write to in order to synchronize start with DSP */
62 #define SHMSYNCOFFSET 4 /* GPP byte offset */
63
64 #define BUFFERSIZE 1024
65
66 #define TIHELEN_ACKTIMEOUT 10000
67
68 #define MMU_SECTION_ADDR_MASK 0xFFF00000
69 #define MMU_SSECTION_ADDR_MASK 0xFF000000
70 #define MMU_LARGE_PAGE_MASK 0xFFFF0000
71 #define MMU_SMALL_PAGE_MASK 0xFFFFF000
72 #define OMAP3_IVA2_BOOTADDR_MASK 0xFFFFFC00
73 #define PAGES_II_LVL_TABLE 512
74 #define PHYS_TO_PAGE(phys) pfn_to_page((phys) >> PAGE_SHIFT)
75
76 /*
77 * This is a totally ugly layer violation, but needed until
78 * omap_ctrl_set_dsp_boot*() are provided.
79 */
80 #define OMAP3_IVA2_BOOTMOD_IDLE 1
81 #define OMAP2_CONTROL_GENERAL 0x270
82 #define OMAP343X_CONTROL_IVA2_BOOTADDR (OMAP2_CONTROL_GENERAL + 0x0190)
83 #define OMAP343X_CONTROL_IVA2_BOOTMOD (OMAP2_CONTROL_GENERAL + 0x0194)
84
85 #define OMAP343X_CTRL_REGADDR(reg) \
86 OMAP2_L4_IO_ADDRESS(OMAP343X_CTRL_BASE + (reg))
87
88
89 /* Forward Declarations: */
90 static int bridge_brd_monitor(struct bridge_dev_context *dev_ctxt);
91 static int bridge_brd_read(struct bridge_dev_context *dev_ctxt,
92 u8 *host_buff,
93 u32 dsp_addr, u32 ul_num_bytes,
94 u32 mem_type);
95 static int bridge_brd_start(struct bridge_dev_context *dev_ctxt,
96 u32 dsp_addr);
97 static int bridge_brd_status(struct bridge_dev_context *dev_ctxt,
98 int *board_state);
99 static int bridge_brd_stop(struct bridge_dev_context *dev_ctxt);
100 static int bridge_brd_write(struct bridge_dev_context *dev_ctxt,
101 u8 *host_buff,
102 u32 dsp_addr, u32 ul_num_bytes,
103 u32 mem_type);
104 static int bridge_brd_set_state(struct bridge_dev_context *dev_ctxt,
105 u32 brd_state);
106 static int bridge_brd_mem_copy(struct bridge_dev_context *dev_ctxt,
107 u32 dsp_dest_addr, u32 dsp_src_addr,
108 u32 ul_num_bytes, u32 mem_type);
109 static int bridge_brd_mem_write(struct bridge_dev_context *dev_ctxt,
110 u8 *host_buff, u32 dsp_addr,
111 u32 ul_num_bytes, u32 mem_type);
112 static int bridge_brd_mem_map(struct bridge_dev_context *dev_ctxt,
113 u32 ul_mpu_addr, u32 virt_addr,
114 u32 ul_num_bytes, u32 ul_map_attr,
115 struct page **mapped_pages);
116 static int bridge_brd_mem_un_map(struct bridge_dev_context *dev_ctxt,
117 u32 virt_addr, u32 ul_num_bytes);
118 static int bridge_dev_create(struct bridge_dev_context
119 **dev_cntxt,
120 struct dev_object *hdev_obj,
121 struct cfg_hostres *config_param);
122 static int bridge_dev_ctrl(struct bridge_dev_context *dev_context,
123 u32 dw_cmd, void *pargs);
124 static int bridge_dev_destroy(struct bridge_dev_context *dev_ctxt);
125 static u32 user_va2_pa(struct mm_struct *mm, u32 address);
126 static int pte_update(struct bridge_dev_context *dev_ctxt, u32 pa,
127 u32 va, u32 size,
128 struct hw_mmu_map_attrs_t *map_attrs);
129 static int pte_set(struct pg_table_attrs *pt, u32 pa, u32 va,
130 u32 size, struct hw_mmu_map_attrs_t *attrs);
131 static int mem_map_vmalloc(struct bridge_dev_context *dev_context,
132 u32 ul_mpu_addr, u32 virt_addr,
133 u32 ul_num_bytes,
134 struct hw_mmu_map_attrs_t *hw_attrs);
135
136 bool wait_for_start(struct bridge_dev_context *dev_context, u32 dw_sync_addr);
137
138 /* ----------------------------------- Globals */
139
140 /* Attributes of L2 page tables for DSP MMU */
141 struct page_info {
142 u32 num_entries; /* Number of valid PTEs in the L2 PT */
143 };
144
145 /* Attributes used to manage the DSP MMU page tables */
146 struct pg_table_attrs {
147 spinlock_t pg_lock; /* Critical section object handle */
148
149 u32 l1_base_pa; /* Physical address of the L1 PT */
150 u32 l1_base_va; /* Virtual address of the L1 PT */
151 u32 l1_size; /* Size of the L1 PT */
152 u32 l1_tbl_alloc_pa;
153 /* Physical address of Allocated mem for L1 table. May not be aligned */
154 u32 l1_tbl_alloc_va;
155 /* Virtual address of Allocated mem for L1 table. May not be aligned */
156 u32 l1_tbl_alloc_sz;
157 /* Size of consistent memory allocated for L1 table.
158 * May not be aligned */
159
160 u32 l2_base_pa; /* Physical address of the L2 PT */
161 u32 l2_base_va; /* Virtual address of the L2 PT */
162 u32 l2_size; /* Size of the L2 PT */
163 u32 l2_tbl_alloc_pa;
164 /* Physical address of Allocated mem for L2 table. May not be aligned */
165 u32 l2_tbl_alloc_va;
166 /* Virtual address of Allocated mem for L2 table. May not be aligned */
167 u32 l2_tbl_alloc_sz;
168 /* Size of consistent memory allocated for L2 table.
169 * May not be aligned */
170
171 u32 l2_num_pages; /* Number of allocated L2 PT */
172 /* Array [l2_num_pages] of L2 PT info structs */
173 struct page_info *pg_info;
174 };
175
176 /*
177 * This Bridge driver's function interface table.
178 */
179 static struct bridge_drv_interface drv_interface_fxns = {
180 /* Bridge API ver. for which this bridge driver is built. */
181 BRD_API_MAJOR_VERSION,
182 BRD_API_MINOR_VERSION,
183 bridge_dev_create,
184 bridge_dev_destroy,
185 bridge_dev_ctrl,
186 bridge_brd_monitor,
187 bridge_brd_start,
188 bridge_brd_stop,
189 bridge_brd_status,
190 bridge_brd_read,
191 bridge_brd_write,
192 bridge_brd_set_state,
193 bridge_brd_mem_copy,
194 bridge_brd_mem_write,
195 bridge_brd_mem_map,
196 bridge_brd_mem_un_map,
197 /* The following CHNL functions are provided by chnl_io.lib: */
198 bridge_chnl_create,
199 bridge_chnl_destroy,
200 bridge_chnl_open,
201 bridge_chnl_close,
202 bridge_chnl_add_io_req,
203 bridge_chnl_get_ioc,
204 bridge_chnl_cancel_io,
205 bridge_chnl_flush_io,
206 bridge_chnl_get_info,
207 bridge_chnl_get_mgr_info,
208 bridge_chnl_idle,
209 bridge_chnl_register_notify,
210 /* The following IO functions are provided by chnl_io.lib: */
211 bridge_io_create,
212 bridge_io_destroy,
213 bridge_io_on_loaded,
214 bridge_io_get_proc_load,
215 /* The following msg_ctrl functions are provided by chnl_io.lib: */
216 bridge_msg_create,
217 bridge_msg_create_queue,
218 bridge_msg_delete,
219 bridge_msg_delete_queue,
220 bridge_msg_get,
221 bridge_msg_put,
222 bridge_msg_register_notify,
223 bridge_msg_set_queue_id,
224 };
225
226 static struct notifier_block dsp_mbox_notifier = {
227 .notifier_call = io_mbox_msg,
228 };
229
flush_all(struct bridge_dev_context * dev_context)230 static inline void flush_all(struct bridge_dev_context *dev_context)
231 {
232 if (dev_context->brd_state == BRD_DSP_HIBERNATION ||
233 dev_context->brd_state == BRD_HIBERNATION)
234 wake_dsp(dev_context, NULL);
235
236 hw_mmu_tlb_flush_all(dev_context->dsp_mmu_base);
237 }
238
bad_page_dump(u32 pa,struct page * pg)239 static void bad_page_dump(u32 pa, struct page *pg)
240 {
241 pr_emerg("DSPBRIDGE: MAP function: COUNT 0 FOR PA 0x%x\n", pa);
242 pr_emerg("Bad page state in process '%s'\n"
243 "page:%p flags:0x%0*lx mapping:%p mapcount:%d count:%d\n"
244 "Backtrace:\n",
245 current->comm, pg, (int)(2 * sizeof(unsigned long)),
246 (unsigned long)pg->flags, pg->mapping,
247 page_mapcount(pg), page_count(pg));
248 dump_stack();
249 }
250
251 /*
252 * ======== bridge_drv_entry ========
253 * purpose:
254 * Bridge Driver entry point.
255 */
bridge_drv_entry(struct bridge_drv_interface ** drv_intf,const char * driver_file_name)256 void bridge_drv_entry(struct bridge_drv_interface **drv_intf,
257 const char *driver_file_name)
258 {
259
260 DBC_REQUIRE(driver_file_name != NULL);
261
262 if (strcmp(driver_file_name, "UMA") == 0)
263 *drv_intf = &drv_interface_fxns;
264 else
265 dev_dbg(bridge, "%s Unknown Bridge file name", __func__);
266
267 }
268
269 /*
270 * ======== bridge_brd_monitor ========
271 * purpose:
272 * This bridge_brd_monitor puts DSP into a Loadable state.
273 * i.e Application can load and start the device.
274 *
275 * Preconditions:
276 * Device in 'OFF' state.
277 */
bridge_brd_monitor(struct bridge_dev_context * dev_ctxt)278 static int bridge_brd_monitor(struct bridge_dev_context *dev_ctxt)
279 {
280 struct bridge_dev_context *dev_context = dev_ctxt;
281 u32 temp;
282 struct omap_dsp_platform_data *pdata =
283 omap_dspbridge_dev->dev.platform_data;
284
285 temp = (*pdata->dsp_prm_read)(OMAP3430_IVA2_MOD, OMAP2_PM_PWSTST) &
286 OMAP_POWERSTATEST_MASK;
287 if (!(temp & 0x02)) {
288 /* IVA2 is not in ON state */
289 /* Read and set PM_PWSTCTRL_IVA2 to ON */
290 (*pdata->dsp_prm_rmw_bits)(OMAP_POWERSTATEST_MASK,
291 PWRDM_POWER_ON, OMAP3430_IVA2_MOD, OMAP2_PM_PWSTCTRL);
292 /* Set the SW supervised state transition */
293 (*pdata->dsp_cm_write)(OMAP34XX_CLKSTCTRL_FORCE_WAKEUP,
294 OMAP3430_IVA2_MOD, OMAP2_CM_CLKSTCTRL);
295
296 /* Wait until the state has moved to ON */
297 while ((*pdata->dsp_prm_read)(OMAP3430_IVA2_MOD, OMAP2_PM_PWSTST) &
298 OMAP_INTRANSITION_MASK)
299 ;
300 /* Disable Automatic transition */
301 (*pdata->dsp_cm_write)(OMAP34XX_CLKSTCTRL_DISABLE_AUTO,
302 OMAP3430_IVA2_MOD, OMAP2_CM_CLKSTCTRL);
303 }
304 (*pdata->dsp_prm_rmw_bits)(OMAP3430_RST2_IVA2_MASK, 0,
305 OMAP3430_IVA2_MOD, OMAP2_RM_RSTCTRL);
306 dsp_clk_enable(DSP_CLK_IVA2);
307
308 /* set the device state to IDLE */
309 dev_context->brd_state = BRD_IDLE;
310
311 return 0;
312 }
313
314 /*
315 * ======== bridge_brd_read ========
316 * purpose:
317 * Reads buffers for DSP memory.
318 */
bridge_brd_read(struct bridge_dev_context * dev_ctxt,u8 * host_buff,u32 dsp_addr,u32 ul_num_bytes,u32 mem_type)319 static int bridge_brd_read(struct bridge_dev_context *dev_ctxt,
320 u8 *host_buff, u32 dsp_addr,
321 u32 ul_num_bytes, u32 mem_type)
322 {
323 int status = 0;
324 struct bridge_dev_context *dev_context = dev_ctxt;
325 u32 offset;
326 u32 dsp_base_addr = dev_ctxt->dsp_base_addr;
327
328 if (dsp_addr < dev_context->dsp_start_add) {
329 status = -EPERM;
330 return status;
331 }
332 /* change here to account for the 3 bands of the DSP internal memory */
333 if ((dsp_addr - dev_context->dsp_start_add) <
334 dev_context->internal_size) {
335 offset = dsp_addr - dev_context->dsp_start_add;
336 } else {
337 status = read_ext_dsp_data(dev_context, host_buff, dsp_addr,
338 ul_num_bytes, mem_type);
339 return status;
340 }
341 /* copy the data from DSP memory, */
342 memcpy(host_buff, (void *)(dsp_base_addr + offset), ul_num_bytes);
343 return status;
344 }
345
346 /*
347 * ======== bridge_brd_set_state ========
348 * purpose:
349 * This routine updates the Board status.
350 */
bridge_brd_set_state(struct bridge_dev_context * dev_ctxt,u32 brd_state)351 static int bridge_brd_set_state(struct bridge_dev_context *dev_ctxt,
352 u32 brd_state)
353 {
354 int status = 0;
355 struct bridge_dev_context *dev_context = dev_ctxt;
356
357 dev_context->brd_state = brd_state;
358 return status;
359 }
360
361 /*
362 * ======== bridge_brd_start ========
363 * purpose:
364 * Initializes DSP MMU and Starts DSP.
365 *
366 * Preconditions:
367 * a) DSP domain is 'ACTIVE'.
368 * b) DSP_RST1 is asserted.
369 * b) DSP_RST2 is released.
370 */
bridge_brd_start(struct bridge_dev_context * dev_ctxt,u32 dsp_addr)371 static int bridge_brd_start(struct bridge_dev_context *dev_ctxt,
372 u32 dsp_addr)
373 {
374 int status = 0;
375 struct bridge_dev_context *dev_context = dev_ctxt;
376 u32 dw_sync_addr = 0;
377 u32 ul_shm_base; /* Gpp Phys SM base addr(byte) */
378 u32 ul_shm_base_virt; /* Dsp Virt SM base addr */
379 u32 ul_tlb_base_virt; /* Base of MMU TLB entry */
380 /* Offset of shm_base_virt from tlb_base_virt */
381 u32 ul_shm_offset_virt;
382 s32 entry_ndx;
383 s32 itmp_entry_ndx = 0; /* DSP-MMU TLB entry base address */
384 struct cfg_hostres *resources = NULL;
385 u32 temp;
386 u32 ul_dsp_clk_rate;
387 u32 ul_dsp_clk_addr;
388 u32 ul_bios_gp_timer;
389 u32 clk_cmd;
390 struct io_mgr *hio_mgr;
391 u32 ul_load_monitor_timer;
392 struct omap_dsp_platform_data *pdata =
393 omap_dspbridge_dev->dev.platform_data;
394
395 /* The device context contains all the mmu setup info from when the
396 * last dsp base image was loaded. The first entry is always
397 * SHMMEM base. */
398 /* Get SHM_BEG - convert to byte address */
399 (void)dev_get_symbol(dev_context->dev_obj, SHMBASENAME,
400 &ul_shm_base_virt);
401 ul_shm_base_virt *= DSPWORDSIZE;
402 DBC_ASSERT(ul_shm_base_virt != 0);
403 /* DSP Virtual address */
404 ul_tlb_base_virt = dev_context->atlb_entry[0].dsp_va;
405 DBC_ASSERT(ul_tlb_base_virt <= ul_shm_base_virt);
406 ul_shm_offset_virt =
407 ul_shm_base_virt - (ul_tlb_base_virt * DSPWORDSIZE);
408 /* Kernel logical address */
409 ul_shm_base = dev_context->atlb_entry[0].gpp_va + ul_shm_offset_virt;
410
411 DBC_ASSERT(ul_shm_base != 0);
412 /* 2nd wd is used as sync field */
413 dw_sync_addr = ul_shm_base + SHMSYNCOFFSET;
414 /* Write a signature into the shm base + offset; this will
415 * get cleared when the DSP program starts. */
416 if ((ul_shm_base_virt == 0) || (ul_shm_base == 0)) {
417 pr_err("%s: Illegal SM base\n", __func__);
418 status = -EPERM;
419 } else
420 __raw_writel(0xffffffff, dw_sync_addr);
421
422 if (!status) {
423 resources = dev_context->resources;
424 if (!resources)
425 status = -EPERM;
426
427 /* Assert RST1 i.e only the RST only for DSP megacell */
428 if (!status) {
429 (*pdata->dsp_prm_rmw_bits)(OMAP3430_RST1_IVA2_MASK,
430 OMAP3430_RST1_IVA2_MASK, OMAP3430_IVA2_MOD,
431 OMAP2_RM_RSTCTRL);
432 /* Mask address with 1K for compatibility */
433 __raw_writel(dsp_addr & OMAP3_IVA2_BOOTADDR_MASK,
434 OMAP343X_CTRL_REGADDR(
435 OMAP343X_CONTROL_IVA2_BOOTADDR));
436 /*
437 * Set bootmode to self loop if dsp_debug flag is true
438 */
439 __raw_writel((dsp_debug) ? OMAP3_IVA2_BOOTMOD_IDLE : 0,
440 OMAP343X_CTRL_REGADDR(
441 OMAP343X_CONTROL_IVA2_BOOTMOD));
442 }
443 }
444 if (!status) {
445 /* Reset and Unreset the RST2, so that BOOTADDR is copied to
446 * IVA2 SYSC register */
447 (*pdata->dsp_prm_rmw_bits)(OMAP3430_RST2_IVA2_MASK,
448 OMAP3430_RST2_IVA2_MASK, OMAP3430_IVA2_MOD, OMAP2_RM_RSTCTRL);
449 udelay(100);
450 (*pdata->dsp_prm_rmw_bits)(OMAP3430_RST2_IVA2_MASK, 0,
451 OMAP3430_IVA2_MOD, OMAP2_RM_RSTCTRL);
452 udelay(100);
453
454 /* Disbale the DSP MMU */
455 hw_mmu_disable(resources->dmmu_base);
456 /* Disable TWL */
457 hw_mmu_twl_disable(resources->dmmu_base);
458
459 /* Only make TLB entry if both addresses are non-zero */
460 for (entry_ndx = 0; entry_ndx < BRDIOCTL_NUMOFMMUTLB;
461 entry_ndx++) {
462 struct bridge_ioctl_extproc *e = &dev_context->atlb_entry[entry_ndx];
463 struct hw_mmu_map_attrs_t map_attrs = {
464 .endianism = e->endianism,
465 .element_size = e->elem_size,
466 .mixed_size = e->mixed_mode,
467 };
468
469 if (!e->gpp_pa || !e->dsp_va)
470 continue;
471
472 dev_dbg(bridge,
473 "MMU %d, pa: 0x%x, va: 0x%x, size: 0x%x",
474 itmp_entry_ndx,
475 e->gpp_pa,
476 e->dsp_va,
477 e->size);
478
479 hw_mmu_tlb_add(dev_context->dsp_mmu_base,
480 e->gpp_pa,
481 e->dsp_va,
482 e->size,
483 itmp_entry_ndx,
484 &map_attrs, 1, 1);
485
486 itmp_entry_ndx++;
487 }
488 }
489
490 /* Lock the above TLB entries and get the BIOS and load monitor timer
491 * information */
492 if (!status) {
493 hw_mmu_num_locked_set(resources->dmmu_base, itmp_entry_ndx);
494 hw_mmu_victim_num_set(resources->dmmu_base, itmp_entry_ndx);
495 hw_mmu_ttb_set(resources->dmmu_base,
496 dev_context->pt_attrs->l1_base_pa);
497 hw_mmu_twl_enable(resources->dmmu_base);
498 /* Enable the SmartIdle and AutoIdle bit for MMU_SYSCONFIG */
499
500 temp = __raw_readl((resources->dmmu_base) + 0x10);
501 temp = (temp & 0xFFFFFFEF) | 0x11;
502 __raw_writel(temp, (resources->dmmu_base) + 0x10);
503
504 /* Let the DSP MMU run */
505 hw_mmu_enable(resources->dmmu_base);
506
507 /* Enable the BIOS clock */
508 (void)dev_get_symbol(dev_context->dev_obj,
509 BRIDGEINIT_BIOSGPTIMER, &ul_bios_gp_timer);
510 (void)dev_get_symbol(dev_context->dev_obj,
511 BRIDGEINIT_LOADMON_GPTIMER,
512 &ul_load_monitor_timer);
513 }
514
515 if (!status) {
516 if (ul_load_monitor_timer != 0xFFFF) {
517 clk_cmd = (BPWR_ENABLE_CLOCK << MBX_PM_CLK_CMDSHIFT) |
518 ul_load_monitor_timer;
519 dsp_peripheral_clk_ctrl(dev_context, &clk_cmd);
520 } else {
521 dev_dbg(bridge, "Not able to get the symbol for Load "
522 "Monitor Timer\n");
523 }
524 }
525
526 if (!status) {
527 if (ul_bios_gp_timer != 0xFFFF) {
528 clk_cmd = (BPWR_ENABLE_CLOCK << MBX_PM_CLK_CMDSHIFT) |
529 ul_bios_gp_timer;
530 dsp_peripheral_clk_ctrl(dev_context, &clk_cmd);
531 } else {
532 dev_dbg(bridge,
533 "Not able to get the symbol for BIOS Timer\n");
534 }
535 }
536
537 if (!status) {
538 /* Set the DSP clock rate */
539 (void)dev_get_symbol(dev_context->dev_obj,
540 "_BRIDGEINIT_DSP_FREQ", &ul_dsp_clk_addr);
541 /*Set Autoidle Mode for IVA2 PLL */
542 (*pdata->dsp_cm_write)(1 << OMAP3430_AUTO_IVA2_DPLL_SHIFT,
543 OMAP3430_IVA2_MOD, OMAP3430_CM_AUTOIDLE_PLL);
544
545 if ((unsigned int *)ul_dsp_clk_addr != NULL) {
546 /* Get the clock rate */
547 ul_dsp_clk_rate = dsp_clk_get_iva2_rate();
548 dev_dbg(bridge, "%s: DSP clock rate (KHZ): 0x%x \n",
549 __func__, ul_dsp_clk_rate);
550 (void)bridge_brd_write(dev_context,
551 (u8 *) &ul_dsp_clk_rate,
552 ul_dsp_clk_addr, sizeof(u32), 0);
553 }
554 /*
555 * Enable Mailbox events and also drain any pending
556 * stale messages.
557 */
558 dev_context->mbox = omap_mbox_get("dsp", &dsp_mbox_notifier);
559 if (IS_ERR(dev_context->mbox)) {
560 dev_context->mbox = NULL;
561 pr_err("%s: Failed to get dsp mailbox handle\n",
562 __func__);
563 status = -EPERM;
564 }
565
566 }
567 if (!status) {
568 /*PM_IVA2GRPSEL_PER = 0xC0;*/
569 temp = readl(resources->per_pm_base + 0xA8);
570 temp = (temp & 0xFFFFFF30) | 0xC0;
571 writel(temp, resources->per_pm_base + 0xA8);
572
573 /*PM_MPUGRPSEL_PER &= 0xFFFFFF3F; */
574 temp = readl(resources->per_pm_base + 0xA4);
575 temp = (temp & 0xFFFFFF3F);
576 writel(temp, resources->per_pm_base + 0xA4);
577 /*CM_SLEEPDEP_PER |= 0x04; */
578 temp = readl(resources->per_base + 0x44);
579 temp = (temp & 0xFFFFFFFB) | 0x04;
580 writel(temp, resources->per_base + 0x44);
581
582 /*CM_CLKSTCTRL_IVA2 = 0x00000003 -To Allow automatic transitions */
583 (*pdata->dsp_cm_write)(OMAP34XX_CLKSTCTRL_ENABLE_AUTO,
584 OMAP3430_IVA2_MOD, OMAP2_CM_CLKSTCTRL);
585
586 /* Let DSP go */
587 dev_dbg(bridge, "%s Unreset\n", __func__);
588 /* Enable DSP MMU Interrupts */
589 hw_mmu_event_enable(resources->dmmu_base,
590 HW_MMU_ALL_INTERRUPTS);
591 /* release the RST1, DSP starts executing now .. */
592 (*pdata->dsp_prm_rmw_bits)(OMAP3430_RST1_IVA2_MASK, 0,
593 OMAP3430_IVA2_MOD, OMAP2_RM_RSTCTRL);
594
595 dev_dbg(bridge, "Waiting for Sync @ 0x%x\n", dw_sync_addr);
596 dev_dbg(bridge, "DSP c_int00 Address = 0x%x\n", dsp_addr);
597 if (dsp_debug)
598 while (__raw_readw(dw_sync_addr))
599 ;
600
601 /* Wait for DSP to clear word in shared memory */
602 /* Read the Location */
603 if (!wait_for_start(dev_context, dw_sync_addr))
604 status = -ETIMEDOUT;
605
606 /* Start wdt */
607 dsp_wdt_sm_set((void *)ul_shm_base);
608 dsp_wdt_enable(true);
609
610 status = dev_get_io_mgr(dev_context->dev_obj, &hio_mgr);
611 if (hio_mgr) {
612 io_sh_msetting(hio_mgr, SHM_OPPINFO, NULL);
613 /* Write the synchronization bit to indicate the
614 * completion of OPP table update to DSP
615 */
616 __raw_writel(0XCAFECAFE, dw_sync_addr);
617
618 /* update board state */
619 dev_context->brd_state = BRD_RUNNING;
620 /* (void)chnlsm_enable_interrupt(dev_context); */
621 } else {
622 dev_context->brd_state = BRD_UNKNOWN;
623 }
624 }
625 return status;
626 }
627
628 /*
629 * ======== bridge_brd_stop ========
630 * purpose:
631 * Puts DSP in self loop.
632 *
633 * Preconditions :
634 * a) None
635 */
bridge_brd_stop(struct bridge_dev_context * dev_ctxt)636 static int bridge_brd_stop(struct bridge_dev_context *dev_ctxt)
637 {
638 int status = 0;
639 struct bridge_dev_context *dev_context = dev_ctxt;
640 struct pg_table_attrs *pt_attrs;
641 u32 dsp_pwr_state;
642 struct omap_dsp_platform_data *pdata =
643 omap_dspbridge_dev->dev.platform_data;
644
645 if (dev_context->brd_state == BRD_STOPPED)
646 return status;
647
648 /* as per TRM, it is advised to first drive the IVA2 to 'Standby' mode,
649 * before turning off the clocks.. This is to ensure that there are no
650 * pending L3 or other transactons from IVA2 */
651 dsp_pwr_state = (*pdata->dsp_prm_read)(OMAP3430_IVA2_MOD, OMAP2_PM_PWSTST) &
652 OMAP_POWERSTATEST_MASK;
653 if (dsp_pwr_state != PWRDM_POWER_OFF) {
654 (*pdata->dsp_prm_rmw_bits)(OMAP3430_RST2_IVA2_MASK, 0,
655 OMAP3430_IVA2_MOD, OMAP2_RM_RSTCTRL);
656 sm_interrupt_dsp(dev_context, MBX_PM_DSPIDLE);
657 mdelay(10);
658
659 /* IVA2 is not in OFF state */
660 /* Set PM_PWSTCTRL_IVA2 to OFF */
661 (*pdata->dsp_prm_rmw_bits)(OMAP_POWERSTATEST_MASK,
662 PWRDM_POWER_OFF, OMAP3430_IVA2_MOD, OMAP2_PM_PWSTCTRL);
663 /* Set the SW supervised state transition for Sleep */
664 (*pdata->dsp_cm_write)(OMAP34XX_CLKSTCTRL_FORCE_SLEEP,
665 OMAP3430_IVA2_MOD, OMAP2_CM_CLKSTCTRL);
666 }
667 udelay(10);
668 /* Release the Ext Base virtual Address as the next DSP Program
669 * may have a different load address */
670 if (dev_context->dsp_ext_base_addr)
671 dev_context->dsp_ext_base_addr = 0;
672
673 dev_context->brd_state = BRD_STOPPED; /* update board state */
674
675 dsp_wdt_enable(false);
676
677 /* This is a good place to clear the MMU page tables as well */
678 if (dev_context->pt_attrs) {
679 pt_attrs = dev_context->pt_attrs;
680 memset((u8 *) pt_attrs->l1_base_va, 0x00, pt_attrs->l1_size);
681 memset((u8 *) pt_attrs->l2_base_va, 0x00, pt_attrs->l2_size);
682 memset((u8 *) pt_attrs->pg_info, 0x00,
683 (pt_attrs->l2_num_pages * sizeof(struct page_info)));
684 }
685 /* Disable the mailbox interrupts */
686 if (dev_context->mbox) {
687 omap_mbox_disable_irq(dev_context->mbox, IRQ_RX);
688 omap_mbox_put(dev_context->mbox, &dsp_mbox_notifier);
689 dev_context->mbox = NULL;
690 }
691 /* Reset IVA2 clocks*/
692 (*pdata->dsp_prm_write)(OMAP3430_RST1_IVA2_MASK | OMAP3430_RST2_IVA2_MASK |
693 OMAP3430_RST3_IVA2_MASK, OMAP3430_IVA2_MOD, OMAP2_RM_RSTCTRL);
694
695 dsp_clock_disable_all(dev_context->dsp_per_clks);
696 dsp_clk_disable(DSP_CLK_IVA2);
697
698 return status;
699 }
700
701 /*
702 * ======== bridge_brd_status ========
703 * Returns the board status.
704 */
bridge_brd_status(struct bridge_dev_context * dev_ctxt,int * board_state)705 static int bridge_brd_status(struct bridge_dev_context *dev_ctxt,
706 int *board_state)
707 {
708 struct bridge_dev_context *dev_context = dev_ctxt;
709 *board_state = dev_context->brd_state;
710 return 0;
711 }
712
713 /*
714 * ======== bridge_brd_write ========
715 * Copies the buffers to DSP internal or external memory.
716 */
bridge_brd_write(struct bridge_dev_context * dev_ctxt,u8 * host_buff,u32 dsp_addr,u32 ul_num_bytes,u32 mem_type)717 static int bridge_brd_write(struct bridge_dev_context *dev_ctxt,
718 u8 *host_buff, u32 dsp_addr,
719 u32 ul_num_bytes, u32 mem_type)
720 {
721 int status = 0;
722 struct bridge_dev_context *dev_context = dev_ctxt;
723
724 if (dsp_addr < dev_context->dsp_start_add) {
725 status = -EPERM;
726 return status;
727 }
728 if ((dsp_addr - dev_context->dsp_start_add) <
729 dev_context->internal_size) {
730 status = write_dsp_data(dev_ctxt, host_buff, dsp_addr,
731 ul_num_bytes, mem_type);
732 } else {
733 status = write_ext_dsp_data(dev_context, host_buff, dsp_addr,
734 ul_num_bytes, mem_type, false);
735 }
736
737 return status;
738 }
739
740 /*
741 * ======== bridge_dev_create ========
742 * Creates a driver object. Puts DSP in self loop.
743 */
bridge_dev_create(struct bridge_dev_context ** dev_cntxt,struct dev_object * hdev_obj,struct cfg_hostres * config_param)744 static int bridge_dev_create(struct bridge_dev_context
745 **dev_cntxt,
746 struct dev_object *hdev_obj,
747 struct cfg_hostres *config_param)
748 {
749 int status = 0;
750 struct bridge_dev_context *dev_context = NULL;
751 s32 entry_ndx;
752 struct cfg_hostres *resources = config_param;
753 struct pg_table_attrs *pt_attrs;
754 u32 pg_tbl_pa;
755 u32 pg_tbl_va;
756 u32 align_size;
757 struct drv_data *drv_datap = dev_get_drvdata(bridge);
758
759 /* Allocate and initialize a data structure to contain the bridge driver
760 * state, which becomes the context for later calls into this driver */
761 dev_context = kzalloc(sizeof(struct bridge_dev_context), GFP_KERNEL);
762 if (!dev_context) {
763 status = -ENOMEM;
764 goto func_end;
765 }
766
767 dev_context->dsp_start_add = (u32) OMAP_GEM_BASE;
768 dev_context->self_loop = (u32) NULL;
769 dev_context->dsp_per_clks = 0;
770 dev_context->internal_size = OMAP_DSP_SIZE;
771 /* Clear dev context MMU table entries.
772 * These get set on bridge_io_on_loaded() call after program loaded. */
773 for (entry_ndx = 0; entry_ndx < BRDIOCTL_NUMOFMMUTLB; entry_ndx++) {
774 dev_context->atlb_entry[entry_ndx].gpp_pa =
775 dev_context->atlb_entry[entry_ndx].dsp_va = 0;
776 }
777 dev_context->dsp_base_addr = (u32) MEM_LINEAR_ADDRESS((void *)
778 (config_param->
779 mem_base
780 [3]),
781 config_param->
782 mem_length
783 [3]);
784 if (!dev_context->dsp_base_addr)
785 status = -EPERM;
786
787 pt_attrs = kzalloc(sizeof(struct pg_table_attrs), GFP_KERNEL);
788 if (pt_attrs != NULL) {
789 pt_attrs->l1_size = SZ_16K; /* 4096 entries of 32 bits */
790 align_size = pt_attrs->l1_size;
791 /* Align sizes are expected to be power of 2 */
792 /* we like to get aligned on L1 table size */
793 pg_tbl_va = (u32) mem_alloc_phys_mem(pt_attrs->l1_size,
794 align_size, &pg_tbl_pa);
795
796 /* Check if the PA is aligned for us */
797 if ((pg_tbl_pa) & (align_size - 1)) {
798 /* PA not aligned to page table size ,
799 * try with more allocation and align */
800 mem_free_phys_mem((void *)pg_tbl_va, pg_tbl_pa,
801 pt_attrs->l1_size);
802 /* we like to get aligned on L1 table size */
803 pg_tbl_va =
804 (u32) mem_alloc_phys_mem((pt_attrs->l1_size) * 2,
805 align_size, &pg_tbl_pa);
806 /* We should be able to get aligned table now */
807 pt_attrs->l1_tbl_alloc_pa = pg_tbl_pa;
808 pt_attrs->l1_tbl_alloc_va = pg_tbl_va;
809 pt_attrs->l1_tbl_alloc_sz = pt_attrs->l1_size * 2;
810 /* Align the PA to the next 'align' boundary */
811 pt_attrs->l1_base_pa =
812 ((pg_tbl_pa) +
813 (align_size - 1)) & (~(align_size - 1));
814 pt_attrs->l1_base_va =
815 pg_tbl_va + (pt_attrs->l1_base_pa - pg_tbl_pa);
816 } else {
817 /* We got aligned PA, cool */
818 pt_attrs->l1_tbl_alloc_pa = pg_tbl_pa;
819 pt_attrs->l1_tbl_alloc_va = pg_tbl_va;
820 pt_attrs->l1_tbl_alloc_sz = pt_attrs->l1_size;
821 pt_attrs->l1_base_pa = pg_tbl_pa;
822 pt_attrs->l1_base_va = pg_tbl_va;
823 }
824 if (pt_attrs->l1_base_va)
825 memset((u8 *) pt_attrs->l1_base_va, 0x00,
826 pt_attrs->l1_size);
827
828 /* number of L2 page tables = DMM pool used + SHMMEM +EXTMEM +
829 * L4 pages */
830 pt_attrs->l2_num_pages = ((DMMPOOLSIZE >> 20) + 6);
831 pt_attrs->l2_size = HW_MMU_COARSE_PAGE_SIZE *
832 pt_attrs->l2_num_pages;
833 align_size = 4; /* Make it u32 aligned */
834 /* we like to get aligned on L1 table size */
835 pg_tbl_va = (u32) mem_alloc_phys_mem(pt_attrs->l2_size,
836 align_size, &pg_tbl_pa);
837 pt_attrs->l2_tbl_alloc_pa = pg_tbl_pa;
838 pt_attrs->l2_tbl_alloc_va = pg_tbl_va;
839 pt_attrs->l2_tbl_alloc_sz = pt_attrs->l2_size;
840 pt_attrs->l2_base_pa = pg_tbl_pa;
841 pt_attrs->l2_base_va = pg_tbl_va;
842
843 if (pt_attrs->l2_base_va)
844 memset((u8 *) pt_attrs->l2_base_va, 0x00,
845 pt_attrs->l2_size);
846
847 pt_attrs->pg_info = kzalloc(pt_attrs->l2_num_pages *
848 sizeof(struct page_info), GFP_KERNEL);
849 dev_dbg(bridge,
850 "L1 pa %x, va %x, size %x\n L2 pa %x, va "
851 "%x, size %x\n", pt_attrs->l1_base_pa,
852 pt_attrs->l1_base_va, pt_attrs->l1_size,
853 pt_attrs->l2_base_pa, pt_attrs->l2_base_va,
854 pt_attrs->l2_size);
855 dev_dbg(bridge, "pt_attrs %p L2 NumPages %x pg_info %p\n",
856 pt_attrs, pt_attrs->l2_num_pages, pt_attrs->pg_info);
857 }
858 if ((pt_attrs != NULL) && (pt_attrs->l1_base_va != 0) &&
859 (pt_attrs->l2_base_va != 0) && (pt_attrs->pg_info != NULL))
860 dev_context->pt_attrs = pt_attrs;
861 else
862 status = -ENOMEM;
863
864 if (!status) {
865 spin_lock_init(&pt_attrs->pg_lock);
866 dev_context->tc_word_swap_on = drv_datap->tc_wordswapon;
867
868 /* Set the Clock Divisor for the DSP module */
869 udelay(5);
870 /* MMU address is obtained from the host
871 * resources struct */
872 dev_context->dsp_mmu_base = resources->dmmu_base;
873 }
874 if (!status) {
875 dev_context->dev_obj = hdev_obj;
876 /* Store current board state. */
877 dev_context->brd_state = BRD_UNKNOWN;
878 dev_context->resources = resources;
879 dsp_clk_enable(DSP_CLK_IVA2);
880 bridge_brd_stop(dev_context);
881 /* Return ptr to our device state to the DSP API for storage */
882 *dev_cntxt = dev_context;
883 } else {
884 if (pt_attrs != NULL) {
885 kfree(pt_attrs->pg_info);
886
887 if (pt_attrs->l2_tbl_alloc_va) {
888 mem_free_phys_mem((void *)
889 pt_attrs->l2_tbl_alloc_va,
890 pt_attrs->l2_tbl_alloc_pa,
891 pt_attrs->l2_tbl_alloc_sz);
892 }
893 if (pt_attrs->l1_tbl_alloc_va) {
894 mem_free_phys_mem((void *)
895 pt_attrs->l1_tbl_alloc_va,
896 pt_attrs->l1_tbl_alloc_pa,
897 pt_attrs->l1_tbl_alloc_sz);
898 }
899 }
900 kfree(pt_attrs);
901 kfree(dev_context);
902 }
903 func_end:
904 return status;
905 }
906
907 /*
908 * ======== bridge_dev_ctrl ========
909 * Receives device specific commands.
910 */
bridge_dev_ctrl(struct bridge_dev_context * dev_context,u32 dw_cmd,void * pargs)911 static int bridge_dev_ctrl(struct bridge_dev_context *dev_context,
912 u32 dw_cmd, void *pargs)
913 {
914 int status = 0;
915 struct bridge_ioctl_extproc *pa_ext_proc =
916 (struct bridge_ioctl_extproc *)pargs;
917 s32 ndx;
918
919 switch (dw_cmd) {
920 case BRDIOCTL_CHNLREAD:
921 break;
922 case BRDIOCTL_CHNLWRITE:
923 break;
924 case BRDIOCTL_SETMMUCONFIG:
925 /* store away dsp-mmu setup values for later use */
926 for (ndx = 0; ndx < BRDIOCTL_NUMOFMMUTLB; ndx++, pa_ext_proc++)
927 dev_context->atlb_entry[ndx] = *pa_ext_proc;
928 break;
929 case BRDIOCTL_DEEPSLEEP:
930 case BRDIOCTL_EMERGENCYSLEEP:
931 /* Currently only DSP Idle is supported Need to update for
932 * later releases */
933 status = sleep_dsp(dev_context, PWR_DEEPSLEEP, pargs);
934 break;
935 case BRDIOCTL_WAKEUP:
936 status = wake_dsp(dev_context, pargs);
937 break;
938 case BRDIOCTL_CLK_CTRL:
939 status = 0;
940 /* Looking For Baseport Fix for Clocks */
941 status = dsp_peripheral_clk_ctrl(dev_context, pargs);
942 break;
943 case BRDIOCTL_PWR_HIBERNATE:
944 status = handle_hibernation_from_dsp(dev_context);
945 break;
946 case BRDIOCTL_PRESCALE_NOTIFY:
947 status = pre_scale_dsp(dev_context, pargs);
948 break;
949 case BRDIOCTL_POSTSCALE_NOTIFY:
950 status = post_scale_dsp(dev_context, pargs);
951 break;
952 case BRDIOCTL_CONSTRAINT_REQUEST:
953 status = handle_constraints_set(dev_context, pargs);
954 break;
955 default:
956 status = -EPERM;
957 break;
958 }
959 return status;
960 }
961
962 /*
963 * ======== bridge_dev_destroy ========
964 * Destroys the driver object.
965 */
bridge_dev_destroy(struct bridge_dev_context * dev_ctxt)966 static int bridge_dev_destroy(struct bridge_dev_context *dev_ctxt)
967 {
968 struct pg_table_attrs *pt_attrs;
969 int status = 0;
970 struct bridge_dev_context *dev_context = (struct bridge_dev_context *)
971 dev_ctxt;
972 struct cfg_hostres *host_res;
973 u32 shm_size;
974 struct drv_data *drv_datap = dev_get_drvdata(bridge);
975
976 /* It should never happen */
977 if (!dev_ctxt)
978 return -EFAULT;
979
980 /* first put the device to stop state */
981 bridge_brd_stop(dev_context);
982 if (dev_context->pt_attrs) {
983 pt_attrs = dev_context->pt_attrs;
984 kfree(pt_attrs->pg_info);
985
986 if (pt_attrs->l2_tbl_alloc_va) {
987 mem_free_phys_mem((void *)pt_attrs->l2_tbl_alloc_va,
988 pt_attrs->l2_tbl_alloc_pa,
989 pt_attrs->l2_tbl_alloc_sz);
990 }
991 if (pt_attrs->l1_tbl_alloc_va) {
992 mem_free_phys_mem((void *)pt_attrs->l1_tbl_alloc_va,
993 pt_attrs->l1_tbl_alloc_pa,
994 pt_attrs->l1_tbl_alloc_sz);
995 }
996 kfree(pt_attrs);
997
998 }
999
1000 if (dev_context->resources) {
1001 host_res = dev_context->resources;
1002 shm_size = drv_datap->shm_size;
1003 if (shm_size >= 0x10000) {
1004 if ((host_res->mem_base[1]) &&
1005 (host_res->mem_phys[1])) {
1006 mem_free_phys_mem((void *)
1007 host_res->mem_base
1008 [1],
1009 host_res->mem_phys
1010 [1], shm_size);
1011 }
1012 } else {
1013 dev_dbg(bridge, "%s: Error getting shm size "
1014 "from registry: %x. Not calling "
1015 "mem_free_phys_mem\n", __func__,
1016 status);
1017 }
1018 host_res->mem_base[1] = 0;
1019 host_res->mem_phys[1] = 0;
1020
1021 if (host_res->mem_base[0])
1022 iounmap((void *)host_res->mem_base[0]);
1023 if (host_res->mem_base[2])
1024 iounmap((void *)host_res->mem_base[2]);
1025 if (host_res->mem_base[3])
1026 iounmap((void *)host_res->mem_base[3]);
1027 if (host_res->mem_base[4])
1028 iounmap((void *)host_res->mem_base[4]);
1029 if (host_res->dmmu_base)
1030 iounmap(host_res->dmmu_base);
1031 if (host_res->per_base)
1032 iounmap(host_res->per_base);
1033 if (host_res->per_pm_base)
1034 iounmap((void *)host_res->per_pm_base);
1035 if (host_res->core_pm_base)
1036 iounmap((void *)host_res->core_pm_base);
1037
1038 host_res->mem_base[0] = (u32) NULL;
1039 host_res->mem_base[2] = (u32) NULL;
1040 host_res->mem_base[3] = (u32) NULL;
1041 host_res->mem_base[4] = (u32) NULL;
1042 host_res->dmmu_base = NULL;
1043
1044 kfree(host_res);
1045 }
1046
1047 /* Free the driver's device context: */
1048 kfree(drv_datap->base_img);
1049 kfree((void *)dev_ctxt);
1050 return status;
1051 }
1052
bridge_brd_mem_copy(struct bridge_dev_context * dev_ctxt,u32 dsp_dest_addr,u32 dsp_src_addr,u32 ul_num_bytes,u32 mem_type)1053 static int bridge_brd_mem_copy(struct bridge_dev_context *dev_ctxt,
1054 u32 dsp_dest_addr, u32 dsp_src_addr,
1055 u32 ul_num_bytes, u32 mem_type)
1056 {
1057 int status = 0;
1058 u32 src_addr = dsp_src_addr;
1059 u32 dest_addr = dsp_dest_addr;
1060 u32 copy_bytes = 0;
1061 u32 total_bytes = ul_num_bytes;
1062 u8 host_buf[BUFFERSIZE];
1063 struct bridge_dev_context *dev_context = dev_ctxt;
1064 while (total_bytes > 0 && !status) {
1065 copy_bytes =
1066 total_bytes > BUFFERSIZE ? BUFFERSIZE : total_bytes;
1067 /* Read from External memory */
1068 status = read_ext_dsp_data(dev_ctxt, host_buf, src_addr,
1069 copy_bytes, mem_type);
1070 if (!status) {
1071 if (dest_addr < (dev_context->dsp_start_add +
1072 dev_context->internal_size)) {
1073 /* Write to Internal memory */
1074 status = write_dsp_data(dev_ctxt, host_buf,
1075 dest_addr, copy_bytes,
1076 mem_type);
1077 } else {
1078 /* Write to External memory */
1079 status =
1080 write_ext_dsp_data(dev_ctxt, host_buf,
1081 dest_addr, copy_bytes,
1082 mem_type, false);
1083 }
1084 }
1085 total_bytes -= copy_bytes;
1086 src_addr += copy_bytes;
1087 dest_addr += copy_bytes;
1088 }
1089 return status;
1090 }
1091
1092 /* Mem Write does not halt the DSP to write unlike bridge_brd_write */
bridge_brd_mem_write(struct bridge_dev_context * dev_ctxt,u8 * host_buff,u32 dsp_addr,u32 ul_num_bytes,u32 mem_type)1093 static int bridge_brd_mem_write(struct bridge_dev_context *dev_ctxt,
1094 u8 *host_buff, u32 dsp_addr,
1095 u32 ul_num_bytes, u32 mem_type)
1096 {
1097 int status = 0;
1098 struct bridge_dev_context *dev_context = dev_ctxt;
1099 u32 ul_remain_bytes = 0;
1100 u32 ul_bytes = 0;
1101 ul_remain_bytes = ul_num_bytes;
1102 while (ul_remain_bytes > 0 && !status) {
1103 ul_bytes =
1104 ul_remain_bytes > BUFFERSIZE ? BUFFERSIZE : ul_remain_bytes;
1105 if (dsp_addr < (dev_context->dsp_start_add +
1106 dev_context->internal_size)) {
1107 status =
1108 write_dsp_data(dev_ctxt, host_buff, dsp_addr,
1109 ul_bytes, mem_type);
1110 } else {
1111 status = write_ext_dsp_data(dev_ctxt, host_buff,
1112 dsp_addr, ul_bytes,
1113 mem_type, true);
1114 }
1115 ul_remain_bytes -= ul_bytes;
1116 dsp_addr += ul_bytes;
1117 host_buff = host_buff + ul_bytes;
1118 }
1119 return status;
1120 }
1121
1122 /*
1123 * ======== bridge_brd_mem_map ========
1124 * This function maps MPU buffer to the DSP address space. It performs
1125 * linear to physical address translation if required. It translates each
1126 * page since linear addresses can be physically non-contiguous
1127 * All address & size arguments are assumed to be page aligned (in proc.c)
1128 *
1129 * TODO: Disable MMU while updating the page tables (but that'll stall DSP)
1130 */
bridge_brd_mem_map(struct bridge_dev_context * dev_ctxt,u32 ul_mpu_addr,u32 virt_addr,u32 ul_num_bytes,u32 ul_map_attr,struct page ** mapped_pages)1131 static int bridge_brd_mem_map(struct bridge_dev_context *dev_ctxt,
1132 u32 ul_mpu_addr, u32 virt_addr,
1133 u32 ul_num_bytes, u32 ul_map_attr,
1134 struct page **mapped_pages)
1135 {
1136 u32 attrs;
1137 int status = 0;
1138 struct bridge_dev_context *dev_context = dev_ctxt;
1139 struct hw_mmu_map_attrs_t hw_attrs;
1140 struct vm_area_struct *vma;
1141 struct mm_struct *mm = current->mm;
1142 u32 write = 0;
1143 u32 num_usr_pgs = 0;
1144 struct page *mapped_page, *pg;
1145 s32 pg_num;
1146 u32 va = virt_addr;
1147 struct task_struct *curr_task = current;
1148 u32 pg_i = 0;
1149 u32 mpu_addr, pa;
1150
1151 dev_dbg(bridge,
1152 "%s hDevCtxt %p, pa %x, va %x, size %x, ul_map_attr %x\n",
1153 __func__, dev_ctxt, ul_mpu_addr, virt_addr, ul_num_bytes,
1154 ul_map_attr);
1155 if (ul_num_bytes == 0)
1156 return -EINVAL;
1157
1158 if (ul_map_attr & DSP_MAP_DIR_MASK) {
1159 attrs = ul_map_attr;
1160 } else {
1161 /* Assign default attributes */
1162 attrs = ul_map_attr | (DSP_MAPVIRTUALADDR | DSP_MAPELEMSIZE16);
1163 }
1164 /* Take mapping properties */
1165 if (attrs & DSP_MAPBIGENDIAN)
1166 hw_attrs.endianism = HW_BIG_ENDIAN;
1167 else
1168 hw_attrs.endianism = HW_LITTLE_ENDIAN;
1169
1170 hw_attrs.mixed_size = (enum hw_mmu_mixed_size_t)
1171 ((attrs & DSP_MAPMIXEDELEMSIZE) >> 2);
1172 /* Ignore element_size if mixed_size is enabled */
1173 if (hw_attrs.mixed_size == 0) {
1174 if (attrs & DSP_MAPELEMSIZE8) {
1175 /* Size is 8 bit */
1176 hw_attrs.element_size = HW_ELEM_SIZE8BIT;
1177 } else if (attrs & DSP_MAPELEMSIZE16) {
1178 /* Size is 16 bit */
1179 hw_attrs.element_size = HW_ELEM_SIZE16BIT;
1180 } else if (attrs & DSP_MAPELEMSIZE32) {
1181 /* Size is 32 bit */
1182 hw_attrs.element_size = HW_ELEM_SIZE32BIT;
1183 } else if (attrs & DSP_MAPELEMSIZE64) {
1184 /* Size is 64 bit */
1185 hw_attrs.element_size = HW_ELEM_SIZE64BIT;
1186 } else {
1187 /*
1188 * Mixedsize isn't enabled, so size can't be
1189 * zero here
1190 */
1191 return -EINVAL;
1192 }
1193 }
1194 if (attrs & DSP_MAPDONOTLOCK)
1195 hw_attrs.donotlockmpupage = 1;
1196 else
1197 hw_attrs.donotlockmpupage = 0;
1198
1199 if (attrs & DSP_MAPVMALLOCADDR) {
1200 return mem_map_vmalloc(dev_ctxt, ul_mpu_addr, virt_addr,
1201 ul_num_bytes, &hw_attrs);
1202 }
1203 /*
1204 * Do OS-specific user-va to pa translation.
1205 * Combine physically contiguous regions to reduce TLBs.
1206 * Pass the translated pa to pte_update.
1207 */
1208 if ((attrs & DSP_MAPPHYSICALADDR)) {
1209 status = pte_update(dev_context, ul_mpu_addr, virt_addr,
1210 ul_num_bytes, &hw_attrs);
1211 goto func_cont;
1212 }
1213
1214 /*
1215 * Important Note: ul_mpu_addr is mapped from user application process
1216 * to current process - it must lie completely within the current
1217 * virtual memory address space in order to be of use to us here!
1218 */
1219 down_read(&mm->mmap_sem);
1220 vma = find_vma(mm, ul_mpu_addr);
1221 if (vma)
1222 dev_dbg(bridge,
1223 "VMAfor UserBuf: ul_mpu_addr=%x, ul_num_bytes=%x, "
1224 "vm_start=%lx, vm_end=%lx, vm_flags=%lx\n", ul_mpu_addr,
1225 ul_num_bytes, vma->vm_start, vma->vm_end,
1226 vma->vm_flags);
1227
1228 /*
1229 * It is observed that under some circumstances, the user buffer is
1230 * spread across several VMAs. So loop through and check if the entire
1231 * user buffer is covered
1232 */
1233 while ((vma) && (ul_mpu_addr + ul_num_bytes > vma->vm_end)) {
1234 /* jump to the next VMA region */
1235 vma = find_vma(mm, vma->vm_end + 1);
1236 dev_dbg(bridge,
1237 "VMA for UserBuf ul_mpu_addr=%x ul_num_bytes=%x, "
1238 "vm_start=%lx, vm_end=%lx, vm_flags=%lx\n", ul_mpu_addr,
1239 ul_num_bytes, vma->vm_start, vma->vm_end,
1240 vma->vm_flags);
1241 }
1242 if (!vma) {
1243 pr_err("%s: Failed to get VMA region for 0x%x (%d)\n",
1244 __func__, ul_mpu_addr, ul_num_bytes);
1245 status = -EINVAL;
1246 up_read(&mm->mmap_sem);
1247 goto func_cont;
1248 }
1249
1250 if (vma->vm_flags & VM_IO) {
1251 num_usr_pgs = ul_num_bytes / PG_SIZE4K;
1252 mpu_addr = ul_mpu_addr;
1253
1254 /* Get the physical addresses for user buffer */
1255 for (pg_i = 0; pg_i < num_usr_pgs; pg_i++) {
1256 pa = user_va2_pa(mm, mpu_addr);
1257 if (!pa) {
1258 status = -EPERM;
1259 pr_err("DSPBRIDGE: VM_IO mapping physical"
1260 "address is invalid\n");
1261 break;
1262 }
1263 if (pfn_valid(__phys_to_pfn(pa))) {
1264 pg = PHYS_TO_PAGE(pa);
1265 get_page(pg);
1266 if (page_count(pg) < 1) {
1267 pr_err("Bad page in VM_IO buffer\n");
1268 bad_page_dump(pa, pg);
1269 }
1270 }
1271 status = pte_set(dev_context->pt_attrs, pa,
1272 va, HW_PAGE_SIZE4KB, &hw_attrs);
1273 if (status)
1274 break;
1275
1276 va += HW_PAGE_SIZE4KB;
1277 mpu_addr += HW_PAGE_SIZE4KB;
1278 pa += HW_PAGE_SIZE4KB;
1279 }
1280 } else {
1281 num_usr_pgs = ul_num_bytes / PG_SIZE4K;
1282 if (vma->vm_flags & (VM_WRITE | VM_MAYWRITE))
1283 write = 1;
1284
1285 for (pg_i = 0; pg_i < num_usr_pgs; pg_i++) {
1286 pg_num = get_user_pages(curr_task, mm, ul_mpu_addr, 1,
1287 write, 1, &mapped_page, NULL);
1288 if (pg_num > 0) {
1289 if (page_count(mapped_page) < 1) {
1290 pr_err("Bad page count after doing"
1291 "get_user_pages on"
1292 "user buffer\n");
1293 bad_page_dump(page_to_phys(mapped_page),
1294 mapped_page);
1295 }
1296 status = pte_set(dev_context->pt_attrs,
1297 page_to_phys(mapped_page), va,
1298 HW_PAGE_SIZE4KB, &hw_attrs);
1299 if (status)
1300 break;
1301
1302 if (mapped_pages)
1303 mapped_pages[pg_i] = mapped_page;
1304
1305 va += HW_PAGE_SIZE4KB;
1306 ul_mpu_addr += HW_PAGE_SIZE4KB;
1307 } else {
1308 pr_err("DSPBRIDGE: get_user_pages FAILED,"
1309 "MPU addr = 0x%x,"
1310 "vma->vm_flags = 0x%lx,"
1311 "get_user_pages Err"
1312 "Value = %d, Buffer"
1313 "size=0x%x\n", ul_mpu_addr,
1314 vma->vm_flags, pg_num, ul_num_bytes);
1315 status = -EPERM;
1316 break;
1317 }
1318 }
1319 }
1320 up_read(&mm->mmap_sem);
1321 func_cont:
1322 if (status) {
1323 /*
1324 * Roll out the mapped pages incase it failed in middle of
1325 * mapping
1326 */
1327 if (pg_i) {
1328 bridge_brd_mem_un_map(dev_context, virt_addr,
1329 (pg_i * PG_SIZE4K));
1330 }
1331 status = -EPERM;
1332 }
1333 /*
1334 * In any case, flush the TLB
1335 * This is called from here instead from pte_update to avoid unnecessary
1336 * repetition while mapping non-contiguous physical regions of a virtual
1337 * region
1338 */
1339 flush_all(dev_context);
1340 dev_dbg(bridge, "%s status %x\n", __func__, status);
1341 return status;
1342 }
1343
1344 /*
1345 * ======== bridge_brd_mem_un_map ========
1346 * Invalidate the PTEs for the DSP VA block to be unmapped.
1347 *
1348 * PTEs of a mapped memory block are contiguous in any page table
1349 * So, instead of looking up the PTE address for every 4K block,
1350 * we clear consecutive PTEs until we unmap all the bytes
1351 */
bridge_brd_mem_un_map(struct bridge_dev_context * dev_ctxt,u32 virt_addr,u32 ul_num_bytes)1352 static int bridge_brd_mem_un_map(struct bridge_dev_context *dev_ctxt,
1353 u32 virt_addr, u32 ul_num_bytes)
1354 {
1355 u32 l1_base_va;
1356 u32 l2_base_va;
1357 u32 l2_base_pa;
1358 u32 l2_page_num;
1359 u32 pte_val;
1360 u32 pte_size;
1361 u32 pte_count;
1362 u32 pte_addr_l1;
1363 u32 pte_addr_l2 = 0;
1364 u32 rem_bytes;
1365 u32 rem_bytes_l2;
1366 u32 va_curr;
1367 struct page *pg = NULL;
1368 int status = 0;
1369 struct bridge_dev_context *dev_context = dev_ctxt;
1370 struct pg_table_attrs *pt = dev_context->pt_attrs;
1371 u32 temp;
1372 u32 paddr;
1373 u32 numof4k_pages = 0;
1374
1375 va_curr = virt_addr;
1376 rem_bytes = ul_num_bytes;
1377 rem_bytes_l2 = 0;
1378 l1_base_va = pt->l1_base_va;
1379 pte_addr_l1 = hw_mmu_pte_addr_l1(l1_base_va, va_curr);
1380 dev_dbg(bridge, "%s dev_ctxt %p, va %x, NumBytes %x l1_base_va %x, "
1381 "pte_addr_l1 %x\n", __func__, dev_ctxt, virt_addr,
1382 ul_num_bytes, l1_base_va, pte_addr_l1);
1383
1384 while (rem_bytes && !status) {
1385 u32 va_curr_orig = va_curr;
1386 /* Find whether the L1 PTE points to a valid L2 PT */
1387 pte_addr_l1 = hw_mmu_pte_addr_l1(l1_base_va, va_curr);
1388 pte_val = *(u32 *) pte_addr_l1;
1389 pte_size = hw_mmu_pte_size_l1(pte_val);
1390
1391 if (pte_size != HW_MMU_COARSE_PAGE_SIZE)
1392 goto skip_coarse_page;
1393
1394 /*
1395 * Get the L2 PA from the L1 PTE, and find
1396 * corresponding L2 VA
1397 */
1398 l2_base_pa = hw_mmu_pte_coarse_l1(pte_val);
1399 l2_base_va = l2_base_pa - pt->l2_base_pa + pt->l2_base_va;
1400 l2_page_num =
1401 (l2_base_pa - pt->l2_base_pa) / HW_MMU_COARSE_PAGE_SIZE;
1402 /*
1403 * Find the L2 PTE address from which we will start
1404 * clearing, the number of PTEs to be cleared on this
1405 * page, and the size of VA space that needs to be
1406 * cleared on this L2 page
1407 */
1408 pte_addr_l2 = hw_mmu_pte_addr_l2(l2_base_va, va_curr);
1409 pte_count = pte_addr_l2 & (HW_MMU_COARSE_PAGE_SIZE - 1);
1410 pte_count = (HW_MMU_COARSE_PAGE_SIZE - pte_count) / sizeof(u32);
1411 if (rem_bytes < (pte_count * PG_SIZE4K))
1412 pte_count = rem_bytes / PG_SIZE4K;
1413 rem_bytes_l2 = pte_count * PG_SIZE4K;
1414
1415 /*
1416 * Unmap the VA space on this L2 PT. A quicker way
1417 * would be to clear pte_count entries starting from
1418 * pte_addr_l2. However, below code checks that we don't
1419 * clear invalid entries or less than 64KB for a 64KB
1420 * entry. Similar checking is done for L1 PTEs too
1421 * below
1422 */
1423 while (rem_bytes_l2 && !status) {
1424 pte_val = *(u32 *) pte_addr_l2;
1425 pte_size = hw_mmu_pte_size_l2(pte_val);
1426 /* va_curr aligned to pte_size? */
1427 if (pte_size == 0 || rem_bytes_l2 < pte_size ||
1428 va_curr & (pte_size - 1)) {
1429 status = -EPERM;
1430 break;
1431 }
1432
1433 /* Collect Physical addresses from VA */
1434 paddr = (pte_val & ~(pte_size - 1));
1435 if (pte_size == HW_PAGE_SIZE64KB)
1436 numof4k_pages = 16;
1437 else
1438 numof4k_pages = 1;
1439 temp = 0;
1440 while (temp++ < numof4k_pages) {
1441 if (!pfn_valid(__phys_to_pfn(paddr))) {
1442 paddr += HW_PAGE_SIZE4KB;
1443 continue;
1444 }
1445 pg = PHYS_TO_PAGE(paddr);
1446 if (page_count(pg) < 1) {
1447 pr_info("DSPBRIDGE: UNMAP function: "
1448 "COUNT 0 FOR PA 0x%x, size = "
1449 "0x%x\n", paddr, ul_num_bytes);
1450 bad_page_dump(paddr, pg);
1451 } else {
1452 set_page_dirty(pg);
1453 page_cache_release(pg);
1454 }
1455 paddr += HW_PAGE_SIZE4KB;
1456 }
1457 if (hw_mmu_pte_clear(pte_addr_l2, va_curr, pte_size)) {
1458 status = -EPERM;
1459 goto EXIT_LOOP;
1460 }
1461
1462 status = 0;
1463 rem_bytes_l2 -= pte_size;
1464 va_curr += pte_size;
1465 pte_addr_l2 += (pte_size >> 12) * sizeof(u32);
1466 }
1467 spin_lock(&pt->pg_lock);
1468 if (rem_bytes_l2 == 0) {
1469 pt->pg_info[l2_page_num].num_entries -= pte_count;
1470 if (pt->pg_info[l2_page_num].num_entries == 0) {
1471 /*
1472 * Clear the L1 PTE pointing to the L2 PT
1473 */
1474 if (!hw_mmu_pte_clear(l1_base_va, va_curr_orig,
1475 HW_MMU_COARSE_PAGE_SIZE))
1476 status = 0;
1477 else {
1478 status = -EPERM;
1479 spin_unlock(&pt->pg_lock);
1480 goto EXIT_LOOP;
1481 }
1482 }
1483 rem_bytes -= pte_count * PG_SIZE4K;
1484 } else
1485 status = -EPERM;
1486
1487 spin_unlock(&pt->pg_lock);
1488 continue;
1489 skip_coarse_page:
1490 /* va_curr aligned to pte_size? */
1491 /* pte_size = 1 MB or 16 MB */
1492 if (pte_size == 0 || rem_bytes < pte_size ||
1493 va_curr & (pte_size - 1)) {
1494 status = -EPERM;
1495 break;
1496 }
1497
1498 if (pte_size == HW_PAGE_SIZE1MB)
1499 numof4k_pages = 256;
1500 else
1501 numof4k_pages = 4096;
1502 temp = 0;
1503 /* Collect Physical addresses from VA */
1504 paddr = (pte_val & ~(pte_size - 1));
1505 while (temp++ < numof4k_pages) {
1506 if (pfn_valid(__phys_to_pfn(paddr))) {
1507 pg = PHYS_TO_PAGE(paddr);
1508 if (page_count(pg) < 1) {
1509 pr_info("DSPBRIDGE: UNMAP function: "
1510 "COUNT 0 FOR PA 0x%x, size = "
1511 "0x%x\n", paddr, ul_num_bytes);
1512 bad_page_dump(paddr, pg);
1513 } else {
1514 set_page_dirty(pg);
1515 page_cache_release(pg);
1516 }
1517 }
1518 paddr += HW_PAGE_SIZE4KB;
1519 }
1520 if (!hw_mmu_pte_clear(l1_base_va, va_curr, pte_size)) {
1521 status = 0;
1522 rem_bytes -= pte_size;
1523 va_curr += pte_size;
1524 } else {
1525 status = -EPERM;
1526 goto EXIT_LOOP;
1527 }
1528 }
1529 /*
1530 * It is better to flush the TLB here, so that any stale old entries
1531 * get flushed
1532 */
1533 EXIT_LOOP:
1534 flush_all(dev_context);
1535 dev_dbg(bridge,
1536 "%s: va_curr %x, pte_addr_l1 %x pte_addr_l2 %x rem_bytes %x,"
1537 " rem_bytes_l2 %x status %x\n", __func__, va_curr, pte_addr_l1,
1538 pte_addr_l2, rem_bytes, rem_bytes_l2, status);
1539 return status;
1540 }
1541
1542 /*
1543 * ======== user_va2_pa ========
1544 * Purpose:
1545 * This function walks through the page tables to convert a userland
1546 * virtual address to physical address
1547 */
user_va2_pa(struct mm_struct * mm,u32 address)1548 static u32 user_va2_pa(struct mm_struct *mm, u32 address)
1549 {
1550 pgd_t *pgd;
1551 pmd_t *pmd;
1552 pte_t *ptep, pte;
1553
1554 pgd = pgd_offset(mm, address);
1555 if (!(pgd_none(*pgd) || pgd_bad(*pgd))) {
1556 pmd = pmd_offset(pgd, address);
1557 if (!(pmd_none(*pmd) || pmd_bad(*pmd))) {
1558 ptep = pte_offset_map(pmd, address);
1559 if (ptep) {
1560 pte = *ptep;
1561 if (pte_present(pte))
1562 return pte & PAGE_MASK;
1563 }
1564 }
1565 }
1566
1567 return 0;
1568 }
1569
1570 /*
1571 * ======== pte_update ========
1572 * This function calculates the optimum page-aligned addresses and sizes
1573 * Caller must pass page-aligned values
1574 */
pte_update(struct bridge_dev_context * dev_ctxt,u32 pa,u32 va,u32 size,struct hw_mmu_map_attrs_t * map_attrs)1575 static int pte_update(struct bridge_dev_context *dev_ctxt, u32 pa,
1576 u32 va, u32 size,
1577 struct hw_mmu_map_attrs_t *map_attrs)
1578 {
1579 u32 i;
1580 u32 all_bits;
1581 u32 pa_curr = pa;
1582 u32 va_curr = va;
1583 u32 num_bytes = size;
1584 struct bridge_dev_context *dev_context = dev_ctxt;
1585 int status = 0;
1586 u32 page_size[] = { HW_PAGE_SIZE16MB, HW_PAGE_SIZE1MB,
1587 HW_PAGE_SIZE64KB, HW_PAGE_SIZE4KB
1588 };
1589
1590 while (num_bytes && !status) {
1591 /* To find the max. page size with which both PA & VA are
1592 * aligned */
1593 all_bits = pa_curr | va_curr;
1594
1595 for (i = 0; i < 4; i++) {
1596 if ((num_bytes >= page_size[i]) && ((all_bits &
1597 (page_size[i] -
1598 1)) == 0)) {
1599 status =
1600 pte_set(dev_context->pt_attrs, pa_curr,
1601 va_curr, page_size[i], map_attrs);
1602 pa_curr += page_size[i];
1603 va_curr += page_size[i];
1604 num_bytes -= page_size[i];
1605 /* Don't try smaller sizes. Hopefully we have
1606 * reached an address aligned to a bigger page
1607 * size */
1608 break;
1609 }
1610 }
1611 }
1612
1613 return status;
1614 }
1615
1616 /*
1617 * ======== pte_set ========
1618 * This function calculates PTE address (MPU virtual) to be updated
1619 * It also manages the L2 page tables
1620 */
pte_set(struct pg_table_attrs * pt,u32 pa,u32 va,u32 size,struct hw_mmu_map_attrs_t * attrs)1621 static int pte_set(struct pg_table_attrs *pt, u32 pa, u32 va,
1622 u32 size, struct hw_mmu_map_attrs_t *attrs)
1623 {
1624 u32 i;
1625 u32 pte_val;
1626 u32 pte_addr_l1;
1627 u32 pte_size;
1628 /* Base address of the PT that will be updated */
1629 u32 pg_tbl_va;
1630 u32 l1_base_va;
1631 /* Compiler warns that the next three variables might be used
1632 * uninitialized in this function. Doesn't seem so. Working around,
1633 * anyways. */
1634 u32 l2_base_va = 0;
1635 u32 l2_base_pa = 0;
1636 u32 l2_page_num = 0;
1637 int status = 0;
1638
1639 l1_base_va = pt->l1_base_va;
1640 pg_tbl_va = l1_base_va;
1641 if ((size == HW_PAGE_SIZE64KB) || (size == HW_PAGE_SIZE4KB)) {
1642 /* Find whether the L1 PTE points to a valid L2 PT */
1643 pte_addr_l1 = hw_mmu_pte_addr_l1(l1_base_va, va);
1644 if (pte_addr_l1 <= (pt->l1_base_va + pt->l1_size)) {
1645 pte_val = *(u32 *) pte_addr_l1;
1646 pte_size = hw_mmu_pte_size_l1(pte_val);
1647 } else {
1648 return -EPERM;
1649 }
1650 spin_lock(&pt->pg_lock);
1651 if (pte_size == HW_MMU_COARSE_PAGE_SIZE) {
1652 /* Get the L2 PA from the L1 PTE, and find
1653 * corresponding L2 VA */
1654 l2_base_pa = hw_mmu_pte_coarse_l1(pte_val);
1655 l2_base_va =
1656 l2_base_pa - pt->l2_base_pa + pt->l2_base_va;
1657 l2_page_num =
1658 (l2_base_pa -
1659 pt->l2_base_pa) / HW_MMU_COARSE_PAGE_SIZE;
1660 } else if (pte_size == 0) {
1661 /* L1 PTE is invalid. Allocate a L2 PT and
1662 * point the L1 PTE to it */
1663 /* Find a free L2 PT. */
1664 for (i = 0; (i < pt->l2_num_pages) &&
1665 (pt->pg_info[i].num_entries != 0); i++)
1666 ;
1667 if (i < pt->l2_num_pages) {
1668 l2_page_num = i;
1669 l2_base_pa = pt->l2_base_pa + (l2_page_num *
1670 HW_MMU_COARSE_PAGE_SIZE);
1671 l2_base_va = pt->l2_base_va + (l2_page_num *
1672 HW_MMU_COARSE_PAGE_SIZE);
1673 /* Endianness attributes are ignored for
1674 * HW_MMU_COARSE_PAGE_SIZE */
1675 status =
1676 hw_mmu_pte_set(l1_base_va, l2_base_pa, va,
1677 HW_MMU_COARSE_PAGE_SIZE,
1678 attrs);
1679 } else {
1680 status = -ENOMEM;
1681 }
1682 } else {
1683 /* Found valid L1 PTE of another size.
1684 * Should not overwrite it. */
1685 status = -EPERM;
1686 }
1687 if (!status) {
1688 pg_tbl_va = l2_base_va;
1689 if (size == HW_PAGE_SIZE64KB)
1690 pt->pg_info[l2_page_num].num_entries += 16;
1691 else
1692 pt->pg_info[l2_page_num].num_entries++;
1693 dev_dbg(bridge, "PTE: L2 BaseVa %x, BasePa %x, PageNum "
1694 "%x, num_entries %x\n", l2_base_va,
1695 l2_base_pa, l2_page_num,
1696 pt->pg_info[l2_page_num].num_entries);
1697 }
1698 spin_unlock(&pt->pg_lock);
1699 }
1700 if (!status) {
1701 dev_dbg(bridge, "PTE: pg_tbl_va %x, pa %x, va %x, size %x\n",
1702 pg_tbl_va, pa, va, size);
1703 dev_dbg(bridge, "PTE: endianism %x, element_size %x, "
1704 "mixed_size %x\n", attrs->endianism,
1705 attrs->element_size, attrs->mixed_size);
1706 status = hw_mmu_pte_set(pg_tbl_va, pa, va, size, attrs);
1707 }
1708
1709 return status;
1710 }
1711
1712 /* Memory map kernel VA -- memory allocated with vmalloc */
mem_map_vmalloc(struct bridge_dev_context * dev_context,u32 ul_mpu_addr,u32 virt_addr,u32 ul_num_bytes,struct hw_mmu_map_attrs_t * hw_attrs)1713 static int mem_map_vmalloc(struct bridge_dev_context *dev_context,
1714 u32 ul_mpu_addr, u32 virt_addr,
1715 u32 ul_num_bytes,
1716 struct hw_mmu_map_attrs_t *hw_attrs)
1717 {
1718 int status = 0;
1719 struct page *page[1];
1720 u32 i;
1721 u32 pa_curr;
1722 u32 pa_next;
1723 u32 va_curr;
1724 u32 size_curr;
1725 u32 num_pages;
1726 u32 pa;
1727 u32 num_of4k_pages;
1728 u32 temp = 0;
1729
1730 /*
1731 * Do Kernel va to pa translation.
1732 * Combine physically contiguous regions to reduce TLBs.
1733 * Pass the translated pa to pte_update.
1734 */
1735 num_pages = ul_num_bytes / PAGE_SIZE; /* PAGE_SIZE = OS page size */
1736 i = 0;
1737 va_curr = ul_mpu_addr;
1738 page[0] = vmalloc_to_page((void *)va_curr);
1739 pa_next = page_to_phys(page[0]);
1740 while (!status && (i < num_pages)) {
1741 /*
1742 * Reuse pa_next from the previous iteraion to avoid
1743 * an extra va2pa call
1744 */
1745 pa_curr = pa_next;
1746 size_curr = PAGE_SIZE;
1747 /*
1748 * If the next page is physically contiguous,
1749 * map it with the current one by increasing
1750 * the size of the region to be mapped
1751 */
1752 while (++i < num_pages) {
1753 page[0] =
1754 vmalloc_to_page((void *)(va_curr + size_curr));
1755 pa_next = page_to_phys(page[0]);
1756
1757 if (pa_next == (pa_curr + size_curr))
1758 size_curr += PAGE_SIZE;
1759 else
1760 break;
1761
1762 }
1763 if (pa_next == 0) {
1764 status = -ENOMEM;
1765 break;
1766 }
1767 pa = pa_curr;
1768 num_of4k_pages = size_curr / HW_PAGE_SIZE4KB;
1769 while (temp++ < num_of4k_pages) {
1770 get_page(PHYS_TO_PAGE(pa));
1771 pa += HW_PAGE_SIZE4KB;
1772 }
1773 status = pte_update(dev_context, pa_curr, virt_addr +
1774 (va_curr - ul_mpu_addr), size_curr,
1775 hw_attrs);
1776 va_curr += size_curr;
1777 }
1778 /*
1779 * In any case, flush the TLB
1780 * This is called from here instead from pte_update to avoid unnecessary
1781 * repetition while mapping non-contiguous physical regions of a virtual
1782 * region
1783 */
1784 flush_all(dev_context);
1785 dev_dbg(bridge, "%s status %x\n", __func__, status);
1786 return status;
1787 }
1788
1789 /*
1790 * ======== wait_for_start ========
1791 * Wait for the singal from DSP that it has started, or time out.
1792 */
wait_for_start(struct bridge_dev_context * dev_context,u32 dw_sync_addr)1793 bool wait_for_start(struct bridge_dev_context *dev_context, u32 dw_sync_addr)
1794 {
1795 u16 timeout = TIHELEN_ACKTIMEOUT;
1796
1797 /* Wait for response from board */
1798 while (__raw_readw(dw_sync_addr) && --timeout)
1799 udelay(10);
1800
1801 /* If timed out: return false */
1802 if (!timeout) {
1803 pr_err("%s: Timed out waiting DSP to Start\n", __func__);
1804 return false;
1805 }
1806 return true;
1807 }
1808