1 /* SPDX-License-Identifier: MIT */
2 /*
3 * Copyright 2023 Advanced Micro Devices, Inc.
4 *
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the "Software"),
7 * to deal in the Software without restriction, including without limitation
8 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
9 * and/or sell copies of the Software, and to permit persons to whom the
10 * Software is furnished to do so, subject to the following conditions:
11 *
12 * The above copyright notice and this permission notice shall be included in
13 * all copies or substantial portions of the Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
19 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
20 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
21 * OTHER DEALINGS IN THE SOFTWARE.
22 *
23 * Authors: AMD
24 *
25 */
26
27 #include "dcn35_dsc.h"
28 #include "reg_helper.h"
29
30 static void dsc35_enable(struct display_stream_compressor *dsc, int opp_pipe);
31 static void dsc35_get_single_enc_caps(struct dsc_enc_caps *dsc_enc_caps, unsigned int max_dscclk_khz);
32
33 static const struct dsc_funcs dcn35_dsc_funcs = {
34 .dsc_read_state = dsc2_read_state,
35 .dsc_read_reg_state = dsc2_read_reg_state,
36 .dsc_validate_stream = dsc2_validate_stream,
37 .dsc_set_config = dsc2_set_config,
38 .dsc_get_packed_pps = dsc2_get_packed_pps,
39 .dsc_enable = dsc35_enable,
40 .dsc_disable = dsc2_disable,
41 .dsc_disconnect = dsc2_disconnect,
42 .dsc_wait_disconnect_pending_clear = dsc2_wait_disconnect_pending_clear,
43 .dsc_get_single_enc_caps = dsc35_get_single_enc_caps,
44 };
45
46 /* Macro definitios for REG_SET macros*/
47 #define CTX \
48 dsc20->base.ctx
49
50 #define REG(reg)\
51 dsc20->dsc_regs->reg
52
53 #undef FN
54 #define FN(reg_name, field_name) \
55 ((const struct dcn35_dsc_shift *)(dsc20->dsc_shift))->field_name, \
56 ((const struct dcn35_dsc_mask *)(dsc20->dsc_mask))->field_name
57
58 #define DC_LOGGER \
59 dsc->ctx->logger
60
dsc35_construct(struct dcn20_dsc * dsc,struct dc_context * ctx,int inst,const struct dcn20_dsc_registers * dsc_regs,const struct dcn35_dsc_shift * dsc_shift,const struct dcn35_dsc_mask * dsc_mask)61 void dsc35_construct(struct dcn20_dsc *dsc,
62 struct dc_context *ctx,
63 int inst,
64 const struct dcn20_dsc_registers *dsc_regs,
65 const struct dcn35_dsc_shift *dsc_shift,
66 const struct dcn35_dsc_mask *dsc_mask)
67 {
68 dsc->base.ctx = ctx;
69 dsc->base.inst = inst;
70 dsc->base.funcs = &dcn35_dsc_funcs;
71
72 dsc->dsc_regs = dsc_regs;
73 dsc->dsc_shift = (const struct dcn20_dsc_shift *)(dsc_shift);
74 dsc->dsc_mask = (const struct dcn20_dsc_mask *)(dsc_mask);
75
76 dsc->max_image_width = 5184;
77 }
78
dsc35_enable(struct display_stream_compressor * dsc,int opp_pipe)79 static void dsc35_enable(struct display_stream_compressor *dsc, int opp_pipe)
80 {
81 struct dcn20_dsc *dsc20 = TO_DCN20_DSC(dsc);
82 int dsc_clock_en;
83 int dsc_fw_config;
84 int enabled_opp_pipe;
85
86 DC_LOG_DSC("enable DSC %d at opp pipe %d", dsc->inst, opp_pipe);
87
88 // TODO: After an idle exit, the HW default values for power control
89 // are changed intermittently due to unknown reasons. There are cases
90 // when dscc memory are still in shutdown state during enablement.
91 // Reset power control to hw default values.
92 REG_UPDATE_2(DSCC_MEM_POWER_CONTROL,
93 DSCC_MEM_PWR_FORCE, 0,
94 DSCC_MEM_PWR_DIS, 0);
95
96 REG_GET(DSC_TOP_CONTROL, DSC_CLOCK_EN, &dsc_clock_en);
97 REG_GET_2(DSCRM_DSC_FORWARD_CONFIG, DSCRM_DSC_FORWARD_EN, &dsc_fw_config, DSCRM_DSC_OPP_PIPE_SOURCE, &enabled_opp_pipe);
98 if ((dsc_clock_en || dsc_fw_config) && enabled_opp_pipe != opp_pipe) {
99 DC_LOG_DSC("ERROR: DSC %d at opp pipe %d already enabled!", dsc->inst, enabled_opp_pipe);
100 ASSERT(0);
101 }
102
103 REG_UPDATE(DSC_TOP_CONTROL,
104 DSC_CLOCK_EN, 1);
105
106 REG_UPDATE_2(DSCRM_DSC_FORWARD_CONFIG,
107 DSCRM_DSC_FORWARD_EN, 1,
108 DSCRM_DSC_OPP_PIPE_SOURCE, opp_pipe);
109 }
110
dsc35_set_fgcg(struct dcn20_dsc * dsc20,bool enable)111 void dsc35_set_fgcg(struct dcn20_dsc *dsc20, bool enable)
112 {
113 REG_UPDATE(DSC_TOP_CONTROL, DSC_FGCG_REP_DIS, !enable);
114 }
115
dsc35_get_single_enc_caps(struct dsc_enc_caps * dsc_enc_caps,unsigned int max_dscclk_khz)116 void dsc35_get_single_enc_caps(struct dsc_enc_caps *dsc_enc_caps, unsigned int max_dscclk_khz)
117 {
118 dsc_enc_caps->dsc_version = 0x21; /* v1.2 - DP spec defined it in reverse order and we kept it */
119
120 dsc_enc_caps->slice_caps.bits.NUM_SLICES_1 = 1;
121 dsc_enc_caps->slice_caps.bits.NUM_SLICES_2 = 1;
122 dsc_enc_caps->slice_caps.bits.NUM_SLICES_3 = 1;
123 dsc_enc_caps->slice_caps.bits.NUM_SLICES_4 = 1;
124
125 dsc_enc_caps->lb_bit_depth = 13;
126 dsc_enc_caps->is_block_pred_supported = true;
127
128 dsc_enc_caps->color_formats.bits.RGB = 1;
129 dsc_enc_caps->color_formats.bits.YCBCR_444 = 1;
130 dsc_enc_caps->color_formats.bits.YCBCR_SIMPLE_422 = 1;
131 dsc_enc_caps->color_formats.bits.YCBCR_NATIVE_422 = 0;
132 dsc_enc_caps->color_formats.bits.YCBCR_NATIVE_420 = 1;
133
134 dsc_enc_caps->color_depth.bits.COLOR_DEPTH_8_BPC = 1;
135 dsc_enc_caps->color_depth.bits.COLOR_DEPTH_10_BPC = 1;
136 dsc_enc_caps->color_depth.bits.COLOR_DEPTH_12_BPC = 1;
137
138 dsc_enc_caps->max_total_throughput_mps = max_dscclk_khz * 3 / 1000;
139
140 dsc_enc_caps->max_slice_width = 5184; /* (including 64 overlap pixels for eDP MSO mode) */
141 dsc_enc_caps->bpp_increment_div = 16; /* 1/16th of a bit */
142 }
143