1 /*
2 * Copyright 2017 Advanced Micro Devices, Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
21 *
22 * Authors: AMD
23 *
24 */
25
26 #include <drm/display/drm_dsc_helper.h>
27
28 #include "reg_helper.h"
29 #include "dcn20_dsc.h"
30 #include "dsc/dscc_types.h"
31 #include "dsc/rc_calc.h"
32
33 static void dsc_write_to_registers(struct display_stream_compressor *dsc, const struct dsc_reg_values *reg_vals);
34
35 static const struct dsc_funcs dcn20_dsc_funcs = {
36 .dsc_get_enc_caps = dsc2_get_enc_caps,
37 .dsc_read_state = dsc2_read_state,
38 .dsc_read_reg_state = dsc2_read_reg_state,
39 .dsc_validate_stream = dsc2_validate_stream,
40 .dsc_set_config = dsc2_set_config,
41 .dsc_get_packed_pps = dsc2_get_packed_pps,
42 .dsc_enable = dsc2_enable,
43 .dsc_disable = dsc2_disable,
44 .dsc_disconnect = dsc2_disconnect,
45 .dsc_wait_disconnect_pending_clear = dsc2_wait_disconnect_pending_clear,
46 };
47
48 /* Macro definitios for REG_SET macros*/
49 #define CTX \
50 dsc20->base.ctx
51
52 #define REG(reg)\
53 dsc20->dsc_regs->reg
54
55 #undef FN
56 #define FN(reg_name, field_name) \
57 dsc20->dsc_shift->field_name, dsc20->dsc_mask->field_name
58 #define DC_LOGGER \
59 dsc->ctx->logger
60
61 /* API functions (external or via structure->function_pointer) */
62
dsc2_construct(struct dcn20_dsc * dsc,struct dc_context * ctx,int inst,const struct dcn20_dsc_registers * dsc_regs,const struct dcn20_dsc_shift * dsc_shift,const struct dcn20_dsc_mask * dsc_mask)63 void dsc2_construct(struct dcn20_dsc *dsc,
64 struct dc_context *ctx,
65 int inst,
66 const struct dcn20_dsc_registers *dsc_regs,
67 const struct dcn20_dsc_shift *dsc_shift,
68 const struct dcn20_dsc_mask *dsc_mask)
69 {
70 dsc->base.ctx = ctx;
71 dsc->base.inst = inst;
72 dsc->base.funcs = &dcn20_dsc_funcs;
73
74 dsc->dsc_regs = dsc_regs;
75 dsc->dsc_shift = dsc_shift;
76 dsc->dsc_mask = dsc_mask;
77
78 dsc->max_image_width = 5184;
79 }
80
81
82 #define DCN20_MAX_PIXEL_CLOCK_Mhz 1188
83 #define DCN20_MAX_DISPLAY_CLOCK_Mhz 1200
84
85 /* This returns the capabilities for a single DSC encoder engine. Number of slices and total throughput
86 * can be doubled, tripled etc. by using additional DSC engines.
87 */
dsc2_get_enc_caps(struct dsc_enc_caps * dsc_enc_caps,int pixel_clock_100Hz)88 void dsc2_get_enc_caps(struct dsc_enc_caps *dsc_enc_caps, int pixel_clock_100Hz)
89 {
90 dsc_enc_caps->dsc_version = 0x21; /* v1.2 - DP spec defined it in reverse order and we kept it */
91
92 dsc_enc_caps->slice_caps.bits.NUM_SLICES_1 = 1;
93 dsc_enc_caps->slice_caps.bits.NUM_SLICES_2 = 1;
94 dsc_enc_caps->slice_caps.bits.NUM_SLICES_3 = 1;
95 dsc_enc_caps->slice_caps.bits.NUM_SLICES_4 = 1;
96
97 dsc_enc_caps->lb_bit_depth = 13;
98 dsc_enc_caps->is_block_pred_supported = true;
99
100 dsc_enc_caps->color_formats.bits.RGB = 1;
101 dsc_enc_caps->color_formats.bits.YCBCR_444 = 1;
102 dsc_enc_caps->color_formats.bits.YCBCR_SIMPLE_422 = 1;
103 dsc_enc_caps->color_formats.bits.YCBCR_NATIVE_422 = 0;
104 dsc_enc_caps->color_formats.bits.YCBCR_NATIVE_420 = 1;
105
106 dsc_enc_caps->color_depth.bits.COLOR_DEPTH_8_BPC = 1;
107 dsc_enc_caps->color_depth.bits.COLOR_DEPTH_10_BPC = 1;
108 dsc_enc_caps->color_depth.bits.COLOR_DEPTH_12_BPC = 1;
109
110 /* Maximum total throughput with all the slices combined. This is different from how DP spec specifies it.
111 * Our decoder's total throughput in Pix/s is equal to DISPCLK. This is then shared between slices.
112 * The value below is the absolute maximum value. The actual throughput may be lower, but it'll always
113 * be sufficient to process the input pixel rate fed into a single DSC engine.
114 */
115 dsc_enc_caps->max_total_throughput_mps = DCN20_MAX_DISPLAY_CLOCK_Mhz;
116
117 /* For pixel clock bigger than a single-pipe limit we'll need two engines, which then doubles our
118 * throughput and number of slices, but also introduces a lower limit of 2 slices
119 */
120 if (pixel_clock_100Hz >= DCN20_MAX_PIXEL_CLOCK_Mhz*10000) {
121 dsc_enc_caps->slice_caps.bits.NUM_SLICES_1 = 0;
122 dsc_enc_caps->slice_caps.bits.NUM_SLICES_8 = 1;
123 dsc_enc_caps->max_total_throughput_mps = DCN20_MAX_DISPLAY_CLOCK_Mhz * 2;
124 }
125
126 /* For pixel clock bigger than a single-pipe limit needing four engines ODM 4:1, which then quardruples our
127 * throughput and number of slices
128 */
129 if (pixel_clock_100Hz > DCN20_MAX_PIXEL_CLOCK_Mhz*10000*2) {
130 dsc_enc_caps->slice_caps.bits.NUM_SLICES_12 = 1;
131 dsc_enc_caps->slice_caps.bits.NUM_SLICES_16 = 1;
132 dsc_enc_caps->max_total_throughput_mps = DCN20_MAX_DISPLAY_CLOCK_Mhz * 4;
133 }
134
135 dsc_enc_caps->max_slice_width = 5184; /* (including 64 overlap pixels for eDP MSO mode) */
136 dsc_enc_caps->bpp_increment_div = 16; /* 1/16th of a bit */
137 }
138
139
140 /* this function read dsc related register fields to be logged later in dcn10_log_hw_state
141 * into a dcn_dsc_state struct.
142 */
dsc2_read_state(struct display_stream_compressor * dsc,struct dcn_dsc_state * s)143 void dsc2_read_state(struct display_stream_compressor *dsc, struct dcn_dsc_state *s)
144 {
145 struct dcn20_dsc *dsc20 = TO_DCN20_DSC(dsc);
146
147 REG_GET(DSC_TOP_CONTROL, DSC_CLOCK_EN, &s->dsc_clock_en);
148 REG_GET(DSCC_PPS_CONFIG3, SLICE_WIDTH, &s->dsc_slice_width);
149 REG_GET(DSCC_PPS_CONFIG1, BITS_PER_PIXEL, &s->dsc_bits_per_pixel);
150 REG_GET(DSCC_PPS_CONFIG3, SLICE_HEIGHT, &s->dsc_slice_height);
151 REG_GET(DSCC_PPS_CONFIG1, CHUNK_SIZE, &s->dsc_chunk_size);
152 REG_GET(DSCC_PPS_CONFIG2, PIC_WIDTH, &s->dsc_pic_width);
153 REG_GET(DSCC_PPS_CONFIG2, PIC_HEIGHT, &s->dsc_pic_height);
154 REG_GET(DSCC_PPS_CONFIG7, SLICE_BPG_OFFSET, &s->dsc_slice_bpg_offset);
155 REG_GET_2(DSCRM_DSC_FORWARD_CONFIG, DSCRM_DSC_FORWARD_EN, &s->dsc_fw_en,
156 DSCRM_DSC_OPP_PIPE_SOURCE, &s->dsc_opp_source);
157 }
158
dsc2_read_reg_state(struct display_stream_compressor * dsc,struct dcn_dsc_reg_state * dccg_reg_state)159 void dsc2_read_reg_state(struct display_stream_compressor *dsc, struct dcn_dsc_reg_state *dccg_reg_state)
160 {
161 struct dcn20_dsc *dsc20 = TO_DCN20_DSC(dsc);
162
163 dccg_reg_state->dsc_top_control = REG_READ(DSC_TOP_CONTROL);
164 dccg_reg_state->dscc_interrupt_control_status = REG_READ(DSCC_INTERRUPT_CONTROL_STATUS);
165 }
166
dsc2_validate_stream(struct display_stream_compressor * dsc,const struct dsc_config * dsc_cfg)167 bool dsc2_validate_stream(struct display_stream_compressor *dsc, const struct dsc_config *dsc_cfg)
168 {
169 struct dsc_optc_config dsc_optc_cfg;
170 struct dcn20_dsc *dsc20 = TO_DCN20_DSC(dsc);
171
172 if (dsc_cfg->pic_width > dsc20->max_image_width)
173 return false;
174
175 return dsc_prepare_config(dsc_cfg, &dsc20->reg_vals, &dsc_optc_cfg);
176 }
177
178
dsc_config_log(struct display_stream_compressor * dsc,const struct dsc_config * config)179 void dsc_config_log(struct display_stream_compressor *dsc, const struct dsc_config *config)
180 {
181 DC_LOG_DSC("\tnum_slices_h %d", config->dc_dsc_cfg.num_slices_h);
182 DC_LOG_DSC("\tnum_slices_v %d", config->dc_dsc_cfg.num_slices_v);
183 DC_LOG_DSC("\tbits_per_pixel %d (%d.%04d)",
184 config->dc_dsc_cfg.bits_per_pixel,
185 config->dc_dsc_cfg.bits_per_pixel / 16,
186 ((config->dc_dsc_cfg.bits_per_pixel % 16) * 10000) / 16);
187 DC_LOG_DSC("\tcolor_depth %d", config->color_depth);
188 }
189
dsc2_set_config(struct display_stream_compressor * dsc,const struct dsc_config * dsc_cfg,struct dsc_optc_config * dsc_optc_cfg)190 void dsc2_set_config(struct display_stream_compressor *dsc, const struct dsc_config *dsc_cfg,
191 struct dsc_optc_config *dsc_optc_cfg)
192 {
193 bool is_config_ok;
194 struct dcn20_dsc *dsc20 = TO_DCN20_DSC(dsc);
195
196 DC_LOG_DSC("Setting DSC Config at DSC inst %d", dsc->inst);
197 dsc_config_log(dsc, dsc_cfg);
198 is_config_ok = dsc_prepare_config(dsc_cfg, &dsc20->reg_vals, dsc_optc_cfg);
199 ASSERT(is_config_ok);
200 DC_LOG_DSC("programming DSC Picture Parameter Set (PPS):");
201 dsc_log_pps(dsc, &dsc20->reg_vals.pps);
202 dsc_write_to_registers(dsc, &dsc20->reg_vals);
203 }
204
205
dsc2_get_packed_pps(struct display_stream_compressor * dsc,const struct dsc_config * dsc_cfg,uint8_t * dsc_packed_pps)206 bool dsc2_get_packed_pps(struct display_stream_compressor *dsc, const struct dsc_config *dsc_cfg, uint8_t *dsc_packed_pps)
207 {
208 bool is_config_ok;
209 struct dsc_reg_values dsc_reg_vals;
210 struct dsc_optc_config dsc_optc_cfg;
211
212 memset(&dsc_reg_vals, 0, sizeof(dsc_reg_vals));
213 memset(&dsc_optc_cfg, 0, sizeof(dsc_optc_cfg));
214
215 DC_LOG_DSC("Getting packed DSC PPS for DSC Config:");
216 dsc_config_log(dsc, dsc_cfg);
217 DC_LOG_DSC("DSC Picture Parameter Set (PPS):");
218 is_config_ok = dsc_prepare_config(dsc_cfg, &dsc_reg_vals, &dsc_optc_cfg);
219 ASSERT(is_config_ok);
220 drm_dsc_pps_payload_pack((struct drm_dsc_picture_parameter_set *)dsc_packed_pps, &dsc_reg_vals.pps);
221 dsc_log_pps(dsc, &dsc_reg_vals.pps);
222
223 return is_config_ok;
224 }
225
226
dsc2_enable(struct display_stream_compressor * dsc,int opp_pipe)227 void dsc2_enable(struct display_stream_compressor *dsc, int opp_pipe)
228 {
229 struct dcn20_dsc *dsc20 = TO_DCN20_DSC(dsc);
230 int dsc_clock_en;
231 int dsc_fw_config;
232 int enabled_opp_pipe;
233
234 DC_LOG_DSC("enable DSC %d at opp pipe %d", dsc->inst, opp_pipe);
235
236 REG_GET(DSC_TOP_CONTROL, DSC_CLOCK_EN, &dsc_clock_en);
237 REG_GET_2(DSCRM_DSC_FORWARD_CONFIG, DSCRM_DSC_FORWARD_EN, &dsc_fw_config, DSCRM_DSC_OPP_PIPE_SOURCE, &enabled_opp_pipe);
238 if ((dsc_clock_en || dsc_fw_config) && enabled_opp_pipe != opp_pipe) {
239 DC_LOG_DSC("ERROR: DSC %d at opp pipe %d already enabled!", dsc->inst, enabled_opp_pipe);
240 ASSERT(0);
241 }
242
243 REG_UPDATE(DSC_TOP_CONTROL,
244 DSC_CLOCK_EN, 1);
245
246 REG_UPDATE_2(DSCRM_DSC_FORWARD_CONFIG,
247 DSCRM_DSC_FORWARD_EN, 1,
248 DSCRM_DSC_OPP_PIPE_SOURCE, opp_pipe);
249 }
250
251
dsc2_disable(struct display_stream_compressor * dsc)252 void dsc2_disable(struct display_stream_compressor *dsc)
253 {
254 struct dcn20_dsc *dsc20 = TO_DCN20_DSC(dsc);
255 int dsc_clock_en;
256
257 DC_LOG_DSC("disable DSC %d", dsc->inst);
258
259 REG_GET(DSC_TOP_CONTROL, DSC_CLOCK_EN, &dsc_clock_en);
260 if (!dsc_clock_en) {
261 DC_LOG_DSC("DSC %d already disabled!", dsc->inst);
262 }
263
264 REG_UPDATE(DSCRM_DSC_FORWARD_CONFIG,
265 DSCRM_DSC_FORWARD_EN, 0);
266
267 REG_UPDATE(DSC_TOP_CONTROL,
268 DSC_CLOCK_EN, 0);
269 }
270
dsc2_wait_disconnect_pending_clear(struct display_stream_compressor * dsc)271 void dsc2_wait_disconnect_pending_clear(struct display_stream_compressor *dsc)
272 {
273 struct dcn20_dsc *dsc20 = TO_DCN20_DSC(dsc);
274
275 REG_WAIT(DSCRM_DSC_FORWARD_CONFIG, DSCRM_DSC_DOUBLE_BUFFER_REG_UPDATE_PENDING, 0, 2, 50000);
276 }
277
dsc2_disconnect(struct display_stream_compressor * dsc)278 void dsc2_disconnect(struct display_stream_compressor *dsc)
279 {
280 struct dcn20_dsc *dsc20 = TO_DCN20_DSC(dsc);
281
282 DC_LOG_DSC("disconnect DSC %d", dsc->inst);
283
284 REG_UPDATE(DSCRM_DSC_FORWARD_CONFIG,
285 DSCRM_DSC_FORWARD_EN, 0);
286 }
287
288 /* This module's internal functions */
dsc_log_pps(struct display_stream_compressor * dsc,struct drm_dsc_config * pps)289 void dsc_log_pps(struct display_stream_compressor *dsc, struct drm_dsc_config *pps)
290 {
291 int i;
292 int bits_per_pixel = pps->bits_per_pixel;
293
294 DC_LOG_DSC("\tdsc_version_major %d", pps->dsc_version_major);
295 DC_LOG_DSC("\tdsc_version_minor %d", pps->dsc_version_minor);
296 DC_LOG_DSC("\tbits_per_component %d", pps->bits_per_component);
297 DC_LOG_DSC("\tline_buf_depth %d", pps->line_buf_depth);
298 DC_LOG_DSC("\tblock_pred_enable %d", pps->block_pred_enable);
299 DC_LOG_DSC("\tconvert_rgb %d", pps->convert_rgb);
300 DC_LOG_DSC("\tsimple_422 %d", pps->simple_422);
301 DC_LOG_DSC("\tvbr_enable %d", pps->vbr_enable);
302 DC_LOG_DSC("\tbits_per_pixel %d (%d.%04d)", bits_per_pixel, bits_per_pixel / 16, ((bits_per_pixel % 16) * 10000) / 16);
303 DC_LOG_DSC("\tpic_height %d", pps->pic_height);
304 DC_LOG_DSC("\tpic_width %d", pps->pic_width);
305 DC_LOG_DSC("\tslice_height %d", pps->slice_height);
306 DC_LOG_DSC("\tslice_width %d", pps->slice_width);
307 DC_LOG_DSC("\tslice_chunk_size %d", pps->slice_chunk_size);
308 DC_LOG_DSC("\tinitial_xmit_delay %d", pps->initial_xmit_delay);
309 DC_LOG_DSC("\tinitial_dec_delay %d", pps->initial_dec_delay);
310 DC_LOG_DSC("\tinitial_scale_value %d", pps->initial_scale_value);
311 DC_LOG_DSC("\tscale_increment_interval %d", pps->scale_increment_interval);
312 DC_LOG_DSC("\tscale_decrement_interval %d", pps->scale_decrement_interval);
313 DC_LOG_DSC("\tfirst_line_bpg_offset %d", pps->first_line_bpg_offset);
314 DC_LOG_DSC("\tnfl_bpg_offset %d", pps->nfl_bpg_offset);
315 DC_LOG_DSC("\tslice_bpg_offset %d", pps->slice_bpg_offset);
316 DC_LOG_DSC("\tinitial_offset %d", pps->initial_offset);
317 DC_LOG_DSC("\tfinal_offset %d", pps->final_offset);
318 DC_LOG_DSC("\tflatness_min_qp %d", pps->flatness_min_qp);
319 DC_LOG_DSC("\tflatness_max_qp %d", pps->flatness_max_qp);
320 /* DC_LOG_DSC("\trc_parameter_set %d", pps->rc_parameter_set); */
321 DC_LOG_DSC("\tnative_420 %d", pps->native_420);
322 DC_LOG_DSC("\tnative_422 %d", pps->native_422);
323 DC_LOG_DSC("\tsecond_line_bpg_offset %d", pps->second_line_bpg_offset);
324 DC_LOG_DSC("\tnsl_bpg_offset %d", pps->nsl_bpg_offset);
325 DC_LOG_DSC("\tsecond_line_offset_adj %d", pps->second_line_offset_adj);
326 DC_LOG_DSC("\trc_model_size %d", pps->rc_model_size);
327 DC_LOG_DSC("\trc_edge_factor %d", pps->rc_edge_factor);
328 DC_LOG_DSC("\trc_quant_incr_limit0 %d", pps->rc_quant_incr_limit0);
329 DC_LOG_DSC("\trc_quant_incr_limit1 %d", pps->rc_quant_incr_limit1);
330 DC_LOG_DSC("\trc_tgt_offset_high %d", pps->rc_tgt_offset_high);
331 DC_LOG_DSC("\trc_tgt_offset_low %d", pps->rc_tgt_offset_low);
332
333 for (i = 0; i < NUM_BUF_RANGES - 1; i++)
334 DC_LOG_DSC("\trc_buf_thresh[%d] %d", i, pps->rc_buf_thresh[i]);
335
336 for (i = 0; i < NUM_BUF_RANGES; i++) {
337 DC_LOG_DSC("\trc_range_parameters[%d].range_min_qp %d", i, pps->rc_range_params[i].range_min_qp);
338 DC_LOG_DSC("\trc_range_parameters[%d].range_max_qp %d", i, pps->rc_range_params[i].range_max_qp);
339 DC_LOG_DSC("\trc_range_parameters[%d].range_bpg_offset %d", i, pps->rc_range_params[i].range_bpg_offset);
340 }
341 }
342
dsc_override_rc_params(struct rc_params * rc,const struct dc_dsc_rc_params_override * override)343 void dsc_override_rc_params(struct rc_params *rc, const struct dc_dsc_rc_params_override *override)
344 {
345 uint8_t i;
346
347 rc->rc_model_size = override->rc_model_size;
348 for (i = 0; i < DC_DSC_RC_BUF_THRESH_SIZE; i++)
349 rc->rc_buf_thresh[i] = override->rc_buf_thresh[i];
350 for (i = 0; i < DC_DSC_QP_SET_SIZE; i++) {
351 rc->qp_min[i] = override->rc_minqp[i];
352 rc->qp_max[i] = override->rc_maxqp[i];
353 rc->ofs[i] = override->rc_offset[i];
354 }
355
356 rc->rc_tgt_offset_hi = override->rc_tgt_offset_hi;
357 rc->rc_tgt_offset_lo = override->rc_tgt_offset_lo;
358 rc->rc_edge_factor = override->rc_edge_factor;
359 rc->rc_quant_incr_limit0 = override->rc_quant_incr_limit0;
360 rc->rc_quant_incr_limit1 = override->rc_quant_incr_limit1;
361
362 rc->initial_fullness_offset = override->initial_fullness_offset;
363 rc->initial_xmit_delay = override->initial_delay;
364
365 rc->flatness_min_qp = override->flatness_min_qp;
366 rc->flatness_max_qp = override->flatness_max_qp;
367 rc->flatness_det_thresh = override->flatness_det_thresh;
368 }
369
dsc_prepare_config(const struct dsc_config * dsc_cfg,struct dsc_reg_values * dsc_reg_vals,struct dsc_optc_config * dsc_optc_cfg)370 bool dsc_prepare_config(const struct dsc_config *dsc_cfg, struct dsc_reg_values *dsc_reg_vals,
371 struct dsc_optc_config *dsc_optc_cfg)
372 {
373 struct dsc_parameters dsc_params;
374 struct rc_params rc;
375
376 /* Validate input parameters */
377 ASSERT(dsc_cfg->dc_dsc_cfg.num_slices_h);
378 ASSERT(dsc_cfg->dc_dsc_cfg.num_slices_v);
379 ASSERT(dsc_cfg->dc_dsc_cfg.version_minor == 1 || dsc_cfg->dc_dsc_cfg.version_minor == 2);
380 ASSERT(dsc_cfg->pic_width);
381 ASSERT(dsc_cfg->pic_height);
382 ASSERT((dsc_cfg->dc_dsc_cfg.version_minor == 1 &&
383 (8 <= dsc_cfg->dc_dsc_cfg.linebuf_depth && dsc_cfg->dc_dsc_cfg.linebuf_depth <= 13)) ||
384 (dsc_cfg->dc_dsc_cfg.version_minor == 2 &&
385 ((8 <= dsc_cfg->dc_dsc_cfg.linebuf_depth && dsc_cfg->dc_dsc_cfg.linebuf_depth <= 15) ||
386 dsc_cfg->dc_dsc_cfg.linebuf_depth == 0)));
387 ASSERT(96 <= dsc_cfg->dc_dsc_cfg.bits_per_pixel && dsc_cfg->dc_dsc_cfg.bits_per_pixel <= 0x3ff); // 6.0 <= bits_per_pixel <= 63.9375
388
389 if (!dsc_cfg->dc_dsc_cfg.num_slices_v || !dsc_cfg->dc_dsc_cfg.num_slices_h ||
390 !(dsc_cfg->dc_dsc_cfg.version_minor == 1 || dsc_cfg->dc_dsc_cfg.version_minor == 2) ||
391 !dsc_cfg->pic_width || !dsc_cfg->pic_height ||
392 !((dsc_cfg->dc_dsc_cfg.version_minor == 1 && // v1.1 line buffer depth range:
393 8 <= dsc_cfg->dc_dsc_cfg.linebuf_depth && dsc_cfg->dc_dsc_cfg.linebuf_depth <= 13) ||
394 (dsc_cfg->dc_dsc_cfg.version_minor == 2 && // v1.2 line buffer depth range:
395 ((8 <= dsc_cfg->dc_dsc_cfg.linebuf_depth && dsc_cfg->dc_dsc_cfg.linebuf_depth <= 15) ||
396 dsc_cfg->dc_dsc_cfg.linebuf_depth == 0))) ||
397 !(96 <= dsc_cfg->dc_dsc_cfg.bits_per_pixel && dsc_cfg->dc_dsc_cfg.bits_per_pixel <= 0x3ff)) {
398 dm_output_to_console("%s: Invalid parameters\n", __func__);
399 return false;
400 }
401
402 dsc_init_reg_values(dsc_reg_vals);
403
404 /* Copy input config */
405 dsc_reg_vals->pixel_format = dsc_dc_pixel_encoding_to_dsc_pixel_format(dsc_cfg->pixel_encoding, dsc_cfg->dc_dsc_cfg.ycbcr422_simple);
406 dsc_reg_vals->num_slices_h = dsc_cfg->dc_dsc_cfg.num_slices_h;
407 dsc_reg_vals->num_slices_v = dsc_cfg->dc_dsc_cfg.num_slices_v;
408 dsc_reg_vals->pps.dsc_version_minor = dsc_cfg->dc_dsc_cfg.version_minor;
409 dsc_reg_vals->pps.pic_width = dsc_cfg->pic_width;
410 dsc_reg_vals->pps.pic_height = dsc_cfg->pic_height;
411 dsc_reg_vals->pps.bits_per_component = dsc_dc_color_depth_to_dsc_bits_per_comp(dsc_cfg->color_depth);
412 dsc_reg_vals->pps.block_pred_enable = dsc_cfg->dc_dsc_cfg.block_pred_enable;
413 dsc_reg_vals->pps.line_buf_depth = dsc_cfg->dc_dsc_cfg.linebuf_depth;
414 dsc_reg_vals->alternate_ich_encoding_en = dsc_reg_vals->pps.dsc_version_minor == 1 ? 0 : 1;
415 dsc_reg_vals->ich_reset_at_eol = (dsc_cfg->is_odm || dsc_reg_vals->num_slices_h > 1) ? 0xF : 0;
416
417 // Need to find the ceiling value for the slice width
418 dsc_reg_vals->pps.slice_width = (dsc_cfg->pic_width + dsc_cfg->dsc_padding + dsc_cfg->dc_dsc_cfg.num_slices_h - 1) / dsc_cfg->dc_dsc_cfg.num_slices_h;
419 // TODO: in addition to validating slice height (pic height must be divisible by slice height),
420 // see what happens when the same condition doesn't apply for slice_width/pic_width.
421 dsc_reg_vals->pps.slice_height = dsc_cfg->pic_height / dsc_cfg->dc_dsc_cfg.num_slices_v;
422
423 ASSERT(dsc_reg_vals->pps.slice_height * dsc_cfg->dc_dsc_cfg.num_slices_v == dsc_cfg->pic_height);
424 if (!(dsc_reg_vals->pps.slice_height * dsc_cfg->dc_dsc_cfg.num_slices_v == dsc_cfg->pic_height)) {
425 dm_output_to_console("%s: pix height %d not divisible by num_slices_v %d\n\n", __func__, dsc_cfg->pic_height, dsc_cfg->dc_dsc_cfg.num_slices_v);
426 return false;
427 }
428
429 dsc_reg_vals->bpp_x32 = dsc_cfg->dc_dsc_cfg.bits_per_pixel << 1;
430 if (dsc_reg_vals->pixel_format == DSC_PIXFMT_NATIVE_YCBCR420 || dsc_reg_vals->pixel_format == DSC_PIXFMT_NATIVE_YCBCR422)
431 dsc_reg_vals->pps.bits_per_pixel = dsc_reg_vals->bpp_x32;
432 else
433 dsc_reg_vals->pps.bits_per_pixel = dsc_reg_vals->bpp_x32 >> 1;
434
435 dsc_reg_vals->pps.convert_rgb = dsc_reg_vals->pixel_format == DSC_PIXFMT_RGB ? 1 : 0;
436 dsc_reg_vals->pps.native_422 = (dsc_reg_vals->pixel_format == DSC_PIXFMT_NATIVE_YCBCR422);
437 dsc_reg_vals->pps.native_420 = (dsc_reg_vals->pixel_format == DSC_PIXFMT_NATIVE_YCBCR420);
438 dsc_reg_vals->pps.simple_422 = (dsc_reg_vals->pixel_format == DSC_PIXFMT_SIMPLE_YCBCR422);
439
440 calc_rc_params(&rc, &dsc_reg_vals->pps);
441
442 if (dsc_cfg->dc_dsc_cfg.rc_params_ovrd)
443 dsc_override_rc_params(&rc, dsc_cfg->dc_dsc_cfg.rc_params_ovrd);
444
445 if (dscc_compute_dsc_parameters(&dsc_reg_vals->pps, &rc, &dsc_params)) {
446 dm_output_to_console("%s: DSC config failed\n", __func__);
447 return false;
448 }
449
450 dsc_update_from_dsc_parameters(dsc_reg_vals, &dsc_params);
451
452 dsc_optc_cfg->bytes_per_pixel = dsc_params.bytes_per_pixel;
453 dsc_optc_cfg->slice_width = dsc_reg_vals->pps.slice_width;
454 dsc_optc_cfg->is_pixel_format_444 = dsc_reg_vals->pixel_format == DSC_PIXFMT_RGB ||
455 dsc_reg_vals->pixel_format == DSC_PIXFMT_YCBCR444 ||
456 dsc_reg_vals->pixel_format == DSC_PIXFMT_SIMPLE_YCBCR422;
457
458 return true;
459 }
460
461
dsc_dc_pixel_encoding_to_dsc_pixel_format(enum dc_pixel_encoding dc_pix_enc,bool is_ycbcr422_simple)462 enum dsc_pixel_format dsc_dc_pixel_encoding_to_dsc_pixel_format(enum dc_pixel_encoding dc_pix_enc, bool is_ycbcr422_simple)
463 {
464 enum dsc_pixel_format dsc_pix_fmt = DSC_PIXFMT_UNKNOWN;
465
466 /* NOTE: We don't support DSC_PIXFMT_SIMPLE_YCBCR422 */
467
468 switch (dc_pix_enc) {
469 case PIXEL_ENCODING_RGB:
470 dsc_pix_fmt = DSC_PIXFMT_RGB;
471 break;
472 case PIXEL_ENCODING_YCBCR422:
473 if (is_ycbcr422_simple)
474 dsc_pix_fmt = DSC_PIXFMT_SIMPLE_YCBCR422;
475 else
476 dsc_pix_fmt = DSC_PIXFMT_NATIVE_YCBCR422;
477 break;
478 case PIXEL_ENCODING_YCBCR444:
479 dsc_pix_fmt = DSC_PIXFMT_YCBCR444;
480 break;
481 case PIXEL_ENCODING_YCBCR420:
482 dsc_pix_fmt = DSC_PIXFMT_NATIVE_YCBCR420;
483 break;
484 default:
485 dsc_pix_fmt = DSC_PIXFMT_UNKNOWN;
486 break;
487 }
488
489 ASSERT(dsc_pix_fmt != DSC_PIXFMT_UNKNOWN);
490 return dsc_pix_fmt;
491 }
492
493
dsc_dc_color_depth_to_dsc_bits_per_comp(enum dc_color_depth dc_color_depth)494 enum dsc_bits_per_comp dsc_dc_color_depth_to_dsc_bits_per_comp(enum dc_color_depth dc_color_depth)
495 {
496 enum dsc_bits_per_comp bpc = DSC_BPC_UNKNOWN;
497
498 switch (dc_color_depth) {
499 case COLOR_DEPTH_888:
500 bpc = DSC_BPC_8;
501 break;
502 case COLOR_DEPTH_101010:
503 bpc = DSC_BPC_10;
504 break;
505 case COLOR_DEPTH_121212:
506 bpc = DSC_BPC_12;
507 break;
508 default:
509 bpc = DSC_BPC_UNKNOWN;
510 break;
511 }
512
513 return bpc;
514 }
515
516
dsc_init_reg_values(struct dsc_reg_values * reg_vals)517 void dsc_init_reg_values(struct dsc_reg_values *reg_vals)
518 {
519 int i;
520
521 memset(reg_vals, 0, sizeof(struct dsc_reg_values));
522
523 /* Non-PPS values */
524 reg_vals->dsc_clock_enable = 1;
525 reg_vals->dsc_clock_gating_disable = 0;
526 reg_vals->underflow_recovery_en = 0;
527 reg_vals->underflow_occurred_int_en = 0;
528 reg_vals->underflow_occurred_status = 0;
529 reg_vals->ich_reset_at_eol = 0;
530 reg_vals->alternate_ich_encoding_en = 0;
531 reg_vals->rc_buffer_model_size = 0;
532 /*reg_vals->disable_ich = 0;*/
533 reg_vals->dsc_dbg_en = 0;
534
535 for (i = 0; i < 4; i++)
536 reg_vals->rc_buffer_model_overflow_int_en[i] = 0;
537
538 /* PPS values */
539 reg_vals->pps.dsc_version_minor = 2;
540 reg_vals->pps.dsc_version_major = 1;
541 reg_vals->pps.line_buf_depth = 9;
542 reg_vals->pps.bits_per_component = 8;
543 reg_vals->pps.block_pred_enable = 1;
544 reg_vals->pps.slice_chunk_size = 0;
545 reg_vals->pps.pic_width = 0;
546 reg_vals->pps.pic_height = 0;
547 reg_vals->pps.slice_width = 0;
548 reg_vals->pps.slice_height = 0;
549 reg_vals->pps.initial_xmit_delay = 170;
550 reg_vals->pps.initial_dec_delay = 0;
551 reg_vals->pps.initial_scale_value = 0;
552 reg_vals->pps.scale_increment_interval = 0;
553 reg_vals->pps.scale_decrement_interval = 0;
554 reg_vals->pps.nfl_bpg_offset = 0;
555 reg_vals->pps.slice_bpg_offset = 0;
556 reg_vals->pps.nsl_bpg_offset = 0;
557 reg_vals->pps.initial_offset = 6144;
558 reg_vals->pps.final_offset = 0;
559 reg_vals->pps.flatness_min_qp = 3;
560 reg_vals->pps.flatness_max_qp = 12;
561 reg_vals->pps.rc_model_size = 8192;
562 reg_vals->pps.rc_edge_factor = 6;
563 reg_vals->pps.rc_quant_incr_limit0 = 11;
564 reg_vals->pps.rc_quant_incr_limit1 = 11;
565 reg_vals->pps.rc_tgt_offset_low = 3;
566 reg_vals->pps.rc_tgt_offset_high = 3;
567 }
568
569 /* Updates dsc_reg_values::reg_vals::xxx fields based on the values from computed params.
570 * This is required because dscc_compute_dsc_parameters returns a modified PPS, which in turn
571 * affects non-PPS register values.
572 */
dsc_update_from_dsc_parameters(struct dsc_reg_values * reg_vals,const struct dsc_parameters * dsc_params)573 void dsc_update_from_dsc_parameters(struct dsc_reg_values *reg_vals, const struct dsc_parameters *dsc_params)
574 {
575 int i;
576
577 reg_vals->pps = dsc_params->pps;
578
579 // pps_computed will have the "expanded" values; need to shift them to make them fit for regs.
580 for (i = 0; i < NUM_BUF_RANGES - 1; i++)
581 reg_vals->pps.rc_buf_thresh[i] = reg_vals->pps.rc_buf_thresh[i] >> 6;
582
583 reg_vals->rc_buffer_model_size = dsc_params->rc_buffer_model_size;
584 }
585
dsc_write_to_registers(struct display_stream_compressor * dsc,const struct dsc_reg_values * reg_vals)586 static void dsc_write_to_registers(struct display_stream_compressor *dsc, const struct dsc_reg_values *reg_vals)
587 {
588 uint32_t temp_int;
589 struct dcn20_dsc *dsc20 = TO_DCN20_DSC(dsc);
590
591 REG_SET(DSC_DEBUG_CONTROL, 0,
592 DSC_DBG_EN, reg_vals->dsc_dbg_en);
593
594 // dsccif registers
595 REG_SET_5(DSCCIF_CONFIG0, 0,
596 INPUT_INTERFACE_UNDERFLOW_RECOVERY_EN, reg_vals->underflow_recovery_en,
597 INPUT_INTERFACE_UNDERFLOW_OCCURRED_INT_EN, reg_vals->underflow_occurred_int_en,
598 INPUT_INTERFACE_UNDERFLOW_OCCURRED_STATUS, reg_vals->underflow_occurred_status,
599 INPUT_PIXEL_FORMAT, reg_vals->pixel_format,
600 DSCCIF_CONFIG0__BITS_PER_COMPONENT, reg_vals->pps.bits_per_component);
601
602 REG_SET_2(DSCCIF_CONFIG1, 0,
603 PIC_WIDTH, reg_vals->pps.pic_width,
604 PIC_HEIGHT, reg_vals->pps.pic_height);
605
606 // dscc registers
607 if (dsc20->dsc_mask->ICH_RESET_AT_END_OF_LINE == 0) {
608 REG_SET_3(DSCC_CONFIG0, 0,
609 NUMBER_OF_SLICES_PER_LINE, reg_vals->num_slices_h - 1,
610 ALTERNATE_ICH_ENCODING_EN, reg_vals->alternate_ich_encoding_en,
611 NUMBER_OF_SLICES_IN_VERTICAL_DIRECTION, reg_vals->num_slices_v - 1);
612 } else {
613 REG_SET_4(DSCC_CONFIG0, 0, ICH_RESET_AT_END_OF_LINE,
614 reg_vals->ich_reset_at_eol, NUMBER_OF_SLICES_PER_LINE,
615 reg_vals->num_slices_h - 1, ALTERNATE_ICH_ENCODING_EN,
616 reg_vals->alternate_ich_encoding_en, NUMBER_OF_SLICES_IN_VERTICAL_DIRECTION,
617 reg_vals->num_slices_v - 1);
618 }
619
620 REG_SET(DSCC_CONFIG1, 0,
621 DSCC_RATE_CONTROL_BUFFER_MODEL_SIZE, reg_vals->rc_buffer_model_size);
622 /*REG_SET_2(DSCC_CONFIG1, 0,
623 DSCC_RATE_CONTROL_BUFFER_MODEL_SIZE, reg_vals->rc_buffer_model_size,
624 DSCC_DISABLE_ICH, reg_vals->disable_ich);*/
625
626 REG_SET_4(DSCC_INTERRUPT_CONTROL_STATUS, 0,
627 DSCC_RATE_CONTROL_BUFFER_MODEL0_OVERFLOW_OCCURRED_INT_EN, reg_vals->rc_buffer_model_overflow_int_en[0],
628 DSCC_RATE_CONTROL_BUFFER_MODEL1_OVERFLOW_OCCURRED_INT_EN, reg_vals->rc_buffer_model_overflow_int_en[1],
629 DSCC_RATE_CONTROL_BUFFER_MODEL2_OVERFLOW_OCCURRED_INT_EN, reg_vals->rc_buffer_model_overflow_int_en[2],
630 DSCC_RATE_CONTROL_BUFFER_MODEL3_OVERFLOW_OCCURRED_INT_EN, reg_vals->rc_buffer_model_overflow_int_en[3]);
631
632 REG_SET_3(DSCC_PPS_CONFIG0, 0,
633 DSC_VERSION_MINOR, reg_vals->pps.dsc_version_minor,
634 LINEBUF_DEPTH, reg_vals->pps.line_buf_depth,
635 DSCC_PPS_CONFIG0__BITS_PER_COMPONENT, reg_vals->pps.bits_per_component);
636
637 if (reg_vals->pixel_format == DSC_PIXFMT_NATIVE_YCBCR420 || reg_vals->pixel_format == DSC_PIXFMT_NATIVE_YCBCR422)
638 temp_int = reg_vals->bpp_x32;
639 else
640 temp_int = reg_vals->bpp_x32 >> 1;
641
642 REG_SET_7(DSCC_PPS_CONFIG1, 0,
643 BITS_PER_PIXEL, temp_int,
644 SIMPLE_422, reg_vals->pixel_format == DSC_PIXFMT_SIMPLE_YCBCR422,
645 CONVERT_RGB, reg_vals->pixel_format == DSC_PIXFMT_RGB,
646 BLOCK_PRED_ENABLE, reg_vals->pps.block_pred_enable,
647 NATIVE_422, reg_vals->pixel_format == DSC_PIXFMT_NATIVE_YCBCR422,
648 NATIVE_420, reg_vals->pixel_format == DSC_PIXFMT_NATIVE_YCBCR420,
649 CHUNK_SIZE, reg_vals->pps.slice_chunk_size);
650
651 REG_SET_2(DSCC_PPS_CONFIG2, 0,
652 PIC_WIDTH, reg_vals->pps.pic_width,
653 PIC_HEIGHT, reg_vals->pps.pic_height);
654
655 REG_SET_2(DSCC_PPS_CONFIG3, 0,
656 SLICE_WIDTH, reg_vals->pps.slice_width,
657 SLICE_HEIGHT, reg_vals->pps.slice_height);
658
659 REG_SET(DSCC_PPS_CONFIG4, 0,
660 INITIAL_XMIT_DELAY, reg_vals->pps.initial_xmit_delay);
661
662 REG_SET_2(DSCC_PPS_CONFIG5, 0,
663 INITIAL_SCALE_VALUE, reg_vals->pps.initial_scale_value,
664 SCALE_INCREMENT_INTERVAL, reg_vals->pps.scale_increment_interval);
665
666 REG_SET_3(DSCC_PPS_CONFIG6, 0,
667 SCALE_DECREMENT_INTERVAL, reg_vals->pps.scale_decrement_interval,
668 FIRST_LINE_BPG_OFFSET, reg_vals->pps.first_line_bpg_offset,
669 SECOND_LINE_BPG_OFFSET, reg_vals->pps.second_line_bpg_offset);
670
671 REG_SET_2(DSCC_PPS_CONFIG7, 0,
672 NFL_BPG_OFFSET, reg_vals->pps.nfl_bpg_offset,
673 SLICE_BPG_OFFSET, reg_vals->pps.slice_bpg_offset);
674
675 REG_SET_2(DSCC_PPS_CONFIG8, 0,
676 NSL_BPG_OFFSET, reg_vals->pps.nsl_bpg_offset,
677 SECOND_LINE_OFFSET_ADJ, reg_vals->pps.second_line_offset_adj);
678
679 REG_SET_2(DSCC_PPS_CONFIG9, 0,
680 INITIAL_OFFSET, reg_vals->pps.initial_offset,
681 FINAL_OFFSET, reg_vals->pps.final_offset);
682
683 REG_SET_3(DSCC_PPS_CONFIG10, 0,
684 FLATNESS_MIN_QP, reg_vals->pps.flatness_min_qp,
685 FLATNESS_MAX_QP, reg_vals->pps.flatness_max_qp,
686 RC_MODEL_SIZE, reg_vals->pps.rc_model_size);
687
688 REG_SET_5(DSCC_PPS_CONFIG11, 0,
689 RC_EDGE_FACTOR, reg_vals->pps.rc_edge_factor,
690 RC_QUANT_INCR_LIMIT0, reg_vals->pps.rc_quant_incr_limit0,
691 RC_QUANT_INCR_LIMIT1, reg_vals->pps.rc_quant_incr_limit1,
692 RC_TGT_OFFSET_LO, reg_vals->pps.rc_tgt_offset_low,
693 RC_TGT_OFFSET_HI, reg_vals->pps.rc_tgt_offset_high);
694
695 REG_SET_4(DSCC_PPS_CONFIG12, 0,
696 RC_BUF_THRESH0, reg_vals->pps.rc_buf_thresh[0],
697 RC_BUF_THRESH1, reg_vals->pps.rc_buf_thresh[1],
698 RC_BUF_THRESH2, reg_vals->pps.rc_buf_thresh[2],
699 RC_BUF_THRESH3, reg_vals->pps.rc_buf_thresh[3]);
700
701 REG_SET_4(DSCC_PPS_CONFIG13, 0,
702 RC_BUF_THRESH4, reg_vals->pps.rc_buf_thresh[4],
703 RC_BUF_THRESH5, reg_vals->pps.rc_buf_thresh[5],
704 RC_BUF_THRESH6, reg_vals->pps.rc_buf_thresh[6],
705 RC_BUF_THRESH7, reg_vals->pps.rc_buf_thresh[7]);
706
707 REG_SET_4(DSCC_PPS_CONFIG14, 0,
708 RC_BUF_THRESH8, reg_vals->pps.rc_buf_thresh[8],
709 RC_BUF_THRESH9, reg_vals->pps.rc_buf_thresh[9],
710 RC_BUF_THRESH10, reg_vals->pps.rc_buf_thresh[10],
711 RC_BUF_THRESH11, reg_vals->pps.rc_buf_thresh[11]);
712
713 REG_SET_5(DSCC_PPS_CONFIG15, 0,
714 RC_BUF_THRESH12, reg_vals->pps.rc_buf_thresh[12],
715 RC_BUF_THRESH13, reg_vals->pps.rc_buf_thresh[13],
716 RANGE_MIN_QP0, reg_vals->pps.rc_range_params[0].range_min_qp,
717 RANGE_MAX_QP0, reg_vals->pps.rc_range_params[0].range_max_qp,
718 RANGE_BPG_OFFSET0, reg_vals->pps.rc_range_params[0].range_bpg_offset);
719
720 REG_SET_6(DSCC_PPS_CONFIG16, 0,
721 RANGE_MIN_QP1, reg_vals->pps.rc_range_params[1].range_min_qp,
722 RANGE_MAX_QP1, reg_vals->pps.rc_range_params[1].range_max_qp,
723 RANGE_BPG_OFFSET1, reg_vals->pps.rc_range_params[1].range_bpg_offset,
724 RANGE_MIN_QP2, reg_vals->pps.rc_range_params[2].range_min_qp,
725 RANGE_MAX_QP2, reg_vals->pps.rc_range_params[2].range_max_qp,
726 RANGE_BPG_OFFSET2, reg_vals->pps.rc_range_params[2].range_bpg_offset);
727
728 REG_SET_6(DSCC_PPS_CONFIG17, 0,
729 RANGE_MIN_QP3, reg_vals->pps.rc_range_params[3].range_min_qp,
730 RANGE_MAX_QP3, reg_vals->pps.rc_range_params[3].range_max_qp,
731 RANGE_BPG_OFFSET3, reg_vals->pps.rc_range_params[3].range_bpg_offset,
732 RANGE_MIN_QP4, reg_vals->pps.rc_range_params[4].range_min_qp,
733 RANGE_MAX_QP4, reg_vals->pps.rc_range_params[4].range_max_qp,
734 RANGE_BPG_OFFSET4, reg_vals->pps.rc_range_params[4].range_bpg_offset);
735
736 REG_SET_6(DSCC_PPS_CONFIG18, 0,
737 RANGE_MIN_QP5, reg_vals->pps.rc_range_params[5].range_min_qp,
738 RANGE_MAX_QP5, reg_vals->pps.rc_range_params[5].range_max_qp,
739 RANGE_BPG_OFFSET5, reg_vals->pps.rc_range_params[5].range_bpg_offset,
740 RANGE_MIN_QP6, reg_vals->pps.rc_range_params[6].range_min_qp,
741 RANGE_MAX_QP6, reg_vals->pps.rc_range_params[6].range_max_qp,
742 RANGE_BPG_OFFSET6, reg_vals->pps.rc_range_params[6].range_bpg_offset);
743
744 REG_SET_6(DSCC_PPS_CONFIG19, 0,
745 RANGE_MIN_QP7, reg_vals->pps.rc_range_params[7].range_min_qp,
746 RANGE_MAX_QP7, reg_vals->pps.rc_range_params[7].range_max_qp,
747 RANGE_BPG_OFFSET7, reg_vals->pps.rc_range_params[7].range_bpg_offset,
748 RANGE_MIN_QP8, reg_vals->pps.rc_range_params[8].range_min_qp,
749 RANGE_MAX_QP8, reg_vals->pps.rc_range_params[8].range_max_qp,
750 RANGE_BPG_OFFSET8, reg_vals->pps.rc_range_params[8].range_bpg_offset);
751
752 REG_SET_6(DSCC_PPS_CONFIG20, 0,
753 RANGE_MIN_QP9, reg_vals->pps.rc_range_params[9].range_min_qp,
754 RANGE_MAX_QP9, reg_vals->pps.rc_range_params[9].range_max_qp,
755 RANGE_BPG_OFFSET9, reg_vals->pps.rc_range_params[9].range_bpg_offset,
756 RANGE_MIN_QP10, reg_vals->pps.rc_range_params[10].range_min_qp,
757 RANGE_MAX_QP10, reg_vals->pps.rc_range_params[10].range_max_qp,
758 RANGE_BPG_OFFSET10, reg_vals->pps.rc_range_params[10].range_bpg_offset);
759
760 REG_SET_6(DSCC_PPS_CONFIG21, 0,
761 RANGE_MIN_QP11, reg_vals->pps.rc_range_params[11].range_min_qp,
762 RANGE_MAX_QP11, reg_vals->pps.rc_range_params[11].range_max_qp,
763 RANGE_BPG_OFFSET11, reg_vals->pps.rc_range_params[11].range_bpg_offset,
764 RANGE_MIN_QP12, reg_vals->pps.rc_range_params[12].range_min_qp,
765 RANGE_MAX_QP12, reg_vals->pps.rc_range_params[12].range_max_qp,
766 RANGE_BPG_OFFSET12, reg_vals->pps.rc_range_params[12].range_bpg_offset);
767
768 REG_SET_6(DSCC_PPS_CONFIG22, 0,
769 RANGE_MIN_QP13, reg_vals->pps.rc_range_params[13].range_min_qp,
770 RANGE_MAX_QP13, reg_vals->pps.rc_range_params[13].range_max_qp,
771 RANGE_BPG_OFFSET13, reg_vals->pps.rc_range_params[13].range_bpg_offset,
772 RANGE_MIN_QP14, reg_vals->pps.rc_range_params[14].range_min_qp,
773 RANGE_MAX_QP14, reg_vals->pps.rc_range_params[14].range_max_qp,
774 RANGE_BPG_OFFSET14, reg_vals->pps.rc_range_params[14].range_bpg_offset);
775
776 }
777