1 /* SPDX-License-Identifier: GPL-2.0-only */ 2 /* 3 * Copyright (c) 2022. Qualcomm Innovation Center, Inc. All rights reserved. 4 * Copyright (c) 2015-2018, 2020 The Linux Foundation. All rights reserved. 5 * Copyright (c) 2023, Linaro Limited 6 */ 7 8 #ifndef _DPU_6_4_SM6350_H 9 #define _DPU_6_4_SM6350_H 10 11 static const struct dpu_caps sm6350_dpu_caps = { 12 .max_mixer_width = DEFAULT_DPU_OUTPUT_LINE_WIDTH, 13 .max_mixer_blendstages = 0x7, 14 .has_src_split = true, 15 .has_dim_layer = true, 16 .has_idle_pc = true, 17 .max_linewidth = DEFAULT_DPU_OUTPUT_LINE_WIDTH, 18 .pixel_ram_size = DEFAULT_PIXEL_RAM_SIZE, 19 }; 20 21 static const struct dpu_mdp_cfg sm6350_mdp = { 22 .name = "top_0", 23 .base = 0x0, .len = 0x494, 24 .clk_ctrls = { 25 [DPU_CLK_CTRL_VIG0] = { .reg_off = 0x2ac, .bit_off = 0 }, 26 [DPU_CLK_CTRL_DMA0] = { .reg_off = 0x2ac, .bit_off = 8 }, 27 [DPU_CLK_CTRL_DMA1] = { .reg_off = 0x2b4, .bit_off = 8 }, 28 [DPU_CLK_CTRL_DMA2] = { .reg_off = 0x2c4, .bit_off = 8 }, 29 [DPU_CLK_CTRL_WB2] = { .reg_off = 0x2bc, .bit_off = 16 }, 30 [DPU_CLK_CTRL_REG_DMA] = { .reg_off = 0x2bc, .bit_off = 20 }, 31 }, 32 }; 33 34 static const struct dpu_ctl_cfg sm6350_ctl[] = { 35 { 36 .name = "ctl_0", .id = CTL_0, 37 .base = 0x1000, .len = 0x1dc, 38 .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 9), 39 }, { 40 .name = "ctl_1", .id = CTL_1, 41 .base = 0x1200, .len = 0x1dc, 42 .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 10), 43 }, { 44 .name = "ctl_2", .id = CTL_2, 45 .base = 0x1400, .len = 0x1dc, 46 .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 11), 47 }, { 48 .name = "ctl_3", .id = CTL_3, 49 .base = 0x1600, .len = 0x1dc, 50 .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 12), 51 }, 52 }; 53 54 static const struct dpu_sspp_cfg sm6350_sspp[] = { 55 { 56 .name = "sspp_0", .id = SSPP_VIG0, 57 .base = 0x4000, .len = 0x1f8, 58 .features = VIG_SDM845_MASK_NO_SDMA, 59 .sblk = &dpu_vig_sblk_qseed3_3_0, 60 .xin_id = 0, 61 .type = SSPP_TYPE_VIG, 62 .clk_ctrl = DPU_CLK_CTRL_VIG0, 63 }, { 64 .name = "sspp_8", .id = SSPP_DMA0, 65 .base = 0x24000, .len = 0x1f8, 66 .features = DMA_SDM845_MASK_NO_SDMA, 67 .sblk = &dpu_dma_sblk, 68 .xin_id = 1, 69 .type = SSPP_TYPE_DMA, 70 .clk_ctrl = DPU_CLK_CTRL_DMA0, 71 }, { 72 .name = "sspp_9", .id = SSPP_DMA1, 73 .base = 0x26000, .len = 0x1f8, 74 .features = DMA_CURSOR_SDM845_MASK_NO_SDMA, 75 .sblk = &dpu_dma_sblk, 76 .xin_id = 5, 77 .type = SSPP_TYPE_DMA, 78 .clk_ctrl = DPU_CLK_CTRL_DMA1, 79 }, { 80 .name = "sspp_10", .id = SSPP_DMA2, 81 .base = 0x28000, .len = 0x1f8, 82 .features = DMA_CURSOR_SDM845_MASK_NO_SDMA, 83 .sblk = &dpu_dma_sblk, 84 .xin_id = 9, 85 .type = SSPP_TYPE_DMA, 86 .clk_ctrl = DPU_CLK_CTRL_DMA2, 87 }, 88 }; 89 90 static const struct dpu_lm_cfg sm6350_lm[] = { 91 { 92 .name = "lm_0", .id = LM_0, 93 .base = 0x44000, .len = 0x320, 94 .features = MIXER_MSM8998_MASK, 95 .sblk = &sc7180_lm_sblk, 96 .lm_pair = LM_1, 97 .pingpong = PINGPONG_0, 98 .dspp = DSPP_0, 99 }, { 100 .name = "lm_1", .id = LM_1, 101 .base = 0x45000, .len = 0x320, 102 .features = MIXER_MSM8998_MASK, 103 .sblk = &sc7180_lm_sblk, 104 .lm_pair = LM_0, 105 .pingpong = PINGPONG_1, 106 .dspp = 0, 107 }, 108 }; 109 110 static const struct dpu_dspp_cfg sm6350_dspp[] = { 111 { 112 .name = "dspp_0", .id = DSPP_0, 113 .base = 0x54000, .len = 0x1800, 114 .sblk = &sdm845_dspp_sblk, 115 }, 116 }; 117 118 static struct dpu_pingpong_cfg sm6350_pp[] = { 119 { 120 .name = "pingpong_0", .id = PINGPONG_0, 121 .base = 0x70000, .len = 0xd4, 122 .sblk = &sdm845_pp_sblk, 123 .merge_3d = 0, 124 .intr_done = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 8), 125 }, { 126 .name = "pingpong_1", .id = PINGPONG_1, 127 .base = 0x70800, .len = 0xd4, 128 .sblk = &sdm845_pp_sblk, 129 .merge_3d = 0, 130 .intr_done = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 9), 131 }, 132 }; 133 134 static const struct dpu_dsc_cfg sm6350_dsc[] = { 135 { 136 .name = "dsc_0", .id = DSC_0, 137 .base = 0x80000, .len = 0x140, 138 }, 139 }; 140 141 static const struct dpu_wb_cfg sm6350_wb[] = { 142 { 143 .name = "wb_2", .id = WB_2, 144 .base = 0x65000, .len = 0x2c8, 145 .features = WB_SDM845_MASK, 146 .format_list = wb2_formats_rgb_yuv, 147 .num_formats = ARRAY_SIZE(wb2_formats_rgb_yuv), 148 .clk_ctrl = DPU_CLK_CTRL_WB2, 149 .xin_id = 6, 150 .vbif_idx = VBIF_RT, 151 .maxlinewidth = 1920, 152 .intr_wb_done = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 4), 153 }, 154 }; 155 156 static const struct dpu_intf_cfg sm6350_intf[] = { 157 { 158 .name = "intf_0", .id = INTF_0, 159 .base = 0x6a000, .len = 0x280, 160 .type = INTF_DP, 161 .controller_id = MSM_DP_CONTROLLER_0, 162 .prog_fetch_lines_worst_case = 35, 163 .intr_underrun = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 24), 164 .intr_vsync = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 25), 165 }, { 166 .name = "intf_1", .id = INTF_1, 167 .base = 0x6a800, .len = 0x2c0, 168 .type = INTF_DSI, 169 .controller_id = MSM_DSI_CONTROLLER_0, 170 .prog_fetch_lines_worst_case = 35, 171 .intr_underrun = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 26), 172 .intr_vsync = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 27), 173 .intr_tear_rd_ptr = DPU_IRQ_IDX(MDP_INTF1_TEAR_INTR, 2), 174 }, 175 }; 176 177 static const struct dpu_perf_cfg sm6350_perf_data = { 178 .max_bw_low = 4200000, 179 .max_bw_high = 5100000, 180 .min_core_ib = 2500000, 181 .min_llcc_ib = 0, 182 .min_dram_ib = 1600000, 183 .min_prefill_lines = 35, 184 /* TODO: confirm danger_lut_tbl */ 185 .danger_lut_tbl = {0xffff, 0xffff, 0x0}, 186 .safe_lut_tbl = {0xff00, 0xff00, 0xffff}, 187 .qos_lut_tbl = { 188 {.nentry = ARRAY_SIZE(sm6350_qos_linear_macrotile), 189 .entries = sm6350_qos_linear_macrotile 190 }, 191 {.nentry = ARRAY_SIZE(sm6350_qos_linear_macrotile), 192 .entries = sm6350_qos_linear_macrotile 193 }, 194 {.nentry = ARRAY_SIZE(sc7180_qos_nrt), 195 .entries = sc7180_qos_nrt 196 }, 197 }, 198 .cdp_cfg = { 199 {.rd_enable = 1, .wr_enable = 1}, 200 {.rd_enable = 1, .wr_enable = 0} 201 }, 202 .clk_inefficiency_factor = 105, 203 .bw_inefficiency_factor = 120, 204 }; 205 206 static const struct dpu_mdss_version sm6350_mdss_ver = { 207 .core_major_ver = 6, 208 .core_minor_ver = 4, 209 }; 210 211 const struct dpu_mdss_cfg dpu_sm6350_cfg = { 212 .mdss_ver = &sm6350_mdss_ver, 213 .caps = &sm6350_dpu_caps, 214 .mdp = &sm6350_mdp, 215 .cdm = &dpu_cdm_5_x, 216 .ctl_count = ARRAY_SIZE(sm6350_ctl), 217 .ctl = sm6350_ctl, 218 .sspp_count = ARRAY_SIZE(sm6350_sspp), 219 .sspp = sm6350_sspp, 220 .mixer_count = ARRAY_SIZE(sm6350_lm), 221 .mixer = sm6350_lm, 222 .dspp_count = ARRAY_SIZE(sm6350_dspp), 223 .dspp = sm6350_dspp, 224 .dsc_count = ARRAY_SIZE(sm6350_dsc), 225 .dsc = sm6350_dsc, 226 .pingpong_count = ARRAY_SIZE(sm6350_pp), 227 .pingpong = sm6350_pp, 228 .wb_count = ARRAY_SIZE(sm6350_wb), 229 .wb = sm6350_wb, 230 .intf_count = ARRAY_SIZE(sm6350_intf), 231 .intf = sm6350_intf, 232 .vbif_count = ARRAY_SIZE(sdm845_vbif), 233 .vbif = sdm845_vbif, 234 .perf = &sm6350_perf_data, 235 }; 236 237 #endif 238