1 /* SPDX-License-Identifier: GPL-2.0-only */ 2 /* 3 * Copyright (c) 2023 Marijn Suijten <marijn.suijten@somainline.org>. All rights reserved. 4 * Copyright (c) 2022. Qualcomm Innovation Center, Inc. All rights reserved. 5 * Copyright (c) 2015-2018, 2020 The Linux Foundation. All rights reserved. 6 */ 7 8 #ifndef _DPU_5_4_SM6125_H 9 #define _DPU_5_4_SM6125_H 10 11 static const struct dpu_caps sm6125_dpu_caps = { 12 .max_mixer_width = DEFAULT_DPU_OUTPUT_LINE_WIDTH, 13 .max_mixer_blendstages = 0x6, 14 .has_dim_layer = true, 15 .has_idle_pc = true, 16 .max_linewidth = 2160, 17 .pixel_ram_size = DEFAULT_PIXEL_RAM_SIZE, 18 .max_hdeci_exp = MAX_HORZ_DECIMATION, 19 .max_vdeci_exp = MAX_VERT_DECIMATION, 20 }; 21 22 static const struct dpu_mdp_cfg sm6125_mdp = { 23 .name = "top_0", 24 .base = 0x0, .len = 0x45c, 25 .clk_ctrls = { 26 [DPU_CLK_CTRL_VIG0] = { .reg_off = 0x2ac, .bit_off = 0 }, 27 [DPU_CLK_CTRL_DMA0] = { .reg_off = 0x2ac, .bit_off = 8 }, 28 [DPU_CLK_CTRL_DMA1] = { .reg_off = 0x2b4, .bit_off = 8 }, 29 [DPU_CLK_CTRL_WB2] = { .reg_off = 0x2bc, .bit_off = 16 }, 30 }, 31 }; 32 33 static const struct dpu_ctl_cfg sm6125_ctl[] = { 34 { 35 .name = "ctl_0", .id = CTL_0, 36 .base = 0x1000, .len = 0x1e0, 37 .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 9), 38 }, { 39 .name = "ctl_1", .id = CTL_1, 40 .base = 0x1200, .len = 0x1e0, 41 .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 10), 42 }, { 43 .name = "ctl_2", .id = CTL_2, 44 .base = 0x1400, .len = 0x1e0, 45 .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 11), 46 }, { 47 .name = "ctl_3", .id = CTL_3, 48 .base = 0x1600, .len = 0x1e0, 49 .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 12), 50 }, { 51 .name = "ctl_4", .id = CTL_4, 52 .base = 0x1800, .len = 0x1e0, 53 .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 13), 54 }, { 55 .name = "ctl_5", .id = CTL_5, 56 .base = 0x1a00, .len = 0x1e0, 57 .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 23), 58 }, 59 }; 60 61 static const struct dpu_sspp_cfg sm6125_sspp[] = { 62 { 63 .name = "sspp_0", .id = SSPP_VIG0, 64 .base = 0x4000, .len = 0x1f0, 65 .features = VIG_SDM845_MASK_NO_SDMA, 66 .sblk = &dpu_vig_sblk_qseed3_2_4, 67 .xin_id = 0, 68 .type = SSPP_TYPE_VIG, 69 .clk_ctrl = DPU_CLK_CTRL_VIG0, 70 }, { 71 .name = "sspp_8", .id = SSPP_DMA0, 72 .base = 0x24000, .len = 0x1f0, 73 .features = DMA_SDM845_MASK_NO_SDMA, 74 .sblk = &dpu_dma_sblk, 75 .xin_id = 1, 76 .type = SSPP_TYPE_DMA, 77 .clk_ctrl = DPU_CLK_CTRL_DMA0, 78 }, { 79 .name = "sspp_9", .id = SSPP_DMA1, 80 .base = 0x26000, .len = 0x1f0, 81 .features = DMA_SDM845_MASK_NO_SDMA, 82 .sblk = &dpu_dma_sblk, 83 .xin_id = 5, 84 .type = SSPP_TYPE_DMA, 85 .clk_ctrl = DPU_CLK_CTRL_DMA1, 86 }, 87 }; 88 89 static const struct dpu_lm_cfg sm6125_lm[] = { 90 { 91 .name = "lm_0", .id = LM_0, 92 .base = 0x44000, .len = 0x320, 93 .sblk = &sdm845_lm_sblk, 94 .pingpong = PINGPONG_0, 95 .dspp = DSPP_0, 96 .lm_pair = LM_1, 97 }, { 98 .name = "lm_1", .id = LM_1, 99 .base = 0x45000, .len = 0x320, 100 .sblk = &sdm845_lm_sblk, 101 .pingpong = PINGPONG_1, 102 .dspp = 0, 103 .lm_pair = LM_0, 104 }, 105 }; 106 107 static const struct dpu_dspp_cfg sm6125_dspp[] = { 108 { 109 .name = "dspp_0", .id = DSPP_0, 110 .base = 0x54000, .len = 0x1800, 111 .sblk = &sdm845_dspp_sblk, 112 }, 113 }; 114 115 static const struct dpu_pingpong_cfg sm6125_pp[] = { 116 { 117 .name = "pingpong_0", .id = PINGPONG_0, 118 .base = 0x70000, .len = 0xd4, 119 .merge_3d = 0, 120 .sblk = &sdm845_pp_sblk, 121 .intr_done = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 8), 122 }, { 123 .name = "pingpong_1", .id = PINGPONG_1, 124 .base = 0x70800, .len = 0xd4, 125 .merge_3d = 0, 126 .sblk = &sdm845_pp_sblk, 127 .intr_done = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 9), 128 }, 129 }; 130 131 static const struct dpu_wb_cfg sm6125_wb[] = { 132 { 133 .name = "wb_2", .id = WB_2, 134 .base = 0x65000, .len = 0x2c8, 135 .features = WB_SDM845_MASK, 136 .format_list = wb2_formats_rgb_yuv, 137 .num_formats = ARRAY_SIZE(wb2_formats_rgb_yuv), 138 .clk_ctrl = DPU_CLK_CTRL_WB2, 139 .xin_id = 6, 140 .vbif_idx = VBIF_RT, 141 .maxlinewidth = 2160, 142 .intr_wb_done = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 4), 143 }, 144 }; 145 146 static const struct dpu_intf_cfg sm6125_intf[] = { 147 { 148 .name = "intf_0", .id = INTF_0, 149 .base = 0x6a000, .len = 0x280, 150 .type = INTF_DP, 151 .controller_id = MSM_DP_CONTROLLER_0, 152 .prog_fetch_lines_worst_case = 24, 153 .intr_underrun = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 24), 154 .intr_vsync = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 25), 155 }, { 156 .name = "intf_1", .id = INTF_1, 157 .base = 0x6a800, .len = 0x2c0, 158 .type = INTF_DSI, 159 .controller_id = 0, 160 .prog_fetch_lines_worst_case = 24, 161 .intr_underrun = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 26), 162 .intr_vsync = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 27), 163 .intr_tear_rd_ptr = DPU_IRQ_IDX(MDP_INTF1_TEAR_INTR, 2), 164 }, 165 }; 166 167 static const struct dpu_perf_cfg sm6125_perf_data = { 168 .max_bw_low = 4100000, 169 .max_bw_high = 4100000, 170 .min_core_ib = 2400000, 171 .min_llcc_ib = 0, /* No LLCC on this SoC */ 172 .min_dram_ib = 800000, 173 .min_prefill_lines = 24, 174 .danger_lut_tbl = {0xf, 0xffff, 0x0}, 175 .safe_lut_tbl = {0xfff8, 0xf000, 0xffff}, 176 .qos_lut_tbl = { 177 {.nentry = ARRAY_SIZE(sm8150_qos_linear), 178 .entries = sm8150_qos_linear 179 }, 180 {.nentry = ARRAY_SIZE(sc7180_qos_macrotile), 181 .entries = sc7180_qos_macrotile 182 }, 183 {.nentry = ARRAY_SIZE(sc7180_qos_nrt), 184 .entries = sc7180_qos_nrt 185 }, 186 /* TODO: macrotile-qseed is different from macrotile */ 187 }, 188 .cdp_cfg = { 189 {.rd_enable = 1, .wr_enable = 1}, 190 {.rd_enable = 1, .wr_enable = 0} 191 }, 192 .clk_inefficiency_factor = 105, 193 .bw_inefficiency_factor = 120, 194 }; 195 196 static const struct dpu_mdss_version sm6125_mdss_ver = { 197 .core_major_ver = 5, 198 .core_minor_ver = 4, 199 }; 200 201 const struct dpu_mdss_cfg dpu_sm6125_cfg = { 202 .mdss_ver = &sm6125_mdss_ver, 203 .caps = &sm6125_dpu_caps, 204 .mdp = &sm6125_mdp, 205 .cdm = &dpu_cdm_5_x, 206 .ctl_count = ARRAY_SIZE(sm6125_ctl), 207 .ctl = sm6125_ctl, 208 .sspp_count = ARRAY_SIZE(sm6125_sspp), 209 .sspp = sm6125_sspp, 210 .mixer_count = ARRAY_SIZE(sm6125_lm), 211 .mixer = sm6125_lm, 212 .dspp_count = ARRAY_SIZE(sm6125_dspp), 213 .dspp = sm6125_dspp, 214 .pingpong_count = ARRAY_SIZE(sm6125_pp), 215 .pingpong = sm6125_pp, 216 .wb_count = ARRAY_SIZE(sm6125_wb), 217 .wb = sm6125_wb, 218 .intf_count = ARRAY_SIZE(sm6125_intf), 219 .intf = sm6125_intf, 220 .vbif_count = ARRAY_SIZE(sdm845_vbif), 221 .vbif = sdm845_vbif, 222 .perf = &sm6125_perf_data, 223 }; 224 225 #endif 226