1 /*
2 * SPDX-License-Identifier: GPL-2.0
3 * Copyright (c) 2018, The Linux Foundation
4 */
5
6 #include <linux/irq.h>
7 #include <linux/irqchip.h>
8 #include <linux/irqdesc.h>
9 #include <linux/irqchip/chained_irq.h>
10 #include "dpu_kms.h"
11
12 #define to_dpu_mdss(x) container_of(x, struct dpu_mdss, base)
13
14 #define HW_REV 0x0
15 #define HW_INTR_STATUS 0x0010
16
17 #define UBWC_STATIC 0x144
18 #define UBWC_CTRL_2 0x150
19 #define UBWC_PREDICTION_MODE 0x154
20
21 /* Max BW defined in KBps */
22 #define MAX_BW 6800000
23
24 struct dpu_irq_controller {
25 unsigned long enabled_mask;
26 struct irq_domain *domain;
27 };
28
29 struct dpu_mdss {
30 struct msm_mdss base;
31 void __iomem *mmio;
32 struct dss_module_power mp;
33 struct dpu_irq_controller irq_controller;
34 struct icc_path *path[2];
35 u32 num_paths;
36 };
37
dpu_mdss_parse_data_bus_icc_path(struct drm_device * dev,struct dpu_mdss * dpu_mdss)38 static int dpu_mdss_parse_data_bus_icc_path(struct drm_device *dev,
39 struct dpu_mdss *dpu_mdss)
40 {
41 struct icc_path *path0 = of_icc_get(dev->dev, "mdp0-mem");
42 struct icc_path *path1 = of_icc_get(dev->dev, "mdp1-mem");
43
44 if (IS_ERR_OR_NULL(path0))
45 return PTR_ERR_OR_ZERO(path0);
46
47 dpu_mdss->path[0] = path0;
48 dpu_mdss->num_paths = 1;
49
50 if (!IS_ERR_OR_NULL(path1)) {
51 dpu_mdss->path[1] = path1;
52 dpu_mdss->num_paths++;
53 }
54
55 return 0;
56 }
57
dpu_mdss_icc_request_bw(struct msm_mdss * mdss)58 static void dpu_mdss_icc_request_bw(struct msm_mdss *mdss)
59 {
60 struct dpu_mdss *dpu_mdss = to_dpu_mdss(mdss);
61 int i;
62 u64 avg_bw = dpu_mdss->num_paths ? MAX_BW / dpu_mdss->num_paths : 0;
63
64 for (i = 0; i < dpu_mdss->num_paths; i++)
65 icc_set_bw(dpu_mdss->path[i], avg_bw, kBps_to_icc(MAX_BW));
66 }
67
dpu_mdss_irq(struct irq_desc * desc)68 static void dpu_mdss_irq(struct irq_desc *desc)
69 {
70 struct dpu_mdss *dpu_mdss = irq_desc_get_handler_data(desc);
71 struct irq_chip *chip = irq_desc_get_chip(desc);
72 u32 interrupts;
73
74 chained_irq_enter(chip, desc);
75
76 interrupts = readl_relaxed(dpu_mdss->mmio + HW_INTR_STATUS);
77
78 while (interrupts) {
79 irq_hw_number_t hwirq = fls(interrupts) - 1;
80 unsigned int mapping;
81 int rc;
82
83 mapping = irq_find_mapping(dpu_mdss->irq_controller.domain,
84 hwirq);
85 if (mapping == 0) {
86 DRM_ERROR("couldn't find irq mapping for %lu\n", hwirq);
87 break;
88 }
89
90 rc = generic_handle_irq(mapping);
91 if (rc < 0) {
92 DRM_ERROR("handle irq fail: irq=%lu mapping=%u rc=%d\n",
93 hwirq, mapping, rc);
94 break;
95 }
96
97 interrupts &= ~(1 << hwirq);
98 }
99
100 chained_irq_exit(chip, desc);
101 }
102
dpu_mdss_irq_mask(struct irq_data * irqd)103 static void dpu_mdss_irq_mask(struct irq_data *irqd)
104 {
105 struct dpu_mdss *dpu_mdss = irq_data_get_irq_chip_data(irqd);
106
107 /* memory barrier */
108 smp_mb__before_atomic();
109 clear_bit(irqd->hwirq, &dpu_mdss->irq_controller.enabled_mask);
110 /* memory barrier */
111 smp_mb__after_atomic();
112 }
113
dpu_mdss_irq_unmask(struct irq_data * irqd)114 static void dpu_mdss_irq_unmask(struct irq_data *irqd)
115 {
116 struct dpu_mdss *dpu_mdss = irq_data_get_irq_chip_data(irqd);
117
118 /* memory barrier */
119 smp_mb__before_atomic();
120 set_bit(irqd->hwirq, &dpu_mdss->irq_controller.enabled_mask);
121 /* memory barrier */
122 smp_mb__after_atomic();
123 }
124
125 static struct irq_chip dpu_mdss_irq_chip = {
126 .name = "dpu_mdss",
127 .irq_mask = dpu_mdss_irq_mask,
128 .irq_unmask = dpu_mdss_irq_unmask,
129 };
130
131 static struct lock_class_key dpu_mdss_lock_key, dpu_mdss_request_key;
132
dpu_mdss_irqdomain_map(struct irq_domain * domain,unsigned int irq,irq_hw_number_t hwirq)133 static int dpu_mdss_irqdomain_map(struct irq_domain *domain,
134 unsigned int irq, irq_hw_number_t hwirq)
135 {
136 struct dpu_mdss *dpu_mdss = domain->host_data;
137
138 irq_set_lockdep_class(irq, &dpu_mdss_lock_key, &dpu_mdss_request_key);
139 irq_set_chip_and_handler(irq, &dpu_mdss_irq_chip, handle_level_irq);
140 return irq_set_chip_data(irq, dpu_mdss);
141 }
142
143 static const struct irq_domain_ops dpu_mdss_irqdomain_ops = {
144 .map = dpu_mdss_irqdomain_map,
145 .xlate = irq_domain_xlate_onecell,
146 };
147
_dpu_mdss_irq_domain_add(struct dpu_mdss * dpu_mdss)148 static int _dpu_mdss_irq_domain_add(struct dpu_mdss *dpu_mdss)
149 {
150 struct device *dev;
151 struct irq_domain *domain;
152
153 dev = dpu_mdss->base.dev->dev;
154
155 domain = irq_domain_add_linear(dev->of_node, 32,
156 &dpu_mdss_irqdomain_ops, dpu_mdss);
157 if (!domain) {
158 DPU_ERROR("failed to add irq_domain\n");
159 return -EINVAL;
160 }
161
162 dpu_mdss->irq_controller.enabled_mask = 0;
163 dpu_mdss->irq_controller.domain = domain;
164
165 return 0;
166 }
167
_dpu_mdss_irq_domain_fini(struct dpu_mdss * dpu_mdss)168 static void _dpu_mdss_irq_domain_fini(struct dpu_mdss *dpu_mdss)
169 {
170 if (dpu_mdss->irq_controller.domain) {
171 irq_domain_remove(dpu_mdss->irq_controller.domain);
172 dpu_mdss->irq_controller.domain = NULL;
173 }
174 }
dpu_mdss_enable(struct msm_mdss * mdss)175 static int dpu_mdss_enable(struct msm_mdss *mdss)
176 {
177 struct dpu_mdss *dpu_mdss = to_dpu_mdss(mdss);
178 struct dss_module_power *mp = &dpu_mdss->mp;
179 int ret;
180
181 dpu_mdss_icc_request_bw(mdss);
182
183 ret = msm_dss_enable_clk(mp->clk_config, mp->num_clk, true);
184 if (ret) {
185 DPU_ERROR("clock enable failed, ret:%d\n", ret);
186 return ret;
187 }
188
189 /*
190 * ubwc config is part of the "mdss" region which is not accessible
191 * from the rest of the driver. hardcode known configurations here
192 */
193 switch (readl_relaxed(dpu_mdss->mmio + HW_REV)) {
194 case DPU_HW_VER_500:
195 case DPU_HW_VER_501:
196 writel_relaxed(0x420, dpu_mdss->mmio + UBWC_STATIC);
197 break;
198 case DPU_HW_VER_600:
199 /* TODO: 0x102e for LP_DDR4 */
200 writel_relaxed(0x103e, dpu_mdss->mmio + UBWC_STATIC);
201 writel_relaxed(2, dpu_mdss->mmio + UBWC_CTRL_2);
202 writel_relaxed(1, dpu_mdss->mmio + UBWC_PREDICTION_MODE);
203 break;
204 case DPU_HW_VER_620:
205 writel_relaxed(0x1e, dpu_mdss->mmio + UBWC_STATIC);
206 break;
207 }
208
209 return ret;
210 }
211
dpu_mdss_disable(struct msm_mdss * mdss)212 static int dpu_mdss_disable(struct msm_mdss *mdss)
213 {
214 struct dpu_mdss *dpu_mdss = to_dpu_mdss(mdss);
215 struct dss_module_power *mp = &dpu_mdss->mp;
216 int ret, i;
217
218 ret = msm_dss_enable_clk(mp->clk_config, mp->num_clk, false);
219 if (ret)
220 DPU_ERROR("clock disable failed, ret:%d\n", ret);
221
222 for (i = 0; i < dpu_mdss->num_paths; i++)
223 icc_set_bw(dpu_mdss->path[i], 0, 0);
224
225 return ret;
226 }
227
dpu_mdss_destroy(struct drm_device * dev)228 static void dpu_mdss_destroy(struct drm_device *dev)
229 {
230 struct platform_device *pdev = to_platform_device(dev->dev);
231 struct msm_drm_private *priv = dev->dev_private;
232 struct dpu_mdss *dpu_mdss = to_dpu_mdss(priv->mdss);
233 struct dss_module_power *mp = &dpu_mdss->mp;
234 int irq;
235 int i;
236
237 pm_runtime_suspend(dev->dev);
238 pm_runtime_disable(dev->dev);
239 _dpu_mdss_irq_domain_fini(dpu_mdss);
240 irq = platform_get_irq(pdev, 0);
241 irq_set_chained_handler_and_data(irq, NULL, NULL);
242 msm_dss_put_clk(mp->clk_config, mp->num_clk);
243 devm_kfree(&pdev->dev, mp->clk_config);
244
245 for (i = 0; i < dpu_mdss->num_paths; i++)
246 icc_put(dpu_mdss->path[i]);
247
248 if (dpu_mdss->mmio)
249 devm_iounmap(&pdev->dev, dpu_mdss->mmio);
250 dpu_mdss->mmio = NULL;
251 priv->mdss = NULL;
252 }
253
254 static const struct msm_mdss_funcs mdss_funcs = {
255 .enable = dpu_mdss_enable,
256 .disable = dpu_mdss_disable,
257 .destroy = dpu_mdss_destroy,
258 };
259
dpu_mdss_init(struct drm_device * dev)260 int dpu_mdss_init(struct drm_device *dev)
261 {
262 struct platform_device *pdev = to_platform_device(dev->dev);
263 struct msm_drm_private *priv = dev->dev_private;
264 struct dpu_mdss *dpu_mdss;
265 struct dss_module_power *mp;
266 int ret = 0;
267 int irq;
268
269 dpu_mdss = devm_kzalloc(dev->dev, sizeof(*dpu_mdss), GFP_KERNEL);
270 if (!dpu_mdss)
271 return -ENOMEM;
272
273 dpu_mdss->mmio = msm_ioremap(pdev, "mdss", "mdss");
274 if (IS_ERR(dpu_mdss->mmio))
275 return PTR_ERR(dpu_mdss->mmio);
276
277 DRM_DEBUG("mapped mdss address space @%pK\n", dpu_mdss->mmio);
278
279 if (!of_device_is_compatible(dev->dev->of_node, "qcom,sc7180-mdss")) {
280 ret = dpu_mdss_parse_data_bus_icc_path(dev, dpu_mdss);
281 if (ret)
282 return ret;
283 }
284
285 mp = &dpu_mdss->mp;
286 ret = msm_dss_parse_clock(pdev, mp);
287 if (ret) {
288 DPU_ERROR("failed to parse clocks, ret=%d\n", ret);
289 goto clk_parse_err;
290 }
291
292 dpu_mdss->base.dev = dev;
293 dpu_mdss->base.funcs = &mdss_funcs;
294
295 ret = _dpu_mdss_irq_domain_add(dpu_mdss);
296 if (ret)
297 goto irq_domain_error;
298
299 irq = platform_get_irq(pdev, 0);
300 if (irq < 0)
301 goto irq_error;
302
303 irq_set_chained_handler_and_data(irq, dpu_mdss_irq,
304 dpu_mdss);
305
306 priv->mdss = &dpu_mdss->base;
307
308 pm_runtime_enable(dev->dev);
309
310 dpu_mdss_icc_request_bw(priv->mdss);
311
312 return ret;
313
314 irq_error:
315 _dpu_mdss_irq_domain_fini(dpu_mdss);
316 irq_domain_error:
317 msm_dss_put_clk(mp->clk_config, mp->num_clk);
318 clk_parse_err:
319 devm_kfree(&pdev->dev, mp->clk_config);
320 if (dpu_mdss->mmio)
321 devm_iounmap(&pdev->dev, dpu_mdss->mmio);
322 dpu_mdss->mmio = NULL;
323 return ret;
324 }
325