1 // SPDX-License-Identifier: GPL-2.0-only
2 /*
3 * Copyright (c) 2022-2024 Qualcomm Innovation Center, Inc. All rights reserved.
4 */
5
6 #define pr_fmt(fmt) "[drm:%s:%d] " fmt, __func__, __LINE__
7
8 #include <linux/debugfs.h>
9
10 #include <drm/drm_framebuffer.h>
11 #include <drm/drm_managed.h>
12
13 #include "dpu_encoder_phys.h"
14 #include "dpu_formats.h"
15 #include "dpu_hw_top.h"
16 #include "dpu_hw_wb.h"
17 #include "dpu_hw_lm.h"
18 #include "dpu_hw_merge3d.h"
19 #include "dpu_hw_interrupts.h"
20 #include "dpu_core_irq.h"
21 #include "dpu_vbif.h"
22 #include "dpu_crtc.h"
23 #include "disp/msm_disp_snapshot.h"
24
25 #define to_dpu_encoder_phys_wb(x) \
26 container_of(x, struct dpu_encoder_phys_wb, base)
27
28 /**
29 * dpu_encoder_phys_wb_is_master - report wb always as master encoder
30 * @phys_enc: Pointer to physical encoder
31 */
dpu_encoder_phys_wb_is_master(struct dpu_encoder_phys * phys_enc)32 static bool dpu_encoder_phys_wb_is_master(struct dpu_encoder_phys *phys_enc)
33 {
34 /* there is only one physical enc for dpu_writeback */
35 return true;
36 }
37
_dpu_encoder_phys_wb_clk_force_ctrl(struct dpu_hw_wb * wb,struct dpu_hw_mdp * mdp,bool enable,bool * forced_on)38 static bool _dpu_encoder_phys_wb_clk_force_ctrl(struct dpu_hw_wb *wb,
39 struct dpu_hw_mdp *mdp,
40 bool enable, bool *forced_on)
41 {
42 if (wb->ops.setup_clk_force_ctrl) {
43 *forced_on = wb->ops.setup_clk_force_ctrl(wb, enable);
44 return true;
45 }
46
47 if (mdp->ops.setup_clk_force_ctrl) {
48 *forced_on = mdp->ops.setup_clk_force_ctrl(mdp, wb->caps->clk_ctrl, enable);
49 return true;
50 }
51
52 return false;
53 }
54
55 /**
56 * dpu_encoder_phys_wb_set_ot_limit - set OT limit for writeback interface
57 * @phys_enc: Pointer to physical encoder
58 */
dpu_encoder_phys_wb_set_ot_limit(struct dpu_encoder_phys * phys_enc)59 static void dpu_encoder_phys_wb_set_ot_limit(
60 struct dpu_encoder_phys *phys_enc)
61 {
62 struct dpu_hw_wb *hw_wb = phys_enc->hw_wb;
63 struct dpu_vbif_set_ot_params ot_params;
64 bool forced_on = false;
65
66 memset(&ot_params, 0, sizeof(ot_params));
67 ot_params.xin_id = hw_wb->caps->xin_id;
68 ot_params.num = hw_wb->idx - WB_0;
69 ot_params.width = phys_enc->cached_mode.hdisplay;
70 ot_params.height = phys_enc->cached_mode.vdisplay;
71 ot_params.is_wfd = !dpu_encoder_helper_get_cwb_mask(phys_enc);
72 ot_params.frame_rate = drm_mode_vrefresh(&phys_enc->cached_mode);
73 ot_params.vbif_idx = hw_wb->caps->vbif_idx;
74 ot_params.rd = false;
75
76 if (!_dpu_encoder_phys_wb_clk_force_ctrl(hw_wb, phys_enc->dpu_kms->hw_mdp,
77 true, &forced_on))
78 return;
79
80 dpu_vbif_set_ot_limit(phys_enc->dpu_kms, &ot_params);
81
82 if (forced_on)
83 _dpu_encoder_phys_wb_clk_force_ctrl(hw_wb, phys_enc->dpu_kms->hw_mdp,
84 false, &forced_on);
85 }
86
87 /**
88 * dpu_encoder_phys_wb_set_qos_remap - set QoS remapper for writeback
89 * @phys_enc: Pointer to physical encoder
90 */
dpu_encoder_phys_wb_set_qos_remap(struct dpu_encoder_phys * phys_enc)91 static void dpu_encoder_phys_wb_set_qos_remap(
92 struct dpu_encoder_phys *phys_enc)
93 {
94 struct dpu_hw_wb *hw_wb;
95 struct dpu_vbif_set_qos_params qos_params;
96 bool forced_on = false;
97
98 if (!phys_enc || !phys_enc->parent || !phys_enc->parent->crtc) {
99 DPU_ERROR("invalid arguments\n");
100 return;
101 }
102
103 if (!phys_enc->hw_wb || !phys_enc->hw_wb->caps) {
104 DPU_ERROR("invalid writeback hardware\n");
105 return;
106 }
107
108 hw_wb = phys_enc->hw_wb;
109
110 memset(&qos_params, 0, sizeof(qos_params));
111 qos_params.vbif_idx = hw_wb->caps->vbif_idx;
112 qos_params.xin_id = hw_wb->caps->xin_id;
113 qos_params.num = hw_wb->idx - WB_0;
114 qos_params.is_rt = dpu_encoder_helper_get_cwb_mask(phys_enc);
115
116 DPU_DEBUG("[qos_remap] wb:%d vbif:%d xin:%d is_rt:%d\n",
117 qos_params.num,
118 qos_params.vbif_idx,
119 qos_params.xin_id, qos_params.is_rt);
120
121 if (!_dpu_encoder_phys_wb_clk_force_ctrl(hw_wb, phys_enc->dpu_kms->hw_mdp,
122 true, &forced_on))
123 return;
124
125 dpu_vbif_set_qos_remap(phys_enc->dpu_kms, &qos_params);
126
127 if (forced_on)
128 _dpu_encoder_phys_wb_clk_force_ctrl(hw_wb, phys_enc->dpu_kms->hw_mdp,
129 false, &forced_on);
130 }
131
132 /**
133 * dpu_encoder_phys_wb_set_qos - set QoS/danger/safe LUTs for writeback
134 * @phys_enc: Pointer to physical encoder
135 */
dpu_encoder_phys_wb_set_qos(struct dpu_encoder_phys * phys_enc)136 static void dpu_encoder_phys_wb_set_qos(struct dpu_encoder_phys *phys_enc)
137 {
138 struct dpu_hw_wb *hw_wb;
139 struct dpu_hw_qos_cfg qos_cfg;
140 const struct dpu_mdss_cfg *catalog;
141 const struct dpu_qos_lut_tbl *qos_lut_tb;
142
143 if (!phys_enc || !phys_enc->dpu_kms || !phys_enc->dpu_kms->catalog) {
144 DPU_ERROR("invalid parameter(s)\n");
145 return;
146 }
147
148 catalog = phys_enc->dpu_kms->catalog;
149
150 hw_wb = phys_enc->hw_wb;
151
152 memset(&qos_cfg, 0, sizeof(struct dpu_hw_qos_cfg));
153 qos_cfg.danger_safe_en = true;
154 qos_cfg.danger_lut =
155 catalog->perf->danger_lut_tbl[DPU_QOS_LUT_USAGE_NRT];
156
157 qos_cfg.safe_lut = catalog->perf->safe_lut_tbl[DPU_QOS_LUT_USAGE_NRT];
158
159 qos_lut_tb = &catalog->perf->qos_lut_tbl[DPU_QOS_LUT_USAGE_NRT];
160 qos_cfg.creq_lut = _dpu_hw_get_qos_lut(qos_lut_tb, 0);
161
162 if (hw_wb->ops.setup_qos_lut)
163 hw_wb->ops.setup_qos_lut(hw_wb, &qos_cfg);
164 }
165
166 /**
167 * dpu_encoder_phys_wb_setup_fb - setup output framebuffer
168 * @phys_enc: Pointer to physical encoder
169 * @format: Format of the framebuffer
170 */
dpu_encoder_phys_wb_setup_fb(struct dpu_encoder_phys * phys_enc,const struct msm_format * format)171 static void dpu_encoder_phys_wb_setup_fb(struct dpu_encoder_phys *phys_enc,
172 const struct msm_format *format)
173 {
174 struct dpu_encoder_phys_wb *wb_enc = to_dpu_encoder_phys_wb(phys_enc);
175 struct dpu_hw_wb *hw_wb;
176 struct dpu_hw_wb_cfg *wb_cfg;
177 u32 cdp_usage;
178
179 if (!phys_enc || !phys_enc->dpu_kms || !phys_enc->dpu_kms->catalog) {
180 DPU_ERROR("invalid encoder\n");
181 return;
182 }
183
184 hw_wb = phys_enc->hw_wb;
185 wb_cfg = &wb_enc->wb_cfg;
186 if (dpu_encoder_helper_get_cwb_mask(phys_enc))
187 cdp_usage = DPU_PERF_CDP_USAGE_RT;
188 else
189 cdp_usage = DPU_PERF_CDP_USAGE_NRT;
190
191 wb_cfg->intf_mode = phys_enc->intf_mode;
192 wb_cfg->roi.x1 = 0;
193 wb_cfg->roi.x2 = phys_enc->cached_mode.hdisplay;
194 wb_cfg->roi.y1 = 0;
195 wb_cfg->roi.y2 = phys_enc->cached_mode.vdisplay;
196
197 if (hw_wb->ops.setup_roi)
198 hw_wb->ops.setup_roi(hw_wb, wb_cfg);
199
200 if (hw_wb->ops.setup_outformat)
201 hw_wb->ops.setup_outformat(hw_wb, wb_cfg, format);
202
203 if (hw_wb->ops.setup_cdp) {
204 const struct dpu_perf_cfg *perf = phys_enc->dpu_kms->catalog->perf;
205
206 hw_wb->ops.setup_cdp(hw_wb, format,
207 perf->cdp_cfg[cdp_usage].wr_enable);
208 }
209
210 if (hw_wb->ops.setup_outaddress)
211 hw_wb->ops.setup_outaddress(hw_wb, wb_cfg);
212 }
213
214 /**
215 * dpu_encoder_phys_wb_setup_ctl - setup wb pipeline for ctl path
216 * @phys_enc:Pointer to physical encoder
217 */
dpu_encoder_phys_wb_setup_ctl(struct dpu_encoder_phys * phys_enc)218 static void dpu_encoder_phys_wb_setup_ctl(struct dpu_encoder_phys *phys_enc)
219 {
220 struct dpu_hw_wb *hw_wb;
221 struct dpu_hw_ctl *ctl;
222 struct dpu_hw_cdm *hw_cdm;
223
224 if (!phys_enc) {
225 DPU_ERROR("invalid encoder\n");
226 return;
227 }
228
229 hw_wb = phys_enc->hw_wb;
230 ctl = phys_enc->hw_ctl;
231 hw_cdm = phys_enc->hw_cdm;
232
233 if (test_bit(DPU_CTL_ACTIVE_CFG, &ctl->caps->features) &&
234 (phys_enc->hw_ctl &&
235 phys_enc->hw_ctl->ops.setup_intf_cfg)) {
236 struct dpu_hw_intf_cfg intf_cfg = {0};
237 struct dpu_hw_pingpong *hw_pp = phys_enc->hw_pp;
238 enum dpu_3d_blend_mode mode_3d;
239
240 mode_3d = dpu_encoder_helper_get_3d_blend_mode(phys_enc);
241
242 intf_cfg.intf = DPU_NONE;
243 intf_cfg.wb = hw_wb->idx;
244 intf_cfg.cwb = dpu_encoder_helper_get_cwb_mask(phys_enc);
245
246 if (mode_3d && hw_pp && hw_pp->merge_3d)
247 intf_cfg.merge_3d = hw_pp->merge_3d->idx;
248
249 if (hw_cdm)
250 intf_cfg.cdm = hw_cdm->idx;
251
252 if (phys_enc->hw_pp->merge_3d && phys_enc->hw_pp->merge_3d->ops.setup_3d_mode)
253 phys_enc->hw_pp->merge_3d->ops.setup_3d_mode(phys_enc->hw_pp->merge_3d,
254 mode_3d);
255
256 /* setup which pp blk will connect to this wb */
257 if (hw_pp && phys_enc->hw_wb->ops.bind_pingpong_blk)
258 phys_enc->hw_wb->ops.bind_pingpong_blk(phys_enc->hw_wb,
259 phys_enc->hw_pp->idx);
260
261 phys_enc->hw_ctl->ops.setup_intf_cfg(phys_enc->hw_ctl, &intf_cfg);
262 } else if (phys_enc->hw_ctl && phys_enc->hw_ctl->ops.setup_intf_cfg) {
263 struct dpu_hw_intf_cfg intf_cfg = {0};
264
265 intf_cfg.intf = DPU_NONE;
266 intf_cfg.wb = hw_wb->idx;
267 intf_cfg.mode_3d =
268 dpu_encoder_helper_get_3d_blend_mode(phys_enc);
269 phys_enc->hw_ctl->ops.setup_intf_cfg(phys_enc->hw_ctl, &intf_cfg);
270 }
271 }
272
273 /**
274 * _dpu_encoder_phys_wb_update_flush - flush hardware update
275 * @phys_enc: Pointer to physical encoder
276 */
_dpu_encoder_phys_wb_update_flush(struct dpu_encoder_phys * phys_enc)277 static void _dpu_encoder_phys_wb_update_flush(struct dpu_encoder_phys *phys_enc)
278 {
279 struct dpu_hw_wb *hw_wb;
280 struct dpu_hw_ctl *hw_ctl;
281 struct dpu_hw_pingpong *hw_pp;
282 struct dpu_hw_cdm *hw_cdm;
283 u32 pending_flush = 0;
284 u32 mode_3d;
285
286 if (!phys_enc)
287 return;
288
289 hw_wb = phys_enc->hw_wb;
290 hw_pp = phys_enc->hw_pp;
291 hw_ctl = phys_enc->hw_ctl;
292 hw_cdm = phys_enc->hw_cdm;
293 mode_3d = dpu_encoder_helper_get_3d_blend_mode(phys_enc);
294
295 DPU_DEBUG("[wb:%d]\n", hw_wb->idx - WB_0);
296
297 if (!hw_ctl) {
298 DPU_DEBUG("[wb:%d] no ctl assigned\n", hw_wb->idx - WB_0);
299 return;
300 }
301
302 if (hw_ctl->ops.update_pending_flush_wb)
303 hw_ctl->ops.update_pending_flush_wb(hw_ctl, hw_wb->idx);
304
305 if (mode_3d && hw_ctl->ops.update_pending_flush_merge_3d &&
306 hw_pp && hw_pp->merge_3d)
307 hw_ctl->ops.update_pending_flush_merge_3d(hw_ctl,
308 hw_pp->merge_3d->idx);
309
310 if (hw_cdm && hw_ctl->ops.update_pending_flush_cdm)
311 hw_ctl->ops.update_pending_flush_cdm(hw_ctl, hw_cdm->idx);
312
313 if (hw_ctl->ops.get_pending_flush)
314 pending_flush = hw_ctl->ops.get_pending_flush(hw_ctl);
315
316 DPU_DEBUG("Pending flush mask for CTL_%d is 0x%x, WB %d\n",
317 hw_ctl->idx - CTL_0, pending_flush,
318 hw_wb->idx - WB_0);
319 }
320
321 /**
322 * dpu_encoder_phys_wb_setup - setup writeback encoder
323 * @phys_enc: Pointer to physical encoder
324 */
dpu_encoder_phys_wb_setup(struct dpu_encoder_phys * phys_enc)325 static void dpu_encoder_phys_wb_setup(
326 struct dpu_encoder_phys *phys_enc)
327 {
328 struct dpu_hw_wb *hw_wb = phys_enc->hw_wb;
329 struct drm_display_mode mode = phys_enc->cached_mode;
330 struct dpu_encoder_phys_wb *wb_enc = to_dpu_encoder_phys_wb(phys_enc);
331 const struct msm_format *format;
332
333 format = msm_framebuffer_format(wb_enc->wb_job->fb);
334
335 DPU_DEBUG("[mode_set:%d, \"%s\",%d,%d]\n",
336 hw_wb->idx - WB_0, mode.name,
337 mode.hdisplay, mode.vdisplay);
338
339 dpu_encoder_phys_wb_set_ot_limit(phys_enc);
340
341 dpu_encoder_phys_wb_set_qos_remap(phys_enc);
342
343 dpu_encoder_phys_wb_set_qos(phys_enc);
344
345 dpu_encoder_phys_wb_setup_fb(phys_enc, format);
346
347 dpu_encoder_helper_phys_setup_cdm(phys_enc, format, CDM_CDWN_OUTPUT_WB);
348
349 dpu_encoder_helper_phys_setup_cwb(phys_enc, true);
350
351 dpu_encoder_phys_wb_setup_ctl(phys_enc);
352 }
353
354 /**
355 * dpu_encoder_phys_wb_done_irq - writeback interrupt handler
356 * @arg: Pointer to writeback encoder
357 */
dpu_encoder_phys_wb_done_irq(void * arg)358 static void dpu_encoder_phys_wb_done_irq(void *arg)
359 {
360 struct dpu_encoder_phys *phys_enc = arg;
361 struct dpu_encoder_phys_wb *wb_enc = to_dpu_encoder_phys_wb(phys_enc);
362
363 struct dpu_hw_wb *hw_wb = phys_enc->hw_wb;
364 unsigned long lock_flags;
365 u32 event = DPU_ENCODER_FRAME_EVENT_DONE;
366
367 DPU_DEBUG("[wb:%d]\n", hw_wb->idx - WB_0);
368
369 dpu_encoder_frame_done_callback(phys_enc->parent, phys_enc, event);
370
371 dpu_encoder_vblank_callback(phys_enc->parent, phys_enc);
372
373 spin_lock_irqsave(phys_enc->enc_spinlock, lock_flags);
374 atomic_add_unless(&phys_enc->pending_kickoff_cnt, -1, 0);
375 spin_unlock_irqrestore(phys_enc->enc_spinlock, lock_flags);
376
377 if (wb_enc->wb_conn)
378 drm_writeback_signal_completion(wb_enc->wb_conn, 0);
379
380 /* Signal any waiting atomic commit thread */
381 wake_up_all(&phys_enc->pending_kickoff_wq);
382 }
383
384 /**
385 * dpu_encoder_phys_wb_irq_enable - irq control of WB
386 * @phys: Pointer to physical encoder
387 */
dpu_encoder_phys_wb_irq_enable(struct dpu_encoder_phys * phys)388 static void dpu_encoder_phys_wb_irq_enable(struct dpu_encoder_phys *phys)
389 {
390
391 struct dpu_encoder_phys_wb *wb_enc = to_dpu_encoder_phys_wb(phys);
392
393 if (atomic_inc_return(&wb_enc->wbirq_refcount) == 1)
394 dpu_core_irq_register_callback(phys->dpu_kms,
395 phys->irq[INTR_IDX_WB_DONE],
396 dpu_encoder_phys_wb_done_irq,
397 phys);
398 }
399
400 /**
401 * dpu_encoder_phys_wb_irq_disable - irq control of WB
402 * @phys: Pointer to physical encoder
403 */
dpu_encoder_phys_wb_irq_disable(struct dpu_encoder_phys * phys)404 static void dpu_encoder_phys_wb_irq_disable(struct dpu_encoder_phys *phys)
405 {
406
407 struct dpu_encoder_phys_wb *wb_enc = to_dpu_encoder_phys_wb(phys);
408
409 if (atomic_dec_return(&wb_enc->wbirq_refcount) == 0)
410 dpu_core_irq_unregister_callback(phys->dpu_kms, phys->irq[INTR_IDX_WB_DONE]);
411 }
412
dpu_encoder_phys_wb_atomic_mode_set(struct dpu_encoder_phys * phys_enc,struct drm_crtc_state * crtc_state,struct drm_connector_state * conn_state)413 static void dpu_encoder_phys_wb_atomic_mode_set(
414 struct dpu_encoder_phys *phys_enc,
415 struct drm_crtc_state *crtc_state,
416 struct drm_connector_state *conn_state)
417 {
418
419 phys_enc->irq[INTR_IDX_WB_DONE] = phys_enc->hw_wb->caps->intr_wb_done;
420 }
421
_dpu_encoder_phys_wb_handle_wbdone_timeout(struct dpu_encoder_phys * phys_enc)422 static void _dpu_encoder_phys_wb_handle_wbdone_timeout(
423 struct dpu_encoder_phys *phys_enc)
424 {
425 struct dpu_encoder_phys_wb *wb_enc = to_dpu_encoder_phys_wb(phys_enc);
426 u32 frame_event = DPU_ENCODER_FRAME_EVENT_ERROR;
427
428 wb_enc->wb_done_timeout_cnt++;
429
430 if (wb_enc->wb_done_timeout_cnt == 1)
431 msm_disp_snapshot_state(phys_enc->parent->dev);
432
433 atomic_add_unless(&phys_enc->pending_kickoff_cnt, -1, 0);
434
435 /* request a ctl reset before the next kickoff */
436 phys_enc->enable_state = DPU_ENC_ERR_NEEDS_HW_RESET;
437
438 if (wb_enc->wb_conn)
439 drm_writeback_signal_completion(wb_enc->wb_conn, 0);
440
441 dpu_encoder_frame_done_callback(phys_enc->parent, phys_enc, frame_event);
442 }
443
444 /**
445 * dpu_encoder_phys_wb_wait_for_commit_done - wait until request is committed
446 * @phys_enc: Pointer to physical encoder
447 */
dpu_encoder_phys_wb_wait_for_commit_done(struct dpu_encoder_phys * phys_enc)448 static int dpu_encoder_phys_wb_wait_for_commit_done(
449 struct dpu_encoder_phys *phys_enc)
450 {
451 unsigned long ret;
452 struct dpu_encoder_wait_info wait_info;
453 struct dpu_encoder_phys_wb *wb_enc = to_dpu_encoder_phys_wb(phys_enc);
454
455 wait_info.wq = &phys_enc->pending_kickoff_wq;
456 wait_info.atomic_cnt = &phys_enc->pending_kickoff_cnt;
457 wait_info.timeout_ms = KICKOFF_TIMEOUT_MS;
458
459 ret = dpu_encoder_helper_wait_for_irq(phys_enc,
460 phys_enc->irq[INTR_IDX_WB_DONE],
461 dpu_encoder_phys_wb_done_irq, &wait_info);
462 if (ret == -ETIMEDOUT)
463 _dpu_encoder_phys_wb_handle_wbdone_timeout(phys_enc);
464 else if (!ret)
465 wb_enc->wb_done_timeout_cnt = 0;
466
467 return ret;
468 }
469
470 /**
471 * dpu_encoder_phys_wb_prepare_for_kickoff - pre-kickoff processing
472 * @phys_enc: Pointer to physical encoder
473 * Returns: Zero on success
474 */
dpu_encoder_phys_wb_prepare_for_kickoff(struct dpu_encoder_phys * phys_enc)475 static void dpu_encoder_phys_wb_prepare_for_kickoff(
476 struct dpu_encoder_phys *phys_enc)
477 {
478 struct dpu_encoder_phys_wb *wb_enc = to_dpu_encoder_phys_wb(phys_enc);
479 struct drm_connector *drm_conn;
480 struct drm_connector_state *state;
481
482 DPU_DEBUG("[wb:%d]\n", phys_enc->hw_wb->idx - WB_0);
483
484 if (!wb_enc->wb_conn || !wb_enc->wb_job) {
485 DPU_ERROR("invalid wb_conn or wb_job\n");
486 return;
487 }
488
489 drm_conn = &wb_enc->wb_conn->base;
490 state = drm_conn->state;
491
492 if (wb_enc->wb_conn && wb_enc->wb_job)
493 drm_writeback_queue_job(wb_enc->wb_conn, state);
494
495 dpu_encoder_phys_wb_setup(phys_enc);
496
497 _dpu_encoder_phys_wb_update_flush(phys_enc);
498 }
499
500 /**
501 * dpu_encoder_phys_wb_needs_single_flush - trigger flush processing
502 * @phys_enc: Pointer to physical encoder
503 */
dpu_encoder_phys_wb_needs_single_flush(struct dpu_encoder_phys * phys_enc)504 static bool dpu_encoder_phys_wb_needs_single_flush(struct dpu_encoder_phys *phys_enc)
505 {
506 DPU_DEBUG("[wb:%d]\n", phys_enc->hw_wb->idx - WB_0);
507 return false;
508 }
509
510 /**
511 * dpu_encoder_phys_wb_handle_post_kickoff - post-kickoff processing
512 * @phys_enc: Pointer to physical encoder
513 */
dpu_encoder_phys_wb_handle_post_kickoff(struct dpu_encoder_phys * phys_enc)514 static void dpu_encoder_phys_wb_handle_post_kickoff(
515 struct dpu_encoder_phys *phys_enc)
516 {
517 DPU_DEBUG("[wb:%d]\n", phys_enc->hw_wb->idx - WB_0);
518
519 }
520
521 /**
522 * dpu_encoder_phys_wb_enable - enable writeback encoder
523 * @phys_enc: Pointer to physical encoder
524 */
dpu_encoder_phys_wb_enable(struct dpu_encoder_phys * phys_enc)525 static void dpu_encoder_phys_wb_enable(struct dpu_encoder_phys *phys_enc)
526 {
527 DPU_DEBUG("[wb:%d]\n", phys_enc->hw_wb->idx - WB_0);
528 phys_enc->enable_state = DPU_ENC_ENABLED;
529 }
530 /**
531 * dpu_encoder_phys_wb_disable - disable writeback encoder
532 * @phys_enc: Pointer to physical encoder
533 */
dpu_encoder_phys_wb_disable(struct dpu_encoder_phys * phys_enc)534 static void dpu_encoder_phys_wb_disable(struct dpu_encoder_phys *phys_enc)
535 {
536 struct dpu_hw_wb *hw_wb = phys_enc->hw_wb;
537 struct dpu_hw_ctl *hw_ctl = phys_enc->hw_ctl;
538
539 DPU_DEBUG("[wb:%d]\n", hw_wb->idx - WB_0);
540
541 if (phys_enc->enable_state == DPU_ENC_DISABLED) {
542 DPU_ERROR("encoder is already disabled\n");
543 return;
544 }
545
546 /* reset h/w before final flush */
547 phys_enc->hw_ctl->ops.clear_pending_flush(phys_enc->hw_ctl);
548
549 /*
550 * New CTL reset sequence from 5.0 MDP onwards.
551 * If has_3d_merge_reset is not set, legacy reset
552 * sequence is executed.
553 *
554 * Legacy reset sequence has not been implemented yet.
555 * Any target earlier than SM8150 will need it and when
556 * WB support is added to those targets will need to add
557 * the legacy teardown sequence as well.
558 */
559 if (hw_ctl->caps->features & BIT(DPU_CTL_ACTIVE_CFG))
560 dpu_encoder_helper_phys_cleanup(phys_enc);
561
562 phys_enc->enable_state = DPU_ENC_DISABLED;
563 }
564
dpu_encoder_phys_wb_prepare_wb_job(struct dpu_encoder_phys * phys_enc,struct drm_writeback_job * job)565 static void dpu_encoder_phys_wb_prepare_wb_job(struct dpu_encoder_phys *phys_enc,
566 struct drm_writeback_job *job)
567 {
568 const struct msm_format *format;
569 struct msm_gem_address_space *aspace;
570 struct dpu_hw_wb_cfg *wb_cfg;
571 int ret;
572 struct dpu_encoder_phys_wb *wb_enc = to_dpu_encoder_phys_wb(phys_enc);
573
574 if (!job->fb)
575 return;
576
577 wb_enc->wb_job = job;
578 wb_enc->wb_conn = job->connector;
579 aspace = phys_enc->dpu_kms->base.aspace;
580
581 wb_cfg = &wb_enc->wb_cfg;
582
583 memset(wb_cfg, 0, sizeof(struct dpu_hw_wb_cfg));
584
585 ret = msm_framebuffer_prepare(job->fb, aspace, false);
586 if (ret) {
587 DPU_ERROR("prep fb failed, %d\n", ret);
588 return;
589 }
590
591 format = msm_framebuffer_format(job->fb);
592
593 ret = dpu_format_populate_plane_sizes(job->fb, &wb_cfg->dest);
594 if (ret) {
595 DPU_DEBUG("failed to populate plane sizes%d\n", ret);
596 return;
597 }
598
599 dpu_format_populate_addrs(aspace, job->fb, &wb_cfg->dest);
600
601 wb_cfg->dest.width = job->fb->width;
602 wb_cfg->dest.height = job->fb->height;
603 wb_cfg->dest.num_planes = format->num_planes;
604
605 if ((format->fetch_type == MDP_PLANE_PLANAR) &&
606 (format->element[0] == C1_B_Cb))
607 swap(wb_cfg->dest.plane_addr[1], wb_cfg->dest.plane_addr[2]);
608
609 DPU_DEBUG("[fb_offset:%8.8x,%8.8x,%8.8x,%8.8x]\n",
610 wb_cfg->dest.plane_addr[0], wb_cfg->dest.plane_addr[1],
611 wb_cfg->dest.plane_addr[2], wb_cfg->dest.plane_addr[3]);
612
613 DPU_DEBUG("[fb_stride:%8.8x,%8.8x,%8.8x,%8.8x]\n",
614 wb_cfg->dest.plane_pitch[0], wb_cfg->dest.plane_pitch[1],
615 wb_cfg->dest.plane_pitch[2], wb_cfg->dest.plane_pitch[3]);
616 }
617
dpu_encoder_phys_wb_cleanup_wb_job(struct dpu_encoder_phys * phys_enc,struct drm_writeback_job * job)618 static void dpu_encoder_phys_wb_cleanup_wb_job(struct dpu_encoder_phys *phys_enc,
619 struct drm_writeback_job *job)
620 {
621 struct dpu_encoder_phys_wb *wb_enc = to_dpu_encoder_phys_wb(phys_enc);
622 struct msm_gem_address_space *aspace;
623
624 if (!job->fb)
625 return;
626
627 aspace = phys_enc->dpu_kms->base.aspace;
628
629 msm_framebuffer_cleanup(job->fb, aspace, false);
630 wb_enc->wb_job = NULL;
631 wb_enc->wb_conn = NULL;
632 }
633
dpu_encoder_phys_wb_is_valid_for_commit(struct dpu_encoder_phys * phys_enc)634 static bool dpu_encoder_phys_wb_is_valid_for_commit(struct dpu_encoder_phys *phys_enc)
635 {
636 struct dpu_encoder_phys_wb *wb_enc = to_dpu_encoder_phys_wb(phys_enc);
637
638 if (wb_enc->wb_job)
639 return true;
640 else
641 return false;
642 }
643
644 /**
645 * dpu_encoder_phys_wb_init_ops - initialize writeback operations
646 * @ops: Pointer to encoder operation table
647 */
dpu_encoder_phys_wb_init_ops(struct dpu_encoder_phys_ops * ops)648 static void dpu_encoder_phys_wb_init_ops(struct dpu_encoder_phys_ops *ops)
649 {
650 ops->is_master = dpu_encoder_phys_wb_is_master;
651 ops->atomic_mode_set = dpu_encoder_phys_wb_atomic_mode_set;
652 ops->enable = dpu_encoder_phys_wb_enable;
653 ops->disable = dpu_encoder_phys_wb_disable;
654 ops->wait_for_commit_done = dpu_encoder_phys_wb_wait_for_commit_done;
655 ops->prepare_for_kickoff = dpu_encoder_phys_wb_prepare_for_kickoff;
656 ops->handle_post_kickoff = dpu_encoder_phys_wb_handle_post_kickoff;
657 ops->needs_single_flush = dpu_encoder_phys_wb_needs_single_flush;
658 ops->trigger_start = dpu_encoder_helper_trigger_start;
659 ops->prepare_wb_job = dpu_encoder_phys_wb_prepare_wb_job;
660 ops->cleanup_wb_job = dpu_encoder_phys_wb_cleanup_wb_job;
661 ops->irq_enable = dpu_encoder_phys_wb_irq_enable;
662 ops->irq_disable = dpu_encoder_phys_wb_irq_disable;
663 ops->is_valid_for_commit = dpu_encoder_phys_wb_is_valid_for_commit;
664
665 }
666
667 /**
668 * dpu_encoder_phys_wb_init - initialize writeback encoder
669 * @dev: Corresponding device for devres management
670 * @p: Pointer to init info structure with initialization params
671 */
dpu_encoder_phys_wb_init(struct drm_device * dev,struct dpu_enc_phys_init_params * p)672 struct dpu_encoder_phys *dpu_encoder_phys_wb_init(struct drm_device *dev,
673 struct dpu_enc_phys_init_params *p)
674 {
675 struct dpu_encoder_phys *phys_enc = NULL;
676 struct dpu_encoder_phys_wb *wb_enc = NULL;
677
678 DPU_DEBUG("\n");
679
680 if (!p || !p->parent) {
681 DPU_ERROR("invalid params\n");
682 return ERR_PTR(-EINVAL);
683 }
684
685 wb_enc = drmm_kzalloc(dev, sizeof(*wb_enc), GFP_KERNEL);
686 if (!wb_enc) {
687 DPU_ERROR("failed to allocate wb phys_enc enc\n");
688 return ERR_PTR(-ENOMEM);
689 }
690
691 phys_enc = &wb_enc->base;
692
693 dpu_encoder_phys_init(phys_enc, p);
694
695 dpu_encoder_phys_wb_init_ops(&phys_enc->ops);
696 phys_enc->intf_mode = INTF_MODE_WB_LINE;
697
698 atomic_set(&wb_enc->wbirq_refcount, 0);
699
700 wb_enc->wb_done_timeout_cnt = 0;
701
702 DPU_DEBUG("Created dpu_encoder_phys for wb %d\n", phys_enc->hw_wb->idx);
703
704 return phys_enc;
705 }
706