1 // SPDX-License-Identifier: GPL-2.0-only
2 /*
3 * Copyright (C) 2013 Red Hat
4 * Copyright (c) 2014-2018, 2020-2021 The Linux Foundation. All rights reserved.
5 * Copyright (c) 2022-2024 Qualcomm Innovation Center, Inc. All rights reserved.
6 *
7 * Author: Rob Clark <robdclark@gmail.com>
8 */
9
10 #define pr_fmt(fmt) "[drm:%s:%d] " fmt, __func__, __LINE__
11 #include <linux/debugfs.h>
12 #include <linux/kthread.h>
13 #include <linux/seq_file.h>
14
15 #include <drm/drm_atomic.h>
16 #include <drm/drm_crtc.h>
17 #include <drm/drm_file.h>
18 #include <drm/drm_probe_helper.h>
19 #include <drm/drm_framebuffer.h>
20
21 #include "msm_drv.h"
22 #include "dpu_kms.h"
23 #include "dpu_hwio.h"
24 #include "dpu_hw_catalog.h"
25 #include "dpu_hw_intf.h"
26 #include "dpu_hw_ctl.h"
27 #include "dpu_hw_cwb.h"
28 #include "dpu_hw_dspp.h"
29 #include "dpu_hw_dsc.h"
30 #include "dpu_hw_merge3d.h"
31 #include "dpu_hw_cdm.h"
32 #include "dpu_formats.h"
33 #include "dpu_encoder_phys.h"
34 #include "dpu_crtc.h"
35 #include "dpu_trace.h"
36 #include "dpu_core_irq.h"
37 #include "disp/msm_disp_snapshot.h"
38
39 #define DPU_DEBUG_ENC(e, fmt, ...) DRM_DEBUG_ATOMIC("enc%d " fmt,\
40 (e) ? (e)->base.base.id : -1, ##__VA_ARGS__)
41
42 #define DPU_ERROR_ENC(e, fmt, ...) DPU_ERROR("enc%d " fmt,\
43 (e) ? (e)->base.base.id : -1, ##__VA_ARGS__)
44
45 #define DPU_ERROR_ENC_RATELIMITED(e, fmt, ...) DPU_ERROR_RATELIMITED("enc%d " fmt,\
46 (e) ? (e)->base.base.id : -1, ##__VA_ARGS__)
47
48 /*
49 * Two to anticipate panels that can do cmd/vid dynamic switching
50 * plan is to create all possible physical encoder types, and switch between
51 * them at runtime
52 */
53 #define NUM_PHYS_ENCODER_TYPES 2
54
55 #define MAX_PHYS_ENCODERS_PER_VIRTUAL \
56 (MAX_H_TILES_PER_DISPLAY * NUM_PHYS_ENCODER_TYPES)
57
58 #define MAX_CHANNELS_PER_ENC 2
59
60 #define IDLE_SHORT_TIMEOUT 1
61
62 /* timeout in frames waiting for frame done */
63 #define DPU_ENCODER_FRAME_DONE_TIMEOUT_FRAMES 5
64
65 /**
66 * enum dpu_enc_rc_events - events for resource control state machine
67 * @DPU_ENC_RC_EVENT_KICKOFF:
68 * This event happens at NORMAL priority.
69 * Event that signals the start of the transfer. When this event is
70 * received, enable MDP/DSI core clocks. Regardless of the previous
71 * state, the resource should be in ON state at the end of this event.
72 * @DPU_ENC_RC_EVENT_FRAME_DONE:
73 * This event happens at INTERRUPT level.
74 * Event signals the end of the data transfer after the PP FRAME_DONE
75 * event. At the end of this event, a delayed work is scheduled to go to
76 * IDLE_PC state after IDLE_TIMEOUT time.
77 * @DPU_ENC_RC_EVENT_PRE_STOP:
78 * This event happens at NORMAL priority.
79 * This event, when received during the ON state, leave the RC STATE
80 * in the PRE_OFF state. It should be followed by the STOP event as
81 * part of encoder disable.
82 * If received during IDLE or OFF states, it will do nothing.
83 * @DPU_ENC_RC_EVENT_STOP:
84 * This event happens at NORMAL priority.
85 * When this event is received, disable all the MDP/DSI core clocks, and
86 * disable IRQs. It should be called from the PRE_OFF or IDLE states.
87 * IDLE is expected when IDLE_PC has run, and PRE_OFF did nothing.
88 * PRE_OFF is expected when PRE_STOP was executed during the ON state.
89 * Resource state should be in OFF at the end of the event.
90 * @DPU_ENC_RC_EVENT_ENTER_IDLE:
91 * This event happens at NORMAL priority from a work item.
92 * Event signals that there were no frame updates for IDLE_TIMEOUT time.
93 * This would disable MDP/DSI core clocks and change the resource state
94 * to IDLE.
95 */
96 enum dpu_enc_rc_events {
97 DPU_ENC_RC_EVENT_KICKOFF = 1,
98 DPU_ENC_RC_EVENT_FRAME_DONE,
99 DPU_ENC_RC_EVENT_PRE_STOP,
100 DPU_ENC_RC_EVENT_STOP,
101 DPU_ENC_RC_EVENT_ENTER_IDLE
102 };
103
104 /*
105 * enum dpu_enc_rc_states - states that the resource control maintains
106 * @DPU_ENC_RC_STATE_OFF: Resource is in OFF state
107 * @DPU_ENC_RC_STATE_PRE_OFF: Resource is transitioning to OFF state
108 * @DPU_ENC_RC_STATE_ON: Resource is in ON state
109 * @DPU_ENC_RC_STATE_MODESET: Resource is in modeset state
110 * @DPU_ENC_RC_STATE_IDLE: Resource is in IDLE state
111 */
112 enum dpu_enc_rc_states {
113 DPU_ENC_RC_STATE_OFF,
114 DPU_ENC_RC_STATE_PRE_OFF,
115 DPU_ENC_RC_STATE_ON,
116 DPU_ENC_RC_STATE_IDLE
117 };
118
119 /**
120 * struct dpu_encoder_virt - virtual encoder. Container of one or more physical
121 * encoders. Virtual encoder manages one "logical" display. Physical
122 * encoders manage one intf block, tied to a specific panel/sub-panel.
123 * Virtual encoder defers as much as possible to the physical encoders.
124 * Virtual encoder registers itself with the DRM Framework as the encoder.
125 * @base: drm_encoder base class for registration with DRM
126 * @enc_spinlock: Virtual-Encoder-Wide Spin Lock for IRQ purposes
127 * @enabled: True if the encoder is active, protected by enc_lock
128 * @commit_done_timedout: True if there has been a timeout on commit after
129 * enabling the encoder.
130 * @num_phys_encs: Actual number of physical encoders contained.
131 * @phys_encs: Container of physical encoders managed.
132 * @cur_master: Pointer to the current master in this mode. Optimization
133 * Only valid after enable. Cleared as disable.
134 * @cur_slave: As above but for the slave encoder.
135 * @hw_pp: Handle to the pingpong blocks used for the display. No.
136 * pingpong blocks can be different than num_phys_encs.
137 * @hw_cwb: Handle to the CWB muxes used for concurrent writeback
138 * display. Number of CWB muxes can be different than
139 * num_phys_encs.
140 * @hw_dsc: Handle to the DSC blocks used for the display.
141 * @dsc_mask: Bitmask of used DSC blocks.
142 * @cwb_mask: Bitmask of used CWB muxes
143 * @intfs_swapped: Whether or not the phys_enc interfaces have been swapped
144 * for partial update right-only cases, such as pingpong
145 * split where virtual pingpong does not generate IRQs
146 * @crtc: Pointer to the currently assigned crtc. Normally you
147 * would use crtc->state->encoder_mask to determine the
148 * link between encoder/crtc. However in this case we need
149 * to track crtc in the disable() hook which is called
150 * _after_ encoder_mask is cleared.
151 * @connector: If a mode is set, cached pointer to the active connector
152 * @enc_lock: Lock around physical encoder
153 * create/destroy/enable/disable
154 * @frame_busy_mask: Bitmask tracking which phys_enc we are still
155 * busy processing current command.
156 * Bit0 = phys_encs[0] etc.
157 * @frame_done_timeout_ms: frame done timeout in ms
158 * @frame_done_timeout_cnt: atomic counter tracking the number of frame
159 * done timeouts
160 * @frame_done_timer: watchdog timer for frame done event
161 * @disp_info: local copy of msm_display_info struct
162 * @idle_pc_supported: indicate if idle power collaps is supported
163 * @rc_lock: resource control mutex lock to protect
164 * virt encoder over various state changes
165 * @rc_state: resource controller state
166 * @delayed_off_work: delayed worker to schedule disabling of
167 * clks and resources after IDLE_TIMEOUT time.
168 * @topology: topology of the display
169 * @idle_timeout: idle timeout duration in milliseconds
170 * @wide_bus_en: wide bus is enabled on this interface
171 * @dsc: drm_dsc_config pointer, for DSC-enabled encoders
172 */
173 struct dpu_encoder_virt {
174 struct drm_encoder base;
175 spinlock_t enc_spinlock;
176
177 bool enabled;
178 bool commit_done_timedout;
179
180 unsigned int num_phys_encs;
181 struct dpu_encoder_phys *phys_encs[MAX_PHYS_ENCODERS_PER_VIRTUAL];
182 struct dpu_encoder_phys *cur_master;
183 struct dpu_encoder_phys *cur_slave;
184 struct dpu_hw_pingpong *hw_pp[MAX_CHANNELS_PER_ENC];
185 struct dpu_hw_cwb *hw_cwb[MAX_CHANNELS_PER_ENC];
186 struct dpu_hw_dsc *hw_dsc[MAX_CHANNELS_PER_ENC];
187
188 unsigned int dsc_mask;
189 unsigned int cwb_mask;
190
191 bool intfs_swapped;
192
193 struct drm_crtc *crtc;
194 struct drm_connector *connector;
195
196 struct mutex enc_lock;
197 DECLARE_BITMAP(frame_busy_mask, MAX_PHYS_ENCODERS_PER_VIRTUAL);
198
199 atomic_t frame_done_timeout_ms;
200 atomic_t frame_done_timeout_cnt;
201 struct timer_list frame_done_timer;
202
203 struct msm_display_info disp_info;
204
205 bool idle_pc_supported;
206 struct mutex rc_lock;
207 enum dpu_enc_rc_states rc_state;
208 struct delayed_work delayed_off_work;
209 struct msm_display_topology topology;
210
211 u32 idle_timeout;
212
213 bool wide_bus_en;
214
215 /* DSC configuration */
216 struct drm_dsc_config *dsc;
217 };
218
219 #define to_dpu_encoder_virt(x) container_of(x, struct dpu_encoder_virt, base)
220
221 static u32 dither_matrix[DITHER_MATRIX_SZ] = {
222 15, 7, 13, 5, 3, 11, 1, 9, 12, 4, 14, 6, 0, 8, 2, 10
223 };
224
225 /**
226 * dpu_encoder_get_drm_fmt - return DRM fourcc format
227 * @phys_enc: Pointer to physical encoder structure
228 */
dpu_encoder_get_drm_fmt(struct dpu_encoder_phys * phys_enc)229 u32 dpu_encoder_get_drm_fmt(struct dpu_encoder_phys *phys_enc)
230 {
231 struct drm_encoder *drm_enc;
232 struct dpu_encoder_virt *dpu_enc;
233 struct drm_display_info *info;
234 struct drm_display_mode *mode;
235
236 drm_enc = phys_enc->parent;
237 dpu_enc = to_dpu_encoder_virt(drm_enc);
238 info = &dpu_enc->connector->display_info;
239 mode = &phys_enc->cached_mode;
240
241 if (drm_mode_is_420_only(info, mode))
242 return DRM_FORMAT_YUV420;
243
244 return DRM_FORMAT_RGB888;
245 }
246
247 /**
248 * dpu_encoder_needs_periph_flush - return true if physical encoder requires
249 * peripheral flush
250 * @phys_enc: Pointer to physical encoder structure
251 */
dpu_encoder_needs_periph_flush(struct dpu_encoder_phys * phys_enc)252 bool dpu_encoder_needs_periph_flush(struct dpu_encoder_phys *phys_enc)
253 {
254 struct drm_encoder *drm_enc;
255 struct dpu_encoder_virt *dpu_enc;
256 struct msm_display_info *disp_info;
257 struct msm_drm_private *priv;
258 struct drm_display_mode *mode;
259
260 drm_enc = phys_enc->parent;
261 dpu_enc = to_dpu_encoder_virt(drm_enc);
262 disp_info = &dpu_enc->disp_info;
263 priv = drm_enc->dev->dev_private;
264 mode = &phys_enc->cached_mode;
265
266 return phys_enc->hw_intf->cap->type == INTF_DP &&
267 msm_dp_needs_periph_flush(priv->dp[disp_info->h_tile_instance[0]], mode);
268 }
269
270 /**
271 * dpu_encoder_is_widebus_enabled - return bool value if widebus is enabled
272 * @drm_enc: Pointer to previously created drm encoder structure
273 */
dpu_encoder_is_widebus_enabled(const struct drm_encoder * drm_enc)274 bool dpu_encoder_is_widebus_enabled(const struct drm_encoder *drm_enc)
275 {
276 const struct dpu_encoder_virt *dpu_enc;
277 struct msm_drm_private *priv = drm_enc->dev->dev_private;
278 const struct msm_display_info *disp_info;
279 int index;
280
281 dpu_enc = to_dpu_encoder_virt(drm_enc);
282 disp_info = &dpu_enc->disp_info;
283 index = disp_info->h_tile_instance[0];
284
285 if (disp_info->intf_type == INTF_DP)
286 return msm_dp_wide_bus_available(priv->dp[index]);
287 else if (disp_info->intf_type == INTF_DSI)
288 return msm_dsi_wide_bus_enabled(priv->dsi[index]);
289
290 return false;
291 }
292
293 /**
294 * dpu_encoder_is_dsc_enabled - indicate whether dsc is enabled
295 * for the encoder.
296 * @drm_enc: Pointer to previously created drm encoder structure
297 */
dpu_encoder_is_dsc_enabled(const struct drm_encoder * drm_enc)298 bool dpu_encoder_is_dsc_enabled(const struct drm_encoder *drm_enc)
299 {
300 const struct dpu_encoder_virt *dpu_enc = to_dpu_encoder_virt(drm_enc);
301
302 return dpu_enc->dsc ? true : false;
303 }
304
305 /**
306 * dpu_encoder_get_crc_values_cnt - get number of physical encoders contained
307 * in virtual encoder that can collect CRC values
308 * @drm_enc: Pointer to previously created drm encoder structure
309 * Returns: Number of physical encoders for given drm encoder
310 */
dpu_encoder_get_crc_values_cnt(const struct drm_encoder * drm_enc)311 int dpu_encoder_get_crc_values_cnt(const struct drm_encoder *drm_enc)
312 {
313 struct dpu_encoder_virt *dpu_enc;
314 int i, num_intf = 0;
315
316 dpu_enc = to_dpu_encoder_virt(drm_enc);
317
318 for (i = 0; i < dpu_enc->num_phys_encs; i++) {
319 struct dpu_encoder_phys *phys = dpu_enc->phys_encs[i];
320
321 if (phys->hw_intf && phys->hw_intf->ops.setup_misr
322 && phys->hw_intf->ops.collect_misr)
323 num_intf++;
324 }
325
326 return num_intf;
327 }
328
329 /**
330 * dpu_encoder_setup_misr - enable misr calculations
331 * @drm_enc: Pointer to previously created drm encoder structure
332 */
dpu_encoder_setup_misr(const struct drm_encoder * drm_enc)333 void dpu_encoder_setup_misr(const struct drm_encoder *drm_enc)
334 {
335 struct dpu_encoder_virt *dpu_enc;
336
337 int i;
338
339 dpu_enc = to_dpu_encoder_virt(drm_enc);
340
341 for (i = 0; i < dpu_enc->num_phys_encs; i++) {
342 struct dpu_encoder_phys *phys = dpu_enc->phys_encs[i];
343
344 if (!phys->hw_intf || !phys->hw_intf->ops.setup_misr)
345 continue;
346
347 phys->hw_intf->ops.setup_misr(phys->hw_intf);
348 }
349 }
350
351 /**
352 * dpu_encoder_get_crc - get the crc value from interface blocks
353 * @drm_enc: Pointer to previously created drm encoder structure
354 * @crcs: array to fill with CRC data
355 * @pos: offset into the @crcs array
356 * Returns: 0 on success, error otherwise
357 */
dpu_encoder_get_crc(const struct drm_encoder * drm_enc,u32 * crcs,int pos)358 int dpu_encoder_get_crc(const struct drm_encoder *drm_enc, u32 *crcs, int pos)
359 {
360 struct dpu_encoder_virt *dpu_enc;
361
362 int i, rc = 0, entries_added = 0;
363
364 if (!drm_enc->crtc) {
365 DRM_ERROR("no crtc found for encoder %d\n", drm_enc->index);
366 return -EINVAL;
367 }
368
369 dpu_enc = to_dpu_encoder_virt(drm_enc);
370
371 for (i = 0; i < dpu_enc->num_phys_encs; i++) {
372 struct dpu_encoder_phys *phys = dpu_enc->phys_encs[i];
373
374 if (!phys->hw_intf || !phys->hw_intf->ops.collect_misr)
375 continue;
376
377 rc = phys->hw_intf->ops.collect_misr(phys->hw_intf, &crcs[pos + entries_added]);
378 if (rc)
379 return rc;
380 entries_added++;
381 }
382
383 return entries_added;
384 }
385
_dpu_encoder_setup_dither(struct dpu_hw_pingpong * hw_pp,unsigned bpc)386 static void _dpu_encoder_setup_dither(struct dpu_hw_pingpong *hw_pp, unsigned bpc)
387 {
388 struct dpu_hw_dither_cfg dither_cfg = { 0 };
389
390 if (!hw_pp->ops.setup_dither)
391 return;
392
393 switch (bpc) {
394 case 6:
395 dither_cfg.c0_bitdepth = 6;
396 dither_cfg.c1_bitdepth = 6;
397 dither_cfg.c2_bitdepth = 6;
398 dither_cfg.c3_bitdepth = 6;
399 dither_cfg.temporal_en = 0;
400 break;
401 default:
402 hw_pp->ops.setup_dither(hw_pp, NULL);
403 return;
404 }
405
406 memcpy(&dither_cfg.matrix, dither_matrix,
407 sizeof(u32) * DITHER_MATRIX_SZ);
408
409 hw_pp->ops.setup_dither(hw_pp, &dither_cfg);
410 }
411
dpu_encoder_helper_get_intf_type(enum dpu_intf_mode intf_mode)412 static char *dpu_encoder_helper_get_intf_type(enum dpu_intf_mode intf_mode)
413 {
414 switch (intf_mode) {
415 case INTF_MODE_VIDEO:
416 return "INTF_MODE_VIDEO";
417 case INTF_MODE_CMD:
418 return "INTF_MODE_CMD";
419 case INTF_MODE_WB_BLOCK:
420 return "INTF_MODE_WB_BLOCK";
421 case INTF_MODE_WB_LINE:
422 return "INTF_MODE_WB_LINE";
423 default:
424 return "INTF_MODE_UNKNOWN";
425 }
426 }
427
428 /**
429 * dpu_encoder_helper_report_irq_timeout - utility to report error that irq has
430 * timed out, including reporting frame error event to crtc and debug dump
431 * @phys_enc: Pointer to physical encoder structure
432 * @intr_idx: Failing interrupt index
433 */
dpu_encoder_helper_report_irq_timeout(struct dpu_encoder_phys * phys_enc,enum dpu_intr_idx intr_idx)434 void dpu_encoder_helper_report_irq_timeout(struct dpu_encoder_phys *phys_enc,
435 enum dpu_intr_idx intr_idx)
436 {
437 DRM_ERROR("irq timeout id=%u, intf_mode=%s intf=%d wb=%d, pp=%d, intr=%d\n",
438 DRMID(phys_enc->parent),
439 dpu_encoder_helper_get_intf_type(phys_enc->intf_mode),
440 phys_enc->hw_intf ? phys_enc->hw_intf->idx - INTF_0 : -1,
441 phys_enc->hw_wb ? phys_enc->hw_wb->idx - WB_0 : -1,
442 phys_enc->hw_pp->idx - PINGPONG_0, intr_idx);
443
444 dpu_encoder_frame_done_callback(phys_enc->parent, phys_enc,
445 DPU_ENCODER_FRAME_EVENT_ERROR);
446 }
447
448 static int dpu_encoder_helper_wait_event_timeout(int32_t drm_id,
449 u32 irq_idx, struct dpu_encoder_wait_info *info);
450
451 /**
452 * dpu_encoder_helper_wait_for_irq - utility to wait on an irq.
453 * note: will call dpu_encoder_helper_wait_for_irq on timeout
454 * @phys_enc: Pointer to physical encoder structure
455 * @irq_idx: IRQ index
456 * @func: IRQ callback to be called in case of timeout
457 * @wait_info: wait info struct
458 * @return: 0 or -ERROR
459 */
dpu_encoder_helper_wait_for_irq(struct dpu_encoder_phys * phys_enc,unsigned int irq_idx,void (* func)(void * arg),struct dpu_encoder_wait_info * wait_info)460 int dpu_encoder_helper_wait_for_irq(struct dpu_encoder_phys *phys_enc,
461 unsigned int irq_idx,
462 void (*func)(void *arg),
463 struct dpu_encoder_wait_info *wait_info)
464 {
465 u32 irq_status;
466 int ret;
467
468 if (!wait_info) {
469 DPU_ERROR("invalid params\n");
470 return -EINVAL;
471 }
472 /* note: do master / slave checking outside */
473
474 /* return EWOULDBLOCK since we know the wait isn't necessary */
475 if (phys_enc->enable_state == DPU_ENC_DISABLED) {
476 DRM_ERROR("encoder is disabled id=%u, callback=%ps, IRQ=[%d, %d]\n",
477 DRMID(phys_enc->parent), func,
478 DPU_IRQ_REG(irq_idx), DPU_IRQ_BIT(irq_idx));
479 return -EWOULDBLOCK;
480 }
481
482 if (irq_idx == 0) {
483 DRM_DEBUG_KMS("skip irq wait id=%u, callback=%ps\n",
484 DRMID(phys_enc->parent), func);
485 return 0;
486 }
487
488 DRM_DEBUG_KMS("id=%u, callback=%ps, IRQ=[%d, %d], pp=%d, pending_cnt=%d\n",
489 DRMID(phys_enc->parent), func,
490 DPU_IRQ_REG(irq_idx), DPU_IRQ_BIT(irq_idx), phys_enc->hw_pp->idx - PINGPONG_0,
491 atomic_read(wait_info->atomic_cnt));
492
493 ret = dpu_encoder_helper_wait_event_timeout(
494 DRMID(phys_enc->parent),
495 irq_idx,
496 wait_info);
497
498 if (ret <= 0) {
499 irq_status = dpu_core_irq_read(phys_enc->dpu_kms, irq_idx);
500 if (irq_status) {
501 unsigned long flags;
502
503 DRM_DEBUG_KMS("IRQ=[%d, %d] not triggered id=%u, callback=%ps, pp=%d, atomic_cnt=%d\n",
504 DPU_IRQ_REG(irq_idx), DPU_IRQ_BIT(irq_idx),
505 DRMID(phys_enc->parent), func,
506 phys_enc->hw_pp->idx - PINGPONG_0,
507 atomic_read(wait_info->atomic_cnt));
508 local_irq_save(flags);
509 func(phys_enc);
510 local_irq_restore(flags);
511 ret = 0;
512 } else {
513 ret = -ETIMEDOUT;
514 DRM_DEBUG_KMS("IRQ=[%d, %d] timeout id=%u, callback=%ps, pp=%d, atomic_cnt=%d\n",
515 DPU_IRQ_REG(irq_idx), DPU_IRQ_BIT(irq_idx),
516 DRMID(phys_enc->parent), func,
517 phys_enc->hw_pp->idx - PINGPONG_0,
518 atomic_read(wait_info->atomic_cnt));
519 }
520 } else {
521 ret = 0;
522 trace_dpu_enc_irq_wait_success(DRMID(phys_enc->parent),
523 func, DPU_IRQ_REG(irq_idx), DPU_IRQ_BIT(irq_idx),
524 phys_enc->hw_pp->idx - PINGPONG_0,
525 atomic_read(wait_info->atomic_cnt));
526 }
527
528 return ret;
529 }
530
531 /**
532 * dpu_encoder_get_vsync_count - get vsync count for the encoder.
533 * @drm_enc: Pointer to previously created drm encoder structure
534 */
dpu_encoder_get_vsync_count(struct drm_encoder * drm_enc)535 int dpu_encoder_get_vsync_count(struct drm_encoder *drm_enc)
536 {
537 struct dpu_encoder_virt *dpu_enc = to_dpu_encoder_virt(drm_enc);
538 struct dpu_encoder_phys *phys = dpu_enc ? dpu_enc->cur_master : NULL;
539 return phys ? atomic_read(&phys->vsync_cnt) : 0;
540 }
541
542 /**
543 * dpu_encoder_get_linecount - get interface line count for the encoder.
544 * @drm_enc: Pointer to previously created drm encoder structure
545 */
dpu_encoder_get_linecount(struct drm_encoder * drm_enc)546 int dpu_encoder_get_linecount(struct drm_encoder *drm_enc)
547 {
548 struct dpu_encoder_virt *dpu_enc;
549 struct dpu_encoder_phys *phys;
550 int linecount = 0;
551
552 dpu_enc = to_dpu_encoder_virt(drm_enc);
553 phys = dpu_enc ? dpu_enc->cur_master : NULL;
554
555 if (phys && phys->ops.get_line_count)
556 linecount = phys->ops.get_line_count(phys);
557
558 return linecount;
559 }
560
561 /**
562 * dpu_encoder_helper_split_config - split display configuration helper function
563 * This helper function may be used by physical encoders to configure
564 * the split display related registers.
565 * @phys_enc: Pointer to physical encoder structure
566 * @interface: enum dpu_intf setting
567 */
dpu_encoder_helper_split_config(struct dpu_encoder_phys * phys_enc,enum dpu_intf interface)568 void dpu_encoder_helper_split_config(
569 struct dpu_encoder_phys *phys_enc,
570 enum dpu_intf interface)
571 {
572 struct dpu_encoder_virt *dpu_enc;
573 struct split_pipe_cfg cfg = { 0 };
574 struct dpu_hw_mdp *hw_mdptop;
575 struct msm_display_info *disp_info;
576
577 if (!phys_enc->hw_mdptop || !phys_enc->parent) {
578 DPU_ERROR("invalid arg(s), encoder %d\n", phys_enc != NULL);
579 return;
580 }
581
582 dpu_enc = to_dpu_encoder_virt(phys_enc->parent);
583 hw_mdptop = phys_enc->hw_mdptop;
584 disp_info = &dpu_enc->disp_info;
585
586 if (disp_info->intf_type != INTF_DSI)
587 return;
588
589 /**
590 * disable split modes since encoder will be operating in as the only
591 * encoder, either for the entire use case in the case of, for example,
592 * single DSI, or for this frame in the case of left/right only partial
593 * update.
594 */
595 if (phys_enc->split_role == ENC_ROLE_SOLO) {
596 if (hw_mdptop->ops.setup_split_pipe)
597 hw_mdptop->ops.setup_split_pipe(hw_mdptop, &cfg);
598 return;
599 }
600
601 cfg.en = true;
602 cfg.mode = phys_enc->intf_mode;
603 cfg.intf = interface;
604
605 if (cfg.en && phys_enc->ops.needs_single_flush &&
606 phys_enc->ops.needs_single_flush(phys_enc))
607 cfg.split_flush_en = true;
608
609 if (phys_enc->split_role == ENC_ROLE_MASTER) {
610 DPU_DEBUG_ENC(dpu_enc, "enable %d\n", cfg.en);
611
612 if (hw_mdptop->ops.setup_split_pipe)
613 hw_mdptop->ops.setup_split_pipe(hw_mdptop, &cfg);
614 }
615 }
616
617 /**
618 * dpu_encoder_use_dsc_merge - returns true if the encoder uses DSC merge topology.
619 * @drm_enc: Pointer to previously created drm encoder structure
620 */
dpu_encoder_use_dsc_merge(struct drm_encoder * drm_enc)621 bool dpu_encoder_use_dsc_merge(struct drm_encoder *drm_enc)
622 {
623 struct dpu_encoder_virt *dpu_enc = to_dpu_encoder_virt(drm_enc);
624 int i, intf_count = 0, num_dsc = 0;
625
626 for (i = 0; i < MAX_PHYS_ENCODERS_PER_VIRTUAL; i++)
627 if (dpu_enc->phys_encs[i])
628 intf_count++;
629
630 for (i = 0; i < MAX_CHANNELS_PER_ENC; i++)
631 if (dpu_enc->hw_dsc[i])
632 num_dsc++;
633
634 return (num_dsc > 0) && (num_dsc > intf_count);
635 }
636
637 /**
638 * dpu_encoder_get_dsc_config - get DSC config for the DPU encoder
639 * This helper function is used by physical encoder to get DSC config
640 * used for this encoder.
641 * @drm_enc: Pointer to encoder structure
642 */
dpu_encoder_get_dsc_config(struct drm_encoder * drm_enc)643 struct drm_dsc_config *dpu_encoder_get_dsc_config(struct drm_encoder *drm_enc)
644 {
645 struct msm_drm_private *priv = drm_enc->dev->dev_private;
646 struct dpu_encoder_virt *dpu_enc = to_dpu_encoder_virt(drm_enc);
647 int index = dpu_enc->disp_info.h_tile_instance[0];
648
649 if (dpu_enc->disp_info.intf_type == INTF_DSI)
650 return msm_dsi_get_dsc_config(priv->dsi[index]);
651
652 return NULL;
653 }
654
dpu_encoder_update_topology(struct drm_encoder * drm_enc,struct msm_display_topology * topology,struct drm_atomic_state * state,const struct drm_display_mode * adj_mode)655 void dpu_encoder_update_topology(struct drm_encoder *drm_enc,
656 struct msm_display_topology *topology,
657 struct drm_atomic_state *state,
658 const struct drm_display_mode *adj_mode)
659 {
660 struct dpu_encoder_virt *dpu_enc = to_dpu_encoder_virt(drm_enc);
661 struct msm_drm_private *priv = dpu_enc->base.dev->dev_private;
662 struct msm_display_info *disp_info = &dpu_enc->disp_info;
663 struct dpu_kms *dpu_kms = to_dpu_kms(priv->kms);
664 struct drm_connector *connector;
665 struct drm_connector_state *conn_state;
666 struct drm_framebuffer *fb;
667 struct drm_dsc_config *dsc;
668
669 int i;
670
671 for (i = 0; i < MAX_PHYS_ENCODERS_PER_VIRTUAL; i++)
672 if (dpu_enc->phys_encs[i])
673 topology->num_intf++;
674
675 dsc = dpu_encoder_get_dsc_config(drm_enc);
676
677 /* We only support 2 DSC mode (with 2 LM and 1 INTF) */
678 if (dsc) {
679 /*
680 * Use 2 DSC encoders, 2 layer mixers and 1 or 2 interfaces
681 * when Display Stream Compression (DSC) is enabled,
682 * and when enough DSC blocks are available.
683 * This is power-optimal and can drive up to (including) 4k
684 * screens.
685 */
686 WARN(topology->num_intf > 2,
687 "DSC topology cannot support more than 2 interfaces\n");
688 if (topology->num_intf >= 2 || dpu_kms->catalog->dsc_count >= 2)
689 topology->num_dsc = 2;
690 else
691 topology->num_dsc = 1;
692 }
693
694 connector = drm_atomic_get_new_connector_for_encoder(state, drm_enc);
695 if (!connector)
696 return;
697 conn_state = drm_atomic_get_new_connector_state(state, connector);
698 if (!conn_state)
699 return;
700
701 /*
702 * Use CDM only for writeback or DP at the moment as other interfaces cannot handle it.
703 * If writeback itself cannot handle cdm for some reason it will fail in its atomic_check()
704 * earlier.
705 */
706 if (disp_info->intf_type == INTF_WB && conn_state->writeback_job) {
707 fb = conn_state->writeback_job->fb;
708
709 if (fb && MSM_FORMAT_IS_YUV(msm_framebuffer_format(fb)))
710 topology->num_cdm++;
711 } else if (disp_info->intf_type == INTF_DP) {
712 if (msm_dp_is_yuv_420_enabled(priv->dp[disp_info->h_tile_instance[0]], adj_mode))
713 topology->num_cdm++;
714 }
715 }
716
dpu_encoder_needs_modeset(struct drm_encoder * drm_enc,struct drm_atomic_state * state)717 bool dpu_encoder_needs_modeset(struct drm_encoder *drm_enc, struct drm_atomic_state *state)
718 {
719 struct drm_connector *connector;
720 struct drm_connector_state *conn_state;
721 struct drm_framebuffer *fb;
722 struct dpu_encoder_virt *dpu_enc = to_dpu_encoder_virt(drm_enc);
723
724 if (!drm_enc || !state)
725 return false;
726
727 connector = drm_atomic_get_new_connector_for_encoder(state, drm_enc);
728 if (!connector)
729 return false;
730
731 conn_state = drm_atomic_get_new_connector_state(state, connector);
732
733 /**
734 * These checks are duplicated from dpu_encoder_update_topology() since
735 * CRTC and encoder don't hold topology information
736 */
737 if (dpu_enc->disp_info.intf_type == INTF_WB && conn_state->writeback_job) {
738 fb = conn_state->writeback_job->fb;
739 if (fb && MSM_FORMAT_IS_YUV(msm_framebuffer_format(fb))) {
740 if (!dpu_enc->cur_master->hw_cdm)
741 return true;
742 } else {
743 if (dpu_enc->cur_master->hw_cdm)
744 return true;
745 }
746 }
747
748 return false;
749 }
750
_dpu_encoder_update_vsync_source(struct dpu_encoder_virt * dpu_enc,struct msm_display_info * disp_info)751 static void _dpu_encoder_update_vsync_source(struct dpu_encoder_virt *dpu_enc,
752 struct msm_display_info *disp_info)
753 {
754 struct dpu_vsync_source_cfg vsync_cfg = { 0 };
755 struct msm_drm_private *priv;
756 struct dpu_kms *dpu_kms;
757 struct dpu_hw_mdp *hw_mdptop;
758 struct drm_encoder *drm_enc;
759 struct dpu_encoder_phys *phys_enc;
760 int i;
761
762 if (!dpu_enc || !disp_info) {
763 DPU_ERROR("invalid param dpu_enc:%d or disp_info:%d\n",
764 dpu_enc != NULL, disp_info != NULL);
765 return;
766 } else if (dpu_enc->num_phys_encs > ARRAY_SIZE(dpu_enc->hw_pp)) {
767 DPU_ERROR("invalid num phys enc %d/%d\n",
768 dpu_enc->num_phys_encs,
769 (int) ARRAY_SIZE(dpu_enc->hw_pp));
770 return;
771 }
772
773 drm_enc = &dpu_enc->base;
774 /* this pointers are checked in virt_enable_helper */
775 priv = drm_enc->dev->dev_private;
776
777 dpu_kms = to_dpu_kms(priv->kms);
778 hw_mdptop = dpu_kms->hw_mdp;
779 if (!hw_mdptop) {
780 DPU_ERROR("invalid mdptop\n");
781 return;
782 }
783
784 if (hw_mdptop->ops.setup_vsync_source) {
785 for (i = 0; i < dpu_enc->num_phys_encs; i++)
786 vsync_cfg.ppnumber[i] = dpu_enc->hw_pp[i]->idx;
787
788 vsync_cfg.pp_count = dpu_enc->num_phys_encs;
789 vsync_cfg.frame_rate = drm_mode_vrefresh(&dpu_enc->base.crtc->state->adjusted_mode);
790
791 vsync_cfg.vsync_source = disp_info->vsync_source;
792
793 hw_mdptop->ops.setup_vsync_source(hw_mdptop, &vsync_cfg);
794
795 for (i = 0; i < dpu_enc->num_phys_encs; i++) {
796 phys_enc = dpu_enc->phys_encs[i];
797
798 if (phys_enc->has_intf_te && phys_enc->hw_intf->ops.vsync_sel)
799 phys_enc->hw_intf->ops.vsync_sel(phys_enc->hw_intf,
800 vsync_cfg.vsync_source);
801 }
802 }
803 }
804
_dpu_encoder_irq_enable(struct drm_encoder * drm_enc)805 static void _dpu_encoder_irq_enable(struct drm_encoder *drm_enc)
806 {
807 struct dpu_encoder_virt *dpu_enc;
808 int i;
809
810 if (!drm_enc) {
811 DPU_ERROR("invalid encoder\n");
812 return;
813 }
814
815 dpu_enc = to_dpu_encoder_virt(drm_enc);
816
817 DPU_DEBUG_ENC(dpu_enc, "\n");
818 for (i = 0; i < dpu_enc->num_phys_encs; i++) {
819 struct dpu_encoder_phys *phys = dpu_enc->phys_encs[i];
820
821 phys->ops.irq_enable(phys);
822 }
823 }
824
_dpu_encoder_irq_disable(struct drm_encoder * drm_enc)825 static void _dpu_encoder_irq_disable(struct drm_encoder *drm_enc)
826 {
827 struct dpu_encoder_virt *dpu_enc;
828 int i;
829
830 if (!drm_enc) {
831 DPU_ERROR("invalid encoder\n");
832 return;
833 }
834
835 dpu_enc = to_dpu_encoder_virt(drm_enc);
836
837 DPU_DEBUG_ENC(dpu_enc, "\n");
838 for (i = 0; i < dpu_enc->num_phys_encs; i++) {
839 struct dpu_encoder_phys *phys = dpu_enc->phys_encs[i];
840
841 phys->ops.irq_disable(phys);
842 }
843 }
844
_dpu_encoder_resource_enable(struct drm_encoder * drm_enc)845 static void _dpu_encoder_resource_enable(struct drm_encoder *drm_enc)
846 {
847 struct msm_drm_private *priv;
848 struct dpu_kms *dpu_kms;
849 struct dpu_encoder_virt *dpu_enc;
850
851 dpu_enc = to_dpu_encoder_virt(drm_enc);
852 priv = drm_enc->dev->dev_private;
853 dpu_kms = to_dpu_kms(priv->kms);
854
855 trace_dpu_enc_rc_enable(DRMID(drm_enc));
856
857 if (!dpu_enc->cur_master) {
858 DPU_ERROR("encoder master not set\n");
859 return;
860 }
861
862 /* enable DPU core clks */
863 pm_runtime_get_sync(&dpu_kms->pdev->dev);
864
865 /* enable all the irq */
866 _dpu_encoder_irq_enable(drm_enc);
867 }
868
_dpu_encoder_resource_disable(struct drm_encoder * drm_enc)869 static void _dpu_encoder_resource_disable(struct drm_encoder *drm_enc)
870 {
871 struct msm_drm_private *priv;
872 struct dpu_kms *dpu_kms;
873 struct dpu_encoder_virt *dpu_enc;
874
875 dpu_enc = to_dpu_encoder_virt(drm_enc);
876 priv = drm_enc->dev->dev_private;
877 dpu_kms = to_dpu_kms(priv->kms);
878
879 trace_dpu_enc_rc_disable(DRMID(drm_enc));
880
881 if (!dpu_enc->cur_master) {
882 DPU_ERROR("encoder master not set\n");
883 return;
884 }
885
886 /* disable all the irq */
887 _dpu_encoder_irq_disable(drm_enc);
888
889 /* disable DPU core clks */
890 pm_runtime_put_sync(&dpu_kms->pdev->dev);
891 }
892
dpu_encoder_resource_control(struct drm_encoder * drm_enc,u32 sw_event)893 static int dpu_encoder_resource_control(struct drm_encoder *drm_enc,
894 u32 sw_event)
895 {
896 struct dpu_encoder_virt *dpu_enc;
897 struct msm_drm_private *priv;
898 bool is_vid_mode = false;
899
900 if (!drm_enc || !drm_enc->dev || !drm_enc->crtc) {
901 DPU_ERROR("invalid parameters\n");
902 return -EINVAL;
903 }
904 dpu_enc = to_dpu_encoder_virt(drm_enc);
905 priv = drm_enc->dev->dev_private;
906 is_vid_mode = !dpu_enc->disp_info.is_cmd_mode;
907
908 /*
909 * when idle_pc is not supported, process only KICKOFF, STOP and MODESET
910 * events and return early for other events (ie wb display).
911 */
912 if (!dpu_enc->idle_pc_supported &&
913 (sw_event != DPU_ENC_RC_EVENT_KICKOFF &&
914 sw_event != DPU_ENC_RC_EVENT_STOP &&
915 sw_event != DPU_ENC_RC_EVENT_PRE_STOP))
916 return 0;
917
918 trace_dpu_enc_rc(DRMID(drm_enc), sw_event, dpu_enc->idle_pc_supported,
919 dpu_enc->rc_state, "begin");
920
921 switch (sw_event) {
922 case DPU_ENC_RC_EVENT_KICKOFF:
923 /* cancel delayed off work, if any */
924 if (cancel_delayed_work_sync(&dpu_enc->delayed_off_work))
925 DPU_DEBUG_ENC(dpu_enc, "sw_event:%d, work cancelled\n",
926 sw_event);
927
928 mutex_lock(&dpu_enc->rc_lock);
929
930 /* return if the resource control is already in ON state */
931 if (dpu_enc->rc_state == DPU_ENC_RC_STATE_ON) {
932 DRM_DEBUG_ATOMIC("id;%u, sw_event:%d, rc in ON state\n",
933 DRMID(drm_enc), sw_event);
934 mutex_unlock(&dpu_enc->rc_lock);
935 return 0;
936 } else if (dpu_enc->rc_state != DPU_ENC_RC_STATE_OFF &&
937 dpu_enc->rc_state != DPU_ENC_RC_STATE_IDLE) {
938 DRM_DEBUG_ATOMIC("id;%u, sw_event:%d, rc in state %d\n",
939 DRMID(drm_enc), sw_event,
940 dpu_enc->rc_state);
941 mutex_unlock(&dpu_enc->rc_lock);
942 return -EINVAL;
943 }
944
945 if (is_vid_mode && dpu_enc->rc_state == DPU_ENC_RC_STATE_IDLE)
946 _dpu_encoder_irq_enable(drm_enc);
947 else
948 _dpu_encoder_resource_enable(drm_enc);
949
950 dpu_enc->rc_state = DPU_ENC_RC_STATE_ON;
951
952 trace_dpu_enc_rc(DRMID(drm_enc), sw_event,
953 dpu_enc->idle_pc_supported, dpu_enc->rc_state,
954 "kickoff");
955
956 mutex_unlock(&dpu_enc->rc_lock);
957 break;
958
959 case DPU_ENC_RC_EVENT_FRAME_DONE:
960 /*
961 * mutex lock is not used as this event happens at interrupt
962 * context. And locking is not required as, the other events
963 * like KICKOFF and STOP does a wait-for-idle before executing
964 * the resource_control
965 */
966 if (dpu_enc->rc_state != DPU_ENC_RC_STATE_ON) {
967 DRM_DEBUG_KMS("id:%d, sw_event:%d,rc:%d-unexpected\n",
968 DRMID(drm_enc), sw_event,
969 dpu_enc->rc_state);
970 return -EINVAL;
971 }
972
973 /*
974 * schedule off work item only when there are no
975 * frames pending
976 */
977 if (dpu_crtc_frame_pending(drm_enc->crtc) > 1) {
978 DRM_DEBUG_KMS("id:%d skip schedule work\n",
979 DRMID(drm_enc));
980 return 0;
981 }
982
983 queue_delayed_work(priv->wq, &dpu_enc->delayed_off_work,
984 msecs_to_jiffies(dpu_enc->idle_timeout));
985
986 trace_dpu_enc_rc(DRMID(drm_enc), sw_event,
987 dpu_enc->idle_pc_supported, dpu_enc->rc_state,
988 "frame done");
989 break;
990
991 case DPU_ENC_RC_EVENT_PRE_STOP:
992 /* cancel delayed off work, if any */
993 if (cancel_delayed_work_sync(&dpu_enc->delayed_off_work))
994 DPU_DEBUG_ENC(dpu_enc, "sw_event:%d, work cancelled\n",
995 sw_event);
996
997 mutex_lock(&dpu_enc->rc_lock);
998
999 if (is_vid_mode &&
1000 dpu_enc->rc_state == DPU_ENC_RC_STATE_IDLE) {
1001 _dpu_encoder_irq_enable(drm_enc);
1002 }
1003 /* skip if is already OFF or IDLE, resources are off already */
1004 else if (dpu_enc->rc_state == DPU_ENC_RC_STATE_OFF ||
1005 dpu_enc->rc_state == DPU_ENC_RC_STATE_IDLE) {
1006 DRM_DEBUG_KMS("id:%u, sw_event:%d, rc in %d state\n",
1007 DRMID(drm_enc), sw_event,
1008 dpu_enc->rc_state);
1009 mutex_unlock(&dpu_enc->rc_lock);
1010 return 0;
1011 }
1012
1013 dpu_enc->rc_state = DPU_ENC_RC_STATE_PRE_OFF;
1014
1015 trace_dpu_enc_rc(DRMID(drm_enc), sw_event,
1016 dpu_enc->idle_pc_supported, dpu_enc->rc_state,
1017 "pre stop");
1018
1019 mutex_unlock(&dpu_enc->rc_lock);
1020 break;
1021
1022 case DPU_ENC_RC_EVENT_STOP:
1023 mutex_lock(&dpu_enc->rc_lock);
1024
1025 /* return if the resource control is already in OFF state */
1026 if (dpu_enc->rc_state == DPU_ENC_RC_STATE_OFF) {
1027 DRM_DEBUG_KMS("id: %u, sw_event:%d, rc in OFF state\n",
1028 DRMID(drm_enc), sw_event);
1029 mutex_unlock(&dpu_enc->rc_lock);
1030 return 0;
1031 } else if (dpu_enc->rc_state == DPU_ENC_RC_STATE_ON) {
1032 DRM_ERROR("id: %u, sw_event:%d, rc in state %d\n",
1033 DRMID(drm_enc), sw_event, dpu_enc->rc_state);
1034 mutex_unlock(&dpu_enc->rc_lock);
1035 return -EINVAL;
1036 }
1037
1038 /**
1039 * expect to arrive here only if in either idle state or pre-off
1040 * and in IDLE state the resources are already disabled
1041 */
1042 if (dpu_enc->rc_state == DPU_ENC_RC_STATE_PRE_OFF)
1043 _dpu_encoder_resource_disable(drm_enc);
1044
1045 dpu_enc->rc_state = DPU_ENC_RC_STATE_OFF;
1046
1047 trace_dpu_enc_rc(DRMID(drm_enc), sw_event,
1048 dpu_enc->idle_pc_supported, dpu_enc->rc_state,
1049 "stop");
1050
1051 mutex_unlock(&dpu_enc->rc_lock);
1052 break;
1053
1054 case DPU_ENC_RC_EVENT_ENTER_IDLE:
1055 mutex_lock(&dpu_enc->rc_lock);
1056
1057 if (dpu_enc->rc_state != DPU_ENC_RC_STATE_ON) {
1058 DRM_ERROR("id: %u, sw_event:%d, rc:%d !ON state\n",
1059 DRMID(drm_enc), sw_event, dpu_enc->rc_state);
1060 mutex_unlock(&dpu_enc->rc_lock);
1061 return 0;
1062 }
1063
1064 /*
1065 * if we are in ON but a frame was just kicked off,
1066 * ignore the IDLE event, it's probably a stale timer event
1067 */
1068 if (dpu_enc->frame_busy_mask[0]) {
1069 DRM_ERROR("id:%u, sw_event:%d, rc:%d frame pending\n",
1070 DRMID(drm_enc), sw_event, dpu_enc->rc_state);
1071 mutex_unlock(&dpu_enc->rc_lock);
1072 return 0;
1073 }
1074
1075 if (is_vid_mode)
1076 _dpu_encoder_irq_disable(drm_enc);
1077 else
1078 _dpu_encoder_resource_disable(drm_enc);
1079
1080 dpu_enc->rc_state = DPU_ENC_RC_STATE_IDLE;
1081
1082 trace_dpu_enc_rc(DRMID(drm_enc), sw_event,
1083 dpu_enc->idle_pc_supported, dpu_enc->rc_state,
1084 "idle");
1085
1086 mutex_unlock(&dpu_enc->rc_lock);
1087 break;
1088
1089 default:
1090 DRM_ERROR("id:%u, unexpected sw_event: %d\n", DRMID(drm_enc),
1091 sw_event);
1092 trace_dpu_enc_rc(DRMID(drm_enc), sw_event,
1093 dpu_enc->idle_pc_supported, dpu_enc->rc_state,
1094 "error");
1095 break;
1096 }
1097
1098 trace_dpu_enc_rc(DRMID(drm_enc), sw_event,
1099 dpu_enc->idle_pc_supported, dpu_enc->rc_state,
1100 "end");
1101 return 0;
1102 }
1103
1104 /**
1105 * dpu_encoder_prepare_wb_job - prepare writeback job for the encoder.
1106 * @drm_enc: Pointer to previously created drm encoder structure
1107 * @job: Pointer to the current drm writeback job
1108 */
dpu_encoder_prepare_wb_job(struct drm_encoder * drm_enc,struct drm_writeback_job * job)1109 void dpu_encoder_prepare_wb_job(struct drm_encoder *drm_enc,
1110 struct drm_writeback_job *job)
1111 {
1112 struct dpu_encoder_virt *dpu_enc;
1113 int i;
1114
1115 dpu_enc = to_dpu_encoder_virt(drm_enc);
1116
1117 for (i = 0; i < dpu_enc->num_phys_encs; i++) {
1118 struct dpu_encoder_phys *phys = dpu_enc->phys_encs[i];
1119
1120 if (phys->ops.prepare_wb_job)
1121 phys->ops.prepare_wb_job(phys, job);
1122
1123 }
1124 }
1125
1126 /**
1127 * dpu_encoder_cleanup_wb_job - cleanup writeback job for the encoder.
1128 * @drm_enc: Pointer to previously created drm encoder structure
1129 * @job: Pointer to the current drm writeback job
1130 */
dpu_encoder_cleanup_wb_job(struct drm_encoder * drm_enc,struct drm_writeback_job * job)1131 void dpu_encoder_cleanup_wb_job(struct drm_encoder *drm_enc,
1132 struct drm_writeback_job *job)
1133 {
1134 struct dpu_encoder_virt *dpu_enc;
1135 int i;
1136
1137 dpu_enc = to_dpu_encoder_virt(drm_enc);
1138
1139 for (i = 0; i < dpu_enc->num_phys_encs; i++) {
1140 struct dpu_encoder_phys *phys = dpu_enc->phys_encs[i];
1141
1142 if (phys->ops.cleanup_wb_job)
1143 phys->ops.cleanup_wb_job(phys, job);
1144
1145 }
1146 }
1147
dpu_encoder_virt_atomic_mode_set(struct drm_encoder * drm_enc,struct drm_crtc_state * crtc_state,struct drm_connector_state * conn_state)1148 static void dpu_encoder_virt_atomic_mode_set(struct drm_encoder *drm_enc,
1149 struct drm_crtc_state *crtc_state,
1150 struct drm_connector_state *conn_state)
1151 {
1152 struct dpu_encoder_virt *dpu_enc;
1153 struct msm_drm_private *priv;
1154 struct dpu_kms *dpu_kms;
1155 struct dpu_global_state *global_state;
1156 struct dpu_hw_blk *hw_pp[MAX_CHANNELS_PER_ENC];
1157 struct dpu_hw_blk *hw_ctl[MAX_CHANNELS_PER_ENC];
1158 struct dpu_hw_blk *hw_dsc[MAX_CHANNELS_PER_ENC];
1159 struct dpu_hw_blk *hw_cwb[MAX_CHANNELS_PER_ENC];
1160 int num_ctl, num_pp, num_dsc;
1161 int num_cwb = 0;
1162 bool is_cwb_encoder;
1163 unsigned int dsc_mask = 0;
1164 unsigned int cwb_mask = 0;
1165 int i;
1166
1167 if (!drm_enc) {
1168 DPU_ERROR("invalid encoder\n");
1169 return;
1170 }
1171
1172 dpu_enc = to_dpu_encoder_virt(drm_enc);
1173 DPU_DEBUG_ENC(dpu_enc, "\n");
1174
1175 priv = drm_enc->dev->dev_private;
1176 dpu_kms = to_dpu_kms(priv->kms);
1177 is_cwb_encoder = drm_crtc_in_clone_mode(crtc_state) &&
1178 dpu_enc->disp_info.intf_type == INTF_WB;
1179
1180 global_state = dpu_kms_get_existing_global_state(dpu_kms);
1181 if (IS_ERR_OR_NULL(global_state)) {
1182 DPU_ERROR("Failed to get global state");
1183 return;
1184 }
1185
1186 trace_dpu_enc_mode_set(DRMID(drm_enc));
1187
1188 /* Query resource that have been reserved in atomic check step. */
1189 if (is_cwb_encoder) {
1190 num_pp = dpu_rm_get_assigned_resources(&dpu_kms->rm, global_state,
1191 drm_enc->crtc,
1192 DPU_HW_BLK_DCWB_PINGPONG,
1193 hw_pp, ARRAY_SIZE(hw_pp));
1194 num_cwb = dpu_rm_get_assigned_resources(&dpu_kms->rm, global_state,
1195 drm_enc->crtc,
1196 DPU_HW_BLK_CWB,
1197 hw_cwb, ARRAY_SIZE(hw_cwb));
1198 } else {
1199 num_pp = dpu_rm_get_assigned_resources(&dpu_kms->rm, global_state,
1200 drm_enc->crtc,
1201 DPU_HW_BLK_PINGPONG, hw_pp,
1202 ARRAY_SIZE(hw_pp));
1203 }
1204
1205 for (i = 0; i < num_cwb; i++) {
1206 dpu_enc->hw_cwb[i] = to_dpu_hw_cwb(hw_cwb[i]);
1207 cwb_mask |= BIT(dpu_enc->hw_cwb[i]->idx - CWB_0);
1208 }
1209
1210 dpu_enc->cwb_mask = cwb_mask;
1211
1212 num_ctl = dpu_rm_get_assigned_resources(&dpu_kms->rm, global_state,
1213 drm_enc->crtc, DPU_HW_BLK_CTL, hw_ctl, ARRAY_SIZE(hw_ctl));
1214
1215 for (i = 0; i < MAX_CHANNELS_PER_ENC; i++)
1216 dpu_enc->hw_pp[i] = i < num_pp ? to_dpu_hw_pingpong(hw_pp[i])
1217 : NULL;
1218
1219 num_dsc = dpu_rm_get_assigned_resources(&dpu_kms->rm, global_state,
1220 drm_enc->crtc, DPU_HW_BLK_DSC,
1221 hw_dsc, ARRAY_SIZE(hw_dsc));
1222 for (i = 0; i < num_dsc; i++) {
1223 dpu_enc->hw_dsc[i] = to_dpu_hw_dsc(hw_dsc[i]);
1224 dsc_mask |= BIT(dpu_enc->hw_dsc[i]->idx - DSC_0);
1225 }
1226
1227 dpu_enc->dsc_mask = dsc_mask;
1228
1229 if ((dpu_enc->disp_info.intf_type == INTF_WB && conn_state->writeback_job) ||
1230 dpu_enc->disp_info.intf_type == INTF_DP) {
1231 struct dpu_hw_blk *hw_cdm = NULL;
1232
1233 dpu_rm_get_assigned_resources(&dpu_kms->rm, global_state,
1234 drm_enc->crtc, DPU_HW_BLK_CDM,
1235 &hw_cdm, 1);
1236 dpu_enc->cur_master->hw_cdm = hw_cdm ? to_dpu_hw_cdm(hw_cdm) : NULL;
1237 }
1238
1239 for (i = 0; i < dpu_enc->num_phys_encs; i++) {
1240 struct dpu_encoder_phys *phys = dpu_enc->phys_encs[i];
1241
1242 phys->hw_pp = dpu_enc->hw_pp[i];
1243 if (!phys->hw_pp) {
1244 DPU_ERROR_ENC(dpu_enc,
1245 "no pp block assigned at idx: %d\n", i);
1246 return;
1247 }
1248
1249 phys->hw_ctl = i < num_ctl ? to_dpu_hw_ctl(hw_ctl[i]) : NULL;
1250 if (!phys->hw_ctl) {
1251 DPU_ERROR_ENC(dpu_enc,
1252 "no ctl block assigned at idx: %d\n", i);
1253 return;
1254 }
1255
1256 phys->cached_mode = crtc_state->adjusted_mode;
1257 if (phys->ops.atomic_mode_set)
1258 phys->ops.atomic_mode_set(phys, crtc_state, conn_state);
1259 }
1260 }
1261
_dpu_encoder_virt_enable_helper(struct drm_encoder * drm_enc)1262 static void _dpu_encoder_virt_enable_helper(struct drm_encoder *drm_enc)
1263 {
1264 struct dpu_encoder_virt *dpu_enc = NULL;
1265 int i;
1266
1267 if (!drm_enc || !drm_enc->dev) {
1268 DPU_ERROR("invalid parameters\n");
1269 return;
1270 }
1271
1272 dpu_enc = to_dpu_encoder_virt(drm_enc);
1273 if (!dpu_enc || !dpu_enc->cur_master) {
1274 DPU_ERROR("invalid dpu encoder/master\n");
1275 return;
1276 }
1277
1278
1279 if (dpu_enc->disp_info.intf_type == INTF_DP &&
1280 dpu_enc->cur_master->hw_mdptop &&
1281 dpu_enc->cur_master->hw_mdptop->ops.intf_audio_select)
1282 dpu_enc->cur_master->hw_mdptop->ops.intf_audio_select(
1283 dpu_enc->cur_master->hw_mdptop);
1284
1285 if (dpu_enc->disp_info.is_cmd_mode)
1286 _dpu_encoder_update_vsync_source(dpu_enc, &dpu_enc->disp_info);
1287
1288 if (dpu_enc->disp_info.intf_type == INTF_DSI &&
1289 !WARN_ON(dpu_enc->num_phys_encs == 0)) {
1290 unsigned bpc = dpu_enc->connector->display_info.bpc;
1291 for (i = 0; i < MAX_CHANNELS_PER_ENC; i++) {
1292 if (!dpu_enc->hw_pp[i])
1293 continue;
1294 _dpu_encoder_setup_dither(dpu_enc->hw_pp[i], bpc);
1295 }
1296 }
1297 }
1298
1299 /**
1300 * dpu_encoder_virt_runtime_resume - pm runtime resume the encoder configs
1301 * @drm_enc: encoder pointer
1302 */
dpu_encoder_virt_runtime_resume(struct drm_encoder * drm_enc)1303 void dpu_encoder_virt_runtime_resume(struct drm_encoder *drm_enc)
1304 {
1305 struct dpu_encoder_virt *dpu_enc = to_dpu_encoder_virt(drm_enc);
1306
1307 mutex_lock(&dpu_enc->enc_lock);
1308
1309 if (!dpu_enc->enabled)
1310 goto out;
1311
1312 if (dpu_enc->cur_slave && dpu_enc->cur_slave->ops.restore)
1313 dpu_enc->cur_slave->ops.restore(dpu_enc->cur_slave);
1314 if (dpu_enc->cur_master && dpu_enc->cur_master->ops.restore)
1315 dpu_enc->cur_master->ops.restore(dpu_enc->cur_master);
1316
1317 _dpu_encoder_virt_enable_helper(drm_enc);
1318
1319 out:
1320 mutex_unlock(&dpu_enc->enc_lock);
1321 }
1322
dpu_encoder_virt_atomic_enable(struct drm_encoder * drm_enc,struct drm_atomic_state * state)1323 static void dpu_encoder_virt_atomic_enable(struct drm_encoder *drm_enc,
1324 struct drm_atomic_state *state)
1325 {
1326 struct dpu_encoder_virt *dpu_enc = NULL;
1327 int ret = 0;
1328 struct drm_display_mode *cur_mode = NULL;
1329
1330 dpu_enc = to_dpu_encoder_virt(drm_enc);
1331 dpu_enc->dsc = dpu_encoder_get_dsc_config(drm_enc);
1332
1333 atomic_set(&dpu_enc->frame_done_timeout_cnt, 0);
1334
1335 mutex_lock(&dpu_enc->enc_lock);
1336
1337 dpu_enc->commit_done_timedout = false;
1338
1339 dpu_enc->connector = drm_atomic_get_new_connector_for_encoder(state, drm_enc);
1340
1341 cur_mode = &dpu_enc->base.crtc->state->adjusted_mode;
1342
1343 dpu_enc->wide_bus_en = dpu_encoder_is_widebus_enabled(drm_enc);
1344
1345 trace_dpu_enc_enable(DRMID(drm_enc), cur_mode->hdisplay,
1346 cur_mode->vdisplay);
1347
1348 /* always enable slave encoder before master */
1349 if (dpu_enc->cur_slave && dpu_enc->cur_slave->ops.enable)
1350 dpu_enc->cur_slave->ops.enable(dpu_enc->cur_slave);
1351
1352 if (dpu_enc->cur_master && dpu_enc->cur_master->ops.enable)
1353 dpu_enc->cur_master->ops.enable(dpu_enc->cur_master);
1354
1355 ret = dpu_encoder_resource_control(drm_enc, DPU_ENC_RC_EVENT_KICKOFF);
1356 if (ret) {
1357 DPU_ERROR_ENC(dpu_enc, "dpu resource control failed: %d\n",
1358 ret);
1359 goto out;
1360 }
1361
1362 _dpu_encoder_virt_enable_helper(drm_enc);
1363
1364 dpu_enc->enabled = true;
1365
1366 out:
1367 mutex_unlock(&dpu_enc->enc_lock);
1368 }
1369
dpu_encoder_virt_atomic_disable(struct drm_encoder * drm_enc,struct drm_atomic_state * state)1370 static void dpu_encoder_virt_atomic_disable(struct drm_encoder *drm_enc,
1371 struct drm_atomic_state *state)
1372 {
1373 struct dpu_encoder_virt *dpu_enc = NULL;
1374 struct drm_crtc *crtc;
1375 struct drm_crtc_state *old_state = NULL;
1376 int i = 0;
1377
1378 dpu_enc = to_dpu_encoder_virt(drm_enc);
1379 DPU_DEBUG_ENC(dpu_enc, "\n");
1380
1381 crtc = drm_atomic_get_old_crtc_for_encoder(state, drm_enc);
1382 if (crtc)
1383 old_state = drm_atomic_get_old_crtc_state(state, crtc);
1384
1385 /*
1386 * The encoder is already disabled if self refresh mode was set earlier,
1387 * in the old_state for the corresponding crtc.
1388 */
1389 if (old_state && old_state->self_refresh_active)
1390 return;
1391
1392 mutex_lock(&dpu_enc->enc_lock);
1393 dpu_enc->enabled = false;
1394
1395 trace_dpu_enc_disable(DRMID(drm_enc));
1396
1397 /* wait for idle */
1398 dpu_encoder_wait_for_tx_complete(drm_enc);
1399
1400 dpu_encoder_resource_control(drm_enc, DPU_ENC_RC_EVENT_PRE_STOP);
1401
1402 for (i = 0; i < dpu_enc->num_phys_encs; i++) {
1403 struct dpu_encoder_phys *phys = dpu_enc->phys_encs[i];
1404
1405 if (phys->ops.disable)
1406 phys->ops.disable(phys);
1407 }
1408
1409
1410 /* after phys waits for frame-done, should be no more frames pending */
1411 if (atomic_xchg(&dpu_enc->frame_done_timeout_ms, 0)) {
1412 DPU_ERROR("enc%d timeout pending\n", drm_enc->base.id);
1413 timer_delete_sync(&dpu_enc->frame_done_timer);
1414 }
1415
1416 dpu_encoder_resource_control(drm_enc, DPU_ENC_RC_EVENT_STOP);
1417
1418 dpu_enc->connector = NULL;
1419
1420 DPU_DEBUG_ENC(dpu_enc, "encoder disabled\n");
1421
1422 mutex_unlock(&dpu_enc->enc_lock);
1423 }
1424
dpu_encoder_get_intf(const struct dpu_mdss_cfg * catalog,struct dpu_rm * dpu_rm,enum dpu_intf_type type,u32 controller_id)1425 static struct dpu_hw_intf *dpu_encoder_get_intf(const struct dpu_mdss_cfg *catalog,
1426 struct dpu_rm *dpu_rm,
1427 enum dpu_intf_type type, u32 controller_id)
1428 {
1429 int i = 0;
1430
1431 if (type == INTF_WB)
1432 return NULL;
1433
1434 for (i = 0; i < catalog->intf_count; i++) {
1435 if (catalog->intf[i].type == type
1436 && catalog->intf[i].controller_id == controller_id) {
1437 return dpu_rm_get_intf(dpu_rm, catalog->intf[i].id);
1438 }
1439 }
1440
1441 return NULL;
1442 }
1443
1444 /**
1445 * dpu_encoder_vblank_callback - Notify virtual encoder of vblank IRQ reception
1446 * @drm_enc: Pointer to drm encoder structure
1447 * @phy_enc: Pointer to physical encoder
1448 * Note: This is called from IRQ handler context.
1449 */
dpu_encoder_vblank_callback(struct drm_encoder * drm_enc,struct dpu_encoder_phys * phy_enc)1450 void dpu_encoder_vblank_callback(struct drm_encoder *drm_enc,
1451 struct dpu_encoder_phys *phy_enc)
1452 {
1453 struct dpu_encoder_virt *dpu_enc = NULL;
1454 unsigned long lock_flags;
1455
1456 if (!drm_enc || !phy_enc)
1457 return;
1458
1459 DPU_ATRACE_BEGIN("encoder_vblank_callback");
1460 dpu_enc = to_dpu_encoder_virt(drm_enc);
1461
1462 atomic_inc(&phy_enc->vsync_cnt);
1463
1464 spin_lock_irqsave(&dpu_enc->enc_spinlock, lock_flags);
1465 if (dpu_enc->crtc)
1466 dpu_crtc_vblank_callback(dpu_enc->crtc);
1467 spin_unlock_irqrestore(&dpu_enc->enc_spinlock, lock_flags);
1468
1469 DPU_ATRACE_END("encoder_vblank_callback");
1470 }
1471
1472 /**
1473 * dpu_encoder_underrun_callback - Notify virtual encoder of underrun IRQ reception
1474 * @drm_enc: Pointer to drm encoder structure
1475 * @phy_enc: Pointer to physical encoder
1476 * Note: This is called from IRQ handler context.
1477 */
dpu_encoder_underrun_callback(struct drm_encoder * drm_enc,struct dpu_encoder_phys * phy_enc)1478 void dpu_encoder_underrun_callback(struct drm_encoder *drm_enc,
1479 struct dpu_encoder_phys *phy_enc)
1480 {
1481 if (!phy_enc)
1482 return;
1483
1484 DPU_ATRACE_BEGIN("encoder_underrun_callback");
1485 atomic_inc(&phy_enc->underrun_cnt);
1486
1487 /* trigger dump only on the first underrun */
1488 if (atomic_read(&phy_enc->underrun_cnt) == 1)
1489 msm_disp_snapshot_state(drm_enc->dev);
1490
1491 trace_dpu_enc_underrun_cb(DRMID(drm_enc),
1492 atomic_read(&phy_enc->underrun_cnt));
1493 DPU_ATRACE_END("encoder_underrun_callback");
1494 }
1495
1496 /**
1497 * dpu_encoder_assign_crtc - Link the encoder to the crtc it's assigned to
1498 * @drm_enc: encoder pointer
1499 * @crtc: crtc pointer
1500 */
dpu_encoder_assign_crtc(struct drm_encoder * drm_enc,struct drm_crtc * crtc)1501 void dpu_encoder_assign_crtc(struct drm_encoder *drm_enc, struct drm_crtc *crtc)
1502 {
1503 struct dpu_encoder_virt *dpu_enc = to_dpu_encoder_virt(drm_enc);
1504 unsigned long lock_flags;
1505
1506 spin_lock_irqsave(&dpu_enc->enc_spinlock, lock_flags);
1507 /* crtc should always be cleared before re-assigning */
1508 WARN_ON(crtc && dpu_enc->crtc);
1509 dpu_enc->crtc = crtc;
1510 spin_unlock_irqrestore(&dpu_enc->enc_spinlock, lock_flags);
1511 }
1512
1513 /**
1514 * dpu_encoder_toggle_vblank_for_crtc - Toggles vblank interrupts on or off if
1515 * the encoder is assigned to the given crtc
1516 * @drm_enc: encoder pointer
1517 * @crtc: crtc pointer
1518 * @enable: true if vblank should be enabled
1519 */
dpu_encoder_toggle_vblank_for_crtc(struct drm_encoder * drm_enc,struct drm_crtc * crtc,bool enable)1520 void dpu_encoder_toggle_vblank_for_crtc(struct drm_encoder *drm_enc,
1521 struct drm_crtc *crtc, bool enable)
1522 {
1523 struct dpu_encoder_virt *dpu_enc = to_dpu_encoder_virt(drm_enc);
1524 unsigned long lock_flags;
1525 int i;
1526
1527 trace_dpu_enc_vblank_cb(DRMID(drm_enc), enable);
1528
1529 spin_lock_irqsave(&dpu_enc->enc_spinlock, lock_flags);
1530 if (dpu_enc->crtc != crtc) {
1531 spin_unlock_irqrestore(&dpu_enc->enc_spinlock, lock_flags);
1532 return;
1533 }
1534 spin_unlock_irqrestore(&dpu_enc->enc_spinlock, lock_flags);
1535
1536 for (i = 0; i < dpu_enc->num_phys_encs; i++) {
1537 struct dpu_encoder_phys *phys = dpu_enc->phys_encs[i];
1538
1539 if (phys->ops.control_vblank_irq)
1540 phys->ops.control_vblank_irq(phys, enable);
1541 }
1542 }
1543
1544 /**
1545 * dpu_encoder_frame_done_callback - Notify virtual encoder that this phys
1546 * encoder completes last request frame
1547 * @drm_enc: Pointer to drm encoder structure
1548 * @ready_phys: Pointer to physical encoder
1549 * @event: Event to process
1550 */
dpu_encoder_frame_done_callback(struct drm_encoder * drm_enc,struct dpu_encoder_phys * ready_phys,u32 event)1551 void dpu_encoder_frame_done_callback(
1552 struct drm_encoder *drm_enc,
1553 struct dpu_encoder_phys *ready_phys, u32 event)
1554 {
1555 struct dpu_encoder_virt *dpu_enc = to_dpu_encoder_virt(drm_enc);
1556 unsigned int i;
1557
1558 if (event & (DPU_ENCODER_FRAME_EVENT_DONE
1559 | DPU_ENCODER_FRAME_EVENT_ERROR
1560 | DPU_ENCODER_FRAME_EVENT_PANEL_DEAD)) {
1561
1562 if (!dpu_enc->frame_busy_mask[0]) {
1563 /**
1564 * suppress frame_done without waiter,
1565 * likely autorefresh
1566 */
1567 trace_dpu_enc_frame_done_cb_not_busy(DRMID(drm_enc), event,
1568 dpu_encoder_helper_get_intf_type(ready_phys->intf_mode),
1569 ready_phys->hw_intf ? ready_phys->hw_intf->idx : -1,
1570 ready_phys->hw_wb ? ready_phys->hw_wb->idx : -1);
1571 return;
1572 }
1573
1574 /* One of the physical encoders has become idle */
1575 for (i = 0; i < dpu_enc->num_phys_encs; i++) {
1576 if (dpu_enc->phys_encs[i] == ready_phys) {
1577 trace_dpu_enc_frame_done_cb(DRMID(drm_enc), i,
1578 dpu_enc->frame_busy_mask[0]);
1579 clear_bit(i, dpu_enc->frame_busy_mask);
1580 }
1581 }
1582
1583 if (!dpu_enc->frame_busy_mask[0]) {
1584 atomic_set(&dpu_enc->frame_done_timeout_ms, 0);
1585 timer_delete(&dpu_enc->frame_done_timer);
1586
1587 dpu_encoder_resource_control(drm_enc,
1588 DPU_ENC_RC_EVENT_FRAME_DONE);
1589
1590 if (dpu_enc->crtc)
1591 dpu_crtc_frame_event_cb(dpu_enc->crtc, event);
1592 }
1593 } else {
1594 if (dpu_enc->crtc)
1595 dpu_crtc_frame_event_cb(dpu_enc->crtc, event);
1596 }
1597 }
1598
dpu_encoder_off_work(struct work_struct * work)1599 static void dpu_encoder_off_work(struct work_struct *work)
1600 {
1601 struct dpu_encoder_virt *dpu_enc = container_of(work,
1602 struct dpu_encoder_virt, delayed_off_work.work);
1603
1604 dpu_encoder_resource_control(&dpu_enc->base,
1605 DPU_ENC_RC_EVENT_ENTER_IDLE);
1606
1607 dpu_encoder_frame_done_callback(&dpu_enc->base, NULL,
1608 DPU_ENCODER_FRAME_EVENT_IDLE);
1609 }
1610
1611 /**
1612 * _dpu_encoder_trigger_flush - trigger flush for a physical encoder
1613 * @drm_enc: Pointer to drm encoder structure
1614 * @phys: Pointer to physical encoder structure
1615 * @extra_flush_bits: Additional bit mask to include in flush trigger
1616 */
_dpu_encoder_trigger_flush(struct drm_encoder * drm_enc,struct dpu_encoder_phys * phys,uint32_t extra_flush_bits)1617 static void _dpu_encoder_trigger_flush(struct drm_encoder *drm_enc,
1618 struct dpu_encoder_phys *phys, uint32_t extra_flush_bits)
1619 {
1620 struct dpu_encoder_virt *dpu_enc = to_dpu_encoder_virt(drm_enc);
1621 struct dpu_hw_ctl *ctl;
1622 int pending_kickoff_cnt;
1623 u32 ret = UINT_MAX;
1624
1625 if (!phys->hw_pp) {
1626 DPU_ERROR("invalid pingpong hw\n");
1627 return;
1628 }
1629
1630 ctl = phys->hw_ctl;
1631 if (!ctl->ops.trigger_flush) {
1632 DPU_ERROR("missing trigger cb\n");
1633 return;
1634 }
1635
1636 pending_kickoff_cnt = dpu_encoder_phys_inc_pending(phys);
1637
1638 /* Return early if encoder is writeback and in clone mode */
1639 if (drm_enc->encoder_type == DRM_MODE_ENCODER_VIRTUAL &&
1640 dpu_enc->cwb_mask) {
1641 DPU_DEBUG("encoder %d skip flush for concurrent writeback encoder\n",
1642 DRMID(drm_enc));
1643 return;
1644 }
1645
1646
1647 if (extra_flush_bits && ctl->ops.update_pending_flush)
1648 ctl->ops.update_pending_flush(ctl, extra_flush_bits);
1649
1650 ctl->ops.trigger_flush(ctl);
1651
1652 if (ctl->ops.get_pending_flush)
1653 ret = ctl->ops.get_pending_flush(ctl);
1654
1655 trace_dpu_enc_trigger_flush(DRMID(drm_enc),
1656 dpu_encoder_helper_get_intf_type(phys->intf_mode),
1657 phys->hw_intf ? phys->hw_intf->idx : -1,
1658 phys->hw_wb ? phys->hw_wb->idx : -1,
1659 pending_kickoff_cnt, ctl->idx,
1660 extra_flush_bits, ret);
1661 }
1662
1663 /**
1664 * _dpu_encoder_trigger_start - trigger start for a physical encoder
1665 * @phys: Pointer to physical encoder structure
1666 */
_dpu_encoder_trigger_start(struct dpu_encoder_phys * phys)1667 static void _dpu_encoder_trigger_start(struct dpu_encoder_phys *phys)
1668 {
1669 struct dpu_encoder_virt *dpu_enc;
1670
1671 if (!phys) {
1672 DPU_ERROR("invalid argument(s)\n");
1673 return;
1674 }
1675
1676 if (!phys->hw_pp) {
1677 DPU_ERROR("invalid pingpong hw\n");
1678 return;
1679 }
1680
1681 dpu_enc = to_dpu_encoder_virt(phys->parent);
1682
1683 if (phys->parent->encoder_type == DRM_MODE_ENCODER_VIRTUAL &&
1684 dpu_enc->cwb_mask) {
1685 DPU_DEBUG("encoder %d CWB enabled, skipping\n", DRMID(phys->parent));
1686 return;
1687 }
1688
1689 if (phys->ops.trigger_start && phys->enable_state != DPU_ENC_DISABLED)
1690 phys->ops.trigger_start(phys);
1691 }
1692
1693 /**
1694 * dpu_encoder_helper_trigger_start - control start helper function
1695 * This helper function may be optionally specified by physical
1696 * encoders if they require ctl_start triggering.
1697 * @phys_enc: Pointer to physical encoder structure
1698 */
dpu_encoder_helper_trigger_start(struct dpu_encoder_phys * phys_enc)1699 void dpu_encoder_helper_trigger_start(struct dpu_encoder_phys *phys_enc)
1700 {
1701 struct dpu_hw_ctl *ctl;
1702
1703 ctl = phys_enc->hw_ctl;
1704 if (ctl->ops.trigger_start) {
1705 ctl->ops.trigger_start(ctl);
1706 trace_dpu_enc_trigger_start(DRMID(phys_enc->parent), ctl->idx);
1707 }
1708 }
1709
dpu_encoder_helper_wait_event_timeout(int32_t drm_id,unsigned int irq_idx,struct dpu_encoder_wait_info * info)1710 static int dpu_encoder_helper_wait_event_timeout(
1711 int32_t drm_id,
1712 unsigned int irq_idx,
1713 struct dpu_encoder_wait_info *info)
1714 {
1715 int rc = 0;
1716 s64 expected_time = ktime_to_ms(ktime_get()) + info->timeout_ms;
1717 s64 jiffies = msecs_to_jiffies(info->timeout_ms);
1718 s64 time;
1719
1720 do {
1721 rc = wait_event_timeout(*(info->wq),
1722 atomic_read(info->atomic_cnt) == 0, jiffies);
1723 time = ktime_to_ms(ktime_get());
1724
1725 trace_dpu_enc_wait_event_timeout(drm_id,
1726 DPU_IRQ_REG(irq_idx), DPU_IRQ_BIT(irq_idx),
1727 rc, time,
1728 expected_time,
1729 atomic_read(info->atomic_cnt));
1730 /* If we timed out, counter is valid and time is less, wait again */
1731 } while (atomic_read(info->atomic_cnt) && (rc == 0) &&
1732 (time < expected_time));
1733
1734 return rc;
1735 }
1736
dpu_encoder_helper_hw_reset(struct dpu_encoder_phys * phys_enc)1737 static void dpu_encoder_helper_hw_reset(struct dpu_encoder_phys *phys_enc)
1738 {
1739 struct dpu_encoder_virt *dpu_enc;
1740 struct dpu_hw_ctl *ctl;
1741 int rc;
1742 struct drm_encoder *drm_enc;
1743
1744 dpu_enc = to_dpu_encoder_virt(phys_enc->parent);
1745 ctl = phys_enc->hw_ctl;
1746 drm_enc = phys_enc->parent;
1747
1748 if (!ctl->ops.reset)
1749 return;
1750
1751 DRM_DEBUG_KMS("id:%u ctl %d reset\n", DRMID(drm_enc),
1752 ctl->idx);
1753
1754 rc = ctl->ops.reset(ctl);
1755 if (rc) {
1756 DPU_ERROR_ENC(dpu_enc, "ctl %d reset failure\n", ctl->idx);
1757 msm_disp_snapshot_state(drm_enc->dev);
1758 }
1759
1760 phys_enc->enable_state = DPU_ENC_ENABLED;
1761 }
1762
1763 /**
1764 * _dpu_encoder_kickoff_phys - handle physical encoder kickoff
1765 * Iterate through the physical encoders and perform consolidated flush
1766 * and/or control start triggering as needed. This is done in the virtual
1767 * encoder rather than the individual physical ones in order to handle
1768 * use cases that require visibility into multiple physical encoders at
1769 * a time.
1770 * @dpu_enc: Pointer to virtual encoder structure
1771 */
_dpu_encoder_kickoff_phys(struct dpu_encoder_virt * dpu_enc)1772 static void _dpu_encoder_kickoff_phys(struct dpu_encoder_virt *dpu_enc)
1773 {
1774 struct dpu_hw_ctl *ctl;
1775 uint32_t i, pending_flush;
1776 unsigned long lock_flags;
1777
1778 pending_flush = 0x0;
1779
1780 /* update pending counts and trigger kickoff ctl flush atomically */
1781 spin_lock_irqsave(&dpu_enc->enc_spinlock, lock_flags);
1782
1783 /* don't perform flush/start operations for slave encoders */
1784 for (i = 0; i < dpu_enc->num_phys_encs; i++) {
1785 struct dpu_encoder_phys *phys = dpu_enc->phys_encs[i];
1786
1787 if (phys->enable_state == DPU_ENC_DISABLED)
1788 continue;
1789
1790 ctl = phys->hw_ctl;
1791
1792 /*
1793 * This is cleared in frame_done worker, which isn't invoked
1794 * for async commits. So don't set this for async, since it'll
1795 * roll over to the next commit.
1796 */
1797 if (phys->split_role != ENC_ROLE_SLAVE)
1798 set_bit(i, dpu_enc->frame_busy_mask);
1799
1800 if (!phys->ops.needs_single_flush ||
1801 !phys->ops.needs_single_flush(phys))
1802 _dpu_encoder_trigger_flush(&dpu_enc->base, phys, 0x0);
1803 else if (ctl->ops.get_pending_flush)
1804 pending_flush |= ctl->ops.get_pending_flush(ctl);
1805 }
1806
1807 /* for split flush, combine pending flush masks and send to master */
1808 if (pending_flush && dpu_enc->cur_master) {
1809 _dpu_encoder_trigger_flush(
1810 &dpu_enc->base,
1811 dpu_enc->cur_master,
1812 pending_flush);
1813 }
1814
1815 _dpu_encoder_trigger_start(dpu_enc->cur_master);
1816
1817 spin_unlock_irqrestore(&dpu_enc->enc_spinlock, lock_flags);
1818 }
1819
1820 /**
1821 * dpu_encoder_trigger_kickoff_pending - Clear the flush bits from previous
1822 * kickoff and trigger the ctl prepare progress for command mode display.
1823 * @drm_enc: encoder pointer
1824 */
dpu_encoder_trigger_kickoff_pending(struct drm_encoder * drm_enc)1825 void dpu_encoder_trigger_kickoff_pending(struct drm_encoder *drm_enc)
1826 {
1827 struct dpu_encoder_virt *dpu_enc;
1828 struct dpu_encoder_phys *phys;
1829 unsigned int i;
1830 struct dpu_hw_ctl *ctl;
1831 struct msm_display_info *disp_info;
1832
1833 if (!drm_enc) {
1834 DPU_ERROR("invalid encoder\n");
1835 return;
1836 }
1837 dpu_enc = to_dpu_encoder_virt(drm_enc);
1838 disp_info = &dpu_enc->disp_info;
1839
1840 for (i = 0; i < dpu_enc->num_phys_encs; i++) {
1841 phys = dpu_enc->phys_encs[i];
1842
1843 ctl = phys->hw_ctl;
1844 ctl->ops.clear_pending_flush(ctl);
1845
1846 /* update only for command mode primary ctl */
1847 if ((phys == dpu_enc->cur_master) &&
1848 disp_info->is_cmd_mode
1849 && ctl->ops.trigger_pending)
1850 ctl->ops.trigger_pending(ctl);
1851 }
1852 }
1853
_dpu_encoder_calculate_linetime(struct dpu_encoder_virt * dpu_enc,struct drm_display_mode * mode)1854 static u32 _dpu_encoder_calculate_linetime(struct dpu_encoder_virt *dpu_enc,
1855 struct drm_display_mode *mode)
1856 {
1857 u64 pclk_rate;
1858 u32 pclk_period;
1859 u32 line_time;
1860
1861 /*
1862 * For linetime calculation, only operate on master encoder.
1863 */
1864 if (!dpu_enc->cur_master)
1865 return 0;
1866
1867 if (!dpu_enc->cur_master->ops.get_line_count) {
1868 DPU_ERROR("get_line_count function not defined\n");
1869 return 0;
1870 }
1871
1872 pclk_rate = mode->clock; /* pixel clock in kHz */
1873 if (pclk_rate == 0) {
1874 DPU_ERROR("pclk is 0, cannot calculate line time\n");
1875 return 0;
1876 }
1877
1878 pclk_period = DIV_ROUND_UP_ULL(1000000000ull, pclk_rate);
1879 if (pclk_period == 0) {
1880 DPU_ERROR("pclk period is 0\n");
1881 return 0;
1882 }
1883
1884 /*
1885 * Line time calculation based on Pixel clock and HTOTAL.
1886 * Final unit is in ns.
1887 */
1888 line_time = (pclk_period * mode->htotal) / 1000;
1889 if (line_time == 0) {
1890 DPU_ERROR("line time calculation is 0\n");
1891 return 0;
1892 }
1893
1894 DPU_DEBUG_ENC(dpu_enc,
1895 "clk_rate=%lldkHz, clk_period=%d, linetime=%dns\n",
1896 pclk_rate, pclk_period, line_time);
1897
1898 return line_time;
1899 }
1900
1901 /**
1902 * dpu_encoder_vsync_time - get the time of the next vsync
1903 * @drm_enc: encoder pointer
1904 * @wakeup_time: pointer to ktime_t to write the vsync time to
1905 */
dpu_encoder_vsync_time(struct drm_encoder * drm_enc,ktime_t * wakeup_time)1906 int dpu_encoder_vsync_time(struct drm_encoder *drm_enc, ktime_t *wakeup_time)
1907 {
1908 struct drm_display_mode *mode;
1909 struct dpu_encoder_virt *dpu_enc;
1910 u32 cur_line;
1911 u32 line_time;
1912 u32 vtotal, time_to_vsync;
1913 ktime_t cur_time;
1914
1915 dpu_enc = to_dpu_encoder_virt(drm_enc);
1916
1917 if (!drm_enc->crtc || !drm_enc->crtc->state) {
1918 DPU_ERROR("crtc/crtc state object is NULL\n");
1919 return -EINVAL;
1920 }
1921 mode = &drm_enc->crtc->state->adjusted_mode;
1922
1923 line_time = _dpu_encoder_calculate_linetime(dpu_enc, mode);
1924 if (!line_time)
1925 return -EINVAL;
1926
1927 cur_line = dpu_enc->cur_master->ops.get_line_count(dpu_enc->cur_master);
1928
1929 vtotal = mode->vtotal;
1930 if (cur_line >= vtotal)
1931 time_to_vsync = line_time * vtotal;
1932 else
1933 time_to_vsync = line_time * (vtotal - cur_line);
1934
1935 if (time_to_vsync == 0) {
1936 DPU_ERROR("time to vsync should not be zero, vtotal=%d\n",
1937 vtotal);
1938 return -EINVAL;
1939 }
1940
1941 cur_time = ktime_get();
1942 *wakeup_time = ktime_add_ns(cur_time, time_to_vsync);
1943
1944 DPU_DEBUG_ENC(dpu_enc,
1945 "cur_line=%u vtotal=%u time_to_vsync=%u, cur_time=%lld, wakeup_time=%lld\n",
1946 cur_line, vtotal, time_to_vsync,
1947 ktime_to_ms(cur_time),
1948 ktime_to_ms(*wakeup_time));
1949 return 0;
1950 }
1951
1952 static u32
dpu_encoder_dsc_initial_line_calc(struct drm_dsc_config * dsc,u32 enc_ip_width)1953 dpu_encoder_dsc_initial_line_calc(struct drm_dsc_config *dsc,
1954 u32 enc_ip_width)
1955 {
1956 int ssm_delay, total_pixels, soft_slice_per_enc;
1957
1958 soft_slice_per_enc = enc_ip_width / dsc->slice_width;
1959
1960 /*
1961 * minimum number of initial line pixels is a sum of:
1962 * 1. sub-stream multiplexer delay (83 groups for 8bpc,
1963 * 91 for 10 bpc) * 3
1964 * 2. for two soft slice cases, add extra sub-stream multiplexer * 3
1965 * 3. the initial xmit delay
1966 * 4. total pipeline delay through the "lock step" of encoder (47)
1967 * 5. 6 additional pixels as the output of the rate buffer is
1968 * 48 bits wide
1969 */
1970 ssm_delay = ((dsc->bits_per_component < 10) ? 84 : 92);
1971 total_pixels = ssm_delay * 3 + dsc->initial_xmit_delay + 47;
1972 if (soft_slice_per_enc > 1)
1973 total_pixels += (ssm_delay * 3);
1974 return DIV_ROUND_UP(total_pixels, dsc->slice_width);
1975 }
1976
dpu_encoder_dsc_pipe_cfg(struct dpu_hw_ctl * ctl,struct dpu_hw_dsc * hw_dsc,struct dpu_hw_pingpong * hw_pp,struct drm_dsc_config * dsc,u32 common_mode,u32 initial_lines)1977 static void dpu_encoder_dsc_pipe_cfg(struct dpu_hw_ctl *ctl,
1978 struct dpu_hw_dsc *hw_dsc,
1979 struct dpu_hw_pingpong *hw_pp,
1980 struct drm_dsc_config *dsc,
1981 u32 common_mode,
1982 u32 initial_lines)
1983 {
1984 if (hw_dsc->ops.dsc_config)
1985 hw_dsc->ops.dsc_config(hw_dsc, dsc, common_mode, initial_lines);
1986
1987 if (hw_dsc->ops.dsc_config_thresh)
1988 hw_dsc->ops.dsc_config_thresh(hw_dsc, dsc);
1989
1990 if (hw_pp->ops.setup_dsc)
1991 hw_pp->ops.setup_dsc(hw_pp);
1992
1993 if (hw_dsc->ops.dsc_bind_pingpong_blk)
1994 hw_dsc->ops.dsc_bind_pingpong_blk(hw_dsc, hw_pp->idx);
1995
1996 if (hw_pp->ops.enable_dsc)
1997 hw_pp->ops.enable_dsc(hw_pp);
1998
1999 if (ctl->ops.update_pending_flush_dsc)
2000 ctl->ops.update_pending_flush_dsc(ctl, hw_dsc->idx);
2001 }
2002
dpu_encoder_prep_dsc(struct dpu_encoder_virt * dpu_enc,struct drm_dsc_config * dsc)2003 static void dpu_encoder_prep_dsc(struct dpu_encoder_virt *dpu_enc,
2004 struct drm_dsc_config *dsc)
2005 {
2006 struct dpu_encoder_phys *enc_master = dpu_enc->cur_master;
2007 struct dpu_hw_ctl *ctl = enc_master->hw_ctl;
2008 struct dpu_hw_dsc *hw_dsc[MAX_CHANNELS_PER_ENC];
2009 struct dpu_hw_pingpong *hw_pp[MAX_CHANNELS_PER_ENC];
2010 int this_frame_slices;
2011 int intf_ip_w, enc_ip_w;
2012 int dsc_common_mode;
2013 int pic_width;
2014 u32 initial_lines;
2015 int num_dsc = 0;
2016 int i;
2017
2018 for (i = 0; i < MAX_CHANNELS_PER_ENC; i++) {
2019 hw_pp[i] = dpu_enc->hw_pp[i];
2020 hw_dsc[i] = dpu_enc->hw_dsc[i];
2021
2022 if (!hw_pp[i] || !hw_dsc[i])
2023 break;
2024
2025 num_dsc++;
2026 }
2027
2028 pic_width = dsc->pic_width;
2029
2030 dsc_common_mode = 0;
2031 if (num_dsc > 1)
2032 dsc_common_mode |= DSC_MODE_SPLIT_PANEL;
2033 if (dpu_encoder_use_dsc_merge(enc_master->parent))
2034 dsc_common_mode |= DSC_MODE_MULTIPLEX;
2035 if (enc_master->intf_mode == INTF_MODE_VIDEO)
2036 dsc_common_mode |= DSC_MODE_VIDEO;
2037
2038 this_frame_slices = pic_width / dsc->slice_width;
2039 intf_ip_w = this_frame_slices * dsc->slice_width;
2040
2041 enc_ip_w = intf_ip_w / num_dsc;
2042 initial_lines = dpu_encoder_dsc_initial_line_calc(dsc, enc_ip_w);
2043
2044 for (i = 0; i < num_dsc; i++)
2045 dpu_encoder_dsc_pipe_cfg(ctl, hw_dsc[i], hw_pp[i],
2046 dsc, dsc_common_mode, initial_lines);
2047 }
2048
2049 /**
2050 * dpu_encoder_prepare_for_kickoff - schedule double buffer flip of the ctl
2051 * path (i.e. ctl flush and start) at next appropriate time.
2052 * Immediately: if no previous commit is outstanding.
2053 * Delayed: Block until next trigger can be issued.
2054 * @drm_enc: encoder pointer
2055 */
dpu_encoder_prepare_for_kickoff(struct drm_encoder * drm_enc)2056 void dpu_encoder_prepare_for_kickoff(struct drm_encoder *drm_enc)
2057 {
2058 struct dpu_encoder_virt *dpu_enc;
2059 struct dpu_encoder_phys *phys;
2060 bool needs_hw_reset = false;
2061 unsigned int i;
2062
2063 dpu_enc = to_dpu_encoder_virt(drm_enc);
2064
2065 trace_dpu_enc_prepare_kickoff(DRMID(drm_enc));
2066
2067 /* prepare for next kickoff, may include waiting on previous kickoff */
2068 DPU_ATRACE_BEGIN("enc_prepare_for_kickoff");
2069 for (i = 0; i < dpu_enc->num_phys_encs; i++) {
2070 phys = dpu_enc->phys_encs[i];
2071 if (phys->ops.prepare_for_kickoff)
2072 phys->ops.prepare_for_kickoff(phys);
2073 if (phys->enable_state == DPU_ENC_ERR_NEEDS_HW_RESET)
2074 needs_hw_reset = true;
2075 }
2076 DPU_ATRACE_END("enc_prepare_for_kickoff");
2077
2078 dpu_encoder_resource_control(drm_enc, DPU_ENC_RC_EVENT_KICKOFF);
2079
2080 /* if any phys needs reset, reset all phys, in-order */
2081 if (needs_hw_reset) {
2082 trace_dpu_enc_prepare_kickoff_reset(DRMID(drm_enc));
2083 for (i = 0; i < dpu_enc->num_phys_encs; i++) {
2084 dpu_encoder_helper_hw_reset(dpu_enc->phys_encs[i]);
2085 }
2086 }
2087
2088 if (dpu_enc->dsc)
2089 dpu_encoder_prep_dsc(dpu_enc, dpu_enc->dsc);
2090 }
2091
2092 /**
2093 * dpu_encoder_is_valid_for_commit - check if encode has valid parameters for commit.
2094 * @drm_enc: Pointer to drm encoder structure
2095 */
dpu_encoder_is_valid_for_commit(struct drm_encoder * drm_enc)2096 bool dpu_encoder_is_valid_for_commit(struct drm_encoder *drm_enc)
2097 {
2098 struct dpu_encoder_virt *dpu_enc;
2099 unsigned int i;
2100 struct dpu_encoder_phys *phys;
2101
2102 dpu_enc = to_dpu_encoder_virt(drm_enc);
2103
2104 if (drm_enc->encoder_type == DRM_MODE_ENCODER_VIRTUAL) {
2105 for (i = 0; i < dpu_enc->num_phys_encs; i++) {
2106 phys = dpu_enc->phys_encs[i];
2107 if (phys->ops.is_valid_for_commit && !phys->ops.is_valid_for_commit(phys)) {
2108 DPU_DEBUG("invalid FB not kicking off\n");
2109 return false;
2110 }
2111 }
2112 }
2113
2114 return true;
2115 }
2116
2117 /**
2118 * dpu_encoder_start_frame_done_timer - Start the encoder frame done timer
2119 * @drm_enc: Pointer to drm encoder structure
2120 */
dpu_encoder_start_frame_done_timer(struct drm_encoder * drm_enc)2121 void dpu_encoder_start_frame_done_timer(struct drm_encoder *drm_enc)
2122 {
2123 struct dpu_encoder_virt *dpu_enc;
2124 unsigned long timeout_ms;
2125
2126 dpu_enc = to_dpu_encoder_virt(drm_enc);
2127 timeout_ms = DPU_ENCODER_FRAME_DONE_TIMEOUT_FRAMES * 1000 /
2128 drm_mode_vrefresh(&drm_enc->crtc->state->adjusted_mode);
2129
2130 atomic_set(&dpu_enc->frame_done_timeout_ms, timeout_ms);
2131 mod_timer(&dpu_enc->frame_done_timer,
2132 jiffies + msecs_to_jiffies(timeout_ms));
2133
2134 }
2135
2136 /**
2137 * dpu_encoder_kickoff - trigger a double buffer flip of the ctl path
2138 * (i.e. ctl flush and start) immediately.
2139 * @drm_enc: encoder pointer
2140 */
dpu_encoder_kickoff(struct drm_encoder * drm_enc)2141 void dpu_encoder_kickoff(struct drm_encoder *drm_enc)
2142 {
2143 struct dpu_encoder_virt *dpu_enc;
2144 struct dpu_encoder_phys *phys;
2145 unsigned int i;
2146
2147 DPU_ATRACE_BEGIN("encoder_kickoff");
2148 dpu_enc = to_dpu_encoder_virt(drm_enc);
2149
2150 trace_dpu_enc_kickoff(DRMID(drm_enc));
2151
2152 /* All phys encs are ready to go, trigger the kickoff */
2153 _dpu_encoder_kickoff_phys(dpu_enc);
2154
2155 /* allow phys encs to handle any post-kickoff business */
2156 for (i = 0; i < dpu_enc->num_phys_encs; i++) {
2157 phys = dpu_enc->phys_encs[i];
2158 if (phys->ops.handle_post_kickoff)
2159 phys->ops.handle_post_kickoff(phys);
2160 }
2161
2162 DPU_ATRACE_END("encoder_kickoff");
2163 }
2164
dpu_encoder_helper_reset_mixers(struct dpu_encoder_phys * phys_enc)2165 static void dpu_encoder_helper_reset_mixers(struct dpu_encoder_phys *phys_enc)
2166 {
2167 struct dpu_hw_mixer_cfg mixer;
2168 int i, num_lm;
2169 struct dpu_global_state *global_state;
2170 struct dpu_hw_blk *hw_lm[2];
2171 struct dpu_hw_mixer *hw_mixer[2];
2172 struct dpu_hw_ctl *ctl = phys_enc->hw_ctl;
2173
2174 memset(&mixer, 0, sizeof(mixer));
2175
2176 /* reset all mixers for this encoder */
2177 if (ctl->ops.clear_all_blendstages)
2178 ctl->ops.clear_all_blendstages(ctl);
2179
2180 global_state = dpu_kms_get_existing_global_state(phys_enc->dpu_kms);
2181
2182 num_lm = dpu_rm_get_assigned_resources(&phys_enc->dpu_kms->rm, global_state,
2183 phys_enc->parent->crtc, DPU_HW_BLK_LM, hw_lm, ARRAY_SIZE(hw_lm));
2184
2185 for (i = 0; i < num_lm; i++) {
2186 hw_mixer[i] = to_dpu_hw_mixer(hw_lm[i]);
2187 if (ctl->ops.update_pending_flush_mixer)
2188 ctl->ops.update_pending_flush_mixer(ctl, hw_mixer[i]->idx);
2189
2190 /* clear all blendstages */
2191 if (ctl->ops.setup_blendstage)
2192 ctl->ops.setup_blendstage(ctl, hw_mixer[i]->idx, NULL);
2193 }
2194 }
2195
dpu_encoder_dsc_pipe_clr(struct dpu_hw_ctl * ctl,struct dpu_hw_dsc * hw_dsc,struct dpu_hw_pingpong * hw_pp)2196 static void dpu_encoder_dsc_pipe_clr(struct dpu_hw_ctl *ctl,
2197 struct dpu_hw_dsc *hw_dsc,
2198 struct dpu_hw_pingpong *hw_pp)
2199 {
2200 if (hw_dsc->ops.dsc_disable)
2201 hw_dsc->ops.dsc_disable(hw_dsc);
2202
2203 if (hw_pp->ops.disable_dsc)
2204 hw_pp->ops.disable_dsc(hw_pp);
2205
2206 if (hw_dsc->ops.dsc_bind_pingpong_blk)
2207 hw_dsc->ops.dsc_bind_pingpong_blk(hw_dsc, PINGPONG_NONE);
2208
2209 if (ctl->ops.update_pending_flush_dsc)
2210 ctl->ops.update_pending_flush_dsc(ctl, hw_dsc->idx);
2211 }
2212
dpu_encoder_unprep_dsc(struct dpu_encoder_virt * dpu_enc)2213 static void dpu_encoder_unprep_dsc(struct dpu_encoder_virt *dpu_enc)
2214 {
2215 /* coding only for 2LM, 2enc, 1 dsc config */
2216 struct dpu_encoder_phys *enc_master = dpu_enc->cur_master;
2217 struct dpu_hw_ctl *ctl = enc_master->hw_ctl;
2218 struct dpu_hw_dsc *hw_dsc[MAX_CHANNELS_PER_ENC];
2219 struct dpu_hw_pingpong *hw_pp[MAX_CHANNELS_PER_ENC];
2220 int i;
2221
2222 for (i = 0; i < MAX_CHANNELS_PER_ENC; i++) {
2223 hw_pp[i] = dpu_enc->hw_pp[i];
2224 hw_dsc[i] = dpu_enc->hw_dsc[i];
2225
2226 if (hw_pp[i] && hw_dsc[i])
2227 dpu_encoder_dsc_pipe_clr(ctl, hw_dsc[i], hw_pp[i]);
2228 }
2229 }
2230
2231 /**
2232 * dpu_encoder_helper_phys_cleanup - helper to cleanup dpu pipeline
2233 * @phys_enc: Pointer to physical encoder structure
2234 */
dpu_encoder_helper_phys_cleanup(struct dpu_encoder_phys * phys_enc)2235 void dpu_encoder_helper_phys_cleanup(struct dpu_encoder_phys *phys_enc)
2236 {
2237 struct dpu_hw_ctl *ctl = phys_enc->hw_ctl;
2238 struct dpu_hw_intf_cfg intf_cfg = { 0 };
2239 int i;
2240 struct dpu_encoder_virt *dpu_enc;
2241
2242 dpu_enc = to_dpu_encoder_virt(phys_enc->parent);
2243
2244 ctl->ops.reset(ctl);
2245
2246 dpu_encoder_helper_reset_mixers(phys_enc);
2247
2248 /*
2249 * TODO: move the once-only operation like CTL flush/trigger
2250 * into dpu_encoder_virt_disable() and all operations which need
2251 * to be done per phys encoder into the phys_disable() op.
2252 */
2253 if (phys_enc->hw_wb) {
2254 /* disable the PP block */
2255 if (phys_enc->hw_wb->ops.bind_pingpong_blk)
2256 phys_enc->hw_wb->ops.bind_pingpong_blk(phys_enc->hw_wb, PINGPONG_NONE);
2257
2258 /* mark WB flush as pending */
2259 if (ctl->ops.update_pending_flush_wb)
2260 ctl->ops.update_pending_flush_wb(ctl, phys_enc->hw_wb->idx);
2261 } else {
2262 for (i = 0; i < dpu_enc->num_phys_encs; i++) {
2263 if (dpu_enc->phys_encs[i] && phys_enc->hw_intf->ops.bind_pingpong_blk)
2264 phys_enc->hw_intf->ops.bind_pingpong_blk(
2265 dpu_enc->phys_encs[i]->hw_intf,
2266 PINGPONG_NONE);
2267
2268 /* mark INTF flush as pending */
2269 if (ctl->ops.update_pending_flush_intf)
2270 ctl->ops.update_pending_flush_intf(ctl,
2271 dpu_enc->phys_encs[i]->hw_intf->idx);
2272 }
2273 }
2274
2275 if (phys_enc->hw_pp && phys_enc->hw_pp->ops.setup_dither)
2276 phys_enc->hw_pp->ops.setup_dither(phys_enc->hw_pp, NULL);
2277
2278 if (dpu_enc->cwb_mask)
2279 dpu_encoder_helper_phys_setup_cwb(phys_enc, false);
2280
2281 /* reset the merge 3D HW block */
2282 if (phys_enc->hw_pp && phys_enc->hw_pp->merge_3d) {
2283 phys_enc->hw_pp->merge_3d->ops.setup_3d_mode(phys_enc->hw_pp->merge_3d,
2284 BLEND_3D_NONE);
2285 if (ctl->ops.update_pending_flush_merge_3d)
2286 ctl->ops.update_pending_flush_merge_3d(ctl,
2287 phys_enc->hw_pp->merge_3d->idx);
2288 }
2289
2290 if (phys_enc->hw_cdm) {
2291 if (phys_enc->hw_cdm->ops.bind_pingpong_blk && phys_enc->hw_pp)
2292 phys_enc->hw_cdm->ops.bind_pingpong_blk(phys_enc->hw_cdm,
2293 PINGPONG_NONE);
2294 if (ctl->ops.update_pending_flush_cdm)
2295 ctl->ops.update_pending_flush_cdm(ctl,
2296 phys_enc->hw_cdm->idx);
2297 }
2298
2299 if (dpu_enc->dsc) {
2300 dpu_encoder_unprep_dsc(dpu_enc);
2301 dpu_enc->dsc = NULL;
2302 }
2303
2304 intf_cfg.stream_sel = 0; /* Don't care value for video mode */
2305 intf_cfg.mode_3d = dpu_encoder_helper_get_3d_blend_mode(phys_enc);
2306 intf_cfg.dsc = dpu_encoder_helper_get_dsc(phys_enc);
2307 intf_cfg.cwb = dpu_enc->cwb_mask;
2308
2309 if (phys_enc->hw_intf)
2310 intf_cfg.intf = phys_enc->hw_intf->idx;
2311 if (phys_enc->hw_wb)
2312 intf_cfg.wb = phys_enc->hw_wb->idx;
2313
2314 if (phys_enc->hw_pp && phys_enc->hw_pp->merge_3d)
2315 intf_cfg.merge_3d = phys_enc->hw_pp->merge_3d->idx;
2316
2317 if (ctl->ops.reset_intf_cfg)
2318 ctl->ops.reset_intf_cfg(ctl, &intf_cfg);
2319
2320 ctl->ops.trigger_flush(ctl);
2321 ctl->ops.trigger_start(ctl);
2322 ctl->ops.clear_pending_flush(ctl);
2323 }
2324
dpu_encoder_helper_phys_setup_cwb(struct dpu_encoder_phys * phys_enc,bool enable)2325 void dpu_encoder_helper_phys_setup_cwb(struct dpu_encoder_phys *phys_enc,
2326 bool enable)
2327 {
2328 struct dpu_encoder_virt *dpu_enc = to_dpu_encoder_virt(phys_enc->parent);
2329 struct dpu_hw_cwb *hw_cwb;
2330 struct dpu_hw_ctl *hw_ctl;
2331 struct dpu_hw_cwb_setup_cfg cwb_cfg;
2332
2333 struct dpu_kms *dpu_kms;
2334 struct dpu_global_state *global_state;
2335 struct dpu_hw_blk *rt_pp_list[MAX_CHANNELS_PER_ENC];
2336 int num_pp;
2337
2338 if (!phys_enc->hw_wb)
2339 return;
2340
2341 hw_ctl = phys_enc->hw_ctl;
2342
2343 if (!phys_enc->hw_ctl) {
2344 DPU_DEBUG("[wb:%d] no ctl assigned\n",
2345 phys_enc->hw_wb->idx - WB_0);
2346 return;
2347 }
2348
2349 dpu_kms = phys_enc->dpu_kms;
2350 global_state = dpu_kms_get_existing_global_state(dpu_kms);
2351 num_pp = dpu_rm_get_assigned_resources(&dpu_kms->rm, global_state,
2352 phys_enc->parent->crtc,
2353 DPU_HW_BLK_PINGPONG, rt_pp_list,
2354 ARRAY_SIZE(rt_pp_list));
2355
2356 if (num_pp == 0 || num_pp > MAX_CHANNELS_PER_ENC) {
2357 DPU_DEBUG_ENC(dpu_enc, "invalid num_pp %d\n", num_pp);
2358 return;
2359 }
2360
2361 /*
2362 * The CWB mux supports using LM or DSPP as tap points. For now,
2363 * always use LM tap point
2364 */
2365 cwb_cfg.input = INPUT_MODE_LM_OUT;
2366
2367 for (int i = 0; i < MAX_CHANNELS_PER_ENC; i++) {
2368 hw_cwb = dpu_enc->hw_cwb[i];
2369 if (!hw_cwb)
2370 continue;
2371
2372 if (enable) {
2373 struct dpu_hw_pingpong *hw_pp =
2374 to_dpu_hw_pingpong(rt_pp_list[i]);
2375 cwb_cfg.pp_idx = hw_pp->idx;
2376 } else {
2377 cwb_cfg.pp_idx = PINGPONG_NONE;
2378 }
2379
2380 hw_cwb->ops.config_cwb(hw_cwb, &cwb_cfg);
2381
2382 if (hw_ctl->ops.update_pending_flush_cwb)
2383 hw_ctl->ops.update_pending_flush_cwb(hw_ctl, hw_cwb->idx);
2384 }
2385 }
2386
2387 /**
2388 * dpu_encoder_helper_phys_setup_cdm - setup chroma down sampling block
2389 * @phys_enc: Pointer to physical encoder
2390 * @dpu_fmt: Pinter to the format description
2391 * @output_type: HDMI/WB
2392 */
dpu_encoder_helper_phys_setup_cdm(struct dpu_encoder_phys * phys_enc,const struct msm_format * dpu_fmt,u32 output_type)2393 void dpu_encoder_helper_phys_setup_cdm(struct dpu_encoder_phys *phys_enc,
2394 const struct msm_format *dpu_fmt,
2395 u32 output_type)
2396 {
2397 struct dpu_hw_cdm *hw_cdm;
2398 struct dpu_hw_cdm_cfg *cdm_cfg;
2399 struct dpu_hw_pingpong *hw_pp;
2400 int ret;
2401
2402 if (!phys_enc)
2403 return;
2404
2405 cdm_cfg = &phys_enc->cdm_cfg;
2406 hw_pp = phys_enc->hw_pp;
2407 hw_cdm = phys_enc->hw_cdm;
2408
2409 if (!hw_cdm)
2410 return;
2411
2412 if (!MSM_FORMAT_IS_YUV(dpu_fmt)) {
2413 DPU_DEBUG("[enc:%d] cdm_disable fmt:%p4cc\n", DRMID(phys_enc->parent),
2414 &dpu_fmt->pixel_format);
2415 if (hw_cdm->ops.bind_pingpong_blk)
2416 hw_cdm->ops.bind_pingpong_blk(hw_cdm, PINGPONG_NONE);
2417
2418 return;
2419 }
2420
2421 memset(cdm_cfg, 0, sizeof(struct dpu_hw_cdm_cfg));
2422
2423 cdm_cfg->output_width = phys_enc->cached_mode.hdisplay;
2424 cdm_cfg->output_height = phys_enc->cached_mode.vdisplay;
2425 cdm_cfg->output_fmt = dpu_fmt;
2426 cdm_cfg->output_type = output_type;
2427 cdm_cfg->output_bit_depth = MSM_FORMAT_IS_DX(dpu_fmt) ?
2428 CDM_CDWN_OUTPUT_10BIT : CDM_CDWN_OUTPUT_8BIT;
2429 cdm_cfg->csc_cfg = &dpu_csc10_rgb2yuv_601l;
2430
2431 /* enable 10 bit logic */
2432 switch (cdm_cfg->output_fmt->chroma_sample) {
2433 case CHROMA_FULL:
2434 cdm_cfg->h_cdwn_type = CDM_CDWN_DISABLE;
2435 cdm_cfg->v_cdwn_type = CDM_CDWN_DISABLE;
2436 break;
2437 case CHROMA_H2V1:
2438 cdm_cfg->h_cdwn_type = CDM_CDWN_COSITE;
2439 cdm_cfg->v_cdwn_type = CDM_CDWN_DISABLE;
2440 break;
2441 case CHROMA_420:
2442 cdm_cfg->h_cdwn_type = CDM_CDWN_COSITE;
2443 cdm_cfg->v_cdwn_type = CDM_CDWN_OFFSITE;
2444 break;
2445 case CHROMA_H1V2:
2446 default:
2447 DPU_ERROR("[enc:%d] unsupported chroma sampling type\n",
2448 DRMID(phys_enc->parent));
2449 cdm_cfg->h_cdwn_type = CDM_CDWN_DISABLE;
2450 cdm_cfg->v_cdwn_type = CDM_CDWN_DISABLE;
2451 break;
2452 }
2453
2454 DPU_DEBUG("[enc:%d] cdm_enable:%d,%d,%p4cc,%d,%d,%d,%d]\n",
2455 DRMID(phys_enc->parent), cdm_cfg->output_width,
2456 cdm_cfg->output_height, &cdm_cfg->output_fmt->pixel_format,
2457 cdm_cfg->output_type, cdm_cfg->output_bit_depth,
2458 cdm_cfg->h_cdwn_type, cdm_cfg->v_cdwn_type);
2459
2460 if (hw_cdm->ops.enable) {
2461 cdm_cfg->pp_id = hw_pp->idx;
2462 ret = hw_cdm->ops.enable(hw_cdm, cdm_cfg);
2463 if (ret < 0) {
2464 DPU_ERROR("[enc:%d] failed to enable CDM; ret:%d\n",
2465 DRMID(phys_enc->parent), ret);
2466 return;
2467 }
2468 }
2469 }
2470
2471 #ifdef CONFIG_DEBUG_FS
_dpu_encoder_status_show(struct seq_file * s,void * data)2472 static int _dpu_encoder_status_show(struct seq_file *s, void *data)
2473 {
2474 struct drm_encoder *drm_enc = s->private;
2475 struct dpu_encoder_virt *dpu_enc = to_dpu_encoder_virt(drm_enc);
2476 int i;
2477
2478 mutex_lock(&dpu_enc->enc_lock);
2479 for (i = 0; i < dpu_enc->num_phys_encs; i++) {
2480 struct dpu_encoder_phys *phys = dpu_enc->phys_encs[i];
2481
2482 seq_printf(s, "intf:%d wb:%d vsync:%8d underrun:%8d frame_done_cnt:%d",
2483 phys->hw_intf ? phys->hw_intf->idx - INTF_0 : -1,
2484 phys->hw_wb ? phys->hw_wb->idx - WB_0 : -1,
2485 atomic_read(&phys->vsync_cnt),
2486 atomic_read(&phys->underrun_cnt),
2487 atomic_read(&dpu_enc->frame_done_timeout_cnt));
2488
2489 seq_printf(s, "mode: %s\n", dpu_encoder_helper_get_intf_type(phys->intf_mode));
2490 }
2491 mutex_unlock(&dpu_enc->enc_lock);
2492
2493 return 0;
2494 }
2495
2496 DEFINE_SHOW_ATTRIBUTE(_dpu_encoder_status);
2497
dpu_encoder_debugfs_init(struct drm_encoder * drm_enc,struct dentry * root)2498 static void dpu_encoder_debugfs_init(struct drm_encoder *drm_enc, struct dentry *root)
2499 {
2500 /* don't error check these */
2501 debugfs_create_file("status", 0600,
2502 root, drm_enc, &_dpu_encoder_status_fops);
2503 }
2504 #else
2505 #define dpu_encoder_debugfs_init NULL
2506 #endif
2507
dpu_encoder_virt_add_phys_encs(struct drm_device * dev,struct msm_display_info * disp_info,struct dpu_encoder_virt * dpu_enc,struct dpu_enc_phys_init_params * params)2508 static int dpu_encoder_virt_add_phys_encs(
2509 struct drm_device *dev,
2510 struct msm_display_info *disp_info,
2511 struct dpu_encoder_virt *dpu_enc,
2512 struct dpu_enc_phys_init_params *params)
2513 {
2514 struct dpu_encoder_phys *enc = NULL;
2515
2516 DPU_DEBUG_ENC(dpu_enc, "\n");
2517
2518 /*
2519 * We may create up to NUM_PHYS_ENCODER_TYPES physical encoder types
2520 * in this function, check up-front.
2521 */
2522 if (dpu_enc->num_phys_encs + NUM_PHYS_ENCODER_TYPES >=
2523 ARRAY_SIZE(dpu_enc->phys_encs)) {
2524 DPU_ERROR_ENC(dpu_enc, "too many physical encoders %d\n",
2525 dpu_enc->num_phys_encs);
2526 return -EINVAL;
2527 }
2528
2529
2530 if (disp_info->intf_type == INTF_WB) {
2531 enc = dpu_encoder_phys_wb_init(dev, params);
2532
2533 if (IS_ERR(enc)) {
2534 DPU_ERROR_ENC(dpu_enc, "failed to init wb enc: %ld\n",
2535 PTR_ERR(enc));
2536 return PTR_ERR(enc);
2537 }
2538
2539 dpu_enc->phys_encs[dpu_enc->num_phys_encs] = enc;
2540 ++dpu_enc->num_phys_encs;
2541 } else if (disp_info->is_cmd_mode) {
2542 enc = dpu_encoder_phys_cmd_init(dev, params);
2543
2544 if (IS_ERR(enc)) {
2545 DPU_ERROR_ENC(dpu_enc, "failed to init cmd enc: %ld\n",
2546 PTR_ERR(enc));
2547 return PTR_ERR(enc);
2548 }
2549
2550 dpu_enc->phys_encs[dpu_enc->num_phys_encs] = enc;
2551 ++dpu_enc->num_phys_encs;
2552 } else {
2553 enc = dpu_encoder_phys_vid_init(dev, params);
2554
2555 if (IS_ERR(enc)) {
2556 DPU_ERROR_ENC(dpu_enc, "failed to init vid enc: %ld\n",
2557 PTR_ERR(enc));
2558 return PTR_ERR(enc);
2559 }
2560
2561 dpu_enc->phys_encs[dpu_enc->num_phys_encs] = enc;
2562 ++dpu_enc->num_phys_encs;
2563 }
2564
2565 if (params->split_role == ENC_ROLE_SLAVE)
2566 dpu_enc->cur_slave = enc;
2567 else
2568 dpu_enc->cur_master = enc;
2569
2570 return 0;
2571 }
2572
2573 /**
2574 * dpu_encoder_get_clones - Calculate the possible_clones for DPU encoder
2575 * @drm_enc: DRM encoder pointer
2576 * Returns: possible_clones mask
2577 */
dpu_encoder_get_clones(struct drm_encoder * drm_enc)2578 uint32_t dpu_encoder_get_clones(struct drm_encoder *drm_enc)
2579 {
2580 struct drm_encoder *curr;
2581 int type = drm_enc->encoder_type;
2582 uint32_t clone_mask = drm_encoder_mask(drm_enc);
2583
2584 /*
2585 * Set writeback as possible clones of real-time DSI encoders and vice
2586 * versa
2587 *
2588 * Writeback encoders can't be clones of each other and DSI
2589 * encoders can't be clones of each other.
2590 *
2591 * TODO: Add DP encoders as valid possible clones for writeback encoders
2592 * (and vice versa) once concurrent writeback has been validated for DP
2593 */
2594 drm_for_each_encoder(curr, drm_enc->dev) {
2595 if ((type == DRM_MODE_ENCODER_VIRTUAL &&
2596 curr->encoder_type == DRM_MODE_ENCODER_DSI) ||
2597 (type == DRM_MODE_ENCODER_DSI &&
2598 curr->encoder_type == DRM_MODE_ENCODER_VIRTUAL))
2599 clone_mask |= drm_encoder_mask(curr);
2600 }
2601
2602 return clone_mask;
2603 }
2604
dpu_encoder_setup_display(struct dpu_encoder_virt * dpu_enc,struct dpu_kms * dpu_kms,struct msm_display_info * disp_info)2605 static int dpu_encoder_setup_display(struct dpu_encoder_virt *dpu_enc,
2606 struct dpu_kms *dpu_kms,
2607 struct msm_display_info *disp_info)
2608 {
2609 int ret = 0;
2610 int i = 0;
2611 struct dpu_enc_phys_init_params phys_params;
2612
2613 if (!dpu_enc) {
2614 DPU_ERROR("invalid arg(s), enc %d\n", dpu_enc != NULL);
2615 return -EINVAL;
2616 }
2617
2618 dpu_enc->cur_master = NULL;
2619
2620 memset(&phys_params, 0, sizeof(phys_params));
2621 phys_params.dpu_kms = dpu_kms;
2622 phys_params.parent = &dpu_enc->base;
2623 phys_params.enc_spinlock = &dpu_enc->enc_spinlock;
2624
2625 WARN_ON(disp_info->num_of_h_tiles < 1);
2626
2627 DPU_DEBUG("dsi_info->num_of_h_tiles %d\n", disp_info->num_of_h_tiles);
2628
2629 if (disp_info->intf_type != INTF_WB)
2630 dpu_enc->idle_pc_supported =
2631 dpu_kms->catalog->caps->has_idle_pc;
2632
2633 mutex_lock(&dpu_enc->enc_lock);
2634 for (i = 0; i < disp_info->num_of_h_tiles && !ret; i++) {
2635 /*
2636 * Left-most tile is at index 0, content is controller id
2637 * h_tile_instance_ids[2] = {0, 1}; DSI0 = left, DSI1 = right
2638 * h_tile_instance_ids[2] = {1, 0}; DSI1 = left, DSI0 = right
2639 */
2640 u32 controller_id = disp_info->h_tile_instance[i];
2641
2642 if (disp_info->num_of_h_tiles > 1) {
2643 if (i == 0)
2644 phys_params.split_role = ENC_ROLE_MASTER;
2645 else
2646 phys_params.split_role = ENC_ROLE_SLAVE;
2647 } else {
2648 phys_params.split_role = ENC_ROLE_SOLO;
2649 }
2650
2651 DPU_DEBUG("h_tile_instance %d = %d, split_role %d\n",
2652 i, controller_id, phys_params.split_role);
2653
2654 phys_params.hw_intf = dpu_encoder_get_intf(dpu_kms->catalog, &dpu_kms->rm,
2655 disp_info->intf_type,
2656 controller_id);
2657
2658 if (disp_info->intf_type == INTF_WB && controller_id < WB_MAX)
2659 phys_params.hw_wb = dpu_rm_get_wb(&dpu_kms->rm, controller_id);
2660
2661 if (!phys_params.hw_intf && !phys_params.hw_wb) {
2662 DPU_ERROR_ENC(dpu_enc, "no intf or wb block assigned at idx: %d\n", i);
2663 ret = -EINVAL;
2664 break;
2665 }
2666
2667 if (phys_params.hw_intf && phys_params.hw_wb) {
2668 DPU_ERROR_ENC(dpu_enc,
2669 "invalid phys both intf and wb block at idx: %d\n", i);
2670 ret = -EINVAL;
2671 break;
2672 }
2673
2674 ret = dpu_encoder_virt_add_phys_encs(dpu_kms->dev, disp_info,
2675 dpu_enc, &phys_params);
2676 if (ret) {
2677 DPU_ERROR_ENC(dpu_enc, "failed to add phys encs\n");
2678 break;
2679 }
2680 }
2681
2682 mutex_unlock(&dpu_enc->enc_lock);
2683
2684 return ret;
2685 }
2686
dpu_encoder_frame_done_timeout(struct timer_list * t)2687 static void dpu_encoder_frame_done_timeout(struct timer_list *t)
2688 {
2689 struct dpu_encoder_virt *dpu_enc = from_timer(dpu_enc, t,
2690 frame_done_timer);
2691 struct drm_encoder *drm_enc = &dpu_enc->base;
2692 u32 event;
2693
2694 if (!drm_enc->dev) {
2695 DPU_ERROR("invalid parameters\n");
2696 return;
2697 }
2698
2699 if (!dpu_enc->frame_busy_mask[0] || !dpu_enc->crtc) {
2700 DRM_DEBUG_KMS("id:%u invalid timeout frame_busy_mask=%lu\n",
2701 DRMID(drm_enc), dpu_enc->frame_busy_mask[0]);
2702 return;
2703 } else if (!atomic_xchg(&dpu_enc->frame_done_timeout_ms, 0)) {
2704 DRM_DEBUG_KMS("id:%u invalid timeout\n", DRMID(drm_enc));
2705 return;
2706 }
2707
2708 DPU_ERROR_ENC_RATELIMITED(dpu_enc, "frame done timeout\n");
2709
2710 if (atomic_inc_return(&dpu_enc->frame_done_timeout_cnt) == 1)
2711 msm_disp_snapshot_state(drm_enc->dev);
2712
2713 event = DPU_ENCODER_FRAME_EVENT_ERROR;
2714 trace_dpu_enc_frame_done_timeout(DRMID(drm_enc), event);
2715 dpu_crtc_frame_event_cb(dpu_enc->crtc, event);
2716 }
2717
2718 static const struct drm_encoder_helper_funcs dpu_encoder_helper_funcs = {
2719 .atomic_mode_set = dpu_encoder_virt_atomic_mode_set,
2720 .atomic_disable = dpu_encoder_virt_atomic_disable,
2721 .atomic_enable = dpu_encoder_virt_atomic_enable,
2722 };
2723
2724 static const struct drm_encoder_funcs dpu_encoder_funcs = {
2725 .debugfs_init = dpu_encoder_debugfs_init,
2726 };
2727
2728 /**
2729 * dpu_encoder_init - initialize virtual encoder object
2730 * @dev: Pointer to drm device structure
2731 * @drm_enc_mode: corresponding DRM_MODE_ENCODER_* constant
2732 * @disp_info: Pointer to display information structure
2733 * Returns: Pointer to newly created drm encoder
2734 */
dpu_encoder_init(struct drm_device * dev,int drm_enc_mode,struct msm_display_info * disp_info)2735 struct drm_encoder *dpu_encoder_init(struct drm_device *dev,
2736 int drm_enc_mode,
2737 struct msm_display_info *disp_info)
2738 {
2739 struct msm_drm_private *priv = dev->dev_private;
2740 struct dpu_kms *dpu_kms = to_dpu_kms(priv->kms);
2741 struct dpu_encoder_virt *dpu_enc;
2742 int ret;
2743
2744 dpu_enc = drmm_encoder_alloc(dev, struct dpu_encoder_virt, base,
2745 &dpu_encoder_funcs, drm_enc_mode, NULL);
2746 if (IS_ERR(dpu_enc))
2747 return ERR_CAST(dpu_enc);
2748
2749 drm_encoder_helper_add(&dpu_enc->base, &dpu_encoder_helper_funcs);
2750
2751 spin_lock_init(&dpu_enc->enc_spinlock);
2752 dpu_enc->enabled = false;
2753 mutex_init(&dpu_enc->enc_lock);
2754 mutex_init(&dpu_enc->rc_lock);
2755
2756 ret = dpu_encoder_setup_display(dpu_enc, dpu_kms, disp_info);
2757 if (ret) {
2758 DPU_ERROR("failed to setup encoder\n");
2759 return ERR_PTR(-ENOMEM);
2760 }
2761
2762 atomic_set(&dpu_enc->frame_done_timeout_ms, 0);
2763 atomic_set(&dpu_enc->frame_done_timeout_cnt, 0);
2764 timer_setup(&dpu_enc->frame_done_timer,
2765 dpu_encoder_frame_done_timeout, 0);
2766
2767 INIT_DELAYED_WORK(&dpu_enc->delayed_off_work,
2768 dpu_encoder_off_work);
2769 dpu_enc->idle_timeout = IDLE_TIMEOUT;
2770
2771 memcpy(&dpu_enc->disp_info, disp_info, sizeof(*disp_info));
2772
2773 DPU_DEBUG_ENC(dpu_enc, "created\n");
2774
2775 return &dpu_enc->base;
2776 }
2777
2778 /**
2779 * dpu_encoder_wait_for_commit_done() - Wait for encoder to flush pending state
2780 * @drm_enc: encoder pointer
2781 *
2782 * Wait for hardware to have flushed the current pending changes to hardware at
2783 * a vblank or CTL_START. Physical encoders will map this differently depending
2784 * on the type: vid mode -> vsync_irq, cmd mode -> CTL_START.
2785 *
2786 * Return: 0 on success, -EWOULDBLOCK if already signaled, error otherwise
2787 */
dpu_encoder_wait_for_commit_done(struct drm_encoder * drm_enc)2788 int dpu_encoder_wait_for_commit_done(struct drm_encoder *drm_enc)
2789 {
2790 struct dpu_encoder_virt *dpu_enc = NULL;
2791 int i, ret = 0;
2792
2793 if (!drm_enc) {
2794 DPU_ERROR("invalid encoder\n");
2795 return -EINVAL;
2796 }
2797 dpu_enc = to_dpu_encoder_virt(drm_enc);
2798 DPU_DEBUG_ENC(dpu_enc, "\n");
2799
2800 for (i = 0; i < dpu_enc->num_phys_encs; i++) {
2801 struct dpu_encoder_phys *phys = dpu_enc->phys_encs[i];
2802
2803 if (phys->ops.wait_for_commit_done) {
2804 DPU_ATRACE_BEGIN("wait_for_commit_done");
2805 ret = phys->ops.wait_for_commit_done(phys);
2806 DPU_ATRACE_END("wait_for_commit_done");
2807 if (ret == -ETIMEDOUT && !dpu_enc->commit_done_timedout) {
2808 dpu_enc->commit_done_timedout = true;
2809 msm_disp_snapshot_state(drm_enc->dev);
2810 }
2811 if (ret)
2812 return ret;
2813 }
2814 }
2815
2816 return ret;
2817 }
2818
2819 /**
2820 * dpu_encoder_wait_for_tx_complete() - Wait for encoder to transfer pixels to panel
2821 * @drm_enc: encoder pointer
2822 *
2823 * Wait for the hardware to transfer all the pixels to the panel. Physical
2824 * encoders will map this differently depending on the type: vid mode -> vsync_irq,
2825 * cmd mode -> pp_done.
2826 *
2827 * Return: 0 on success, -EWOULDBLOCK if already signaled, error otherwise
2828 */
dpu_encoder_wait_for_tx_complete(struct drm_encoder * drm_enc)2829 int dpu_encoder_wait_for_tx_complete(struct drm_encoder *drm_enc)
2830 {
2831 struct dpu_encoder_virt *dpu_enc = NULL;
2832 int i, ret = 0;
2833
2834 if (!drm_enc) {
2835 DPU_ERROR("invalid encoder\n");
2836 return -EINVAL;
2837 }
2838 dpu_enc = to_dpu_encoder_virt(drm_enc);
2839 DPU_DEBUG_ENC(dpu_enc, "\n");
2840
2841 for (i = 0; i < dpu_enc->num_phys_encs; i++) {
2842 struct dpu_encoder_phys *phys = dpu_enc->phys_encs[i];
2843
2844 if (phys->ops.wait_for_tx_complete) {
2845 DPU_ATRACE_BEGIN("wait_for_tx_complete");
2846 ret = phys->ops.wait_for_tx_complete(phys);
2847 DPU_ATRACE_END("wait_for_tx_complete");
2848 if (ret)
2849 return ret;
2850 }
2851 }
2852
2853 return ret;
2854 }
2855
2856 /**
2857 * dpu_encoder_get_intf_mode - get interface mode of the given encoder
2858 * @encoder: Pointer to drm encoder object
2859 */
dpu_encoder_get_intf_mode(struct drm_encoder * encoder)2860 enum dpu_intf_mode dpu_encoder_get_intf_mode(struct drm_encoder *encoder)
2861 {
2862 struct dpu_encoder_virt *dpu_enc = NULL;
2863
2864 if (!encoder) {
2865 DPU_ERROR("invalid encoder\n");
2866 return INTF_MODE_NONE;
2867 }
2868 dpu_enc = to_dpu_encoder_virt(encoder);
2869
2870 if (dpu_enc->cur_master)
2871 return dpu_enc->cur_master->intf_mode;
2872
2873 if (dpu_enc->num_phys_encs)
2874 return dpu_enc->phys_encs[0]->intf_mode;
2875
2876 return INTF_MODE_NONE;
2877 }
2878
2879 /**
2880 * dpu_encoder_helper_get_cwb_mask - get CWB blocks mask for the DPU encoder
2881 * @phys_enc: Pointer to physical encoder structure
2882 */
dpu_encoder_helper_get_cwb_mask(struct dpu_encoder_phys * phys_enc)2883 unsigned int dpu_encoder_helper_get_cwb_mask(struct dpu_encoder_phys *phys_enc)
2884 {
2885 struct drm_encoder *encoder = phys_enc->parent;
2886 struct dpu_encoder_virt *dpu_enc = to_dpu_encoder_virt(encoder);
2887
2888 return dpu_enc->cwb_mask;
2889 }
2890
2891 /**
2892 * dpu_encoder_helper_get_dsc - get DSC blocks mask for the DPU encoder
2893 * This helper function is used by physical encoder to get DSC blocks mask
2894 * used for this encoder.
2895 * @phys_enc: Pointer to physical encoder structure
2896 */
dpu_encoder_helper_get_dsc(struct dpu_encoder_phys * phys_enc)2897 unsigned int dpu_encoder_helper_get_dsc(struct dpu_encoder_phys *phys_enc)
2898 {
2899 struct drm_encoder *encoder = phys_enc->parent;
2900 struct dpu_encoder_virt *dpu_enc = to_dpu_encoder_virt(encoder);
2901
2902 return dpu_enc->dsc_mask;
2903 }
2904
dpu_encoder_phys_init(struct dpu_encoder_phys * phys_enc,struct dpu_enc_phys_init_params * p)2905 void dpu_encoder_phys_init(struct dpu_encoder_phys *phys_enc,
2906 struct dpu_enc_phys_init_params *p)
2907 {
2908 phys_enc->hw_mdptop = p->dpu_kms->hw_mdp;
2909 phys_enc->hw_intf = p->hw_intf;
2910 phys_enc->hw_wb = p->hw_wb;
2911 phys_enc->parent = p->parent;
2912 phys_enc->dpu_kms = p->dpu_kms;
2913 phys_enc->split_role = p->split_role;
2914 phys_enc->enc_spinlock = p->enc_spinlock;
2915 phys_enc->enable_state = DPU_ENC_DISABLED;
2916
2917 atomic_set(&phys_enc->pending_kickoff_cnt, 0);
2918 atomic_set(&phys_enc->pending_ctlstart_cnt, 0);
2919
2920 atomic_set(&phys_enc->vsync_cnt, 0);
2921 atomic_set(&phys_enc->underrun_cnt, 0);
2922
2923 init_waitqueue_head(&phys_enc->pending_kickoff_wq);
2924 }
2925