1 // SPDX-License-Identifier: GPL-2.0-only
2 /*
3 * Copyright (C) 2013 Red Hat
4 * Copyright (c) 2014-2018, The Linux Foundation. All rights reserved.
5 * Copyright (c) 2022-2024 Qualcomm Innovation Center, Inc. All rights reserved.
6 *
7 * Author: Rob Clark <robdclark@gmail.com>
8 */
9
10 #define pr_fmt(fmt) "[drm:%s:%d] " fmt, __func__, __LINE__
11
12 #include <linux/debugfs.h>
13 #include <linux/dma-buf.h>
14 #include <linux/of_irq.h>
15 #include <linux/pm_opp.h>
16
17 #include <drm/drm_crtc.h>
18 #include <drm/drm_file.h>
19 #include <drm/drm_framebuffer.h>
20 #include <drm/drm_vblank.h>
21 #include <drm/drm_writeback.h>
22
23 #include "msm_drv.h"
24 #include "msm_mmu.h"
25 #include "msm_mdss.h"
26 #include "msm_gem.h"
27 #include "disp/msm_disp_snapshot.h"
28
29 #include "dpu_core_irq.h"
30 #include "dpu_crtc.h"
31 #include "dpu_encoder.h"
32 #include "dpu_formats.h"
33 #include "dpu_hw_vbif.h"
34 #include "dpu_kms.h"
35 #include "dpu_plane.h"
36 #include "dpu_vbif.h"
37 #include "dpu_writeback.h"
38
39 #define CREATE_TRACE_POINTS
40 #include "dpu_trace.h"
41
42 /*
43 * To enable overall DRM driver logging
44 * # echo 0x2 > /sys/module/drm/parameters/debug
45 *
46 * To enable DRM driver h/w logging
47 * # echo <mask> > /sys/kernel/debug/dri/0/debug/hw_log_mask
48 *
49 * See dpu_hw_mdss.h for h/w logging mask definitions (search for DPU_DBG_MASK_)
50 */
51 #define DPU_DEBUGFS_DIR "msm_dpu"
52 #define DPU_DEBUGFS_HWMASKNAME "hw_log_mask"
53
54 bool dpu_use_virtual_planes;
55 module_param(dpu_use_virtual_planes, bool, 0);
56
57 static int dpu_kms_hw_init(struct msm_kms *kms);
58 static void _dpu_kms_mmu_destroy(struct dpu_kms *dpu_kms);
59
60 #ifdef CONFIG_DEBUG_FS
_dpu_danger_signal_status(struct seq_file * s,bool danger_status)61 static int _dpu_danger_signal_status(struct seq_file *s,
62 bool danger_status)
63 {
64 struct dpu_danger_safe_status status;
65 struct dpu_kms *kms = s->private;
66 int i;
67
68 if (!kms->hw_mdp) {
69 DPU_ERROR("invalid arg(s)\n");
70 return 0;
71 }
72
73 memset(&status, 0, sizeof(struct dpu_danger_safe_status));
74
75 pm_runtime_get_sync(&kms->pdev->dev);
76 if (danger_status) {
77 seq_puts(s, "\nDanger signal status:\n");
78 if (kms->hw_mdp->ops.get_danger_status)
79 kms->hw_mdp->ops.get_danger_status(kms->hw_mdp,
80 &status);
81 } else {
82 seq_puts(s, "\nSafe signal status:\n");
83 if (kms->hw_mdp->ops.get_safe_status)
84 kms->hw_mdp->ops.get_safe_status(kms->hw_mdp,
85 &status);
86 }
87 pm_runtime_put_sync(&kms->pdev->dev);
88
89 seq_printf(s, "MDP : 0x%x\n", status.mdp);
90
91 for (i = SSPP_VIG0; i < SSPP_MAX; i++)
92 seq_printf(s, "SSPP%d : 0x%x \n", i - SSPP_VIG0,
93 status.sspp[i]);
94 seq_puts(s, "\n");
95
96 return 0;
97 }
98
dpu_debugfs_danger_stats_show(struct seq_file * s,void * v)99 static int dpu_debugfs_danger_stats_show(struct seq_file *s, void *v)
100 {
101 return _dpu_danger_signal_status(s, true);
102 }
103 DEFINE_SHOW_ATTRIBUTE(dpu_debugfs_danger_stats);
104
dpu_debugfs_safe_stats_show(struct seq_file * s,void * v)105 static int dpu_debugfs_safe_stats_show(struct seq_file *s, void *v)
106 {
107 return _dpu_danger_signal_status(s, false);
108 }
109 DEFINE_SHOW_ATTRIBUTE(dpu_debugfs_safe_stats);
110
_dpu_plane_danger_read(struct file * file,char __user * buff,size_t count,loff_t * ppos)111 static ssize_t _dpu_plane_danger_read(struct file *file,
112 char __user *buff, size_t count, loff_t *ppos)
113 {
114 struct dpu_kms *kms = file->private_data;
115 int len;
116 char buf[40];
117
118 len = scnprintf(buf, sizeof(buf), "%d\n", !kms->has_danger_ctrl);
119
120 return simple_read_from_buffer(buff, count, ppos, buf, len);
121 }
122
_dpu_plane_set_danger_state(struct dpu_kms * kms,bool enable)123 static void _dpu_plane_set_danger_state(struct dpu_kms *kms, bool enable)
124 {
125 struct drm_plane *plane;
126
127 drm_for_each_plane(plane, kms->dev) {
128 if (plane->fb && plane->state) {
129 dpu_plane_danger_signal_ctrl(plane, enable);
130 DPU_DEBUG("plane:%d img:%dx%d ",
131 plane->base.id, plane->fb->width,
132 plane->fb->height);
133 DPU_DEBUG("src[%d,%d,%d,%d] dst[%d,%d,%d,%d]\n",
134 plane->state->src_x >> 16,
135 plane->state->src_y >> 16,
136 plane->state->src_w >> 16,
137 plane->state->src_h >> 16,
138 plane->state->crtc_x, plane->state->crtc_y,
139 plane->state->crtc_w, plane->state->crtc_h);
140 } else {
141 DPU_DEBUG("Inactive plane:%d\n", plane->base.id);
142 }
143 }
144 }
145
_dpu_plane_danger_write(struct file * file,const char __user * user_buf,size_t count,loff_t * ppos)146 static ssize_t _dpu_plane_danger_write(struct file *file,
147 const char __user *user_buf, size_t count, loff_t *ppos)
148 {
149 struct dpu_kms *kms = file->private_data;
150 int disable_panic;
151 int ret;
152
153 ret = kstrtouint_from_user(user_buf, count, 0, &disable_panic);
154 if (ret)
155 return ret;
156
157 if (disable_panic) {
158 /* Disable panic signal for all active pipes */
159 DPU_DEBUG("Disabling danger:\n");
160 _dpu_plane_set_danger_state(kms, false);
161 kms->has_danger_ctrl = false;
162 } else {
163 /* Enable panic signal for all active pipes */
164 DPU_DEBUG("Enabling danger:\n");
165 kms->has_danger_ctrl = true;
166 _dpu_plane_set_danger_state(kms, true);
167 }
168
169 return count;
170 }
171
172 static const struct file_operations dpu_plane_danger_enable = {
173 .open = simple_open,
174 .read = _dpu_plane_danger_read,
175 .write = _dpu_plane_danger_write,
176 };
177
dpu_debugfs_danger_init(struct dpu_kms * dpu_kms,struct dentry * parent)178 static void dpu_debugfs_danger_init(struct dpu_kms *dpu_kms,
179 struct dentry *parent)
180 {
181 struct dentry *entry = debugfs_create_dir("danger", parent);
182
183 debugfs_create_file("danger_status", 0600, entry,
184 dpu_kms, &dpu_debugfs_danger_stats_fops);
185 debugfs_create_file("safe_status", 0600, entry,
186 dpu_kms, &dpu_debugfs_safe_stats_fops);
187 debugfs_create_file("disable_danger", 0600, entry,
188 dpu_kms, &dpu_plane_danger_enable);
189
190 }
191
192 /*
193 * Companion structure for dpu_debugfs_create_regset32.
194 */
195 struct dpu_debugfs_regset32 {
196 uint32_t offset;
197 uint32_t blk_len;
198 struct dpu_kms *dpu_kms;
199 };
200
dpu_regset32_show(struct seq_file * s,void * data)201 static int dpu_regset32_show(struct seq_file *s, void *data)
202 {
203 struct dpu_debugfs_regset32 *regset = s->private;
204 struct dpu_kms *dpu_kms = regset->dpu_kms;
205 void __iomem *base;
206 uint32_t i, addr;
207
208 if (!dpu_kms->mmio)
209 return 0;
210
211 base = dpu_kms->mmio + regset->offset;
212
213 /* insert padding spaces, if needed */
214 if (regset->offset & 0xF) {
215 seq_printf(s, "[%x]", regset->offset & ~0xF);
216 for (i = 0; i < (regset->offset & 0xF); i += 4)
217 seq_puts(s, " ");
218 }
219
220 pm_runtime_get_sync(&dpu_kms->pdev->dev);
221
222 /* main register output */
223 for (i = 0; i < regset->blk_len; i += 4) {
224 addr = regset->offset + i;
225 if ((addr & 0xF) == 0x0)
226 seq_printf(s, i ? "\n[%x]" : "[%x]", addr);
227 seq_printf(s, " %08x", readl_relaxed(base + i));
228 }
229 seq_puts(s, "\n");
230 pm_runtime_put_sync(&dpu_kms->pdev->dev);
231
232 return 0;
233 }
234 DEFINE_SHOW_ATTRIBUTE(dpu_regset32);
235
236 /**
237 * dpu_debugfs_create_regset32 - Create register read back file for debugfs
238 *
239 * This function is almost identical to the standard debugfs_create_regset32()
240 * function, with the main difference being that a list of register
241 * names/offsets do not need to be provided. The 'read' function simply outputs
242 * sequential register values over a specified range.
243 *
244 * @name: File name within debugfs
245 * @mode: File mode within debugfs
246 * @parent: Parent directory entry within debugfs, can be NULL
247 * @offset: sub-block offset
248 * @length: sub-block length, in bytes
249 * @dpu_kms: pointer to dpu kms structure
250 */
dpu_debugfs_create_regset32(const char * name,umode_t mode,void * parent,uint32_t offset,uint32_t length,struct dpu_kms * dpu_kms)251 void dpu_debugfs_create_regset32(const char *name, umode_t mode,
252 void *parent,
253 uint32_t offset, uint32_t length, struct dpu_kms *dpu_kms)
254 {
255 struct dpu_debugfs_regset32 *regset;
256
257 if (WARN_ON(!name || !dpu_kms || !length))
258 return;
259
260 regset = devm_kzalloc(&dpu_kms->pdev->dev, sizeof(*regset), GFP_KERNEL);
261 if (!regset)
262 return;
263
264 /* make sure offset is a multiple of 4 */
265 regset->offset = round_down(offset, 4);
266 regset->blk_len = length;
267 regset->dpu_kms = dpu_kms;
268
269 debugfs_create_file(name, mode, parent, regset, &dpu_regset32_fops);
270 }
271
dpu_debugfs_sspp_init(struct dpu_kms * dpu_kms,struct dentry * debugfs_root)272 static void dpu_debugfs_sspp_init(struct dpu_kms *dpu_kms, struct dentry *debugfs_root)
273 {
274 struct dentry *entry = debugfs_create_dir("sspp", debugfs_root);
275 int i;
276
277 if (IS_ERR(entry))
278 return;
279
280 for (i = SSPP_NONE; i < SSPP_MAX; i++) {
281 struct dpu_hw_sspp *hw = dpu_rm_get_sspp(&dpu_kms->rm, i);
282
283 if (!hw)
284 continue;
285
286 _dpu_hw_sspp_init_debugfs(hw, dpu_kms, entry);
287 }
288 }
289
dpu_kms_debugfs_init(struct msm_kms * kms,struct drm_minor * minor)290 static int dpu_kms_debugfs_init(struct msm_kms *kms, struct drm_minor *minor)
291 {
292 struct dpu_kms *dpu_kms = to_dpu_kms(kms);
293 void *p = dpu_hw_util_get_log_mask_ptr();
294 struct dentry *entry;
295
296 if (!p)
297 return -EINVAL;
298
299 /* Only create a set of debugfs for the primary node, ignore render nodes */
300 if (minor->type != DRM_MINOR_PRIMARY)
301 return 0;
302
303 entry = debugfs_create_dir("debug", minor->debugfs_root);
304
305 debugfs_create_x32(DPU_DEBUGFS_HWMASKNAME, 0600, entry, p);
306
307 dpu_debugfs_danger_init(dpu_kms, entry);
308 dpu_debugfs_vbif_init(dpu_kms, entry);
309 dpu_debugfs_core_irq_init(dpu_kms, entry);
310 dpu_debugfs_sspp_init(dpu_kms, entry);
311
312 return dpu_core_perf_debugfs_init(dpu_kms, entry);
313 }
314 #endif
315
316 /* Global/shared object state funcs */
317
318 /*
319 * This is a helper that returns the private state currently in operation.
320 * Note that this would return the "old_state" if called in the atomic check
321 * path, and the "new_state" after the atomic swap has been done.
322 */
323 struct dpu_global_state *
dpu_kms_get_existing_global_state(struct dpu_kms * dpu_kms)324 dpu_kms_get_existing_global_state(struct dpu_kms *dpu_kms)
325 {
326 return to_dpu_global_state(dpu_kms->global_state.state);
327 }
328
329 /*
330 * This acquires the modeset lock set aside for global state, creates
331 * a new duplicated private object state.
332 */
dpu_kms_get_global_state(struct drm_atomic_state * s)333 struct dpu_global_state *dpu_kms_get_global_state(struct drm_atomic_state *s)
334 {
335 struct msm_drm_private *priv = s->dev->dev_private;
336 struct dpu_kms *dpu_kms = to_dpu_kms(priv->kms);
337 struct drm_private_state *priv_state;
338
339 priv_state = drm_atomic_get_private_obj_state(s,
340 &dpu_kms->global_state);
341 if (IS_ERR(priv_state))
342 return ERR_CAST(priv_state);
343
344 return to_dpu_global_state(priv_state);
345 }
346
347 static struct drm_private_state *
dpu_kms_global_duplicate_state(struct drm_private_obj * obj)348 dpu_kms_global_duplicate_state(struct drm_private_obj *obj)
349 {
350 struct dpu_global_state *state;
351
352 state = kmemdup(obj->state, sizeof(*state), GFP_KERNEL);
353 if (!state)
354 return NULL;
355
356 __drm_atomic_helper_private_obj_duplicate_state(obj, &state->base);
357
358 return &state->base;
359 }
360
dpu_kms_global_destroy_state(struct drm_private_obj * obj,struct drm_private_state * state)361 static void dpu_kms_global_destroy_state(struct drm_private_obj *obj,
362 struct drm_private_state *state)
363 {
364 struct dpu_global_state *dpu_state = to_dpu_global_state(state);
365
366 kfree(dpu_state);
367 }
368
dpu_kms_global_print_state(struct drm_printer * p,const struct drm_private_state * state)369 static void dpu_kms_global_print_state(struct drm_printer *p,
370 const struct drm_private_state *state)
371 {
372 const struct dpu_global_state *global_state = to_dpu_global_state(state);
373
374 dpu_rm_print_state(p, global_state);
375 }
376
377 static const struct drm_private_state_funcs dpu_kms_global_state_funcs = {
378 .atomic_duplicate_state = dpu_kms_global_duplicate_state,
379 .atomic_destroy_state = dpu_kms_global_destroy_state,
380 .atomic_print_state = dpu_kms_global_print_state,
381 };
382
dpu_kms_global_obj_init(struct dpu_kms * dpu_kms)383 static int dpu_kms_global_obj_init(struct dpu_kms *dpu_kms)
384 {
385 struct dpu_global_state *state;
386
387 state = kzalloc(sizeof(*state), GFP_KERNEL);
388 if (!state)
389 return -ENOMEM;
390
391 drm_atomic_private_obj_init(dpu_kms->dev, &dpu_kms->global_state,
392 &state->base,
393 &dpu_kms_global_state_funcs);
394
395 state->rm = &dpu_kms->rm;
396
397 return 0;
398 }
399
dpu_kms_global_obj_fini(struct dpu_kms * dpu_kms)400 static void dpu_kms_global_obj_fini(struct dpu_kms *dpu_kms)
401 {
402 drm_atomic_private_obj_fini(&dpu_kms->global_state);
403 }
404
dpu_kms_parse_data_bus_icc_path(struct dpu_kms * dpu_kms)405 static int dpu_kms_parse_data_bus_icc_path(struct dpu_kms *dpu_kms)
406 {
407 struct icc_path *path0;
408 struct icc_path *path1;
409 struct device *dpu_dev = &dpu_kms->pdev->dev;
410
411 path0 = msm_icc_get(dpu_dev, "mdp0-mem");
412 path1 = msm_icc_get(dpu_dev, "mdp1-mem");
413
414 if (IS_ERR_OR_NULL(path0))
415 return PTR_ERR_OR_ZERO(path0);
416
417 dpu_kms->path[0] = path0;
418 dpu_kms->num_paths = 1;
419
420 if (!IS_ERR_OR_NULL(path1)) {
421 dpu_kms->path[1] = path1;
422 dpu_kms->num_paths++;
423 }
424 return 0;
425 }
426
dpu_kms_enable_vblank(struct msm_kms * kms,struct drm_crtc * crtc)427 static int dpu_kms_enable_vblank(struct msm_kms *kms, struct drm_crtc *crtc)
428 {
429 return dpu_crtc_vblank(crtc, true);
430 }
431
dpu_kms_disable_vblank(struct msm_kms * kms,struct drm_crtc * crtc)432 static void dpu_kms_disable_vblank(struct msm_kms *kms, struct drm_crtc *crtc)
433 {
434 dpu_crtc_vblank(crtc, false);
435 }
436
dpu_kms_enable_commit(struct msm_kms * kms)437 static void dpu_kms_enable_commit(struct msm_kms *kms)
438 {
439 struct dpu_kms *dpu_kms = to_dpu_kms(kms);
440 pm_runtime_get_sync(&dpu_kms->pdev->dev);
441 }
442
dpu_kms_disable_commit(struct msm_kms * kms)443 static void dpu_kms_disable_commit(struct msm_kms *kms)
444 {
445 struct dpu_kms *dpu_kms = to_dpu_kms(kms);
446 pm_runtime_put_sync(&dpu_kms->pdev->dev);
447 }
448
dpu_kms_check_mode_changed(struct msm_kms * kms,struct drm_atomic_state * state)449 static int dpu_kms_check_mode_changed(struct msm_kms *kms, struct drm_atomic_state *state)
450 {
451 struct drm_crtc_state *new_crtc_state;
452 struct drm_crtc_state *old_crtc_state;
453 struct drm_crtc *crtc;
454 int i;
455
456 for_each_oldnew_crtc_in_state(state, crtc, old_crtc_state, new_crtc_state, i)
457 dpu_crtc_check_mode_changed(old_crtc_state, new_crtc_state);
458
459 return 0;
460 }
461
dpu_kms_flush_commit(struct msm_kms * kms,unsigned crtc_mask)462 static void dpu_kms_flush_commit(struct msm_kms *kms, unsigned crtc_mask)
463 {
464 struct dpu_kms *dpu_kms = to_dpu_kms(kms);
465 struct drm_crtc *crtc;
466
467 for_each_crtc_mask(dpu_kms->dev, crtc, crtc_mask) {
468 if (!crtc->state->active)
469 continue;
470
471 trace_dpu_kms_commit(DRMID(crtc));
472 dpu_crtc_commit_kickoff(crtc);
473 }
474 }
475
dpu_kms_complete_commit(struct msm_kms * kms,unsigned crtc_mask)476 static void dpu_kms_complete_commit(struct msm_kms *kms, unsigned crtc_mask)
477 {
478 struct dpu_kms *dpu_kms = to_dpu_kms(kms);
479 struct drm_crtc *crtc;
480
481 DPU_ATRACE_BEGIN("kms_complete_commit");
482
483 for_each_crtc_mask(dpu_kms->dev, crtc, crtc_mask)
484 dpu_crtc_complete_commit(crtc);
485
486 DPU_ATRACE_END("kms_complete_commit");
487 }
488
dpu_kms_wait_for_commit_done(struct msm_kms * kms,struct drm_crtc * crtc)489 static void dpu_kms_wait_for_commit_done(struct msm_kms *kms,
490 struct drm_crtc *crtc)
491 {
492 struct drm_encoder *encoder;
493 struct drm_device *dev;
494 int ret;
495
496 if (!kms || !crtc || !crtc->state) {
497 DPU_ERROR("invalid params\n");
498 return;
499 }
500
501 dev = crtc->dev;
502
503 if (!crtc->state->enable) {
504 DPU_DEBUG("[crtc:%d] not enable\n", crtc->base.id);
505 return;
506 }
507
508 if (!drm_atomic_crtc_effectively_active(crtc->state)) {
509 DPU_DEBUG("[crtc:%d] not active\n", crtc->base.id);
510 return;
511 }
512
513 list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
514 if (encoder->crtc != crtc)
515 continue;
516 /*
517 * Wait for post-flush if necessary to delay before
518 * plane_cleanup. For example, wait for vsync in case of video
519 * mode panels. This may be a no-op for command mode panels.
520 */
521 trace_dpu_kms_wait_for_commit_done(DRMID(crtc));
522 ret = dpu_encoder_wait_for_commit_done(encoder);
523 if (ret && ret != -EWOULDBLOCK) {
524 DPU_ERROR("wait for commit done returned %d\n", ret);
525 break;
526 }
527 }
528 }
529
dpu_kms_wait_flush(struct msm_kms * kms,unsigned crtc_mask)530 static void dpu_kms_wait_flush(struct msm_kms *kms, unsigned crtc_mask)
531 {
532 struct dpu_kms *dpu_kms = to_dpu_kms(kms);
533 struct drm_crtc *crtc;
534
535 for_each_crtc_mask(dpu_kms->dev, crtc, crtc_mask)
536 dpu_kms_wait_for_commit_done(kms, crtc);
537 }
538
539 static const char *dpu_vsync_sources[] = {
540 [DPU_VSYNC_SOURCE_GPIO_0] = "mdp_vsync_p",
541 [DPU_VSYNC_SOURCE_GPIO_1] = "mdp_vsync_s",
542 [DPU_VSYNC_SOURCE_GPIO_2] = "mdp_vsync_e",
543 [DPU_VSYNC_SOURCE_INTF_0] = "mdp_intf0",
544 [DPU_VSYNC_SOURCE_INTF_1] = "mdp_intf1",
545 [DPU_VSYNC_SOURCE_INTF_2] = "mdp_intf2",
546 [DPU_VSYNC_SOURCE_INTF_3] = "mdp_intf3",
547 [DPU_VSYNC_SOURCE_WD_TIMER_0] = "timer0",
548 [DPU_VSYNC_SOURCE_WD_TIMER_1] = "timer1",
549 [DPU_VSYNC_SOURCE_WD_TIMER_2] = "timer2",
550 [DPU_VSYNC_SOURCE_WD_TIMER_3] = "timer3",
551 [DPU_VSYNC_SOURCE_WD_TIMER_4] = "timer4",
552 };
553
dpu_kms_dsi_set_te_source(struct msm_display_info * info,struct msm_dsi * dsi)554 static int dpu_kms_dsi_set_te_source(struct msm_display_info *info,
555 struct msm_dsi *dsi)
556 {
557 const char *te_source = msm_dsi_get_te_source(dsi);
558 int i;
559
560 if (!te_source) {
561 info->vsync_source = DPU_VSYNC_SOURCE_GPIO_0;
562 return 0;
563 }
564
565 /* we can not use match_string since dpu_vsync_sources is a sparse array */
566 for (i = 0; i < ARRAY_SIZE(dpu_vsync_sources); i++) {
567 if (dpu_vsync_sources[i] &&
568 !strcmp(dpu_vsync_sources[i], te_source)) {
569 info->vsync_source = i;
570 return 0;
571 }
572 }
573
574 return -EINVAL;
575 }
576
_dpu_kms_initialize_dsi(struct drm_device * dev,struct msm_drm_private * priv,struct dpu_kms * dpu_kms)577 static int _dpu_kms_initialize_dsi(struct drm_device *dev,
578 struct msm_drm_private *priv,
579 struct dpu_kms *dpu_kms)
580 {
581 struct drm_encoder *encoder = NULL;
582 struct msm_display_info info;
583 int i, rc = 0;
584
585 if (!(priv->dsi[0] || priv->dsi[1]))
586 return rc;
587
588 /*
589 * We support following confiurations:
590 * - Single DSI host (dsi0 or dsi1)
591 * - Two independent DSI hosts
592 * - Bonded DSI0 and DSI1 hosts
593 *
594 * TODO: Support swapping DSI0 and DSI1 in the bonded setup.
595 */
596 for (i = 0; i < ARRAY_SIZE(priv->dsi); i++) {
597 int other = (i + 1) % 2;
598
599 if (!priv->dsi[i])
600 continue;
601
602 if (msm_dsi_is_bonded_dsi(priv->dsi[i]) &&
603 !msm_dsi_is_master_dsi(priv->dsi[i]))
604 continue;
605
606 memset(&info, 0, sizeof(info));
607 info.intf_type = INTF_DSI;
608
609 info.h_tile_instance[info.num_of_h_tiles++] = i;
610 if (msm_dsi_is_bonded_dsi(priv->dsi[i]))
611 info.h_tile_instance[info.num_of_h_tiles++] = other;
612
613 info.is_cmd_mode = msm_dsi_is_cmd_mode(priv->dsi[i]);
614
615 rc = dpu_kms_dsi_set_te_source(&info, priv->dsi[i]);
616 if (rc) {
617 DPU_ERROR("failed to identify TE source for dsi display\n");
618 return rc;
619 }
620
621 encoder = dpu_encoder_init(dev, DRM_MODE_ENCODER_DSI, &info);
622 if (IS_ERR(encoder)) {
623 DPU_ERROR("encoder init failed for dsi display\n");
624 return PTR_ERR(encoder);
625 }
626
627 rc = msm_dsi_modeset_init(priv->dsi[i], dev, encoder);
628 if (rc) {
629 DPU_ERROR("modeset_init failed for dsi[%d], rc = %d\n",
630 i, rc);
631 break;
632 }
633
634 if (msm_dsi_is_bonded_dsi(priv->dsi[i]) && priv->dsi[other]) {
635 rc = msm_dsi_modeset_init(priv->dsi[other], dev, encoder);
636 if (rc) {
637 DPU_ERROR("modeset_init failed for dsi[%d], rc = %d\n",
638 other, rc);
639 break;
640 }
641 }
642 }
643
644 return rc;
645 }
646
_dpu_kms_initialize_displayport(struct drm_device * dev,struct msm_drm_private * priv,struct dpu_kms * dpu_kms)647 static int _dpu_kms_initialize_displayport(struct drm_device *dev,
648 struct msm_drm_private *priv,
649 struct dpu_kms *dpu_kms)
650 {
651 struct drm_encoder *encoder = NULL;
652 struct msm_display_info info;
653 bool yuv_supported;
654 int rc;
655 int i;
656
657 for (i = 0; i < ARRAY_SIZE(priv->dp); i++) {
658 if (!priv->dp[i])
659 continue;
660
661 memset(&info, 0, sizeof(info));
662 info.num_of_h_tiles = 1;
663 info.h_tile_instance[0] = i;
664 info.intf_type = INTF_DP;
665
666 encoder = dpu_encoder_init(dev, DRM_MODE_ENCODER_TMDS, &info);
667 if (IS_ERR(encoder)) {
668 DPU_ERROR("encoder init failed for dsi display\n");
669 return PTR_ERR(encoder);
670 }
671
672 yuv_supported = !!dpu_kms->catalog->cdm;
673 rc = msm_dp_modeset_init(priv->dp[i], dev, encoder, yuv_supported);
674 if (rc) {
675 DPU_ERROR("modeset_init failed for DP, rc = %d\n", rc);
676 return rc;
677 }
678 }
679
680 return 0;
681 }
682
_dpu_kms_initialize_hdmi(struct drm_device * dev,struct msm_drm_private * priv,struct dpu_kms * dpu_kms)683 static int _dpu_kms_initialize_hdmi(struct drm_device *dev,
684 struct msm_drm_private *priv,
685 struct dpu_kms *dpu_kms)
686 {
687 struct drm_encoder *encoder = NULL;
688 struct msm_display_info info;
689 int rc;
690
691 if (!priv->hdmi)
692 return 0;
693
694 memset(&info, 0, sizeof(info));
695 info.num_of_h_tiles = 1;
696 info.h_tile_instance[0] = 0;
697 info.intf_type = INTF_HDMI;
698
699 encoder = dpu_encoder_init(dev, DRM_MODE_ENCODER_TMDS, &info);
700 if (IS_ERR(encoder)) {
701 DPU_ERROR("encoder init failed for HDMI display\n");
702 return PTR_ERR(encoder);
703 }
704
705 rc = msm_hdmi_modeset_init(priv->hdmi, dev, encoder);
706 if (rc) {
707 DPU_ERROR("modeset_init failed for DP, rc = %d\n", rc);
708 return rc;
709 }
710
711 return 0;
712 }
713
_dpu_kms_initialize_writeback(struct drm_device * dev,struct msm_drm_private * priv,struct dpu_kms * dpu_kms,const u32 * wb_formats,int n_formats)714 static int _dpu_kms_initialize_writeback(struct drm_device *dev,
715 struct msm_drm_private *priv, struct dpu_kms *dpu_kms,
716 const u32 *wb_formats, int n_formats)
717 {
718 struct drm_encoder *encoder = NULL;
719 struct msm_display_info info;
720 const enum dpu_wb wb_idx = WB_2;
721 u32 maxlinewidth;
722 int rc;
723
724 memset(&info, 0, sizeof(info));
725
726 info.num_of_h_tiles = 1;
727 /* use only WB idx 2 instance for DPU */
728 info.h_tile_instance[0] = wb_idx;
729 info.intf_type = INTF_WB;
730
731 maxlinewidth = dpu_rm_get_wb(&dpu_kms->rm, info.h_tile_instance[0])->caps->maxlinewidth;
732
733 encoder = dpu_encoder_init(dev, DRM_MODE_ENCODER_VIRTUAL, &info);
734 if (IS_ERR(encoder)) {
735 DPU_ERROR("encoder init failed for dsi display\n");
736 return PTR_ERR(encoder);
737 }
738
739 rc = dpu_writeback_init(dev, encoder, wb_formats, n_formats, maxlinewidth);
740 if (rc) {
741 DPU_ERROR("dpu_writeback_init, rc = %d\n", rc);
742 return rc;
743 }
744
745 return 0;
746 }
747
748 /**
749 * _dpu_kms_setup_displays - create encoders, bridges and connectors
750 * for underlying displays
751 * @dev: Pointer to drm device structure
752 * @priv: Pointer to private drm device data
753 * @dpu_kms: Pointer to dpu kms structure
754 * Returns: Zero on success
755 */
_dpu_kms_setup_displays(struct drm_device * dev,struct msm_drm_private * priv,struct dpu_kms * dpu_kms)756 static int _dpu_kms_setup_displays(struct drm_device *dev,
757 struct msm_drm_private *priv,
758 struct dpu_kms *dpu_kms)
759 {
760 int rc = 0;
761 int i;
762
763 rc = _dpu_kms_initialize_dsi(dev, priv, dpu_kms);
764 if (rc) {
765 DPU_ERROR("initialize_dsi failed, rc = %d\n", rc);
766 return rc;
767 }
768
769 rc = _dpu_kms_initialize_displayport(dev, priv, dpu_kms);
770 if (rc) {
771 DPU_ERROR("initialize_DP failed, rc = %d\n", rc);
772 return rc;
773 }
774
775 rc = _dpu_kms_initialize_hdmi(dev, priv, dpu_kms);
776 if (rc) {
777 DPU_ERROR("initialize HDMI failed, rc = %d\n", rc);
778 return rc;
779 }
780
781 /* Since WB isn't a driver check the catalog before initializing */
782 if (dpu_kms->catalog->wb_count) {
783 for (i = 0; i < dpu_kms->catalog->wb_count; i++) {
784 if (dpu_kms->catalog->wb[i].id == WB_2) {
785 rc = _dpu_kms_initialize_writeback(dev, priv, dpu_kms,
786 dpu_kms->catalog->wb[i].format_list,
787 dpu_kms->catalog->wb[i].num_formats);
788 if (rc) {
789 DPU_ERROR("initialize_WB failed, rc = %d\n", rc);
790 return rc;
791 }
792 }
793 }
794 }
795
796 return rc;
797 }
798
799 #define MAX_PLANES 20
_dpu_kms_drm_obj_init(struct dpu_kms * dpu_kms)800 static int _dpu_kms_drm_obj_init(struct dpu_kms *dpu_kms)
801 {
802 struct drm_device *dev;
803 struct drm_plane *primary_planes[MAX_PLANES], *plane;
804 struct drm_plane *cursor_planes[MAX_PLANES] = { NULL };
805 struct drm_crtc *crtc;
806 struct drm_encoder *encoder;
807 unsigned int num_encoders;
808
809 struct msm_drm_private *priv;
810 const struct dpu_mdss_cfg *catalog;
811
812 int primary_planes_idx = 0, cursor_planes_idx = 0, i, ret;
813 int max_crtc_count;
814 dev = dpu_kms->dev;
815 priv = dev->dev_private;
816 catalog = dpu_kms->catalog;
817
818 /*
819 * Create encoder and query display drivers to create
820 * bridges and connectors
821 */
822 ret = _dpu_kms_setup_displays(dev, priv, dpu_kms);
823 if (ret)
824 return ret;
825
826 num_encoders = 0;
827 drm_for_each_encoder(encoder, dev) {
828 num_encoders++;
829 if (catalog->cwb_count > 0)
830 encoder->possible_clones = dpu_encoder_get_clones(encoder);
831 }
832
833 max_crtc_count = min(catalog->mixer_count, num_encoders);
834
835 /* Create the planes, keeping track of one primary/cursor per crtc */
836 for (i = 0; i < catalog->sspp_count; i++) {
837 enum drm_plane_type type;
838
839 if ((catalog->sspp[i].features & BIT(DPU_SSPP_CURSOR))
840 && cursor_planes_idx < max_crtc_count)
841 type = DRM_PLANE_TYPE_CURSOR;
842 else if (primary_planes_idx < max_crtc_count)
843 type = DRM_PLANE_TYPE_PRIMARY;
844 else
845 type = DRM_PLANE_TYPE_OVERLAY;
846
847 DPU_DEBUG("Create plane type %d with features %lx (cur %lx)\n",
848 type, catalog->sspp[i].features,
849 catalog->sspp[i].features & BIT(DPU_SSPP_CURSOR));
850
851 if (dpu_use_virtual_planes)
852 plane = dpu_plane_init_virtual(dev, type, (1UL << max_crtc_count) - 1);
853 else
854 plane = dpu_plane_init(dev, catalog->sspp[i].id, type,
855 (1UL << max_crtc_count) - 1);
856 if (IS_ERR(plane)) {
857 DPU_ERROR("dpu_plane_init failed\n");
858 ret = PTR_ERR(plane);
859 return ret;
860 }
861
862 if (type == DRM_PLANE_TYPE_CURSOR)
863 cursor_planes[cursor_planes_idx++] = plane;
864 else if (type == DRM_PLANE_TYPE_PRIMARY)
865 primary_planes[primary_planes_idx++] = plane;
866 }
867
868 max_crtc_count = min(max_crtc_count, primary_planes_idx);
869
870 /* Create one CRTC per encoder */
871 for (i = 0; i < max_crtc_count; i++) {
872 crtc = dpu_crtc_init(dev, primary_planes[i], cursor_planes[i]);
873 if (IS_ERR(crtc)) {
874 ret = PTR_ERR(crtc);
875 return ret;
876 }
877 priv->num_crtcs++;
878 }
879
880 /* All CRTCs are compatible with all encoders */
881 drm_for_each_encoder(encoder, dev)
882 encoder->possible_crtcs = (1 << priv->num_crtcs) - 1;
883
884 return 0;
885 }
886
_dpu_kms_hw_destroy(struct dpu_kms * dpu_kms)887 static void _dpu_kms_hw_destroy(struct dpu_kms *dpu_kms)
888 {
889 int i;
890
891 dpu_kms->hw_intr = NULL;
892
893 /* safe to call these more than once during shutdown */
894 _dpu_kms_mmu_destroy(dpu_kms);
895
896 for (i = 0; i < ARRAY_SIZE(dpu_kms->hw_vbif); i++) {
897 dpu_kms->hw_vbif[i] = NULL;
898 }
899
900 dpu_kms_global_obj_fini(dpu_kms);
901
902 dpu_kms->catalog = NULL;
903
904 dpu_kms->hw_mdp = NULL;
905 }
906
dpu_kms_destroy(struct msm_kms * kms)907 static void dpu_kms_destroy(struct msm_kms *kms)
908 {
909 struct dpu_kms *dpu_kms;
910
911 if (!kms) {
912 DPU_ERROR("invalid kms\n");
913 return;
914 }
915
916 dpu_kms = to_dpu_kms(kms);
917
918 _dpu_kms_hw_destroy(dpu_kms);
919
920 msm_kms_destroy(&dpu_kms->base);
921
922 if (dpu_kms->rpm_enabled)
923 pm_runtime_disable(&dpu_kms->pdev->dev);
924 }
925
dpu_irq_postinstall(struct msm_kms * kms)926 static int dpu_irq_postinstall(struct msm_kms *kms)
927 {
928 struct msm_drm_private *priv;
929 struct dpu_kms *dpu_kms = to_dpu_kms(kms);
930
931 if (!dpu_kms || !dpu_kms->dev)
932 return -EINVAL;
933
934 priv = dpu_kms->dev->dev_private;
935 if (!priv)
936 return -EINVAL;
937
938 return 0;
939 }
940
dpu_kms_mdp_snapshot(struct msm_disp_state * disp_state,struct msm_kms * kms)941 static void dpu_kms_mdp_snapshot(struct msm_disp_state *disp_state, struct msm_kms *kms)
942 {
943 int i;
944 struct dpu_kms *dpu_kms;
945 const struct dpu_mdss_cfg *cat;
946 void __iomem *base;
947
948 dpu_kms = to_dpu_kms(kms);
949
950 cat = dpu_kms->catalog;
951
952 pm_runtime_get_sync(&dpu_kms->pdev->dev);
953
954 /* dump CTL sub-blocks HW regs info */
955 for (i = 0; i < cat->ctl_count; i++)
956 msm_disp_snapshot_add_block(disp_state, cat->ctl[i].len,
957 dpu_kms->mmio + cat->ctl[i].base, "%s",
958 cat->ctl[i].name);
959
960 /* dump DSPP sub-blocks HW regs info */
961 for (i = 0; i < cat->dspp_count; i++) {
962 base = dpu_kms->mmio + cat->dspp[i].base;
963 msm_disp_snapshot_add_block(disp_state, cat->dspp[i].len, base,
964 "%s", cat->dspp[i].name);
965
966 if (cat->dspp[i].sblk && cat->dspp[i].sblk->pcc.len > 0)
967 msm_disp_snapshot_add_block(disp_state, cat->dspp[i].sblk->pcc.len,
968 base + cat->dspp[i].sblk->pcc.base, "%s_%s",
969 cat->dspp[i].name,
970 cat->dspp[i].sblk->pcc.name);
971 }
972
973 /* dump INTF sub-blocks HW regs info */
974 for (i = 0; i < cat->intf_count; i++)
975 msm_disp_snapshot_add_block(disp_state, cat->intf[i].len,
976 dpu_kms->mmio + cat->intf[i].base, "%s",
977 cat->intf[i].name);
978
979 /* dump PP sub-blocks HW regs info */
980 for (i = 0; i < cat->pingpong_count; i++) {
981 base = dpu_kms->mmio + cat->pingpong[i].base;
982 msm_disp_snapshot_add_block(disp_state, cat->pingpong[i].len, base,
983 "%s", cat->pingpong[i].name);
984
985 /* TE2 sub-block has length of 0, so will not print it */
986
987 if (cat->pingpong[i].sblk && cat->pingpong[i].sblk->dither.len > 0)
988 msm_disp_snapshot_add_block(disp_state, cat->pingpong[i].sblk->dither.len,
989 base + cat->pingpong[i].sblk->dither.base,
990 "%s_%s", cat->pingpong[i].name,
991 cat->pingpong[i].sblk->dither.name);
992 }
993
994 /* dump SSPP sub-blocks HW regs info */
995 for (i = 0; i < cat->sspp_count; i++) {
996 base = dpu_kms->mmio + cat->sspp[i].base;
997 msm_disp_snapshot_add_block(disp_state, cat->sspp[i].len, base,
998 "%s", cat->sspp[i].name);
999
1000 if (cat->sspp[i].sblk && cat->sspp[i].sblk->scaler_blk.len > 0)
1001 msm_disp_snapshot_add_block(disp_state, cat->sspp[i].sblk->scaler_blk.len,
1002 base + cat->sspp[i].sblk->scaler_blk.base,
1003 "%s_%s", cat->sspp[i].name,
1004 cat->sspp[i].sblk->scaler_blk.name);
1005
1006 if (cat->sspp[i].sblk && cat->sspp[i].sblk->csc_blk.len > 0)
1007 msm_disp_snapshot_add_block(disp_state, cat->sspp[i].sblk->csc_blk.len,
1008 base + cat->sspp[i].sblk->csc_blk.base,
1009 "%s_%s", cat->sspp[i].name,
1010 cat->sspp[i].sblk->csc_blk.name);
1011 }
1012
1013 /* dump LM sub-blocks HW regs info */
1014 for (i = 0; i < cat->mixer_count; i++)
1015 msm_disp_snapshot_add_block(disp_state, cat->mixer[i].len,
1016 dpu_kms->mmio + cat->mixer[i].base,
1017 "%s", cat->mixer[i].name);
1018
1019 /* dump WB sub-blocks HW regs info */
1020 for (i = 0; i < cat->wb_count; i++)
1021 msm_disp_snapshot_add_block(disp_state, cat->wb[i].len,
1022 dpu_kms->mmio + cat->wb[i].base, "%s",
1023 cat->wb[i].name);
1024
1025 if (cat->mdp[0].features & BIT(DPU_MDP_PERIPH_0_REMOVED)) {
1026 msm_disp_snapshot_add_block(disp_state, MDP_PERIPH_TOP0,
1027 dpu_kms->mmio + cat->mdp[0].base, "top");
1028 msm_disp_snapshot_add_block(disp_state, cat->mdp[0].len - MDP_PERIPH_TOP0_END,
1029 dpu_kms->mmio + cat->mdp[0].base + MDP_PERIPH_TOP0_END, "top_2");
1030 } else {
1031 msm_disp_snapshot_add_block(disp_state, cat->mdp[0].len,
1032 dpu_kms->mmio + cat->mdp[0].base, "top");
1033 }
1034
1035 /* dump CWB sub-blocks HW regs info */
1036 for (i = 0; i < cat->cwb_count; i++)
1037 msm_disp_snapshot_add_block(disp_state, cat->cwb[i].len,
1038 dpu_kms->mmio + cat->cwb[i].base, cat->cwb[i].name);
1039
1040 /* dump DSC sub-blocks HW regs info */
1041 for (i = 0; i < cat->dsc_count; i++) {
1042 base = dpu_kms->mmio + cat->dsc[i].base;
1043 msm_disp_snapshot_add_block(disp_state, cat->dsc[i].len, base,
1044 "%s", cat->dsc[i].name);
1045
1046 if (cat->dsc[i].features & BIT(DPU_DSC_HW_REV_1_2)) {
1047 struct dpu_dsc_blk enc = cat->dsc[i].sblk->enc;
1048 struct dpu_dsc_blk ctl = cat->dsc[i].sblk->ctl;
1049
1050 msm_disp_snapshot_add_block(disp_state, enc.len, base + enc.base, "%s_%s",
1051 cat->dsc[i].name, enc.name);
1052 msm_disp_snapshot_add_block(disp_state, ctl.len, base + ctl.base, "%s_%s",
1053 cat->dsc[i].name, ctl.name);
1054 }
1055 }
1056
1057 if (cat->cdm)
1058 msm_disp_snapshot_add_block(disp_state, cat->cdm->len,
1059 dpu_kms->mmio + cat->cdm->base,
1060 "%s", cat->cdm->name);
1061
1062 for (i = 0; i < dpu_kms->catalog->vbif_count; i++) {
1063 const struct dpu_vbif_cfg *vbif = &dpu_kms->catalog->vbif[i];
1064
1065 msm_disp_snapshot_add_block(disp_state, vbif->len,
1066 dpu_kms->vbif[vbif->id] + vbif->base,
1067 "%s", vbif->name);
1068 }
1069
1070 pm_runtime_put_sync(&dpu_kms->pdev->dev);
1071 }
1072
1073 static const struct msm_kms_funcs kms_funcs = {
1074 .hw_init = dpu_kms_hw_init,
1075 .irq_preinstall = dpu_core_irq_preinstall,
1076 .irq_postinstall = dpu_irq_postinstall,
1077 .irq_uninstall = dpu_core_irq_uninstall,
1078 .irq = dpu_core_irq,
1079 .enable_commit = dpu_kms_enable_commit,
1080 .disable_commit = dpu_kms_disable_commit,
1081 .check_mode_changed = dpu_kms_check_mode_changed,
1082 .flush_commit = dpu_kms_flush_commit,
1083 .wait_flush = dpu_kms_wait_flush,
1084 .complete_commit = dpu_kms_complete_commit,
1085 .enable_vblank = dpu_kms_enable_vblank,
1086 .disable_vblank = dpu_kms_disable_vblank,
1087 .destroy = dpu_kms_destroy,
1088 .snapshot = dpu_kms_mdp_snapshot,
1089 #ifdef CONFIG_DEBUG_FS
1090 .debugfs_init = dpu_kms_debugfs_init,
1091 #endif
1092 };
1093
_dpu_kms_mmu_destroy(struct dpu_kms * dpu_kms)1094 static void _dpu_kms_mmu_destroy(struct dpu_kms *dpu_kms)
1095 {
1096 struct msm_mmu *mmu;
1097
1098 if (!dpu_kms->base.aspace)
1099 return;
1100
1101 mmu = dpu_kms->base.aspace->mmu;
1102
1103 mmu->funcs->detach(mmu);
1104 msm_gem_address_space_put(dpu_kms->base.aspace);
1105
1106 dpu_kms->base.aspace = NULL;
1107 }
1108
_dpu_kms_mmu_init(struct dpu_kms * dpu_kms)1109 static int _dpu_kms_mmu_init(struct dpu_kms *dpu_kms)
1110 {
1111 struct msm_gem_address_space *aspace;
1112
1113 aspace = msm_kms_init_aspace(dpu_kms->dev);
1114 if (IS_ERR(aspace))
1115 return PTR_ERR(aspace);
1116
1117 dpu_kms->base.aspace = aspace;
1118
1119 return 0;
1120 }
1121
1122 /**
1123 * dpu_kms_get_clk_rate() - get the clock rate
1124 * @dpu_kms: pointer to dpu_kms structure
1125 * @clock_name: clock name to get the rate
1126 *
1127 * Return: current clock rate
1128 */
dpu_kms_get_clk_rate(struct dpu_kms * dpu_kms,char * clock_name)1129 unsigned long dpu_kms_get_clk_rate(struct dpu_kms *dpu_kms, char *clock_name)
1130 {
1131 struct clk *clk;
1132
1133 clk = msm_clk_bulk_get_clock(dpu_kms->clocks, dpu_kms->num_clocks, clock_name);
1134 if (!clk)
1135 return 0;
1136
1137 return clk_get_rate(clk);
1138 }
1139
1140 #define DPU_PERF_DEFAULT_MAX_CORE_CLK_RATE 412500000
1141
dpu_kms_hw_init(struct msm_kms * kms)1142 static int dpu_kms_hw_init(struct msm_kms *kms)
1143 {
1144 struct dpu_kms *dpu_kms;
1145 struct drm_device *dev;
1146 int i, rc = -EINVAL;
1147 unsigned long max_core_clk_rate;
1148 u32 core_rev;
1149
1150 if (!kms) {
1151 DPU_ERROR("invalid kms\n");
1152 return rc;
1153 }
1154
1155 dpu_kms = to_dpu_kms(kms);
1156 dev = dpu_kms->dev;
1157
1158 dev->mode_config.cursor_width = 512;
1159 dev->mode_config.cursor_height = 512;
1160
1161 rc = dpu_kms_global_obj_init(dpu_kms);
1162 if (rc)
1163 return rc;
1164
1165 atomic_set(&dpu_kms->bandwidth_ref, 0);
1166
1167 rc = pm_runtime_resume_and_get(&dpu_kms->pdev->dev);
1168 if (rc < 0)
1169 goto error;
1170
1171 core_rev = readl_relaxed(dpu_kms->mmio + 0x0);
1172
1173 pr_info("dpu hardware revision:0x%x\n", core_rev);
1174
1175 dpu_kms->catalog = of_device_get_match_data(dev->dev);
1176 if (!dpu_kms->catalog) {
1177 DPU_ERROR("device config not known!\n");
1178 rc = -EINVAL;
1179 goto err_pm_put;
1180 }
1181
1182 /*
1183 * Now we need to read the HW catalog and initialize resources such as
1184 * clocks, regulators, GDSC/MMAGIC, ioremap the register ranges etc
1185 */
1186 rc = _dpu_kms_mmu_init(dpu_kms);
1187 if (rc) {
1188 DPU_ERROR("dpu_kms_mmu_init failed: %d\n", rc);
1189 goto err_pm_put;
1190 }
1191
1192 dpu_kms->mdss = msm_mdss_get_mdss_data(dpu_kms->pdev->dev.parent);
1193 if (IS_ERR(dpu_kms->mdss)) {
1194 rc = PTR_ERR(dpu_kms->mdss);
1195 DPU_ERROR("failed to get MDSS data: %d\n", rc);
1196 goto err_pm_put;
1197 }
1198
1199 if (!dpu_kms->mdss) {
1200 rc = -EINVAL;
1201 DPU_ERROR("NULL MDSS data\n");
1202 goto err_pm_put;
1203 }
1204
1205 rc = dpu_rm_init(dev, &dpu_kms->rm, dpu_kms->catalog, dpu_kms->mdss, dpu_kms->mmio);
1206 if (rc) {
1207 DPU_ERROR("rm init failed: %d\n", rc);
1208 goto err_pm_put;
1209 }
1210
1211 dpu_kms->hw_mdp = dpu_hw_mdptop_init(dev,
1212 dpu_kms->catalog->mdp,
1213 dpu_kms->mmio,
1214 dpu_kms->catalog->mdss_ver);
1215 if (IS_ERR(dpu_kms->hw_mdp)) {
1216 rc = PTR_ERR(dpu_kms->hw_mdp);
1217 DPU_ERROR("failed to get hw_mdp: %d\n", rc);
1218 dpu_kms->hw_mdp = NULL;
1219 goto err_pm_put;
1220 }
1221
1222 for (i = 0; i < dpu_kms->catalog->vbif_count; i++) {
1223 struct dpu_hw_vbif *hw;
1224 const struct dpu_vbif_cfg *vbif = &dpu_kms->catalog->vbif[i];
1225
1226 hw = dpu_hw_vbif_init(dev, vbif, dpu_kms->vbif[vbif->id]);
1227 if (IS_ERR(hw)) {
1228 rc = PTR_ERR(hw);
1229 DPU_ERROR("failed to init vbif %d: %d\n", vbif->id, rc);
1230 goto err_pm_put;
1231 }
1232
1233 dpu_kms->hw_vbif[vbif->id] = hw;
1234 }
1235
1236 /* TODO: use the same max_freq as in dpu_kms_hw_init */
1237 max_core_clk_rate = dpu_kms_get_clk_rate(dpu_kms, "core");
1238 if (!max_core_clk_rate) {
1239 DPU_DEBUG("max core clk rate not determined, using default\n");
1240 max_core_clk_rate = DPU_PERF_DEFAULT_MAX_CORE_CLK_RATE;
1241 }
1242
1243 rc = dpu_core_perf_init(&dpu_kms->perf, dpu_kms->catalog->perf, max_core_clk_rate);
1244 if (rc) {
1245 DPU_ERROR("failed to init perf %d\n", rc);
1246 goto err_pm_put;
1247 }
1248
1249 /*
1250 * We need to program DP <-> PHY relationship only for SC8180X since it
1251 * has fewer DP controllers than DP PHYs.
1252 * If any other platform requires the same kind of programming, or if
1253 * the INTF <->DP relationship isn't static anymore, this needs to be
1254 * configured through the DT.
1255 */
1256 if (of_device_is_compatible(dpu_kms->pdev->dev.of_node, "qcom,sc8180x-dpu"))
1257 dpu_kms->hw_mdp->ops.dp_phy_intf_sel(dpu_kms->hw_mdp, (unsigned int[]){ 1, 2, });
1258
1259 dpu_kms->hw_intr = dpu_hw_intr_init(dev, dpu_kms->mmio, dpu_kms->catalog);
1260 if (IS_ERR(dpu_kms->hw_intr)) {
1261 rc = PTR_ERR(dpu_kms->hw_intr);
1262 DPU_ERROR("hw_intr init failed: %d\n", rc);
1263 dpu_kms->hw_intr = NULL;
1264 goto err_pm_put;
1265 }
1266
1267 dev->mode_config.min_width = 0;
1268 dev->mode_config.min_height = 0;
1269
1270 dev->mode_config.max_width = DPU_MAX_IMG_WIDTH;
1271 dev->mode_config.max_height = DPU_MAX_IMG_HEIGHT;
1272
1273 dev->max_vblank_count = 0xffffffff;
1274 /* Disable vblank irqs aggressively for power-saving */
1275 dev->vblank_disable_immediate = true;
1276
1277 /*
1278 * _dpu_kms_drm_obj_init should create the DRM related objects
1279 * i.e. CRTCs, planes, encoders, connectors and so forth
1280 */
1281 rc = _dpu_kms_drm_obj_init(dpu_kms);
1282 if (rc) {
1283 DPU_ERROR("modeset init failed: %d\n", rc);
1284 goto err_pm_put;
1285 }
1286
1287 dpu_vbif_init_memtypes(dpu_kms);
1288
1289 pm_runtime_put_sync(&dpu_kms->pdev->dev);
1290
1291 return 0;
1292
1293 err_pm_put:
1294 pm_runtime_put_sync(&dpu_kms->pdev->dev);
1295 error:
1296 _dpu_kms_hw_destroy(dpu_kms);
1297
1298 return rc;
1299 }
1300
dpu_kms_init(struct drm_device * ddev)1301 static int dpu_kms_init(struct drm_device *ddev)
1302 {
1303 struct msm_drm_private *priv = ddev->dev_private;
1304 struct device *dev = ddev->dev;
1305 struct platform_device *pdev = to_platform_device(dev);
1306 struct dpu_kms *dpu_kms = to_dpu_kms(priv->kms);
1307 struct dev_pm_opp *opp;
1308 int ret = 0;
1309 unsigned long max_freq = ULONG_MAX;
1310
1311 opp = dev_pm_opp_find_freq_floor(dev, &max_freq);
1312 if (!IS_ERR(opp))
1313 dev_pm_opp_put(opp);
1314
1315 dev_pm_opp_set_rate(dev, max_freq);
1316
1317 ret = msm_kms_init(&dpu_kms->base, &kms_funcs);
1318 if (ret) {
1319 DPU_ERROR("failed to init kms, ret=%d\n", ret);
1320 return ret;
1321 }
1322 dpu_kms->dev = ddev;
1323
1324 pm_runtime_enable(&pdev->dev);
1325 dpu_kms->rpm_enabled = true;
1326
1327 return 0;
1328 }
1329
dpu_kms_mmap_mdp5(struct dpu_kms * dpu_kms)1330 static int dpu_kms_mmap_mdp5(struct dpu_kms *dpu_kms)
1331 {
1332 struct platform_device *pdev = dpu_kms->pdev;
1333 struct platform_device *mdss_dev;
1334 int ret;
1335
1336 if (!dev_is_platform(dpu_kms->pdev->dev.parent))
1337 return -EINVAL;
1338
1339 mdss_dev = to_platform_device(dpu_kms->pdev->dev.parent);
1340
1341 dpu_kms->mmio = msm_ioremap(pdev, "mdp_phys");
1342 if (IS_ERR(dpu_kms->mmio)) {
1343 ret = PTR_ERR(dpu_kms->mmio);
1344 DPU_ERROR("mdp register memory map failed: %d\n", ret);
1345 dpu_kms->mmio = NULL;
1346 return ret;
1347 }
1348 DRM_DEBUG("mapped dpu address space @%pK\n", dpu_kms->mmio);
1349
1350 dpu_kms->vbif[VBIF_RT] = msm_ioremap_mdss(mdss_dev,
1351 dpu_kms->pdev,
1352 "vbif_phys");
1353 if (IS_ERR(dpu_kms->vbif[VBIF_RT])) {
1354 ret = PTR_ERR(dpu_kms->vbif[VBIF_RT]);
1355 DPU_ERROR("vbif register memory map failed: %d\n", ret);
1356 dpu_kms->vbif[VBIF_RT] = NULL;
1357 return ret;
1358 }
1359
1360 dpu_kms->vbif[VBIF_NRT] = msm_ioremap_mdss(mdss_dev,
1361 dpu_kms->pdev,
1362 "vbif_nrt_phys");
1363 if (IS_ERR(dpu_kms->vbif[VBIF_NRT])) {
1364 dpu_kms->vbif[VBIF_NRT] = NULL;
1365 DPU_DEBUG("VBIF NRT is not defined");
1366 }
1367
1368 return 0;
1369 }
1370
dpu_kms_mmap_dpu(struct dpu_kms * dpu_kms)1371 static int dpu_kms_mmap_dpu(struct dpu_kms *dpu_kms)
1372 {
1373 struct platform_device *pdev = dpu_kms->pdev;
1374 int ret;
1375
1376 dpu_kms->mmio = msm_ioremap(pdev, "mdp");
1377 if (IS_ERR(dpu_kms->mmio)) {
1378 ret = PTR_ERR(dpu_kms->mmio);
1379 DPU_ERROR("mdp register memory map failed: %d\n", ret);
1380 dpu_kms->mmio = NULL;
1381 return ret;
1382 }
1383 DRM_DEBUG("mapped dpu address space @%pK\n", dpu_kms->mmio);
1384
1385 dpu_kms->vbif[VBIF_RT] = msm_ioremap(pdev, "vbif");
1386 if (IS_ERR(dpu_kms->vbif[VBIF_RT])) {
1387 ret = PTR_ERR(dpu_kms->vbif[VBIF_RT]);
1388 DPU_ERROR("vbif register memory map failed: %d\n", ret);
1389 dpu_kms->vbif[VBIF_RT] = NULL;
1390 return ret;
1391 }
1392
1393 dpu_kms->vbif[VBIF_NRT] = msm_ioremap_quiet(pdev, "vbif_nrt");
1394 if (IS_ERR(dpu_kms->vbif[VBIF_NRT])) {
1395 dpu_kms->vbif[VBIF_NRT] = NULL;
1396 DPU_DEBUG("VBIF NRT is not defined");
1397 }
1398
1399 return 0;
1400 }
1401
dpu_dev_probe(struct platform_device * pdev)1402 static int dpu_dev_probe(struct platform_device *pdev)
1403 {
1404 struct device *dev = &pdev->dev;
1405 struct dpu_kms *dpu_kms;
1406 int irq;
1407 int ret = 0;
1408
1409 if (!msm_disp_drv_should_bind(&pdev->dev, true))
1410 return -ENODEV;
1411
1412 dpu_kms = devm_kzalloc(dev, sizeof(*dpu_kms), GFP_KERNEL);
1413 if (!dpu_kms)
1414 return -ENOMEM;
1415
1416 dpu_kms->pdev = pdev;
1417
1418 ret = devm_pm_opp_set_clkname(dev, "core");
1419 if (ret)
1420 return ret;
1421 /* OPP table is optional */
1422 ret = devm_pm_opp_of_add_table(dev);
1423 if (ret && ret != -ENODEV)
1424 return dev_err_probe(dev, ret, "invalid OPP table in device tree\n");
1425
1426 ret = devm_clk_bulk_get_all(&pdev->dev, &dpu_kms->clocks);
1427 if (ret < 0)
1428 return dev_err_probe(dev, ret, "failed to parse clocks\n");
1429
1430 dpu_kms->num_clocks = ret;
1431
1432 irq = platform_get_irq(pdev, 0);
1433 if (irq < 0)
1434 return dev_err_probe(dev, irq, "failed to get irq\n");
1435
1436 dpu_kms->base.irq = irq;
1437
1438 if (of_device_is_compatible(dpu_kms->pdev->dev.of_node, "qcom,mdp5"))
1439 ret = dpu_kms_mmap_mdp5(dpu_kms);
1440 else
1441 ret = dpu_kms_mmap_dpu(dpu_kms);
1442 if (ret)
1443 return ret;
1444
1445 ret = dpu_kms_parse_data_bus_icc_path(dpu_kms);
1446 if (ret)
1447 return ret;
1448
1449 return msm_drv_probe(&pdev->dev, dpu_kms_init, &dpu_kms->base);
1450 }
1451
dpu_dev_remove(struct platform_device * pdev)1452 static void dpu_dev_remove(struct platform_device *pdev)
1453 {
1454 component_master_del(&pdev->dev, &msm_drm_ops);
1455 }
1456
dpu_runtime_suspend(struct device * dev)1457 static int __maybe_unused dpu_runtime_suspend(struct device *dev)
1458 {
1459 int i;
1460 struct platform_device *pdev = to_platform_device(dev);
1461 struct msm_drm_private *priv = platform_get_drvdata(pdev);
1462 struct dpu_kms *dpu_kms = to_dpu_kms(priv->kms);
1463
1464 /* Drop the performance state vote */
1465 dev_pm_opp_set_rate(dev, 0);
1466 clk_bulk_disable_unprepare(dpu_kms->num_clocks, dpu_kms->clocks);
1467
1468 for (i = 0; i < dpu_kms->num_paths; i++)
1469 icc_set_bw(dpu_kms->path[i], 0, 0);
1470
1471 return 0;
1472 }
1473
dpu_runtime_resume(struct device * dev)1474 static int __maybe_unused dpu_runtime_resume(struct device *dev)
1475 {
1476 int rc = -1;
1477 struct platform_device *pdev = to_platform_device(dev);
1478 struct msm_drm_private *priv = platform_get_drvdata(pdev);
1479 struct dpu_kms *dpu_kms = to_dpu_kms(priv->kms);
1480 struct drm_encoder *encoder;
1481 struct drm_device *ddev;
1482
1483 ddev = dpu_kms->dev;
1484
1485 rc = clk_bulk_prepare_enable(dpu_kms->num_clocks, dpu_kms->clocks);
1486 if (rc) {
1487 DPU_ERROR("clock enable failed rc:%d\n", rc);
1488 return rc;
1489 }
1490
1491 dpu_vbif_init_memtypes(dpu_kms);
1492
1493 drm_for_each_encoder(encoder, ddev)
1494 dpu_encoder_virt_runtime_resume(encoder);
1495
1496 return rc;
1497 }
1498
1499 static const struct dev_pm_ops dpu_pm_ops = {
1500 SET_RUNTIME_PM_OPS(dpu_runtime_suspend, dpu_runtime_resume, NULL)
1501 SET_SYSTEM_SLEEP_PM_OPS(pm_runtime_force_suspend,
1502 pm_runtime_force_resume)
1503 .prepare = msm_kms_pm_prepare,
1504 .complete = msm_kms_pm_complete,
1505 };
1506
1507 static const struct of_device_id dpu_dt_match[] = {
1508 { .compatible = "qcom,msm8917-mdp5", .data = &dpu_msm8917_cfg, },
1509 { .compatible = "qcom,msm8937-mdp5", .data = &dpu_msm8937_cfg, },
1510 { .compatible = "qcom,msm8953-mdp5", .data = &dpu_msm8953_cfg, },
1511 { .compatible = "qcom,msm8996-mdp5", .data = &dpu_msm8996_cfg, },
1512 { .compatible = "qcom,msm8998-dpu", .data = &dpu_msm8998_cfg, },
1513 { .compatible = "qcom,qcm2290-dpu", .data = &dpu_qcm2290_cfg, },
1514 { .compatible = "qcom,sa8775p-dpu", .data = &dpu_sa8775p_cfg, },
1515 { .compatible = "qcom,sdm630-mdp5", .data = &dpu_sdm630_cfg, },
1516 { .compatible = "qcom,sdm660-mdp5", .data = &dpu_sdm660_cfg, },
1517 { .compatible = "qcom,sdm670-dpu", .data = &dpu_sdm670_cfg, },
1518 { .compatible = "qcom,sdm845-dpu", .data = &dpu_sdm845_cfg, },
1519 { .compatible = "qcom,sc7180-dpu", .data = &dpu_sc7180_cfg, },
1520 { .compatible = "qcom,sc7280-dpu", .data = &dpu_sc7280_cfg, },
1521 { .compatible = "qcom,sc8180x-dpu", .data = &dpu_sc8180x_cfg, },
1522 { .compatible = "qcom,sc8280xp-dpu", .data = &dpu_sc8280xp_cfg, },
1523 { .compatible = "qcom,sm6115-dpu", .data = &dpu_sm6115_cfg, },
1524 { .compatible = "qcom,sm6125-dpu", .data = &dpu_sm6125_cfg, },
1525 { .compatible = "qcom,sm6150-dpu", .data = &dpu_sm6150_cfg, },
1526 { .compatible = "qcom,sm6350-dpu", .data = &dpu_sm6350_cfg, },
1527 { .compatible = "qcom,sm6375-dpu", .data = &dpu_sm6375_cfg, },
1528 { .compatible = "qcom,sm7150-dpu", .data = &dpu_sm7150_cfg, },
1529 { .compatible = "qcom,sm8150-dpu", .data = &dpu_sm8150_cfg, },
1530 { .compatible = "qcom,sm8250-dpu", .data = &dpu_sm8250_cfg, },
1531 { .compatible = "qcom,sm8350-dpu", .data = &dpu_sm8350_cfg, },
1532 { .compatible = "qcom,sm8450-dpu", .data = &dpu_sm8450_cfg, },
1533 { .compatible = "qcom,sm8550-dpu", .data = &dpu_sm8550_cfg, },
1534 { .compatible = "qcom,sm8650-dpu", .data = &dpu_sm8650_cfg, },
1535 { .compatible = "qcom,x1e80100-dpu", .data = &dpu_x1e80100_cfg, },
1536 {}
1537 };
1538 MODULE_DEVICE_TABLE(of, dpu_dt_match);
1539
1540 static struct platform_driver dpu_driver = {
1541 .probe = dpu_dev_probe,
1542 .remove = dpu_dev_remove,
1543 .shutdown = msm_kms_shutdown,
1544 .driver = {
1545 .name = "msm_dpu",
1546 .of_match_table = dpu_dt_match,
1547 .pm = &dpu_pm_ops,
1548 },
1549 };
1550
msm_dpu_register(void)1551 void __init msm_dpu_register(void)
1552 {
1553 platform_driver_register(&dpu_driver);
1554 }
1555
msm_dpu_unregister(void)1556 void __exit msm_dpu_unregister(void)
1557 {
1558 platform_driver_unregister(&dpu_driver);
1559 }
1560