1 // SPDX-License-Identifier: GPL-2.0-only
2 /*
3 * Copyright (c) 2022-2023 Qualcomm Innovation Center, Inc. All rights reserved.
4 * Copyright (c) 2014-2021 The Linux Foundation. All rights reserved.
5 * Copyright (C) 2013 Red Hat
6 * Author: Rob Clark <robdclark@gmail.com>
7 */
8
9 #define pr_fmt(fmt) "[drm:%s:%d] " fmt, __func__, __LINE__
10 #include <linux/sort.h>
11 #include <linux/debugfs.h>
12 #include <linux/ktime.h>
13 #include <linux/bits.h>
14
15 #include <drm/drm_atomic.h>
16 #include <drm/drm_blend.h>
17 #include <drm/drm_crtc.h>
18 #include <drm/drm_flip_work.h>
19 #include <drm/drm_framebuffer.h>
20 #include <drm/drm_mode.h>
21 #include <drm/drm_probe_helper.h>
22 #include <drm/drm_rect.h>
23 #include <drm/drm_vblank.h>
24 #include <drm/drm_self_refresh_helper.h>
25
26 #include "dpu_kms.h"
27 #include "dpu_hw_lm.h"
28 #include "dpu_hw_ctl.h"
29 #include "dpu_hw_dspp.h"
30 #include "dpu_crtc.h"
31 #include "dpu_plane.h"
32 #include "dpu_encoder.h"
33 #include "dpu_vbif.h"
34 #include "dpu_core_perf.h"
35 #include "dpu_trace.h"
36
37 /* layer mixer index on dpu_crtc */
38 #define LEFT_MIXER 0
39 #define RIGHT_MIXER 1
40
41 /* timeout in ms waiting for frame done */
42 #define DPU_CRTC_FRAME_DONE_TIMEOUT_MS 60
43
44 #define CONVERT_S3_15(val) \
45 (((((u64)val) & ~BIT_ULL(63)) >> 17) & GENMASK_ULL(17, 0))
46
_dpu_crtc_get_kms(struct drm_crtc * crtc)47 static struct dpu_kms *_dpu_crtc_get_kms(struct drm_crtc *crtc)
48 {
49 struct msm_drm_private *priv = crtc->dev->dev_private;
50
51 return to_dpu_kms(priv->kms);
52 }
53
get_encoder_from_crtc(struct drm_crtc * crtc)54 static struct drm_encoder *get_encoder_from_crtc(struct drm_crtc *crtc)
55 {
56 struct drm_device *dev = crtc->dev;
57 struct drm_encoder *encoder;
58
59 drm_for_each_encoder(encoder, dev)
60 if (encoder->crtc == crtc)
61 return encoder;
62
63 return NULL;
64 }
65
dpu_crtc_parse_crc_source(const char * src_name)66 static enum dpu_crtc_crc_source dpu_crtc_parse_crc_source(const char *src_name)
67 {
68 if (!src_name ||
69 !strcmp(src_name, "none"))
70 return DPU_CRTC_CRC_SOURCE_NONE;
71 if (!strcmp(src_name, "auto") ||
72 !strcmp(src_name, "lm"))
73 return DPU_CRTC_CRC_SOURCE_LAYER_MIXER;
74 if (!strcmp(src_name, "encoder"))
75 return DPU_CRTC_CRC_SOURCE_ENCODER;
76
77 return DPU_CRTC_CRC_SOURCE_INVALID;
78 }
79
dpu_crtc_verify_crc_source(struct drm_crtc * crtc,const char * src_name,size_t * values_cnt)80 static int dpu_crtc_verify_crc_source(struct drm_crtc *crtc,
81 const char *src_name, size_t *values_cnt)
82 {
83 enum dpu_crtc_crc_source source = dpu_crtc_parse_crc_source(src_name);
84 struct dpu_crtc_state *crtc_state = to_dpu_crtc_state(crtc->state);
85
86 if (source < 0) {
87 DRM_DEBUG_DRIVER("Invalid source %s for CRTC%d\n", src_name, crtc->index);
88 return -EINVAL;
89 }
90
91 if (source == DPU_CRTC_CRC_SOURCE_LAYER_MIXER) {
92 *values_cnt = crtc_state->num_mixers;
93 } else if (source == DPU_CRTC_CRC_SOURCE_ENCODER) {
94 struct drm_encoder *drm_enc;
95
96 *values_cnt = 0;
97
98 drm_for_each_encoder_mask(drm_enc, crtc->dev, crtc->state->encoder_mask)
99 *values_cnt += dpu_encoder_get_crc_values_cnt(drm_enc);
100 }
101
102 return 0;
103 }
104
dpu_crtc_setup_lm_misr(struct dpu_crtc_state * crtc_state)105 static void dpu_crtc_setup_lm_misr(struct dpu_crtc_state *crtc_state)
106 {
107 struct dpu_crtc_mixer *m;
108 int i;
109
110 for (i = 0; i < crtc_state->num_mixers; ++i) {
111 m = &crtc_state->mixers[i];
112
113 if (!m->hw_lm || !m->hw_lm->ops.setup_misr)
114 continue;
115
116 /* Calculate MISR over 1 frame */
117 m->hw_lm->ops.setup_misr(m->hw_lm);
118 }
119 }
120
dpu_crtc_setup_encoder_misr(struct drm_crtc * crtc)121 static void dpu_crtc_setup_encoder_misr(struct drm_crtc *crtc)
122 {
123 struct drm_encoder *drm_enc;
124
125 drm_for_each_encoder_mask(drm_enc, crtc->dev, crtc->state->encoder_mask)
126 dpu_encoder_setup_misr(drm_enc);
127 }
128
dpu_crtc_set_crc_source(struct drm_crtc * crtc,const char * src_name)129 static int dpu_crtc_set_crc_source(struct drm_crtc *crtc, const char *src_name)
130 {
131 enum dpu_crtc_crc_source source = dpu_crtc_parse_crc_source(src_name);
132 enum dpu_crtc_crc_source current_source;
133 struct dpu_crtc_state *crtc_state;
134 struct drm_device *drm_dev = crtc->dev;
135
136 bool was_enabled;
137 bool enable = false;
138 int ret = 0;
139
140 if (source < 0) {
141 DRM_DEBUG_DRIVER("Invalid CRC source %s for CRTC%d\n", src_name, crtc->index);
142 return -EINVAL;
143 }
144
145 ret = drm_modeset_lock(&crtc->mutex, NULL);
146
147 if (ret)
148 return ret;
149
150 enable = (source != DPU_CRTC_CRC_SOURCE_NONE);
151 crtc_state = to_dpu_crtc_state(crtc->state);
152
153 spin_lock_irq(&drm_dev->event_lock);
154 current_source = crtc_state->crc_source;
155 spin_unlock_irq(&drm_dev->event_lock);
156
157 was_enabled = (current_source != DPU_CRTC_CRC_SOURCE_NONE);
158
159 if (!was_enabled && enable) {
160 ret = drm_crtc_vblank_get(crtc);
161
162 if (ret)
163 goto cleanup;
164
165 } else if (was_enabled && !enable) {
166 drm_crtc_vblank_put(crtc);
167 }
168
169 spin_lock_irq(&drm_dev->event_lock);
170 crtc_state->crc_source = source;
171 spin_unlock_irq(&drm_dev->event_lock);
172
173 crtc_state->crc_frame_skip_count = 0;
174
175 if (source == DPU_CRTC_CRC_SOURCE_LAYER_MIXER)
176 dpu_crtc_setup_lm_misr(crtc_state);
177 else if (source == DPU_CRTC_CRC_SOURCE_ENCODER)
178 dpu_crtc_setup_encoder_misr(crtc);
179 else
180 ret = -EINVAL;
181
182 cleanup:
183 drm_modeset_unlock(&crtc->mutex);
184
185 return ret;
186 }
187
dpu_crtc_get_vblank_counter(struct drm_crtc * crtc)188 static u32 dpu_crtc_get_vblank_counter(struct drm_crtc *crtc)
189 {
190 struct drm_encoder *encoder = get_encoder_from_crtc(crtc);
191 if (!encoder) {
192 DRM_ERROR("no encoder found for crtc %d\n", crtc->index);
193 return 0;
194 }
195
196 return dpu_encoder_get_vsync_count(encoder);
197 }
198
dpu_crtc_get_lm_crc(struct drm_crtc * crtc,struct dpu_crtc_state * crtc_state)199 static int dpu_crtc_get_lm_crc(struct drm_crtc *crtc,
200 struct dpu_crtc_state *crtc_state)
201 {
202 struct dpu_crtc_mixer *m;
203 u32 crcs[CRTC_DUAL_MIXERS];
204
205 int rc = 0;
206 int i;
207
208 BUILD_BUG_ON(ARRAY_SIZE(crcs) != ARRAY_SIZE(crtc_state->mixers));
209
210 for (i = 0; i < crtc_state->num_mixers; ++i) {
211
212 m = &crtc_state->mixers[i];
213
214 if (!m->hw_lm || !m->hw_lm->ops.collect_misr)
215 continue;
216
217 rc = m->hw_lm->ops.collect_misr(m->hw_lm, &crcs[i]);
218
219 if (rc) {
220 if (rc != -ENODATA)
221 DRM_DEBUG_DRIVER("MISR read failed\n");
222 return rc;
223 }
224 }
225
226 return drm_crtc_add_crc_entry(crtc, true,
227 drm_crtc_accurate_vblank_count(crtc), crcs);
228 }
229
dpu_crtc_get_encoder_crc(struct drm_crtc * crtc)230 static int dpu_crtc_get_encoder_crc(struct drm_crtc *crtc)
231 {
232 struct drm_encoder *drm_enc;
233 int rc, pos = 0;
234 u32 crcs[INTF_MAX];
235
236 drm_for_each_encoder_mask(drm_enc, crtc->dev, crtc->state->encoder_mask) {
237 rc = dpu_encoder_get_crc(drm_enc, crcs, pos);
238 if (rc < 0) {
239 if (rc != -ENODATA)
240 DRM_DEBUG_DRIVER("MISR read failed\n");
241
242 return rc;
243 }
244
245 pos += rc;
246 }
247
248 return drm_crtc_add_crc_entry(crtc, true,
249 drm_crtc_accurate_vblank_count(crtc), crcs);
250 }
251
dpu_crtc_get_crc(struct drm_crtc * crtc)252 static int dpu_crtc_get_crc(struct drm_crtc *crtc)
253 {
254 struct dpu_crtc_state *crtc_state = to_dpu_crtc_state(crtc->state);
255
256 /* Skip first 2 frames in case of "uncooked" CRCs */
257 if (crtc_state->crc_frame_skip_count < 2) {
258 crtc_state->crc_frame_skip_count++;
259 return 0;
260 }
261
262 if (crtc_state->crc_source == DPU_CRTC_CRC_SOURCE_LAYER_MIXER)
263 return dpu_crtc_get_lm_crc(crtc, crtc_state);
264 else if (crtc_state->crc_source == DPU_CRTC_CRC_SOURCE_ENCODER)
265 return dpu_crtc_get_encoder_crc(crtc);
266
267 return -EINVAL;
268 }
269
dpu_crtc_get_scanout_position(struct drm_crtc * crtc,bool in_vblank_irq,int * vpos,int * hpos,ktime_t * stime,ktime_t * etime,const struct drm_display_mode * mode)270 static bool dpu_crtc_get_scanout_position(struct drm_crtc *crtc,
271 bool in_vblank_irq,
272 int *vpos, int *hpos,
273 ktime_t *stime, ktime_t *etime,
274 const struct drm_display_mode *mode)
275 {
276 unsigned int pipe = crtc->index;
277 struct drm_encoder *encoder;
278 int line, vsw, vbp, vactive_start, vactive_end, vfp_end;
279
280 encoder = get_encoder_from_crtc(crtc);
281 if (!encoder) {
282 DRM_ERROR("no encoder found for crtc %d\n", pipe);
283 return false;
284 }
285
286 vsw = mode->crtc_vsync_end - mode->crtc_vsync_start;
287 vbp = mode->crtc_vtotal - mode->crtc_vsync_end;
288
289 /*
290 * the line counter is 1 at the start of the VSYNC pulse and VTOTAL at
291 * the end of VFP. Translate the porch values relative to the line
292 * counter positions.
293 */
294
295 vactive_start = vsw + vbp + 1;
296 vactive_end = vactive_start + mode->crtc_vdisplay;
297
298 /* last scan line before VSYNC */
299 vfp_end = mode->crtc_vtotal;
300
301 if (stime)
302 *stime = ktime_get();
303
304 line = dpu_encoder_get_linecount(encoder);
305
306 if (line < vactive_start)
307 line -= vactive_start;
308 else if (line > vactive_end)
309 line = line - vfp_end - vactive_start;
310 else
311 line -= vactive_start;
312
313 *vpos = line;
314 *hpos = 0;
315
316 if (etime)
317 *etime = ktime_get();
318
319 return true;
320 }
321
_dpu_crtc_setup_blend_cfg(struct dpu_crtc_mixer * mixer,struct dpu_plane_state * pstate,const struct msm_format * format,const struct dpu_mdss_version * mdss_ver)322 static void _dpu_crtc_setup_blend_cfg(struct dpu_crtc_mixer *mixer,
323 struct dpu_plane_state *pstate,
324 const struct msm_format *format,
325 const struct dpu_mdss_version *mdss_ver)
326 {
327 struct dpu_hw_mixer *lm = mixer->hw_lm;
328 u32 blend_op;
329 u32 fg_alpha, bg_alpha, max_alpha;
330
331 if (mdss_ver->core_major_ver < 12) {
332 max_alpha = 0xff;
333 fg_alpha = pstate->base.alpha >> 8;
334 } else {
335 max_alpha = 0x3ff;
336 fg_alpha = pstate->base.alpha >> 6;
337 }
338 bg_alpha = max_alpha - fg_alpha;
339
340 /* default to opaque blending */
341 if (pstate->base.pixel_blend_mode == DRM_MODE_BLEND_PIXEL_NONE ||
342 !format->alpha_enable) {
343 blend_op = DPU_BLEND_FG_ALPHA_FG_CONST |
344 DPU_BLEND_BG_ALPHA_BG_CONST;
345 } else if (pstate->base.pixel_blend_mode == DRM_MODE_BLEND_PREMULTI) {
346 blend_op = DPU_BLEND_FG_ALPHA_FG_CONST |
347 DPU_BLEND_BG_ALPHA_FG_PIXEL;
348 if (fg_alpha != max_alpha) {
349 bg_alpha = fg_alpha;
350 blend_op |= DPU_BLEND_BG_MOD_ALPHA |
351 DPU_BLEND_BG_INV_MOD_ALPHA;
352 } else {
353 blend_op |= DPU_BLEND_BG_INV_ALPHA;
354 }
355 } else {
356 /* coverage blending */
357 blend_op = DPU_BLEND_FG_ALPHA_FG_PIXEL |
358 DPU_BLEND_BG_ALPHA_FG_PIXEL;
359 if (fg_alpha != max_alpha) {
360 bg_alpha = fg_alpha;
361 blend_op |= DPU_BLEND_FG_MOD_ALPHA |
362 DPU_BLEND_FG_INV_MOD_ALPHA |
363 DPU_BLEND_BG_MOD_ALPHA |
364 DPU_BLEND_BG_INV_MOD_ALPHA;
365 } else {
366 blend_op |= DPU_BLEND_BG_INV_ALPHA;
367 }
368 }
369
370 lm->ops.setup_blend_config(lm, pstate->stage,
371 fg_alpha, bg_alpha, blend_op);
372
373 DRM_DEBUG_ATOMIC("format:%p4cc, alpha_en:%u blend_op:0x%x\n",
374 &format->pixel_format, format->alpha_enable, blend_op);
375 }
376
_dpu_crtc_program_lm_output_roi(struct drm_crtc * crtc)377 static void _dpu_crtc_program_lm_output_roi(struct drm_crtc *crtc)
378 {
379 struct dpu_crtc_state *crtc_state;
380 int lm_idx, lm_horiz_position;
381
382 crtc_state = to_dpu_crtc_state(crtc->state);
383
384 lm_horiz_position = 0;
385 for (lm_idx = 0; lm_idx < crtc_state->num_mixers; lm_idx++) {
386 const struct drm_rect *lm_roi = &crtc_state->lm_bounds[lm_idx];
387 struct dpu_hw_mixer *hw_lm = crtc_state->mixers[lm_idx].hw_lm;
388 struct dpu_hw_mixer_cfg cfg;
389
390 if (!lm_roi || !drm_rect_visible(lm_roi))
391 continue;
392
393 cfg.out_width = drm_rect_width(lm_roi);
394 cfg.out_height = drm_rect_height(lm_roi);
395 cfg.right_mixer = lm_horiz_position++;
396 cfg.flags = 0;
397 hw_lm->ops.setup_mixer_out(hw_lm, &cfg);
398 }
399 }
400
_dpu_crtc_blend_setup_pipe(struct drm_crtc * crtc,struct drm_plane * plane,struct dpu_crtc_mixer * mixer,u32 num_mixers,enum dpu_stage stage,const struct msm_format * format,uint64_t modifier,struct dpu_sw_pipe * pipe,unsigned int stage_idx,struct dpu_hw_stage_cfg * stage_cfg)401 static void _dpu_crtc_blend_setup_pipe(struct drm_crtc *crtc,
402 struct drm_plane *plane,
403 struct dpu_crtc_mixer *mixer,
404 u32 num_mixers,
405 enum dpu_stage stage,
406 const struct msm_format *format,
407 uint64_t modifier,
408 struct dpu_sw_pipe *pipe,
409 unsigned int stage_idx,
410 struct dpu_hw_stage_cfg *stage_cfg
411 )
412 {
413 u32 lm_idx;
414 enum dpu_sspp sspp_idx;
415 struct drm_plane_state *state;
416
417 sspp_idx = pipe->sspp->idx;
418
419 state = plane->state;
420
421 trace_dpu_crtc_setup_mixer(DRMID(crtc), DRMID(plane),
422 state, to_dpu_plane_state(state), stage_idx,
423 format->pixel_format,
424 modifier);
425
426 DRM_DEBUG_ATOMIC("crtc %d stage:%d - plane %d sspp %d fb %d multirect_idx %d\n",
427 crtc->base.id,
428 stage,
429 plane->base.id,
430 sspp_idx - SSPP_NONE,
431 state->fb ? state->fb->base.id : -1,
432 pipe->multirect_index);
433
434 stage_cfg->stage[stage][stage_idx] = sspp_idx;
435 stage_cfg->multirect_index[stage][stage_idx] = pipe->multirect_index;
436
437 /* blend config update */
438 for (lm_idx = 0; lm_idx < num_mixers; lm_idx++)
439 mixer[lm_idx].lm_ctl->ops.update_pending_flush_sspp(mixer[lm_idx].lm_ctl, sspp_idx);
440 }
441
_dpu_crtc_blend_setup_mixer(struct drm_crtc * crtc,struct dpu_crtc * dpu_crtc,struct dpu_crtc_mixer * mixer,struct dpu_hw_stage_cfg * stage_cfg)442 static void _dpu_crtc_blend_setup_mixer(struct drm_crtc *crtc,
443 struct dpu_crtc *dpu_crtc, struct dpu_crtc_mixer *mixer,
444 struct dpu_hw_stage_cfg *stage_cfg)
445 {
446 struct drm_plane *plane;
447 struct drm_framebuffer *fb;
448 struct drm_plane_state *state;
449 struct dpu_crtc_state *cstate = to_dpu_crtc_state(crtc->state);
450 struct dpu_plane_state *pstate = NULL;
451 const struct msm_format *format;
452 struct dpu_hw_ctl *ctl = mixer->lm_ctl;
453 u32 lm_idx;
454 bool bg_alpha_enable = false;
455 DECLARE_BITMAP(active_fetch, SSPP_MAX);
456 DECLARE_BITMAP(active_pipes, SSPP_MAX);
457
458 memset(active_fetch, 0, sizeof(active_fetch));
459 memset(active_pipes, 0, sizeof(active_pipes));
460 drm_atomic_crtc_for_each_plane(plane, crtc) {
461 state = plane->state;
462 if (!state)
463 continue;
464
465 if (!state->visible)
466 continue;
467
468 pstate = to_dpu_plane_state(state);
469 fb = state->fb;
470
471 format = msm_framebuffer_format(pstate->base.fb);
472
473 if (pstate->stage == DPU_STAGE_BASE && format->alpha_enable)
474 bg_alpha_enable = true;
475
476 set_bit(pstate->pipe.sspp->idx, active_fetch);
477 set_bit(pstate->pipe.sspp->idx, active_pipes);
478 _dpu_crtc_blend_setup_pipe(crtc, plane,
479 mixer, cstate->num_mixers,
480 pstate->stage,
481 format, fb ? fb->modifier : 0,
482 &pstate->pipe, 0, stage_cfg);
483
484 if (pstate->r_pipe.sspp) {
485 set_bit(pstate->r_pipe.sspp->idx, active_fetch);
486 set_bit(pstate->r_pipe.sspp->idx, active_pipes);
487 _dpu_crtc_blend_setup_pipe(crtc, plane,
488 mixer, cstate->num_mixers,
489 pstate->stage,
490 format, fb ? fb->modifier : 0,
491 &pstate->r_pipe, 1, stage_cfg);
492 }
493
494 /* blend config update */
495 for (lm_idx = 0; lm_idx < cstate->num_mixers; lm_idx++) {
496 _dpu_crtc_setup_blend_cfg(mixer + lm_idx, pstate, format,
497 ctl->mdss_ver);
498
499 if (bg_alpha_enable && !format->alpha_enable)
500 mixer[lm_idx].mixer_op_mode = 0;
501 else
502 mixer[lm_idx].mixer_op_mode |=
503 1 << pstate->stage;
504 }
505 }
506
507 if (ctl->ops.set_active_fetch_pipes)
508 ctl->ops.set_active_fetch_pipes(ctl, active_fetch);
509
510 if (ctl->ops.set_active_pipes)
511 ctl->ops.set_active_pipes(ctl, active_pipes);
512
513 _dpu_crtc_program_lm_output_roi(crtc);
514 }
515
516 /**
517 * _dpu_crtc_blend_setup - configure crtc mixers
518 * @crtc: Pointer to drm crtc structure
519 */
_dpu_crtc_blend_setup(struct drm_crtc * crtc)520 static void _dpu_crtc_blend_setup(struct drm_crtc *crtc)
521 {
522 struct dpu_crtc *dpu_crtc = to_dpu_crtc(crtc);
523 struct dpu_crtc_state *cstate = to_dpu_crtc_state(crtc->state);
524 struct dpu_crtc_mixer *mixer = cstate->mixers;
525 struct dpu_hw_ctl *ctl;
526 struct dpu_hw_mixer *lm;
527 struct dpu_hw_stage_cfg stage_cfg;
528 DECLARE_BITMAP(active_lms, LM_MAX);
529 int i;
530
531 DRM_DEBUG_ATOMIC("%s\n", dpu_crtc->name);
532
533 for (i = 0; i < cstate->num_mixers; i++) {
534 mixer[i].mixer_op_mode = 0;
535 if (mixer[i].lm_ctl->ops.clear_all_blendstages)
536 mixer[i].lm_ctl->ops.clear_all_blendstages(
537 mixer[i].lm_ctl);
538 if (mixer[i].lm_ctl->ops.set_active_fetch_pipes)
539 mixer[i].lm_ctl->ops.set_active_fetch_pipes(mixer[i].lm_ctl, NULL);
540 if (mixer[i].lm_ctl->ops.set_active_pipes)
541 mixer[i].lm_ctl->ops.set_active_pipes(mixer[i].lm_ctl, NULL);
542
543 if (mixer[i].hw_lm->ops.clear_all_blendstages)
544 mixer[i].hw_lm->ops.clear_all_blendstages(mixer[i].hw_lm);
545 }
546
547 /* initialize stage cfg */
548 memset(&stage_cfg, 0, sizeof(struct dpu_hw_stage_cfg));
549 memset(active_lms, 0, sizeof(active_lms));
550
551 _dpu_crtc_blend_setup_mixer(crtc, dpu_crtc, mixer, &stage_cfg);
552
553 for (i = 0; i < cstate->num_mixers; i++) {
554 ctl = mixer[i].lm_ctl;
555 lm = mixer[i].hw_lm;
556
557 lm->ops.setup_alpha_out(lm, mixer[i].mixer_op_mode);
558
559 /* stage config flush mask */
560 ctl->ops.update_pending_flush_mixer(ctl,
561 mixer[i].hw_lm->idx);
562
563 set_bit(lm->idx, active_lms);
564 if (ctl->ops.set_active_lms)
565 ctl->ops.set_active_lms(ctl, active_lms);
566
567 DRM_DEBUG_ATOMIC("lm %d, op_mode 0x%X, ctl %d\n",
568 mixer[i].hw_lm->idx - LM_0,
569 mixer[i].mixer_op_mode,
570 ctl->idx - CTL_0);
571
572 if (ctl->ops.setup_blendstage)
573 ctl->ops.setup_blendstage(ctl, mixer[i].hw_lm->idx,
574 &stage_cfg);
575
576 if (lm->ops.setup_blendstage)
577 lm->ops.setup_blendstage(lm, mixer[i].hw_lm->idx,
578 &stage_cfg);
579 }
580 }
581
582 /**
583 * _dpu_crtc_complete_flip - signal pending page_flip events
584 * Any pending vblank events are added to the vblank_event_list
585 * so that the next vblank interrupt shall signal them.
586 * However PAGE_FLIP events are not handled through the vblank_event_list.
587 * This API signals any pending PAGE_FLIP events requested through
588 * DRM_IOCTL_MODE_PAGE_FLIP and are cached in the dpu_crtc->event.
589 * @crtc: Pointer to drm crtc structure
590 */
_dpu_crtc_complete_flip(struct drm_crtc * crtc)591 static void _dpu_crtc_complete_flip(struct drm_crtc *crtc)
592 {
593 struct dpu_crtc *dpu_crtc = to_dpu_crtc(crtc);
594 struct drm_device *dev = crtc->dev;
595 unsigned long flags;
596
597 spin_lock_irqsave(&dev->event_lock, flags);
598 if (dpu_crtc->event) {
599 DRM_DEBUG_VBL("%s: send event: %pK\n", dpu_crtc->name,
600 dpu_crtc->event);
601 trace_dpu_crtc_complete_flip(DRMID(crtc));
602 drm_crtc_send_vblank_event(crtc, dpu_crtc->event);
603 dpu_crtc->event = NULL;
604 }
605 spin_unlock_irqrestore(&dev->event_lock, flags);
606 }
607
608 /**
609 * dpu_crtc_get_intf_mode - get interface mode of the given crtc
610 * @crtc: Pointert to crtc
611 */
dpu_crtc_get_intf_mode(struct drm_crtc * crtc)612 enum dpu_intf_mode dpu_crtc_get_intf_mode(struct drm_crtc *crtc)
613 {
614 struct drm_encoder *encoder;
615
616 /*
617 * TODO: This function is called from dpu debugfs and as part of atomic
618 * check. When called from debugfs, the crtc->mutex must be held to
619 * read crtc->state. However reading crtc->state from atomic check isn't
620 * allowed (unless you have a good reason, a big comment, and a deep
621 * understanding of how the atomic/modeset locks work (<- and this is
622 * probably not possible)). So we'll keep the WARN_ON here for now, but
623 * really we need to figure out a better way to track our operating mode
624 */
625 WARN_ON(!drm_modeset_is_locked(&crtc->mutex));
626
627 /* TODO: Returns the first INTF_MODE, could there be multiple values? */
628 drm_for_each_encoder_mask(encoder, crtc->dev, crtc->state->encoder_mask)
629 return dpu_encoder_get_intf_mode(encoder);
630
631 return INTF_MODE_NONE;
632 }
633
634 /**
635 * dpu_crtc_vblank_callback - called on vblank irq, issues completion events
636 * @crtc: Pointer to drm crtc object
637 */
dpu_crtc_vblank_callback(struct drm_crtc * crtc)638 void dpu_crtc_vblank_callback(struct drm_crtc *crtc)
639 {
640 struct dpu_crtc *dpu_crtc = to_dpu_crtc(crtc);
641
642 /* keep statistics on vblank callback - with auto reset via debugfs */
643 if (ktime_compare(dpu_crtc->vblank_cb_time, ktime_set(0, 0)) == 0)
644 dpu_crtc->vblank_cb_time = ktime_get();
645 else
646 dpu_crtc->vblank_cb_count++;
647
648 dpu_crtc_get_crc(crtc);
649
650 drm_crtc_handle_vblank(crtc);
651 trace_dpu_crtc_vblank_cb(DRMID(crtc));
652 }
653
dpu_crtc_frame_event_work(struct kthread_work * work)654 static void dpu_crtc_frame_event_work(struct kthread_work *work)
655 {
656 struct dpu_crtc_frame_event *fevent = container_of(work,
657 struct dpu_crtc_frame_event, work);
658 struct drm_crtc *crtc = fevent->crtc;
659 struct dpu_crtc *dpu_crtc = to_dpu_crtc(crtc);
660 unsigned long flags;
661 bool frame_done = false;
662
663 DPU_ATRACE_BEGIN("crtc_frame_event");
664
665 DRM_DEBUG_ATOMIC("crtc%d event:%u ts:%lld\n", crtc->base.id, fevent->event,
666 ktime_to_ns(fevent->ts));
667
668 if (fevent->event & (DPU_ENCODER_FRAME_EVENT_DONE
669 | DPU_ENCODER_FRAME_EVENT_ERROR
670 | DPU_ENCODER_FRAME_EVENT_PANEL_DEAD)) {
671
672 if (atomic_read(&dpu_crtc->frame_pending) < 1) {
673 /* ignore vblank when not pending */
674 } else if (atomic_dec_return(&dpu_crtc->frame_pending) == 0) {
675 /* release bandwidth and other resources */
676 trace_dpu_crtc_frame_event_done(DRMID(crtc),
677 fevent->event);
678 dpu_core_perf_crtc_release_bw(crtc);
679 } else {
680 trace_dpu_crtc_frame_event_more_pending(DRMID(crtc),
681 fevent->event);
682 }
683
684 if (fevent->event & (DPU_ENCODER_FRAME_EVENT_DONE
685 | DPU_ENCODER_FRAME_EVENT_ERROR))
686 frame_done = true;
687 }
688
689 if (fevent->event & DPU_ENCODER_FRAME_EVENT_PANEL_DEAD)
690 DPU_ERROR("crtc%d ts:%lld received panel dead event\n",
691 crtc->base.id, ktime_to_ns(fevent->ts));
692
693 if (frame_done)
694 complete_all(&dpu_crtc->frame_done_comp);
695
696 spin_lock_irqsave(&dpu_crtc->spin_lock, flags);
697 list_add_tail(&fevent->list, &dpu_crtc->frame_event_list);
698 spin_unlock_irqrestore(&dpu_crtc->spin_lock, flags);
699 DPU_ATRACE_END("crtc_frame_event");
700 }
701
702 /**
703 * dpu_crtc_frame_event_cb - crtc frame event callback API
704 * @crtc: Pointer to crtc
705 * @event: Event to process
706 *
707 * Encoder may call this for different events from different context - IRQ,
708 * user thread, commit_thread, etc. Each event should be carefully reviewed and
709 * should be processed in proper task context to avoid schedulin delay or
710 * properly manage the irq context's bottom half processing.
711 */
dpu_crtc_frame_event_cb(struct drm_crtc * crtc,u32 event)712 void dpu_crtc_frame_event_cb(struct drm_crtc *crtc, u32 event)
713 {
714 struct dpu_crtc *dpu_crtc;
715 struct msm_drm_private *priv;
716 struct dpu_crtc_frame_event *fevent;
717 unsigned long flags;
718 u32 crtc_id;
719
720 /* Nothing to do on idle event */
721 if (event & DPU_ENCODER_FRAME_EVENT_IDLE)
722 return;
723
724 dpu_crtc = to_dpu_crtc(crtc);
725 priv = crtc->dev->dev_private;
726 crtc_id = drm_crtc_index(crtc);
727
728 trace_dpu_crtc_frame_event_cb(DRMID(crtc), event);
729
730 spin_lock_irqsave(&dpu_crtc->spin_lock, flags);
731 fevent = list_first_entry_or_null(&dpu_crtc->frame_event_list,
732 struct dpu_crtc_frame_event, list);
733 if (fevent)
734 list_del_init(&fevent->list);
735 spin_unlock_irqrestore(&dpu_crtc->spin_lock, flags);
736
737 if (!fevent) {
738 DRM_ERROR_RATELIMITED("crtc%d event %d overflow\n", crtc->base.id, event);
739 return;
740 }
741
742 fevent->event = event;
743 fevent->crtc = crtc;
744 fevent->ts = ktime_get();
745 kthread_queue_work(priv->kms->event_thread[crtc_id].worker, &fevent->work);
746 }
747
748 /**
749 * dpu_crtc_complete_commit - callback signalling completion of current commit
750 * @crtc: Pointer to drm crtc object
751 */
dpu_crtc_complete_commit(struct drm_crtc * crtc)752 void dpu_crtc_complete_commit(struct drm_crtc *crtc)
753 {
754 trace_dpu_crtc_complete_commit(DRMID(crtc));
755 dpu_core_perf_crtc_update(crtc, 0);
756 _dpu_crtc_complete_flip(crtc);
757 }
758
_dpu_crtc_check_and_setup_lm_bounds(struct drm_crtc * crtc,struct drm_crtc_state * state)759 static int _dpu_crtc_check_and_setup_lm_bounds(struct drm_crtc *crtc,
760 struct drm_crtc_state *state)
761 {
762 struct dpu_crtc_state *cstate = to_dpu_crtc_state(state);
763 struct drm_display_mode *adj_mode = &state->adjusted_mode;
764 u32 crtc_split_width = adj_mode->hdisplay / cstate->num_mixers;
765 struct dpu_kms *dpu_kms = _dpu_crtc_get_kms(crtc);
766 int i;
767
768 /* if we cannot merge 2 LMs (no 3d mux) better to fail earlier
769 * before even checking the width after the split
770 */
771 if (!dpu_kms->catalog->caps->has_3d_merge &&
772 adj_mode->hdisplay > dpu_kms->catalog->caps->max_mixer_width)
773 return -E2BIG;
774
775 for (i = 0; i < cstate->num_mixers; i++) {
776 struct drm_rect *r = &cstate->lm_bounds[i];
777 r->x1 = crtc_split_width * i;
778 r->y1 = 0;
779 r->x2 = r->x1 + crtc_split_width;
780 r->y2 = adj_mode->vdisplay;
781
782 trace_dpu_crtc_setup_lm_bounds(DRMID(crtc), i, r);
783
784 if (drm_rect_width(r) > dpu_kms->catalog->caps->max_mixer_width)
785 return -E2BIG;
786 }
787
788 return 0;
789 }
790
_dpu_crtc_get_pcc_coeff(struct drm_crtc_state * state,struct dpu_hw_pcc_cfg * cfg)791 static void _dpu_crtc_get_pcc_coeff(struct drm_crtc_state *state,
792 struct dpu_hw_pcc_cfg *cfg)
793 {
794 struct drm_color_ctm *ctm;
795
796 memset(cfg, 0, sizeof(struct dpu_hw_pcc_cfg));
797
798 ctm = (struct drm_color_ctm *)state->ctm->data;
799
800 if (!ctm)
801 return;
802
803 cfg->r.r = CONVERT_S3_15(ctm->matrix[0]);
804 cfg->g.r = CONVERT_S3_15(ctm->matrix[1]);
805 cfg->b.r = CONVERT_S3_15(ctm->matrix[2]);
806
807 cfg->r.g = CONVERT_S3_15(ctm->matrix[3]);
808 cfg->g.g = CONVERT_S3_15(ctm->matrix[4]);
809 cfg->b.g = CONVERT_S3_15(ctm->matrix[5]);
810
811 cfg->r.b = CONVERT_S3_15(ctm->matrix[6]);
812 cfg->g.b = CONVERT_S3_15(ctm->matrix[7]);
813 cfg->b.b = CONVERT_S3_15(ctm->matrix[8]);
814 }
815
_dpu_crtc_setup_cp_blocks(struct drm_crtc * crtc)816 static void _dpu_crtc_setup_cp_blocks(struct drm_crtc *crtc)
817 {
818 struct drm_crtc_state *state = crtc->state;
819 struct dpu_crtc_state *cstate = to_dpu_crtc_state(crtc->state);
820 struct dpu_crtc_mixer *mixer = cstate->mixers;
821 struct dpu_hw_pcc_cfg cfg;
822 struct dpu_hw_ctl *ctl;
823 struct dpu_hw_dspp *dspp;
824 int i;
825
826
827 if (!state->color_mgmt_changed && !drm_atomic_crtc_needs_modeset(state))
828 return;
829
830 for (i = 0; i < cstate->num_mixers; i++) {
831 ctl = mixer[i].lm_ctl;
832 dspp = mixer[i].hw_dspp;
833
834 if (!dspp || !dspp->ops.setup_pcc)
835 continue;
836
837 if (!state->ctm) {
838 dspp->ops.setup_pcc(dspp, NULL);
839 } else {
840 _dpu_crtc_get_pcc_coeff(state, &cfg);
841 dspp->ops.setup_pcc(dspp, &cfg);
842 }
843
844 /* stage config flush mask */
845 ctl->ops.update_pending_flush_dspp(ctl,
846 mixer[i].hw_dspp->idx, DPU_DSPP_PCC);
847 }
848 }
849
dpu_crtc_atomic_begin(struct drm_crtc * crtc,struct drm_atomic_state * state)850 static void dpu_crtc_atomic_begin(struct drm_crtc *crtc,
851 struct drm_atomic_state *state)
852 {
853 struct dpu_crtc_state *cstate = to_dpu_crtc_state(crtc->state);
854 struct drm_encoder *encoder;
855
856 if (!crtc->state->enable) {
857 DRM_DEBUG_ATOMIC("crtc%d -> enable %d, skip atomic_begin\n",
858 crtc->base.id, crtc->state->enable);
859 return;
860 }
861
862 DRM_DEBUG_ATOMIC("crtc%d\n", crtc->base.id);
863
864 _dpu_crtc_check_and_setup_lm_bounds(crtc, crtc->state);
865
866 /* encoder will trigger pending mask now */
867 drm_for_each_encoder_mask(encoder, crtc->dev, crtc->state->encoder_mask)
868 dpu_encoder_trigger_kickoff_pending(encoder);
869
870 /*
871 * If no mixers have been allocated in dpu_crtc_atomic_check(),
872 * it means we are trying to flush a CRTC whose state is disabled:
873 * nothing else needs to be done.
874 */
875 if (unlikely(!cstate->num_mixers))
876 return;
877
878 _dpu_crtc_blend_setup(crtc);
879
880 _dpu_crtc_setup_cp_blocks(crtc);
881
882 /*
883 * PP_DONE irq is only used by command mode for now.
884 * It is better to request pending before FLUSH and START trigger
885 * to make sure no pp_done irq missed.
886 * This is safe because no pp_done will happen before SW trigger
887 * in command mode.
888 */
889 }
890
dpu_crtc_atomic_flush(struct drm_crtc * crtc,struct drm_atomic_state * state)891 static void dpu_crtc_atomic_flush(struct drm_crtc *crtc,
892 struct drm_atomic_state *state)
893 {
894 struct dpu_crtc *dpu_crtc;
895 struct drm_device *dev;
896 struct drm_plane *plane;
897 struct msm_drm_private *priv;
898 unsigned long flags;
899 struct dpu_crtc_state *cstate;
900
901 if (!crtc->state->enable) {
902 DRM_DEBUG_ATOMIC("crtc%d -> enable %d, skip atomic_flush\n",
903 crtc->base.id, crtc->state->enable);
904 return;
905 }
906
907 DRM_DEBUG_ATOMIC("crtc%d\n", crtc->base.id);
908
909 dpu_crtc = to_dpu_crtc(crtc);
910 cstate = to_dpu_crtc_state(crtc->state);
911 dev = crtc->dev;
912 priv = dev->dev_private;
913
914 if (crtc->index >= ARRAY_SIZE(priv->kms->event_thread)) {
915 DPU_ERROR("invalid crtc index[%d]\n", crtc->index);
916 return;
917 }
918
919 WARN_ON(dpu_crtc->event);
920 spin_lock_irqsave(&dev->event_lock, flags);
921 dpu_crtc->event = crtc->state->event;
922 crtc->state->event = NULL;
923 spin_unlock_irqrestore(&dev->event_lock, flags);
924
925 /*
926 * If no mixers has been allocated in dpu_crtc_atomic_check(),
927 * it means we are trying to flush a CRTC whose state is disabled:
928 * nothing else needs to be done.
929 */
930 if (unlikely(!cstate->num_mixers))
931 return;
932
933 /* update performance setting before crtc kickoff */
934 dpu_core_perf_crtc_update(crtc, 1);
935
936 /*
937 * Final plane updates: Give each plane a chance to complete all
938 * required writes/flushing before crtc's "flush
939 * everything" call below.
940 */
941 drm_atomic_crtc_for_each_plane(plane, crtc) {
942 if (dpu_crtc->smmu_state.transition_error)
943 dpu_plane_set_error(plane, true);
944 dpu_plane_flush(plane);
945 }
946
947 /* Kickoff will be scheduled by outer layer */
948 }
949
950 /**
951 * dpu_crtc_destroy_state - state destroy hook
952 * @crtc: drm CRTC
953 * @state: CRTC state object to release
954 */
dpu_crtc_destroy_state(struct drm_crtc * crtc,struct drm_crtc_state * state)955 static void dpu_crtc_destroy_state(struct drm_crtc *crtc,
956 struct drm_crtc_state *state)
957 {
958 struct dpu_crtc_state *cstate = to_dpu_crtc_state(state);
959
960 DRM_DEBUG_ATOMIC("crtc%d\n", crtc->base.id);
961
962 __drm_atomic_helper_crtc_destroy_state(state);
963
964 kfree(cstate);
965 }
966
_dpu_crtc_wait_for_frame_done(struct drm_crtc * crtc)967 static int _dpu_crtc_wait_for_frame_done(struct drm_crtc *crtc)
968 {
969 struct dpu_crtc *dpu_crtc = to_dpu_crtc(crtc);
970 int ret, rc = 0;
971
972 if (!atomic_read(&dpu_crtc->frame_pending)) {
973 DRM_DEBUG_ATOMIC("no frames pending\n");
974 return 0;
975 }
976
977 DPU_ATRACE_BEGIN("frame done completion wait");
978 ret = wait_for_completion_timeout(&dpu_crtc->frame_done_comp,
979 msecs_to_jiffies(DPU_CRTC_FRAME_DONE_TIMEOUT_MS));
980 if (!ret) {
981 DRM_ERROR("frame done wait timed out, ret:%d\n", ret);
982 rc = -ETIMEDOUT;
983 }
984 DPU_ATRACE_END("frame done completion wait");
985
986 return rc;
987 }
988
dpu_crtc_kickoff_clone_mode(struct drm_crtc * crtc)989 static int dpu_crtc_kickoff_clone_mode(struct drm_crtc *crtc)
990 {
991 struct drm_encoder *encoder;
992 struct drm_encoder *rt_encoder = NULL, *wb_encoder = NULL;
993 struct dpu_kms *dpu_kms = _dpu_crtc_get_kms(crtc);
994
995 /* Find encoder for real time display */
996 drm_for_each_encoder_mask(encoder, crtc->dev,
997 crtc->state->encoder_mask) {
998 if (encoder->encoder_type == DRM_MODE_ENCODER_VIRTUAL)
999 wb_encoder = encoder;
1000 else
1001 rt_encoder = encoder;
1002 }
1003
1004 if (!rt_encoder || !wb_encoder) {
1005 DRM_DEBUG_ATOMIC("real time or wb encoder not found\n");
1006 return -EINVAL;
1007 }
1008
1009 dpu_encoder_prepare_for_kickoff(wb_encoder);
1010 dpu_encoder_prepare_for_kickoff(rt_encoder);
1011
1012 dpu_vbif_clear_errors(dpu_kms);
1013
1014 /*
1015 * Kickoff real time encoder last as it's the encoder that
1016 * will do the flush
1017 */
1018 dpu_encoder_kickoff(wb_encoder);
1019 dpu_encoder_kickoff(rt_encoder);
1020
1021 /* Don't start frame done timers until the kickoffs have finished */
1022 dpu_encoder_start_frame_done_timer(wb_encoder);
1023 dpu_encoder_start_frame_done_timer(rt_encoder);
1024
1025 return 0;
1026 }
1027
1028 /**
1029 * dpu_crtc_commit_kickoff - trigger kickoff of the commit for this crtc
1030 * @crtc: Pointer to drm crtc object
1031 */
dpu_crtc_commit_kickoff(struct drm_crtc * crtc)1032 void dpu_crtc_commit_kickoff(struct drm_crtc *crtc)
1033 {
1034 struct drm_encoder *encoder;
1035 struct dpu_crtc *dpu_crtc = to_dpu_crtc(crtc);
1036 struct dpu_kms *dpu_kms = _dpu_crtc_get_kms(crtc);
1037 struct dpu_crtc_state *cstate = to_dpu_crtc_state(crtc->state);
1038
1039 /*
1040 * If no mixers has been allocated in dpu_crtc_atomic_check(),
1041 * it means we are trying to start a CRTC whose state is disabled:
1042 * nothing else needs to be done.
1043 */
1044 if (unlikely(!cstate->num_mixers))
1045 return;
1046
1047 DPU_ATRACE_BEGIN("crtc_commit");
1048
1049 drm_for_each_encoder_mask(encoder, crtc->dev,
1050 crtc->state->encoder_mask) {
1051 if (!dpu_encoder_is_valid_for_commit(encoder)) {
1052 DRM_DEBUG_ATOMIC("invalid FB not kicking off crtc\n");
1053 goto end;
1054 }
1055 }
1056
1057 if (drm_crtc_in_clone_mode(crtc->state)) {
1058 if (dpu_crtc_kickoff_clone_mode(crtc))
1059 goto end;
1060 } else {
1061 /*
1062 * Encoder will flush/start now, unless it has a tx pending.
1063 * If so, it may delay and flush at an irq event (e.g. ppdone)
1064 */
1065 drm_for_each_encoder_mask(encoder, crtc->dev,
1066 crtc->state->encoder_mask)
1067 dpu_encoder_prepare_for_kickoff(encoder);
1068
1069 dpu_vbif_clear_errors(dpu_kms);
1070
1071 drm_for_each_encoder_mask(encoder, crtc->dev,
1072 crtc->state->encoder_mask) {
1073 dpu_encoder_kickoff(encoder);
1074 dpu_encoder_start_frame_done_timer(encoder);
1075 }
1076 }
1077
1078 if (atomic_inc_return(&dpu_crtc->frame_pending) == 1) {
1079 /* acquire bandwidth and other resources */
1080 DRM_DEBUG_ATOMIC("crtc%d first commit\n", crtc->base.id);
1081 } else
1082 DRM_DEBUG_ATOMIC("crtc%d commit\n", crtc->base.id);
1083
1084 dpu_crtc->play_count++;
1085
1086 reinit_completion(&dpu_crtc->frame_done_comp);
1087
1088 end:
1089 DPU_ATRACE_END("crtc_commit");
1090 }
1091
dpu_crtc_reset(struct drm_crtc * crtc)1092 static void dpu_crtc_reset(struct drm_crtc *crtc)
1093 {
1094 struct dpu_crtc_state *cstate = kzalloc(sizeof(*cstate), GFP_KERNEL);
1095
1096 if (crtc->state)
1097 dpu_crtc_destroy_state(crtc, crtc->state);
1098
1099 if (cstate)
1100 __drm_atomic_helper_crtc_reset(crtc, &cstate->base);
1101 else
1102 __drm_atomic_helper_crtc_reset(crtc, NULL);
1103 }
1104
1105 /**
1106 * dpu_crtc_duplicate_state - state duplicate hook
1107 * @crtc: Pointer to drm crtc structure
1108 */
dpu_crtc_duplicate_state(struct drm_crtc * crtc)1109 static struct drm_crtc_state *dpu_crtc_duplicate_state(struct drm_crtc *crtc)
1110 {
1111 struct dpu_crtc_state *cstate, *old_cstate = to_dpu_crtc_state(crtc->state);
1112
1113 cstate = kmemdup(old_cstate, sizeof(*old_cstate), GFP_KERNEL);
1114 if (!cstate) {
1115 DPU_ERROR("failed to allocate state\n");
1116 return NULL;
1117 }
1118
1119 /* duplicate base helper */
1120 __drm_atomic_helper_crtc_duplicate_state(crtc, &cstate->base);
1121
1122 return &cstate->base;
1123 }
1124
dpu_crtc_atomic_print_state(struct drm_printer * p,const struct drm_crtc_state * state)1125 static void dpu_crtc_atomic_print_state(struct drm_printer *p,
1126 const struct drm_crtc_state *state)
1127 {
1128 const struct dpu_crtc_state *cstate = to_dpu_crtc_state(state);
1129 int i;
1130
1131 for (i = 0; i < cstate->num_mixers; i++) {
1132 drm_printf(p, "\tlm[%d]=%d\n", i, cstate->mixers[i].hw_lm->idx - LM_0);
1133 drm_printf(p, "\tctl[%d]=%d\n", i, cstate->mixers[i].lm_ctl->idx - CTL_0);
1134 if (cstate->mixers[i].hw_dspp)
1135 drm_printf(p, "\tdspp[%d]=%d\n", i, cstate->mixers[i].hw_dspp->idx - DSPP_0);
1136 }
1137 }
1138
dpu_crtc_disable(struct drm_crtc * crtc,struct drm_atomic_state * state)1139 static void dpu_crtc_disable(struct drm_crtc *crtc,
1140 struct drm_atomic_state *state)
1141 {
1142 struct drm_crtc_state *old_crtc_state = drm_atomic_get_old_crtc_state(state,
1143 crtc);
1144 struct dpu_crtc *dpu_crtc = to_dpu_crtc(crtc);
1145 struct dpu_crtc_state *cstate = to_dpu_crtc_state(crtc->state);
1146 struct drm_encoder *encoder;
1147 unsigned long flags;
1148 bool release_bandwidth = false;
1149
1150 DRM_DEBUG_KMS("crtc%d\n", crtc->base.id);
1151
1152 /* If disable is triggered while in self refresh mode,
1153 * reset the encoder software state so that in enable
1154 * it won't trigger a warn while assigning crtc.
1155 */
1156 if (old_crtc_state->self_refresh_active) {
1157 drm_for_each_encoder_mask(encoder, crtc->dev,
1158 old_crtc_state->encoder_mask) {
1159 dpu_encoder_assign_crtc(encoder, NULL);
1160 }
1161 return;
1162 }
1163
1164 /* Disable/save vblank irq handling */
1165 drm_crtc_vblank_off(crtc);
1166
1167 drm_for_each_encoder_mask(encoder, crtc->dev,
1168 old_crtc_state->encoder_mask) {
1169 /* in video mode, we hold an extra bandwidth reference
1170 * as we cannot drop bandwidth at frame-done if any
1171 * crtc is being used in video mode.
1172 */
1173 if (dpu_encoder_get_intf_mode(encoder) == INTF_MODE_VIDEO)
1174 release_bandwidth = true;
1175
1176 /*
1177 * If disable is triggered during psr active(e.g: screen dim in PSR),
1178 * we will need encoder->crtc connection to process the device sleep &
1179 * preserve it during psr sequence.
1180 */
1181 if (!crtc->state->self_refresh_active)
1182 dpu_encoder_assign_crtc(encoder, NULL);
1183 }
1184
1185 /* wait for frame_event_done completion */
1186 if (_dpu_crtc_wait_for_frame_done(crtc))
1187 DPU_ERROR("crtc%d wait for frame done failed;frame_pending%d\n",
1188 crtc->base.id,
1189 atomic_read(&dpu_crtc->frame_pending));
1190
1191 trace_dpu_crtc_disable(DRMID(crtc), false, dpu_crtc);
1192 dpu_crtc->enabled = false;
1193
1194 if (atomic_read(&dpu_crtc->frame_pending)) {
1195 trace_dpu_crtc_disable_frame_pending(DRMID(crtc),
1196 atomic_read(&dpu_crtc->frame_pending));
1197 if (release_bandwidth)
1198 dpu_core_perf_crtc_release_bw(crtc);
1199 atomic_set(&dpu_crtc->frame_pending, 0);
1200 }
1201
1202 dpu_core_perf_crtc_update(crtc, 0);
1203
1204 /* disable clk & bw control until clk & bw properties are set */
1205 cstate->bw_control = false;
1206 cstate->bw_split_vote = false;
1207
1208 if (crtc->state->event && !crtc->state->active) {
1209 spin_lock_irqsave(&crtc->dev->event_lock, flags);
1210 drm_crtc_send_vblank_event(crtc, crtc->state->event);
1211 crtc->state->event = NULL;
1212 spin_unlock_irqrestore(&crtc->dev->event_lock, flags);
1213 }
1214
1215 pm_runtime_put_sync(crtc->dev->dev);
1216 }
1217
dpu_crtc_enable(struct drm_crtc * crtc,struct drm_atomic_state * state)1218 static void dpu_crtc_enable(struct drm_crtc *crtc,
1219 struct drm_atomic_state *state)
1220 {
1221 struct dpu_crtc *dpu_crtc = to_dpu_crtc(crtc);
1222 struct drm_encoder *encoder;
1223 bool request_bandwidth = false;
1224 struct drm_crtc_state *old_crtc_state;
1225
1226 old_crtc_state = drm_atomic_get_old_crtc_state(state, crtc);
1227
1228 pm_runtime_get_sync(crtc->dev->dev);
1229
1230 DRM_DEBUG_KMS("crtc%d\n", crtc->base.id);
1231
1232 drm_for_each_encoder_mask(encoder, crtc->dev, crtc->state->encoder_mask) {
1233 /* in video mode, we hold an extra bandwidth reference
1234 * as we cannot drop bandwidth at frame-done if any
1235 * crtc is being used in video mode.
1236 */
1237 if (dpu_encoder_get_intf_mode(encoder) == INTF_MODE_VIDEO)
1238 request_bandwidth = true;
1239 }
1240
1241 if (request_bandwidth)
1242 atomic_inc(&_dpu_crtc_get_kms(crtc)->bandwidth_ref);
1243
1244 trace_dpu_crtc_enable(DRMID(crtc), true, dpu_crtc);
1245 dpu_crtc->enabled = true;
1246
1247 if (!old_crtc_state->self_refresh_active) {
1248 drm_for_each_encoder_mask(encoder, crtc->dev, crtc->state->encoder_mask)
1249 dpu_encoder_assign_crtc(encoder, crtc);
1250 }
1251
1252 /* Enable/restore vblank irq handling */
1253 drm_crtc_vblank_on(crtc);
1254 }
1255
dpu_crtc_needs_dirtyfb(struct drm_crtc_state * cstate)1256 static bool dpu_crtc_needs_dirtyfb(struct drm_crtc_state *cstate)
1257 {
1258 struct drm_crtc *crtc = cstate->crtc;
1259 struct drm_encoder *encoder;
1260
1261 if (cstate->self_refresh_active)
1262 return true;
1263
1264 drm_for_each_encoder_mask (encoder, crtc->dev, cstate->encoder_mask) {
1265 if (dpu_encoder_get_intf_mode(encoder) == INTF_MODE_CMD) {
1266 return true;
1267 }
1268 }
1269
1270 return false;
1271 }
1272
dpu_crtc_reassign_planes(struct drm_crtc * crtc,struct drm_crtc_state * crtc_state)1273 static int dpu_crtc_reassign_planes(struct drm_crtc *crtc, struct drm_crtc_state *crtc_state)
1274 {
1275 int total_planes = crtc->dev->mode_config.num_total_plane;
1276 struct drm_atomic_state *state = crtc_state->state;
1277 struct dpu_global_state *global_state;
1278 struct drm_plane_state **states;
1279 struct drm_plane *plane;
1280 int ret;
1281
1282 global_state = dpu_kms_get_global_state(crtc_state->state);
1283 if (IS_ERR(global_state))
1284 return PTR_ERR(global_state);
1285
1286 dpu_rm_release_all_sspp(global_state, crtc);
1287
1288 if (!crtc_state->enable)
1289 return 0;
1290
1291 states = kcalloc(total_planes, sizeof(*states), GFP_KERNEL);
1292 if (!states)
1293 return -ENOMEM;
1294
1295 drm_atomic_crtc_state_for_each_plane(plane, crtc_state) {
1296 struct drm_plane_state *plane_state =
1297 drm_atomic_get_plane_state(state, plane);
1298
1299 if (IS_ERR(plane_state)) {
1300 ret = PTR_ERR(plane_state);
1301 goto done;
1302 }
1303
1304 states[plane_state->normalized_zpos] = plane_state;
1305 }
1306
1307 ret = dpu_assign_plane_resources(global_state, state, crtc, states, total_planes);
1308
1309 done:
1310 kfree(states);
1311 return ret;
1312 }
1313
1314 #define MAX_CHANNELS_PER_CRTC 2
1315 #define MAX_HDISPLAY_SPLIT 1080
1316
dpu_crtc_get_topology(struct drm_crtc * crtc,struct dpu_kms * dpu_kms,struct drm_crtc_state * crtc_state)1317 static struct msm_display_topology dpu_crtc_get_topology(
1318 struct drm_crtc *crtc,
1319 struct dpu_kms *dpu_kms,
1320 struct drm_crtc_state *crtc_state)
1321 {
1322 struct drm_display_mode *mode = &crtc_state->adjusted_mode;
1323 struct msm_display_topology topology = {0};
1324 struct drm_encoder *drm_enc;
1325
1326 drm_for_each_encoder_mask(drm_enc, crtc->dev, crtc_state->encoder_mask)
1327 dpu_encoder_update_topology(drm_enc, &topology, crtc_state->state,
1328 &crtc_state->adjusted_mode);
1329
1330 topology.cwb_enabled = drm_crtc_in_clone_mode(crtc_state);
1331
1332 /*
1333 * Datapath topology selection
1334 *
1335 * Dual display
1336 * 2 LM, 2 INTF ( Split display using 2 interfaces)
1337 *
1338 * Single display
1339 * 1 LM, 1 INTF
1340 * 2 LM, 1 INTF (stream merge to support high resolution interfaces)
1341 *
1342 * If DSC is enabled, use 2 LMs for 2:2:1 topology
1343 *
1344 * Add dspps to the reservation requirements if ctm is requested
1345 *
1346 * Only hardcode num_lm to 2 for cases where num_intf == 2 and CWB is not
1347 * enabled. This is because in cases where CWB is enabled, num_intf will
1348 * count both the WB and real-time phys encoders.
1349 *
1350 * For non-DSC CWB usecases, have the num_lm be decided by the
1351 * (mode->hdisplay > MAX_HDISPLAY_SPLIT) check.
1352 */
1353
1354 if (topology.num_intf == 2 && !topology.cwb_enabled)
1355 topology.num_lm = 2;
1356 else if (topology.num_dsc == 2)
1357 topology.num_lm = 2;
1358 else if (dpu_kms->catalog->caps->has_3d_merge)
1359 topology.num_lm = (mode->hdisplay > MAX_HDISPLAY_SPLIT) ? 2 : 1;
1360 else
1361 topology.num_lm = 1;
1362
1363 if (crtc_state->ctm)
1364 topology.num_dspp = topology.num_lm;
1365
1366 return topology;
1367 }
1368
dpu_crtc_assign_resources(struct drm_crtc * crtc,struct drm_crtc_state * crtc_state)1369 static int dpu_crtc_assign_resources(struct drm_crtc *crtc,
1370 struct drm_crtc_state *crtc_state)
1371 {
1372 struct dpu_hw_blk *hw_ctl[MAX_CHANNELS_PER_CRTC];
1373 struct dpu_hw_blk *hw_lm[MAX_CHANNELS_PER_CRTC];
1374 struct dpu_hw_blk *hw_dspp[MAX_CHANNELS_PER_CRTC];
1375 int i, num_lm, num_ctl, num_dspp;
1376 struct dpu_kms *dpu_kms = _dpu_crtc_get_kms(crtc);
1377 struct dpu_global_state *global_state;
1378 struct dpu_crtc_state *cstate;
1379 struct msm_display_topology topology;
1380 int ret;
1381
1382 /*
1383 * Release and Allocate resources on every modeset
1384 */
1385 global_state = dpu_kms_get_global_state(crtc_state->state);
1386 if (IS_ERR(global_state))
1387 return PTR_ERR(global_state);
1388
1389 dpu_rm_release(global_state, crtc);
1390
1391 if (!crtc_state->enable)
1392 return 0;
1393
1394 topology = dpu_crtc_get_topology(crtc, dpu_kms, crtc_state);
1395 ret = dpu_rm_reserve(&dpu_kms->rm, global_state,
1396 crtc_state->crtc, &topology);
1397 if (ret)
1398 return ret;
1399
1400 cstate = to_dpu_crtc_state(crtc_state);
1401
1402 num_ctl = dpu_rm_get_assigned_resources(&dpu_kms->rm, global_state,
1403 crtc_state->crtc,
1404 DPU_HW_BLK_CTL, hw_ctl,
1405 ARRAY_SIZE(hw_ctl));
1406 num_lm = dpu_rm_get_assigned_resources(&dpu_kms->rm, global_state,
1407 crtc_state->crtc,
1408 DPU_HW_BLK_LM, hw_lm,
1409 ARRAY_SIZE(hw_lm));
1410 num_dspp = dpu_rm_get_assigned_resources(&dpu_kms->rm, global_state,
1411 crtc_state->crtc,
1412 DPU_HW_BLK_DSPP, hw_dspp,
1413 ARRAY_SIZE(hw_dspp));
1414
1415 for (i = 0; i < num_lm; i++) {
1416 int ctl_idx = (i < num_ctl) ? i : (num_ctl-1);
1417
1418 cstate->mixers[i].hw_lm = to_dpu_hw_mixer(hw_lm[i]);
1419 cstate->mixers[i].lm_ctl = to_dpu_hw_ctl(hw_ctl[ctl_idx]);
1420 if (i < num_dspp)
1421 cstate->mixers[i].hw_dspp = to_dpu_hw_dspp(hw_dspp[i]);
1422 }
1423
1424 cstate->num_mixers = num_lm;
1425
1426 return 0;
1427 }
1428
1429 /**
1430 * dpu_crtc_check_mode_changed: check if full modeset is required
1431 * @old_crtc_state: Previous CRTC state
1432 * @new_crtc_state: Corresponding CRTC state to be checked
1433 *
1434 * Check if the changes in the object properties demand full mode set.
1435 */
dpu_crtc_check_mode_changed(struct drm_crtc_state * old_crtc_state,struct drm_crtc_state * new_crtc_state)1436 int dpu_crtc_check_mode_changed(struct drm_crtc_state *old_crtc_state,
1437 struct drm_crtc_state *new_crtc_state)
1438 {
1439 struct drm_encoder *drm_enc;
1440 struct drm_crtc *crtc = new_crtc_state->crtc;
1441 bool clone_mode_enabled = drm_crtc_in_clone_mode(old_crtc_state);
1442 bool clone_mode_requested = drm_crtc_in_clone_mode(new_crtc_state);
1443
1444 DRM_DEBUG_ATOMIC("%d\n", crtc->base.id);
1445
1446 /* there might be cases where encoder needs a modeset too */
1447 drm_for_each_encoder_mask(drm_enc, crtc->dev, new_crtc_state->encoder_mask) {
1448 if (dpu_encoder_needs_modeset(drm_enc, new_crtc_state->state))
1449 new_crtc_state->mode_changed = true;
1450 }
1451
1452 if ((clone_mode_requested && !clone_mode_enabled) ||
1453 (!clone_mode_requested && clone_mode_enabled))
1454 new_crtc_state->mode_changed = true;
1455
1456 return 0;
1457 }
1458
dpu_crtc_atomic_check(struct drm_crtc * crtc,struct drm_atomic_state * state)1459 static int dpu_crtc_atomic_check(struct drm_crtc *crtc,
1460 struct drm_atomic_state *state)
1461 {
1462 struct drm_crtc_state *crtc_state = drm_atomic_get_new_crtc_state(state,
1463 crtc);
1464 struct dpu_crtc *dpu_crtc = to_dpu_crtc(crtc);
1465 struct dpu_crtc_state *cstate = to_dpu_crtc_state(crtc_state);
1466
1467 const struct drm_plane_state *pstate;
1468 struct drm_plane *plane;
1469
1470 int rc = 0;
1471
1472 bool needs_dirtyfb = dpu_crtc_needs_dirtyfb(crtc_state);
1473
1474 /* don't reallocate resources if only ACTIVE has beeen changed */
1475 if (crtc_state->mode_changed || crtc_state->connectors_changed) {
1476 rc = dpu_crtc_assign_resources(crtc, crtc_state);
1477 if (rc < 0)
1478 return rc;
1479 }
1480
1481 if (dpu_use_virtual_planes &&
1482 (crtc_state->planes_changed || crtc_state->zpos_changed)) {
1483 rc = dpu_crtc_reassign_planes(crtc, crtc_state);
1484 if (rc < 0)
1485 return rc;
1486 }
1487
1488 if (!crtc_state->enable || !drm_atomic_crtc_effectively_active(crtc_state)) {
1489 DRM_DEBUG_ATOMIC("crtc%d -> enable %d, active %d, skip atomic_check\n",
1490 crtc->base.id, crtc_state->enable,
1491 crtc_state->active);
1492 memset(&cstate->new_perf, 0, sizeof(cstate->new_perf));
1493 return 0;
1494 }
1495
1496 DRM_DEBUG_ATOMIC("%s: check\n", dpu_crtc->name);
1497
1498 if (cstate->num_mixers) {
1499 rc = _dpu_crtc_check_and_setup_lm_bounds(crtc, crtc_state);
1500 if (rc)
1501 return rc;
1502 }
1503
1504 /* FIXME: move this to dpu_plane_atomic_check? */
1505 drm_atomic_crtc_state_for_each_plane_state(plane, pstate, crtc_state) {
1506 struct dpu_plane_state *dpu_pstate = to_dpu_plane_state(pstate);
1507
1508 if (IS_ERR_OR_NULL(pstate)) {
1509 rc = PTR_ERR(pstate);
1510 DPU_ERROR("%s: failed to get plane%d state, %d\n",
1511 dpu_crtc->name, plane->base.id, rc);
1512 return rc;
1513 }
1514
1515 if (!pstate->visible)
1516 continue;
1517
1518 dpu_pstate->needs_dirtyfb = needs_dirtyfb;
1519 }
1520
1521 atomic_inc(&_dpu_crtc_get_kms(crtc)->bandwidth_ref);
1522
1523 rc = dpu_core_perf_crtc_check(crtc, crtc_state);
1524 if (rc) {
1525 DPU_ERROR("crtc%d failed performance check %d\n",
1526 crtc->base.id, rc);
1527 return rc;
1528 }
1529
1530 return 0;
1531 }
1532
dpu_crtc_mode_valid(struct drm_crtc * crtc,const struct drm_display_mode * mode)1533 static enum drm_mode_status dpu_crtc_mode_valid(struct drm_crtc *crtc,
1534 const struct drm_display_mode *mode)
1535 {
1536 struct dpu_kms *dpu_kms = _dpu_crtc_get_kms(crtc);
1537
1538 /* if there is no 3d_mux block we cannot merge LMs so we cannot
1539 * split the large layer into 2 LMs, filter out such modes
1540 */
1541 if (!dpu_kms->catalog->caps->has_3d_merge &&
1542 mode->hdisplay > dpu_kms->catalog->caps->max_mixer_width)
1543 return MODE_BAD_HVALUE;
1544 /*
1545 * max crtc width is equal to the max mixer width * 2 and max height is 4K
1546 */
1547 return drm_mode_validate_size(mode,
1548 2 * dpu_kms->catalog->caps->max_mixer_width,
1549 4096);
1550 }
1551
1552 /**
1553 * dpu_crtc_vblank - enable or disable vblanks for this crtc
1554 * @crtc: Pointer to drm crtc object
1555 * @en: true to enable vblanks, false to disable
1556 */
dpu_crtc_vblank(struct drm_crtc * crtc,bool en)1557 int dpu_crtc_vblank(struct drm_crtc *crtc, bool en)
1558 {
1559 struct dpu_crtc *dpu_crtc = to_dpu_crtc(crtc);
1560 struct drm_encoder *enc;
1561
1562 trace_dpu_crtc_vblank(DRMID(&dpu_crtc->base), en, dpu_crtc);
1563
1564 /*
1565 * Normally we would iterate through encoder_mask in crtc state to find
1566 * attached encoders. In this case, we might be disabling vblank _after_
1567 * encoder_mask has been cleared.
1568 *
1569 * Instead, we "assign" a crtc to the encoder in enable and clear it in
1570 * disable (which is also after encoder_mask is cleared). So instead of
1571 * using encoder mask, we'll ask the encoder to toggle itself iff it's
1572 * currently assigned to our crtc.
1573 *
1574 * Note also that this function cannot be called while crtc is disabled
1575 * since we use drm_crtc_vblank_on/off. So we don't need to worry
1576 * about the assigned crtcs being inconsistent with the current state
1577 * (which means no need to worry about modeset locks).
1578 */
1579 list_for_each_entry(enc, &crtc->dev->mode_config.encoder_list, head) {
1580 trace_dpu_crtc_vblank_enable(DRMID(crtc), DRMID(enc), en,
1581 dpu_crtc);
1582
1583 dpu_encoder_toggle_vblank_for_crtc(enc, crtc, en);
1584 }
1585
1586 return 0;
1587 }
1588
1589 #ifdef CONFIG_DEBUG_FS
_dpu_debugfs_status_show(struct seq_file * s,void * data)1590 static int _dpu_debugfs_status_show(struct seq_file *s, void *data)
1591 {
1592 struct dpu_crtc *dpu_crtc;
1593 struct dpu_plane_state *pstate = NULL;
1594 struct dpu_crtc_mixer *m;
1595
1596 struct drm_crtc *crtc;
1597 struct drm_plane *plane;
1598 struct drm_display_mode *mode;
1599 struct drm_framebuffer *fb;
1600 struct drm_plane_state *state;
1601 struct dpu_crtc_state *cstate;
1602
1603 int i, out_width;
1604
1605 dpu_crtc = s->private;
1606 crtc = &dpu_crtc->base;
1607
1608 drm_modeset_lock_all(crtc->dev);
1609 cstate = to_dpu_crtc_state(crtc->state);
1610
1611 mode = &crtc->state->adjusted_mode;
1612 out_width = mode->hdisplay / cstate->num_mixers;
1613
1614 seq_printf(s, "crtc:%d width:%d height:%d\n", crtc->base.id,
1615 mode->hdisplay, mode->vdisplay);
1616
1617 seq_puts(s, "\n");
1618
1619 for (i = 0; i < cstate->num_mixers; ++i) {
1620 m = &cstate->mixers[i];
1621 seq_printf(s, "\tmixer:%d ctl:%d width:%d height:%d\n",
1622 m->hw_lm->idx - LM_0, m->lm_ctl->idx - CTL_0,
1623 out_width, mode->vdisplay);
1624 }
1625
1626 seq_puts(s, "\n");
1627
1628 drm_atomic_crtc_for_each_plane(plane, crtc) {
1629 pstate = to_dpu_plane_state(plane->state);
1630 state = plane->state;
1631
1632 if (!pstate || !state)
1633 continue;
1634
1635 seq_printf(s, "\tplane:%u stage:%d\n", plane->base.id,
1636 pstate->stage);
1637
1638 if (plane->state->fb) {
1639 fb = plane->state->fb;
1640
1641 seq_printf(s, "\tfb:%d image format:%4.4s wxh:%ux%u ",
1642 fb->base.id, (char *) &fb->format->format,
1643 fb->width, fb->height);
1644 for (i = 0; i < ARRAY_SIZE(fb->format->cpp); ++i)
1645 seq_printf(s, "cpp[%d]:%u ",
1646 i, fb->format->cpp[i]);
1647 seq_puts(s, "\n\t");
1648
1649 seq_printf(s, "modifier:%8llu ", fb->modifier);
1650 seq_puts(s, "\n");
1651
1652 seq_puts(s, "\t");
1653 for (i = 0; i < ARRAY_SIZE(fb->pitches); i++)
1654 seq_printf(s, "pitches[%d]:%8u ", i,
1655 fb->pitches[i]);
1656 seq_puts(s, "\n");
1657
1658 seq_puts(s, "\t");
1659 for (i = 0; i < ARRAY_SIZE(fb->offsets); i++)
1660 seq_printf(s, "offsets[%d]:%8u ", i,
1661 fb->offsets[i]);
1662 seq_puts(s, "\n");
1663 }
1664
1665 seq_printf(s, "\tsrc_x:%4d src_y:%4d src_w:%4d src_h:%4d\n",
1666 state->src_x, state->src_y, state->src_w, state->src_h);
1667
1668 seq_printf(s, "\tdst x:%4d dst_y:%4d dst_w:%4d dst_h:%4d\n",
1669 state->crtc_x, state->crtc_y, state->crtc_w,
1670 state->crtc_h);
1671 seq_printf(s, "\tsspp[0]:%s\n",
1672 pstate->pipe.sspp->cap->name);
1673 seq_printf(s, "\tmultirect[0]: mode: %d index: %d\n",
1674 pstate->pipe.multirect_mode, pstate->pipe.multirect_index);
1675 if (pstate->r_pipe.sspp) {
1676 seq_printf(s, "\tsspp[1]:%s\n",
1677 pstate->r_pipe.sspp->cap->name);
1678 seq_printf(s, "\tmultirect[1]: mode: %d index: %d\n",
1679 pstate->r_pipe.multirect_mode, pstate->r_pipe.multirect_index);
1680 }
1681
1682 seq_puts(s, "\n");
1683 }
1684 if (dpu_crtc->vblank_cb_count) {
1685 ktime_t diff = ktime_sub(ktime_get(), dpu_crtc->vblank_cb_time);
1686 s64 diff_ms = ktime_to_ms(diff);
1687 s64 fps = diff_ms ? div_s64(
1688 dpu_crtc->vblank_cb_count * 1000, diff_ms) : 0;
1689
1690 seq_printf(s,
1691 "vblank fps:%lld count:%u total:%llums total_framecount:%llu\n",
1692 fps, dpu_crtc->vblank_cb_count,
1693 ktime_to_ms(diff), dpu_crtc->play_count);
1694
1695 /* reset time & count for next measurement */
1696 dpu_crtc->vblank_cb_count = 0;
1697 dpu_crtc->vblank_cb_time = ktime_set(0, 0);
1698 }
1699
1700 drm_modeset_unlock_all(crtc->dev);
1701
1702 return 0;
1703 }
1704
1705 DEFINE_SHOW_ATTRIBUTE(_dpu_debugfs_status);
1706
dpu_crtc_debugfs_state_show(struct seq_file * s,void * v)1707 static int dpu_crtc_debugfs_state_show(struct seq_file *s, void *v)
1708 {
1709 struct drm_crtc *crtc = s->private;
1710 struct dpu_crtc *dpu_crtc = to_dpu_crtc(crtc);
1711
1712 seq_printf(s, "client type: %d\n", dpu_crtc_get_client_type(crtc));
1713 seq_printf(s, "intf_mode: %d\n", dpu_crtc_get_intf_mode(crtc));
1714 seq_printf(s, "core_clk_rate: %llu\n",
1715 dpu_crtc->cur_perf.core_clk_rate);
1716 seq_printf(s, "bw_ctl: %uk\n",
1717 (u32)DIV_ROUND_UP_ULL(dpu_crtc->cur_perf.bw_ctl, 1000));
1718 seq_printf(s, "max_per_pipe_ib: %u\n",
1719 dpu_crtc->cur_perf.max_per_pipe_ib);
1720
1721 return 0;
1722 }
1723 DEFINE_SHOW_ATTRIBUTE(dpu_crtc_debugfs_state);
1724
_dpu_crtc_init_debugfs(struct drm_crtc * crtc)1725 static int _dpu_crtc_init_debugfs(struct drm_crtc *crtc)
1726 {
1727 struct dpu_crtc *dpu_crtc = to_dpu_crtc(crtc);
1728
1729 debugfs_create_file("status", 0400,
1730 crtc->debugfs_entry,
1731 dpu_crtc, &_dpu_debugfs_status_fops);
1732 debugfs_create_file("state", 0600,
1733 crtc->debugfs_entry,
1734 &dpu_crtc->base,
1735 &dpu_crtc_debugfs_state_fops);
1736
1737 return 0;
1738 }
1739 #else
_dpu_crtc_init_debugfs(struct drm_crtc * crtc)1740 static int _dpu_crtc_init_debugfs(struct drm_crtc *crtc)
1741 {
1742 return 0;
1743 }
1744 #endif /* CONFIG_DEBUG_FS */
1745
dpu_crtc_late_register(struct drm_crtc * crtc)1746 static int dpu_crtc_late_register(struct drm_crtc *crtc)
1747 {
1748 return _dpu_crtc_init_debugfs(crtc);
1749 }
1750
1751 static const struct drm_crtc_funcs dpu_crtc_funcs = {
1752 .set_config = drm_atomic_helper_set_config,
1753 .page_flip = drm_atomic_helper_page_flip,
1754 .reset = dpu_crtc_reset,
1755 .atomic_duplicate_state = dpu_crtc_duplicate_state,
1756 .atomic_destroy_state = dpu_crtc_destroy_state,
1757 .atomic_print_state = dpu_crtc_atomic_print_state,
1758 .late_register = dpu_crtc_late_register,
1759 .verify_crc_source = dpu_crtc_verify_crc_source,
1760 .set_crc_source = dpu_crtc_set_crc_source,
1761 .enable_vblank = msm_crtc_enable_vblank,
1762 .disable_vblank = msm_crtc_disable_vblank,
1763 .get_vblank_timestamp = drm_crtc_vblank_helper_get_vblank_timestamp,
1764 .get_vblank_counter = dpu_crtc_get_vblank_counter,
1765 };
1766
1767 static const struct drm_crtc_helper_funcs dpu_crtc_helper_funcs = {
1768 .atomic_disable = dpu_crtc_disable,
1769 .atomic_enable = dpu_crtc_enable,
1770 .atomic_check = dpu_crtc_atomic_check,
1771 .atomic_begin = dpu_crtc_atomic_begin,
1772 .atomic_flush = dpu_crtc_atomic_flush,
1773 .mode_valid = dpu_crtc_mode_valid,
1774 .get_scanout_position = dpu_crtc_get_scanout_position,
1775 };
1776
1777 /**
1778 * dpu_crtc_init - create a new crtc object
1779 * @dev: dpu device
1780 * @plane: base plane
1781 * @cursor: cursor plane
1782 * @return: new crtc object or error
1783 *
1784 * initialize CRTC
1785 */
dpu_crtc_init(struct drm_device * dev,struct drm_plane * plane,struct drm_plane * cursor)1786 struct drm_crtc *dpu_crtc_init(struct drm_device *dev, struct drm_plane *plane,
1787 struct drm_plane *cursor)
1788 {
1789 struct msm_drm_private *priv = dev->dev_private;
1790 struct dpu_kms *dpu_kms = to_dpu_kms(priv->kms);
1791 struct drm_crtc *crtc = NULL;
1792 struct dpu_crtc *dpu_crtc;
1793 int i, ret;
1794
1795 dpu_crtc = drmm_crtc_alloc_with_planes(dev, struct dpu_crtc, base,
1796 plane, cursor,
1797 &dpu_crtc_funcs,
1798 NULL);
1799
1800 if (IS_ERR(dpu_crtc))
1801 return ERR_CAST(dpu_crtc);
1802
1803 crtc = &dpu_crtc->base;
1804 crtc->dev = dev;
1805
1806 spin_lock_init(&dpu_crtc->spin_lock);
1807 atomic_set(&dpu_crtc->frame_pending, 0);
1808
1809 init_completion(&dpu_crtc->frame_done_comp);
1810
1811 INIT_LIST_HEAD(&dpu_crtc->frame_event_list);
1812
1813 for (i = 0; i < ARRAY_SIZE(dpu_crtc->frame_events); i++) {
1814 INIT_LIST_HEAD(&dpu_crtc->frame_events[i].list);
1815 list_add(&dpu_crtc->frame_events[i].list,
1816 &dpu_crtc->frame_event_list);
1817 kthread_init_work(&dpu_crtc->frame_events[i].work,
1818 dpu_crtc_frame_event_work);
1819 }
1820
1821 drm_crtc_helper_add(crtc, &dpu_crtc_helper_funcs);
1822
1823 if (dpu_kms->catalog->dspp_count)
1824 drm_crtc_enable_color_mgmt(crtc, 0, true, 0);
1825
1826 /* save user friendly CRTC name for later */
1827 snprintf(dpu_crtc->name, DPU_CRTC_NAME_SIZE, "crtc%u", crtc->base.id);
1828
1829 /* initialize event handling */
1830 spin_lock_init(&dpu_crtc->event_lock);
1831
1832 ret = drm_self_refresh_helper_init(crtc);
1833 if (ret) {
1834 DPU_ERROR("Failed to initialize %s with self-refresh helpers %d\n",
1835 crtc->name, ret);
1836 return ERR_PTR(ret);
1837 }
1838
1839 DRM_DEBUG_KMS("%s: successfully initialized crtc\n", dpu_crtc->name);
1840 return crtc;
1841 }
1842