1 /*
2 * Copyright 2016 Advanced Micro Devices, Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
21 *
22 * Authors: AMD
23 *
24 */
25
26 #include "dm_services.h"
27
28 #include "core_types.h"
29
30 #include "reg_helper.h"
31 #include "dcn401/dcn401_dpp.h"
32 #include "basics/conversion.h"
33 #include "dcn10/dcn10_cm_common.h"
34
35 #define NUM_PHASES 64
36 #define HORZ_MAX_TAPS 8
37 #define VERT_MAX_TAPS 8
38
39 #define BLACK_OFFSET_RGB_Y 0x0
40 #define BLACK_OFFSET_CBCR 0x8000
41
42 #define REG(reg)\
43 dpp->tf_regs->reg
44
45 #define CTX \
46 dpp->base.ctx
47
48 #undef FN
49 #define FN(reg_name, field_name) \
50 dpp->tf_shift->field_name, dpp->tf_mask->field_name
51
52 #define NUM_ELEMENTS(a) (sizeof(a) / sizeof((a)[0]))
53
54
55 enum dcn401_coef_filter_type_sel {
56 SCL_COEF_LUMA_VERT_FILTER = 0,
57 SCL_COEF_LUMA_HORZ_FILTER = 1,
58 SCL_COEF_CHROMA_VERT_FILTER = 2,
59 SCL_COEF_CHROMA_HORZ_FILTER = 3,
60 SCL_COEF_SC_VERT_FILTER = 4,
61 SCL_COEF_SC_HORZ_FILTER = 5
62 };
63
64 enum dscl_autocal_mode {
65 AUTOCAL_MODE_OFF = 0,
66
67 /* Autocal calculate the scaling ratio and initial phase and the
68 * DSCL_MODE_SEL must be set to 1
69 */
70 AUTOCAL_MODE_AUTOSCALE = 1,
71 /* Autocal perform auto centering without replication and the
72 * DSCL_MODE_SEL must be set to 0
73 */
74 AUTOCAL_MODE_AUTOCENTER = 2,
75 /* Autocal perform auto centering and auto replication and the
76 * DSCL_MODE_SEL must be set to 0
77 */
78 AUTOCAL_MODE_AUTOREPLICATE = 3
79 };
80
81 enum dscl_mode_sel {
82 DSCL_MODE_SCALING_444_BYPASS = 0,
83 DSCL_MODE_SCALING_444_RGB_ENABLE = 1,
84 DSCL_MODE_SCALING_444_YCBCR_ENABLE = 2,
85 DSCL_MODE_SCALING_YCBCR_ENABLE = 3,
86 DSCL_MODE_LUMA_SCALING_BYPASS = 4,
87 DSCL_MODE_CHROMA_SCALING_BYPASS = 5,
88 DSCL_MODE_DSCL_BYPASS = 6
89 };
90
dpp401_full_bypass(struct dpp * dpp_base)91 void dpp401_full_bypass(struct dpp *dpp_base)
92 {
93 struct dcn401_dpp *dpp = TO_DCN401_DPP(dpp_base);
94
95 /* Input pixel format: ARGB8888 */
96 REG_SET(CNVC_SURFACE_PIXEL_FORMAT, 0,
97 CNVC_SURFACE_PIXEL_FORMAT, 0x8);
98
99 /* Zero expansion */
100 REG_SET_3(FORMAT_CONTROL, 0,
101 CNVC_BYPASS, 0,
102 FORMAT_CONTROL__ALPHA_EN, 0,
103 FORMAT_EXPANSION_MODE, 0);
104
105 /* COLOR_KEYER_CONTROL.COLOR_KEYER_EN = 0 this should be default */
106 if (dpp->tf_mask->CM_BYPASS_EN)
107 REG_SET(CM_CONTROL, 0, CM_BYPASS_EN, 1);
108 else
109 REG_SET(CM_CONTROL, 0, CM_BYPASS, 1);
110
111 /* Setting degamma bypass for now */
112 REG_SET(CM_DGAM_CONTROL, 0, CM_DGAM_LUT_MODE, 0);
113 }
114
dpp401_set_cursor_attributes(struct dpp * dpp_base,struct dc_cursor_attributes * cursor_attributes)115 void dpp401_set_cursor_attributes(
116 struct dpp *dpp_base,
117 struct dc_cursor_attributes *cursor_attributes)
118 {
119 struct dcn401_dpp *dpp = TO_DCN401_DPP(dpp_base);
120 enum dc_cursor_color_format color_format = cursor_attributes->color_format;
121 int cur_rom_en = 0;
122
123 if (color_format == CURSOR_MODE_COLOR_PRE_MULTIPLIED_ALPHA ||
124 color_format == CURSOR_MODE_COLOR_UN_PRE_MULTIPLIED_ALPHA) {
125 if (cursor_attributes->attribute_flags.bits.ENABLE_CURSOR_DEGAMMA) {
126 cur_rom_en = 1;
127 }
128 }
129
130 REG_UPDATE_3(CURSOR0_CONTROL,
131 CUR0_MODE, color_format,
132 CUR0_EXPANSION_MODE, 0,
133 CUR0_ROM_EN, cur_rom_en);
134
135 if (color_format == CURSOR_MODE_MONO) {
136 /* todo: clarify what to program these to */
137 REG_UPDATE(CURSOR0_COLOR0,
138 CUR0_COLOR0, 0x00000000);
139 REG_UPDATE(CURSOR0_COLOR1,
140 CUR0_COLOR1, 0xFFFFFFFF);
141 }
142
143 dpp_base->att.cur0_ctl.bits.expansion_mode = 0;
144 dpp_base->att.cur0_ctl.bits.cur0_rom_en = cur_rom_en;
145 dpp_base->att.cur0_ctl.bits.mode = color_format;
146 }
147
dpp401_set_cursor_position(struct dpp * dpp_base,const struct dc_cursor_position * pos,const struct dc_cursor_mi_param * param,uint32_t width,uint32_t height)148 void dpp401_set_cursor_position(
149 struct dpp *dpp_base,
150 const struct dc_cursor_position *pos,
151 const struct dc_cursor_mi_param *param,
152 uint32_t width,
153 uint32_t height)
154 {
155 struct dcn401_dpp *dpp = TO_DCN401_DPP(dpp_base);
156 uint32_t cur_en = pos->enable ? 1 : 0;
157
158 if (dpp_base->pos.cur0_ctl.bits.cur0_enable != cur_en) {
159 REG_UPDATE(CURSOR0_CONTROL, CUR0_ENABLE, cur_en);
160
161 dpp_base->pos.cur0_ctl.bits.cur0_enable = cur_en;
162 }
163 }
164
dpp401_set_optional_cursor_attributes(struct dpp * dpp_base,struct dpp_cursor_attributes * attr)165 void dpp401_set_optional_cursor_attributes(
166 struct dpp *dpp_base,
167 struct dpp_cursor_attributes *attr)
168 {
169 struct dcn401_dpp *dpp = TO_DCN401_DPP(dpp_base);
170
171 if (attr) {
172 REG_UPDATE(CURSOR0_FP_SCALE_BIAS_G_Y, CUR0_FP_BIAS_G_Y, attr->bias);
173 REG_UPDATE(CURSOR0_FP_SCALE_BIAS_G_Y, CUR0_FP_SCALE_G_Y, attr->scale);
174 REG_UPDATE(CURSOR0_FP_SCALE_BIAS_RB_CRCB, CUR0_FP_BIAS_RB_CRCB, attr->bias);
175 REG_UPDATE(CURSOR0_FP_SCALE_BIAS_RB_CRCB, CUR0_FP_SCALE_RB_CRCB, attr->scale);
176 }
177 }
178
179 /* Program Cursor matrix block in DPP CM */
dpp401_program_cursor_csc(struct dpp * dpp_base,enum dc_color_space color_space,const struct dpp_input_csc_matrix * tbl_entry)180 static void dpp401_program_cursor_csc(
181 struct dpp *dpp_base,
182 enum dc_color_space color_space,
183 const struct dpp_input_csc_matrix *tbl_entry)
184 {
185 struct dcn401_dpp *dpp = TO_DCN401_DPP(dpp_base);
186 uint32_t mode_select = 0;
187 struct color_matrices_reg cur_matrix_regs;
188 unsigned int i;
189 const uint16_t *regval = NULL;
190 int arr_size = sizeof(dpp_input_csc_matrix) / sizeof(struct dpp_input_csc_matrix);
191
192 if (color_space < COLOR_SPACE_YCBCR601) {
193 REG_SET(CUR0_MATRIX_MODE, 0, CUR0_MATRIX_MODE, CUR_MATRIX_BYPASS);
194 return;
195 }
196
197 /* If adjustments not provided use hardcoded table for color space conversion */
198 if (tbl_entry == NULL) {
199
200 for (i = 0; i < arr_size; i++)
201 if (dpp_input_csc_matrix[i].color_space == color_space) {
202 regval = dpp_input_csc_matrix[i].regval;
203 break;
204 }
205
206 if (regval == NULL) {
207 BREAK_TO_DEBUGGER();
208 REG_SET(CUR0_MATRIX_MODE, 0, CUR0_MATRIX_MODE, CUR_MATRIX_BYPASS);
209 return;
210 }
211 } else {
212 regval = tbl_entry->regval;
213 }
214
215 REG_GET(CUR0_MATRIX_MODE, CUR0_MATRIX_MODE_CURRENT, &mode_select);
216
217 //If current set in use not set A, then use set A, otherwise use set B
218 if (mode_select != CUR_MATRIX_SET_A)
219 mode_select = CUR_MATRIX_SET_A;
220 else
221 mode_select = CUR_MATRIX_SET_B;
222
223 cur_matrix_regs.shifts.csc_c11 = dpp->tf_shift->CUR0_MATRIX_C11_A;
224 cur_matrix_regs.masks.csc_c11 = dpp->tf_mask->CUR0_MATRIX_C11_A;
225 cur_matrix_regs.shifts.csc_c12 = dpp->tf_shift->CUR0_MATRIX_C12_A;
226 cur_matrix_regs.masks.csc_c12 = dpp->tf_mask->CUR0_MATRIX_C12_A;
227
228 if (mode_select == CUR_MATRIX_SET_A) {
229 cur_matrix_regs.csc_c11_c12 = REG(CUR0_MATRIX_C11_C12_A);
230 cur_matrix_regs.csc_c33_c34 = REG(CUR0_MATRIX_C33_C34_A);
231 } else {
232 cur_matrix_regs.csc_c11_c12 = REG(CUR0_MATRIX_C11_C12_B);
233 cur_matrix_regs.csc_c33_c34 = REG(CUR0_MATRIX_C33_C34_B);
234 }
235
236 cm_helper_program_color_matrices(
237 dpp->base.ctx,
238 regval,
239 &cur_matrix_regs);
240
241 //select coefficient set to use
242 REG_SET(CUR0_MATRIX_MODE, 0, CUR0_MATRIX_MODE, mode_select);
243 }
244
245 /* Program Cursor matrix block in DPP CM */
dpp401_set_cursor_matrix(struct dpp * dpp_base,enum dc_color_space color_space,struct dc_csc_transform cursor_csc_color_matrix)246 void dpp401_set_cursor_matrix(
247 struct dpp *dpp_base,
248 enum dc_color_space color_space,
249 struct dc_csc_transform cursor_csc_color_matrix)
250 {
251 //Since we don't have cursor matrix information, force bypass mode by passing in unknown color space
252 dpp401_program_cursor_csc(dpp_base, COLOR_SPACE_UNKNOWN, NULL);
253 }
254