1 /*
2 * Copyright 2020 Advanced Micro Devices, Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
21 *
22 * Authors: AMD
23 *
24 */
25
26 #include "dm_services.h"
27 #include "core_types.h"
28 #include "reg_helper.h"
29 #include "dcn30_dpp.h"
30 #include "basics/conversion.h"
31 #include "dcn30_cm_common.h"
32
33 #define REG(reg)\
34 dpp->tf_regs->reg
35
36 #define CTX \
37 dpp->base.ctx
38
39 #undef FN
40 #define FN(reg_name, field_name) \
41 dpp->tf_shift->field_name, dpp->tf_mask->field_name
42
43
dpp30_read_state(struct dpp * dpp_base,struct dcn_dpp_state * s)44 void dpp30_read_state(struct dpp *dpp_base, struct dcn_dpp_state *s)
45 {
46 struct dcn3_dpp *dpp = TO_DCN30_DPP(dpp_base);
47
48 REG_GET(DPP_CONTROL,
49 DPP_CLOCK_ENABLE, &s->is_enabled);
50
51 // TODO: Implement for DCN3
52 }
53 /*program post scaler scs block in dpp CM*/
dpp3_program_post_csc(struct dpp * dpp_base,enum dc_color_space color_space,enum dcn10_input_csc_select input_select,const struct out_csc_color_matrix * tbl_entry)54 void dpp3_program_post_csc(
55 struct dpp *dpp_base,
56 enum dc_color_space color_space,
57 enum dcn10_input_csc_select input_select,
58 const struct out_csc_color_matrix *tbl_entry)
59 {
60 struct dcn3_dpp *dpp = TO_DCN30_DPP(dpp_base);
61 int i;
62 int arr_size = sizeof(dpp_input_csc_matrix)/sizeof(struct dpp_input_csc_matrix);
63 const uint16_t *regval = NULL;
64 uint32_t cur_select = 0;
65 enum dcn10_input_csc_select select;
66 struct color_matrices_reg gam_regs;
67
68 if (input_select == INPUT_CSC_SELECT_BYPASS) {
69 REG_SET(CM_POST_CSC_CONTROL, 0, CM_POST_CSC_MODE, 0);
70 return;
71 }
72
73 if (tbl_entry == NULL) {
74 for (i = 0; i < arr_size; i++)
75 if (dpp_input_csc_matrix[i].color_space == color_space) {
76 regval = dpp_input_csc_matrix[i].regval;
77 break;
78 }
79
80 if (regval == NULL) {
81 BREAK_TO_DEBUGGER();
82 return;
83 }
84 } else {
85 regval = tbl_entry->regval;
86 }
87
88 /* determine which CSC matrix (icsc or coma) we are using
89 * currently. select the alternate set to double buffer
90 * the CSC update so CSC is updated on frame boundary
91 */
92 REG_GET(CM_POST_CSC_CONTROL,
93 CM_POST_CSC_MODE_CURRENT, &cur_select);
94
95 if (cur_select != INPUT_CSC_SELECT_ICSC)
96 select = INPUT_CSC_SELECT_ICSC;
97 else
98 select = INPUT_CSC_SELECT_COMA;
99
100 gam_regs.shifts.csc_c11 = dpp->tf_shift->CM_POST_CSC_C11;
101 gam_regs.masks.csc_c11 = dpp->tf_mask->CM_POST_CSC_C11;
102 gam_regs.shifts.csc_c12 = dpp->tf_shift->CM_POST_CSC_C12;
103 gam_regs.masks.csc_c12 = dpp->tf_mask->CM_POST_CSC_C12;
104
105 if (select == INPUT_CSC_SELECT_ICSC) {
106
107 gam_regs.csc_c11_c12 = REG(CM_POST_CSC_C11_C12);
108 gam_regs.csc_c33_c34 = REG(CM_POST_CSC_C33_C34);
109
110 } else {
111
112 gam_regs.csc_c11_c12 = REG(CM_POST_CSC_B_C11_C12);
113 gam_regs.csc_c33_c34 = REG(CM_POST_CSC_B_C33_C34);
114
115 }
116
117 cm_helper_program_color_matrices(
118 dpp->base.ctx,
119 regval,
120 &gam_regs);
121
122 REG_SET(CM_POST_CSC_CONTROL, 0,
123 CM_POST_CSC_MODE, select);
124 }
125
126
127 /*CNVC degam unit has read only LUTs*/
dpp3_set_pre_degam(struct dpp * dpp_base,enum dc_transfer_func_predefined tr)128 void dpp3_set_pre_degam(struct dpp *dpp_base, enum dc_transfer_func_predefined tr)
129 {
130 struct dcn3_dpp *dpp = TO_DCN30_DPP(dpp_base);
131 int pre_degam_en = 1;
132 int degamma_lut_selection = 0;
133
134 switch (tr) {
135 case TRANSFER_FUNCTION_LINEAR:
136 case TRANSFER_FUNCTION_UNITY:
137 pre_degam_en = 0; //bypass
138 break;
139 case TRANSFER_FUNCTION_SRGB:
140 degamma_lut_selection = 0;
141 break;
142 case TRANSFER_FUNCTION_BT709:
143 degamma_lut_selection = 4;
144 break;
145 case TRANSFER_FUNCTION_PQ:
146 degamma_lut_selection = 5;
147 break;
148 case TRANSFER_FUNCTION_HLG:
149 degamma_lut_selection = 6;
150 break;
151 case TRANSFER_FUNCTION_GAMMA22:
152 degamma_lut_selection = 1;
153 break;
154 case TRANSFER_FUNCTION_GAMMA24:
155 degamma_lut_selection = 2;
156 break;
157 case TRANSFER_FUNCTION_GAMMA26:
158 degamma_lut_selection = 3;
159 break;
160 default:
161 pre_degam_en = 0;
162 break;
163 }
164
165 REG_SET_2(PRE_DEGAM, 0,
166 PRE_DEGAM_MODE, pre_degam_en,
167 PRE_DEGAM_SELECT, degamma_lut_selection);
168 }
169
dpp3_cnv_setup(struct dpp * dpp_base,enum surface_pixel_format format,enum expansion_mode mode,struct dc_csc_transform input_csc_color_matrix,enum dc_color_space input_color_space,struct cnv_alpha_2bit_lut * alpha_2bit_lut)170 void dpp3_cnv_setup (
171 struct dpp *dpp_base,
172 enum surface_pixel_format format,
173 enum expansion_mode mode,
174 struct dc_csc_transform input_csc_color_matrix,
175 enum dc_color_space input_color_space,
176 struct cnv_alpha_2bit_lut *alpha_2bit_lut)
177 {
178 struct dcn3_dpp *dpp = TO_DCN30_DPP(dpp_base);
179 uint32_t pixel_format = 0;
180 uint32_t alpha_en = 1;
181 enum dc_color_space color_space = COLOR_SPACE_SRGB;
182 enum dcn10_input_csc_select select = INPUT_CSC_SELECT_BYPASS;
183 bool force_disable_cursor = false;
184 uint32_t is_2bit = 0;
185 uint32_t alpha_plane_enable = 0;
186 uint32_t dealpha_en = 0, dealpha_ablnd_en = 0;
187 uint32_t realpha_en = 0, realpha_ablnd_en = 0;
188 uint32_t program_prealpha_dealpha = 0;
189 struct out_csc_color_matrix tbl_entry;
190 int i;
191
192 REG_SET_2(FORMAT_CONTROL, 0,
193 CNVC_BYPASS, 0,
194 FORMAT_EXPANSION_MODE, mode);
195
196 REG_UPDATE(FORMAT_CONTROL, FORMAT_CNV16, 0);
197 REG_UPDATE(FORMAT_CONTROL, CNVC_BYPASS_MSB_ALIGN, 0);
198 REG_UPDATE(FORMAT_CONTROL, CLAMP_POSITIVE, 0);
199 REG_UPDATE(FORMAT_CONTROL, CLAMP_POSITIVE_C, 0);
200
201 REG_UPDATE(FORMAT_CONTROL, FORMAT_CROSSBAR_R, 0);
202 REG_UPDATE(FORMAT_CONTROL, FORMAT_CROSSBAR_G, 1);
203 REG_UPDATE(FORMAT_CONTROL, FORMAT_CROSSBAR_B, 2);
204
205 switch (format) {
206 case SURFACE_PIXEL_FORMAT_GRPH_ARGB1555:
207 pixel_format = 1;
208 break;
209 case SURFACE_PIXEL_FORMAT_GRPH_RGB565:
210 pixel_format = 3;
211 alpha_en = 0;
212 break;
213 case SURFACE_PIXEL_FORMAT_GRPH_ARGB8888:
214 case SURFACE_PIXEL_FORMAT_GRPH_ABGR8888:
215 pixel_format = 8;
216 break;
217 case SURFACE_PIXEL_FORMAT_GRPH_ARGB2101010:
218 case SURFACE_PIXEL_FORMAT_GRPH_ABGR2101010:
219 pixel_format = 10;
220 is_2bit = 1;
221 break;
222 case SURFACE_PIXEL_FORMAT_VIDEO_420_YCbCr:
223 force_disable_cursor = false;
224 pixel_format = 65;
225 color_space = COLOR_SPACE_YCBCR709;
226 select = INPUT_CSC_SELECT_ICSC;
227 break;
228 case SURFACE_PIXEL_FORMAT_VIDEO_420_YCrCb:
229 force_disable_cursor = true;
230 pixel_format = 64;
231 color_space = COLOR_SPACE_YCBCR709;
232 select = INPUT_CSC_SELECT_ICSC;
233 break;
234 case SURFACE_PIXEL_FORMAT_VIDEO_420_10bpc_YCbCr:
235 force_disable_cursor = true;
236 pixel_format = 67;
237 color_space = COLOR_SPACE_YCBCR709;
238 select = INPUT_CSC_SELECT_ICSC;
239 break;
240 case SURFACE_PIXEL_FORMAT_VIDEO_420_10bpc_YCrCb:
241 force_disable_cursor = true;
242 pixel_format = 66;
243 color_space = COLOR_SPACE_YCBCR709;
244 select = INPUT_CSC_SELECT_ICSC;
245 break;
246 case SURFACE_PIXEL_FORMAT_GRPH_ARGB16161616:
247 case SURFACE_PIXEL_FORMAT_GRPH_ABGR16161616:
248 pixel_format = 26; /* ARGB16161616_UNORM */
249 break;
250 case SURFACE_PIXEL_FORMAT_GRPH_ARGB16161616F:
251 pixel_format = 24;
252 break;
253 case SURFACE_PIXEL_FORMAT_GRPH_ABGR16161616F:
254 pixel_format = 25;
255 break;
256 case SURFACE_PIXEL_FORMAT_VIDEO_AYCrCb8888:
257 pixel_format = 12;
258 color_space = COLOR_SPACE_YCBCR709;
259 select = INPUT_CSC_SELECT_ICSC;
260 break;
261 case SURFACE_PIXEL_FORMAT_GRPH_RGB111110_FIX:
262 pixel_format = 112;
263 break;
264 case SURFACE_PIXEL_FORMAT_GRPH_BGR101111_FIX:
265 pixel_format = 113;
266 break;
267 case SURFACE_PIXEL_FORMAT_VIDEO_ACrYCb2101010:
268 pixel_format = 114;
269 color_space = COLOR_SPACE_YCBCR709;
270 select = INPUT_CSC_SELECT_ICSC;
271 is_2bit = 1;
272 break;
273 case SURFACE_PIXEL_FORMAT_VIDEO_CrYCbA1010102:
274 pixel_format = 115;
275 color_space = COLOR_SPACE_YCBCR709;
276 select = INPUT_CSC_SELECT_ICSC;
277 is_2bit = 1;
278 break;
279 case SURFACE_PIXEL_FORMAT_GRPH_RGBE:
280 pixel_format = 116;
281 alpha_plane_enable = 0;
282 break;
283 case SURFACE_PIXEL_FORMAT_GRPH_RGBE_ALPHA:
284 pixel_format = 116;
285 alpha_plane_enable = 1;
286 break;
287 case SURFACE_PIXEL_FORMAT_GRPH_RGB111110_FLOAT:
288 pixel_format = 118;
289 break;
290 case SURFACE_PIXEL_FORMAT_GRPH_BGR101111_FLOAT:
291 pixel_format = 119;
292 break;
293 default:
294 break;
295 }
296
297 /* Set default color space based on format if none is given. */
298 color_space = input_color_space ? input_color_space : color_space;
299
300 if (is_2bit == 1 && alpha_2bit_lut != NULL) {
301 REG_UPDATE(ALPHA_2BIT_LUT, ALPHA_2BIT_LUT0, alpha_2bit_lut->lut0);
302 REG_UPDATE(ALPHA_2BIT_LUT, ALPHA_2BIT_LUT1, alpha_2bit_lut->lut1);
303 REG_UPDATE(ALPHA_2BIT_LUT, ALPHA_2BIT_LUT2, alpha_2bit_lut->lut2);
304 REG_UPDATE(ALPHA_2BIT_LUT, ALPHA_2BIT_LUT3, alpha_2bit_lut->lut3);
305 }
306
307 REG_SET_2(CNVC_SURFACE_PIXEL_FORMAT, 0,
308 CNVC_SURFACE_PIXEL_FORMAT, pixel_format,
309 CNVC_ALPHA_PLANE_ENABLE, alpha_plane_enable);
310 REG_UPDATE(FORMAT_CONTROL, FORMAT_CONTROL__ALPHA_EN, alpha_en);
311
312 if (program_prealpha_dealpha) {
313 dealpha_en = 1;
314 realpha_en = 1;
315 }
316 REG_SET_2(PRE_DEALPHA, 0,
317 PRE_DEALPHA_EN, dealpha_en,
318 PRE_DEALPHA_ABLND_EN, dealpha_ablnd_en);
319 REG_SET_2(PRE_REALPHA, 0,
320 PRE_REALPHA_EN, realpha_en,
321 PRE_REALPHA_ABLND_EN, realpha_ablnd_en);
322
323 /* If input adjustment exists, program the ICSC with those values. */
324 if (input_csc_color_matrix.enable_adjustment == true) {
325 for (i = 0; i < 12; i++)
326 tbl_entry.regval[i] = input_csc_color_matrix.matrix[i];
327
328 tbl_entry.color_space = input_color_space;
329
330 if (color_space >= COLOR_SPACE_YCBCR601)
331 select = INPUT_CSC_SELECT_ICSC;
332 else
333 select = INPUT_CSC_SELECT_BYPASS;
334
335 dpp3_program_post_csc(dpp_base, color_space, select,
336 &tbl_entry);
337 } else {
338 dpp3_program_post_csc(dpp_base, color_space, select, NULL);
339 }
340
341 if (force_disable_cursor) {
342 REG_UPDATE(CURSOR_CONTROL,
343 CURSOR_ENABLE, 0);
344 REG_UPDATE(CURSOR0_CONTROL,
345 CUR0_ENABLE, 0);
346 }
347 }
348
349 #define IDENTITY_RATIO(ratio) (dc_fixpt_u3d19(ratio) == (1 << 19))
350
dpp3_set_cursor_attributes(struct dpp * dpp_base,struct dc_cursor_attributes * cursor_attributes)351 void dpp3_set_cursor_attributes(
352 struct dpp *dpp_base,
353 struct dc_cursor_attributes *cursor_attributes)
354 {
355 enum dc_cursor_color_format color_format = cursor_attributes->color_format;
356 struct dcn3_dpp *dpp = TO_DCN30_DPP(dpp_base);
357 int cur_rom_en = 0;
358
359 if (color_format == CURSOR_MODE_COLOR_PRE_MULTIPLIED_ALPHA ||
360 color_format == CURSOR_MODE_COLOR_UN_PRE_MULTIPLIED_ALPHA) {
361 if (cursor_attributes->attribute_flags.bits.ENABLE_CURSOR_DEGAMMA) {
362 cur_rom_en = 1;
363 }
364 }
365
366 REG_UPDATE_3(CURSOR0_CONTROL,
367 CUR0_MODE, color_format,
368 CUR0_EXPANSION_MODE, 0,
369 CUR0_ROM_EN, cur_rom_en);
370
371 if (color_format == CURSOR_MODE_MONO) {
372 /* todo: clarify what to program these to */
373 REG_UPDATE(CURSOR0_COLOR0,
374 CUR0_COLOR0, 0x00000000);
375 REG_UPDATE(CURSOR0_COLOR1,
376 CUR0_COLOR1, 0xFFFFFFFF);
377 }
378
379 dpp_base->att.cur0_ctl.bits.expansion_mode = 0;
380 dpp_base->att.cur0_ctl.bits.cur0_rom_en = cur_rom_en;
381 dpp_base->att.cur0_ctl.bits.mode = color_format;
382 }
383
384
dpp3_get_optimal_number_of_taps(struct dpp * dpp,struct scaler_data * scl_data,const struct scaling_taps * in_taps)385 bool dpp3_get_optimal_number_of_taps(
386 struct dpp *dpp,
387 struct scaler_data *scl_data,
388 const struct scaling_taps *in_taps)
389 {
390 int num_part_y, num_part_c;
391 int max_taps_y, max_taps_c;
392 int min_taps_y, min_taps_c;
393 enum lb_memory_config lb_config;
394
395 if (scl_data->viewport.width > scl_data->h_active &&
396 dpp->ctx->dc->debug.max_downscale_src_width != 0 &&
397 scl_data->viewport.width > dpp->ctx->dc->debug.max_downscale_src_width)
398 return false;
399
400 /*
401 * Set default taps if none are provided
402 * From programming guide: taps = min{ ceil(2*H_RATIO,1), 8} for downscaling
403 * taps = 4 for upscaling
404 */
405 if (in_taps->h_taps == 0) {
406 if (dc_fixpt_ceil(scl_data->ratios.horz) > 1)
407 scl_data->taps.h_taps = min(2 * dc_fixpt_ceil(scl_data->ratios.horz), 8);
408 else
409 scl_data->taps.h_taps = 4;
410 } else
411 scl_data->taps.h_taps = in_taps->h_taps;
412 if (in_taps->v_taps == 0) {
413 if (dc_fixpt_ceil(scl_data->ratios.vert) > 1)
414 scl_data->taps.v_taps = min(dc_fixpt_ceil(dc_fixpt_mul_int(scl_data->ratios.vert, 2)), 8);
415 else
416 scl_data->taps.v_taps = 4;
417 } else
418 scl_data->taps.v_taps = in_taps->v_taps;
419 if (in_taps->v_taps_c == 0) {
420 if (dc_fixpt_ceil(scl_data->ratios.vert_c) > 1)
421 scl_data->taps.v_taps_c = min(dc_fixpt_ceil(dc_fixpt_mul_int(scl_data->ratios.vert_c, 2)), 8);
422 else
423 scl_data->taps.v_taps_c = 4;
424 } else
425 scl_data->taps.v_taps_c = in_taps->v_taps_c;
426 if (in_taps->h_taps_c == 0) {
427 if (dc_fixpt_ceil(scl_data->ratios.horz_c) > 1)
428 scl_data->taps.h_taps_c = min(2 * dc_fixpt_ceil(scl_data->ratios.horz_c), 8);
429 else
430 scl_data->taps.h_taps_c = 4;
431 } else if ((in_taps->h_taps_c % 2) != 0 && in_taps->h_taps_c != 1)
432 /* Only 1 and even h_taps_c are supported by hw */
433 scl_data->taps.h_taps_c = in_taps->h_taps_c - 1;
434 else
435 scl_data->taps.h_taps_c = in_taps->h_taps_c;
436
437 /*Ensure we can support the requested number of vtaps*/
438 min_taps_y = dc_fixpt_ceil(scl_data->ratios.vert);
439 min_taps_c = dc_fixpt_ceil(scl_data->ratios.vert_c);
440
441 /* Use LB_MEMORY_CONFIG_3 for 4:2:0 */
442 if ((scl_data->format == PIXEL_FORMAT_420BPP8) || (scl_data->format == PIXEL_FORMAT_420BPP10))
443 lb_config = LB_MEMORY_CONFIG_3;
444 else
445 lb_config = LB_MEMORY_CONFIG_0;
446
447 dpp->caps->dscl_calc_lb_num_partitions(
448 scl_data, lb_config, &num_part_y, &num_part_c);
449
450 /* MAX_V_TAPS = MIN (NUM_LINES - MAX(CEILING(V_RATIO,1)-2, 0), 8) */
451 if (dc_fixpt_ceil(scl_data->ratios.vert) > 2)
452 max_taps_y = num_part_y - (dc_fixpt_ceil(scl_data->ratios.vert) - 2);
453 else
454 max_taps_y = num_part_y;
455
456 if (dc_fixpt_ceil(scl_data->ratios.vert_c) > 2)
457 max_taps_c = num_part_c - (dc_fixpt_ceil(scl_data->ratios.vert_c) - 2);
458 else
459 max_taps_c = num_part_c;
460
461 if (max_taps_y < min_taps_y)
462 return false;
463 else if (max_taps_c < min_taps_c)
464 return false;
465
466 if (scl_data->taps.v_taps > max_taps_y)
467 scl_data->taps.v_taps = max_taps_y;
468
469 if (scl_data->taps.v_taps_c > max_taps_c)
470 scl_data->taps.v_taps_c = max_taps_c;
471
472 if (!dpp->ctx->dc->debug.always_scale) {
473 if (IDENTITY_RATIO(scl_data->ratios.horz))
474 scl_data->taps.h_taps = 1;
475 if (IDENTITY_RATIO(scl_data->ratios.vert))
476 scl_data->taps.v_taps = 1;
477 if (IDENTITY_RATIO(scl_data->ratios.horz_c))
478 scl_data->taps.h_taps_c = 1;
479 if (IDENTITY_RATIO(scl_data->ratios.vert_c))
480 scl_data->taps.v_taps_c = 1;
481 }
482
483 return true;
484 }
485
dpp3_deferred_update(struct dpp * dpp_base)486 static void dpp3_deferred_update(struct dpp *dpp_base)
487 {
488 int bypass_state;
489 struct dcn3_dpp *dpp = TO_DCN30_DPP(dpp_base);
490
491 if (dpp_base->deferred_reg_writes.bits.disable_dscl) {
492 REG_UPDATE(DSCL_MEM_PWR_CTRL, LUT_MEM_PWR_FORCE, 3);
493 dpp_base->deferred_reg_writes.bits.disable_dscl = false;
494 }
495
496 if (dpp_base->deferred_reg_writes.bits.disable_gamcor) {
497 REG_GET(CM_GAMCOR_CONTROL, CM_GAMCOR_MODE_CURRENT, &bypass_state);
498 if (bypass_state == 0) { // only program if bypass was latched
499 REG_UPDATE(CM_MEM_PWR_CTRL, GAMCOR_MEM_PWR_FORCE, 3);
500 } else
501 ASSERT(0); // LUT select was updated again before vupdate
502 dpp_base->deferred_reg_writes.bits.disable_gamcor = false;
503 }
504
505 if (dpp_base->deferred_reg_writes.bits.disable_blnd_lut) {
506 REG_GET(CM_BLNDGAM_CONTROL, CM_BLNDGAM_MODE_CURRENT, &bypass_state);
507 if (bypass_state == 0) { // only program if bypass was latched
508 REG_UPDATE(CM_MEM_PWR_CTRL, BLNDGAM_MEM_PWR_FORCE, 3);
509 } else
510 ASSERT(0); // LUT select was updated again before vupdate
511 dpp_base->deferred_reg_writes.bits.disable_blnd_lut = false;
512 }
513
514 if (dpp_base->deferred_reg_writes.bits.disable_3dlut) {
515 REG_GET(CM_3DLUT_MODE, CM_3DLUT_MODE_CURRENT, &bypass_state);
516 if (bypass_state == 0) { // only program if bypass was latched
517 REG_UPDATE(CM_MEM_PWR_CTRL2, HDR3DLUT_MEM_PWR_FORCE, 3);
518 } else
519 ASSERT(0); // LUT select was updated again before vupdate
520 dpp_base->deferred_reg_writes.bits.disable_3dlut = false;
521 }
522
523 if (dpp_base->deferred_reg_writes.bits.disable_shaper) {
524 REG_GET(CM_SHAPER_CONTROL, CM_SHAPER_MODE_CURRENT, &bypass_state);
525 if (bypass_state == 0) { // only program if bypass was latched
526 REG_UPDATE(CM_MEM_PWR_CTRL2, SHAPER_MEM_PWR_FORCE, 3);
527 } else
528 ASSERT(0); // LUT select was updated again before vupdate
529 dpp_base->deferred_reg_writes.bits.disable_shaper = false;
530 }
531 }
532
dpp3_power_on_blnd_lut(struct dpp * dpp_base,bool power_on)533 static void dpp3_power_on_blnd_lut(
534 struct dpp *dpp_base,
535 bool power_on)
536 {
537 struct dcn3_dpp *dpp = TO_DCN30_DPP(dpp_base);
538
539 if (dpp_base->ctx->dc->debug.enable_mem_low_power.bits.cm) {
540 if (power_on) {
541 REG_UPDATE(CM_MEM_PWR_CTRL, BLNDGAM_MEM_PWR_FORCE, 0);
542 REG_WAIT(CM_MEM_PWR_STATUS, BLNDGAM_MEM_PWR_STATE, 0, 1, 5);
543 } else {
544 dpp_base->ctx->dc->optimized_required = true;
545 dpp_base->deferred_reg_writes.bits.disable_blnd_lut = true;
546 }
547 } else {
548 REG_SET(CM_MEM_PWR_CTRL, 0,
549 BLNDGAM_MEM_PWR_FORCE, power_on == true ? 0 : 1);
550 }
551 }
552
dpp3_power_on_hdr3dlut(struct dpp * dpp_base,bool power_on)553 static void dpp3_power_on_hdr3dlut(
554 struct dpp *dpp_base,
555 bool power_on)
556 {
557 struct dcn3_dpp *dpp = TO_DCN30_DPP(dpp_base);
558
559 if (dpp_base->ctx->dc->debug.enable_mem_low_power.bits.cm) {
560 if (power_on) {
561 REG_UPDATE(CM_MEM_PWR_CTRL2, HDR3DLUT_MEM_PWR_FORCE, 0);
562 REG_WAIT(CM_MEM_PWR_STATUS2, HDR3DLUT_MEM_PWR_STATE, 0, 1, 5);
563 } else {
564 dpp_base->ctx->dc->optimized_required = true;
565 dpp_base->deferred_reg_writes.bits.disable_3dlut = true;
566 }
567 }
568 }
569
dpp3_power_on_shaper(struct dpp * dpp_base,bool power_on)570 static void dpp3_power_on_shaper(
571 struct dpp *dpp_base,
572 bool power_on)
573 {
574 struct dcn3_dpp *dpp = TO_DCN30_DPP(dpp_base);
575
576 if (dpp_base->ctx->dc->debug.enable_mem_low_power.bits.cm) {
577 if (power_on) {
578 REG_UPDATE(CM_MEM_PWR_CTRL2, SHAPER_MEM_PWR_FORCE, 0);
579 REG_WAIT(CM_MEM_PWR_STATUS2, SHAPER_MEM_PWR_STATE, 0, 1, 5);
580 } else {
581 dpp_base->ctx->dc->optimized_required = true;
582 dpp_base->deferred_reg_writes.bits.disable_shaper = true;
583 }
584 }
585 }
586
dpp3_configure_blnd_lut(struct dpp * dpp_base,bool is_ram_a)587 static void dpp3_configure_blnd_lut(
588 struct dpp *dpp_base,
589 bool is_ram_a)
590 {
591 struct dcn3_dpp *dpp = TO_DCN30_DPP(dpp_base);
592
593 REG_UPDATE_2(CM_BLNDGAM_LUT_CONTROL,
594 CM_BLNDGAM_LUT_WRITE_COLOR_MASK, 7,
595 CM_BLNDGAM_LUT_HOST_SEL, is_ram_a == true ? 0 : 1);
596
597 REG_SET(CM_BLNDGAM_LUT_INDEX, 0, CM_BLNDGAM_LUT_INDEX, 0);
598 }
599
dpp3_program_blnd_pwl(struct dpp * dpp_base,const struct pwl_result_data * rgb,uint32_t num)600 static void dpp3_program_blnd_pwl(
601 struct dpp *dpp_base,
602 const struct pwl_result_data *rgb,
603 uint32_t num)
604 {
605 uint32_t i;
606 struct dcn3_dpp *dpp = TO_DCN30_DPP(dpp_base);
607 uint32_t last_base_value_red = rgb[num-1].red_reg + rgb[num-1].delta_red_reg;
608 uint32_t last_base_value_green = rgb[num-1].green_reg + rgb[num-1].delta_green_reg;
609 uint32_t last_base_value_blue = rgb[num-1].blue_reg + rgb[num-1].delta_blue_reg;
610
611 if (is_rgb_equal(rgb, num)) {
612 for (i = 0 ; i < num; i++)
613 REG_SET(CM_BLNDGAM_LUT_DATA, 0, CM_BLNDGAM_LUT_DATA, rgb[i].red_reg);
614 REG_SET(CM_BLNDGAM_LUT_DATA, 0, CM_BLNDGAM_LUT_DATA, last_base_value_red);
615 } else {
616 REG_SET(CM_BLNDGAM_LUT_INDEX, 0, CM_BLNDGAM_LUT_INDEX, 0);
617 REG_UPDATE(CM_BLNDGAM_LUT_CONTROL, CM_BLNDGAM_LUT_WRITE_COLOR_MASK, 4);
618 for (i = 0 ; i < num; i++)
619 REG_SET(CM_BLNDGAM_LUT_DATA, 0, CM_BLNDGAM_LUT_DATA, rgb[i].red_reg);
620 REG_SET(CM_BLNDGAM_LUT_DATA, 0, CM_BLNDGAM_LUT_DATA, last_base_value_red);
621
622 REG_SET(CM_BLNDGAM_LUT_INDEX, 0, CM_BLNDGAM_LUT_INDEX, 0);
623 REG_UPDATE(CM_BLNDGAM_LUT_CONTROL, CM_BLNDGAM_LUT_WRITE_COLOR_MASK, 2);
624 for (i = 0 ; i < num; i++)
625 REG_SET(CM_BLNDGAM_LUT_DATA, 0, CM_BLNDGAM_LUT_DATA, rgb[i].green_reg);
626 REG_SET(CM_BLNDGAM_LUT_DATA, 0, CM_BLNDGAM_LUT_DATA, last_base_value_green);
627
628 REG_SET(CM_BLNDGAM_LUT_INDEX, 0, CM_BLNDGAM_LUT_INDEX, 0);
629 REG_UPDATE(CM_BLNDGAM_LUT_CONTROL, CM_BLNDGAM_LUT_WRITE_COLOR_MASK, 1);
630 for (i = 0 ; i < num; i++)
631 REG_SET(CM_BLNDGAM_LUT_DATA, 0, CM_BLNDGAM_LUT_DATA, rgb[i].blue_reg);
632 REG_SET(CM_BLNDGAM_LUT_DATA, 0, CM_BLNDGAM_LUT_DATA, last_base_value_blue);
633 }
634 }
635
dcn3_dpp_cm_get_reg_field(struct dcn3_dpp * dpp,struct dcn3_xfer_func_reg * reg)636 static void dcn3_dpp_cm_get_reg_field(
637 struct dcn3_dpp *dpp,
638 struct dcn3_xfer_func_reg *reg)
639 {
640 reg->shifts.exp_region0_lut_offset = dpp->tf_shift->CM_BLNDGAM_RAMA_EXP_REGION0_LUT_OFFSET;
641 reg->masks.exp_region0_lut_offset = dpp->tf_mask->CM_BLNDGAM_RAMA_EXP_REGION0_LUT_OFFSET;
642 reg->shifts.exp_region0_num_segments = dpp->tf_shift->CM_BLNDGAM_RAMA_EXP_REGION0_NUM_SEGMENTS;
643 reg->masks.exp_region0_num_segments = dpp->tf_mask->CM_BLNDGAM_RAMA_EXP_REGION0_NUM_SEGMENTS;
644 reg->shifts.exp_region1_lut_offset = dpp->tf_shift->CM_BLNDGAM_RAMA_EXP_REGION1_LUT_OFFSET;
645 reg->masks.exp_region1_lut_offset = dpp->tf_mask->CM_BLNDGAM_RAMA_EXP_REGION1_LUT_OFFSET;
646 reg->shifts.exp_region1_num_segments = dpp->tf_shift->CM_BLNDGAM_RAMA_EXP_REGION1_NUM_SEGMENTS;
647 reg->masks.exp_region1_num_segments = dpp->tf_mask->CM_BLNDGAM_RAMA_EXP_REGION1_NUM_SEGMENTS;
648
649 reg->shifts.field_region_end = dpp->tf_shift->CM_BLNDGAM_RAMA_EXP_REGION_END_B;
650 reg->masks.field_region_end = dpp->tf_mask->CM_BLNDGAM_RAMA_EXP_REGION_END_B;
651 reg->shifts.field_region_end_slope = dpp->tf_shift->CM_BLNDGAM_RAMA_EXP_REGION_END_SLOPE_B;
652 reg->masks.field_region_end_slope = dpp->tf_mask->CM_BLNDGAM_RAMA_EXP_REGION_END_SLOPE_B;
653 reg->shifts.field_region_end_base = dpp->tf_shift->CM_BLNDGAM_RAMA_EXP_REGION_END_BASE_B;
654 reg->masks.field_region_end_base = dpp->tf_mask->CM_BLNDGAM_RAMA_EXP_REGION_END_BASE_B;
655 reg->shifts.field_region_linear_slope = dpp->tf_shift->CM_BLNDGAM_RAMA_EXP_REGION_START_SLOPE_B;
656 reg->masks.field_region_linear_slope = dpp->tf_mask->CM_BLNDGAM_RAMA_EXP_REGION_START_SLOPE_B;
657 reg->shifts.exp_region_start = dpp->tf_shift->CM_BLNDGAM_RAMA_EXP_REGION_START_B;
658 reg->masks.exp_region_start = dpp->tf_mask->CM_BLNDGAM_RAMA_EXP_REGION_START_B;
659 reg->shifts.exp_resion_start_segment = dpp->tf_shift->CM_BLNDGAM_RAMA_EXP_REGION_START_SEGMENT_B;
660 reg->masks.exp_resion_start_segment = dpp->tf_mask->CM_BLNDGAM_RAMA_EXP_REGION_START_SEGMENT_B;
661 }
662
663 /*program blnd lut RAM A*/
dpp3_program_blnd_luta_settings(struct dpp * dpp_base,const struct pwl_params * params)664 static void dpp3_program_blnd_luta_settings(
665 struct dpp *dpp_base,
666 const struct pwl_params *params)
667 {
668 struct dcn3_dpp *dpp = TO_DCN30_DPP(dpp_base);
669 struct dcn3_xfer_func_reg gam_regs;
670
671 dcn3_dpp_cm_get_reg_field(dpp, &gam_regs);
672
673 gam_regs.start_cntl_b = REG(CM_BLNDGAM_RAMA_START_CNTL_B);
674 gam_regs.start_cntl_g = REG(CM_BLNDGAM_RAMA_START_CNTL_G);
675 gam_regs.start_cntl_r = REG(CM_BLNDGAM_RAMA_START_CNTL_R);
676 gam_regs.start_slope_cntl_b = REG(CM_BLNDGAM_RAMA_START_SLOPE_CNTL_B);
677 gam_regs.start_slope_cntl_g = REG(CM_BLNDGAM_RAMA_START_SLOPE_CNTL_G);
678 gam_regs.start_slope_cntl_r = REG(CM_BLNDGAM_RAMA_START_SLOPE_CNTL_R);
679 gam_regs.start_end_cntl1_b = REG(CM_BLNDGAM_RAMA_END_CNTL1_B);
680 gam_regs.start_end_cntl2_b = REG(CM_BLNDGAM_RAMA_END_CNTL2_B);
681 gam_regs.start_end_cntl1_g = REG(CM_BLNDGAM_RAMA_END_CNTL1_G);
682 gam_regs.start_end_cntl2_g = REG(CM_BLNDGAM_RAMA_END_CNTL2_G);
683 gam_regs.start_end_cntl1_r = REG(CM_BLNDGAM_RAMA_END_CNTL1_R);
684 gam_regs.start_end_cntl2_r = REG(CM_BLNDGAM_RAMA_END_CNTL2_R);
685 gam_regs.region_start = REG(CM_BLNDGAM_RAMA_REGION_0_1);
686 gam_regs.region_end = REG(CM_BLNDGAM_RAMA_REGION_32_33);
687
688 cm_helper_program_gamcor_xfer_func(dpp->base.ctx, params, &gam_regs);
689 }
690
691 /*program blnd lut RAM B*/
dpp3_program_blnd_lutb_settings(struct dpp * dpp_base,const struct pwl_params * params)692 static void dpp3_program_blnd_lutb_settings(
693 struct dpp *dpp_base,
694 const struct pwl_params *params)
695 {
696 struct dcn3_dpp *dpp = TO_DCN30_DPP(dpp_base);
697 struct dcn3_xfer_func_reg gam_regs;
698
699 dcn3_dpp_cm_get_reg_field(dpp, &gam_regs);
700
701 gam_regs.start_cntl_b = REG(CM_BLNDGAM_RAMB_START_CNTL_B);
702 gam_regs.start_cntl_g = REG(CM_BLNDGAM_RAMB_START_CNTL_G);
703 gam_regs.start_cntl_r = REG(CM_BLNDGAM_RAMB_START_CNTL_R);
704 gam_regs.start_slope_cntl_b = REG(CM_BLNDGAM_RAMB_START_SLOPE_CNTL_B);
705 gam_regs.start_slope_cntl_g = REG(CM_BLNDGAM_RAMB_START_SLOPE_CNTL_G);
706 gam_regs.start_slope_cntl_r = REG(CM_BLNDGAM_RAMB_START_SLOPE_CNTL_R);
707 gam_regs.start_end_cntl1_b = REG(CM_BLNDGAM_RAMB_END_CNTL1_B);
708 gam_regs.start_end_cntl2_b = REG(CM_BLNDGAM_RAMB_END_CNTL2_B);
709 gam_regs.start_end_cntl1_g = REG(CM_BLNDGAM_RAMB_END_CNTL1_G);
710 gam_regs.start_end_cntl2_g = REG(CM_BLNDGAM_RAMB_END_CNTL2_G);
711 gam_regs.start_end_cntl1_r = REG(CM_BLNDGAM_RAMB_END_CNTL1_R);
712 gam_regs.start_end_cntl2_r = REG(CM_BLNDGAM_RAMB_END_CNTL2_R);
713 gam_regs.region_start = REG(CM_BLNDGAM_RAMB_REGION_0_1);
714 gam_regs.region_end = REG(CM_BLNDGAM_RAMB_REGION_32_33);
715
716 cm_helper_program_gamcor_xfer_func(dpp->base.ctx, params, &gam_regs);
717 }
718
dpp3_get_blndgam_current(struct dpp * dpp_base)719 static enum dc_lut_mode dpp3_get_blndgam_current(struct dpp *dpp_base)
720 {
721 enum dc_lut_mode mode;
722 uint32_t mode_current = 0;
723 uint32_t in_use = 0;
724
725 struct dcn3_dpp *dpp = TO_DCN30_DPP(dpp_base);
726
727 REG_GET(CM_BLNDGAM_CONTROL, CM_BLNDGAM_MODE_CURRENT, &mode_current);
728 REG_GET(CM_BLNDGAM_CONTROL, CM_BLNDGAM_SELECT_CURRENT, &in_use);
729
730 switch (mode_current) {
731 case 0:
732 case 1:
733 mode = LUT_BYPASS;
734 break;
735
736 case 2:
737 if (in_use == 0)
738 mode = LUT_RAM_A;
739 else
740 mode = LUT_RAM_B;
741 break;
742 default:
743 mode = LUT_BYPASS;
744 break;
745 }
746
747 return mode;
748 }
749
dpp3_program_blnd_lut(struct dpp * dpp_base,const struct pwl_params * params)750 static bool dpp3_program_blnd_lut(struct dpp *dpp_base,
751 const struct pwl_params *params)
752 {
753 enum dc_lut_mode current_mode;
754 enum dc_lut_mode next_mode;
755 struct dcn3_dpp *dpp = TO_DCN30_DPP(dpp_base);
756
757 if (params == NULL) {
758 REG_SET(CM_BLNDGAM_CONTROL, 0, CM_BLNDGAM_MODE, 0);
759 if (dpp_base->ctx->dc->debug.enable_mem_low_power.bits.cm)
760 dpp3_power_on_blnd_lut(dpp_base, false);
761 return false;
762 }
763
764 current_mode = dpp3_get_blndgam_current(dpp_base);
765 if (current_mode == LUT_BYPASS || current_mode == LUT_RAM_B)
766 next_mode = LUT_RAM_A;
767 else
768 next_mode = LUT_RAM_B;
769
770 dpp3_power_on_blnd_lut(dpp_base, true);
771 dpp3_configure_blnd_lut(dpp_base, next_mode == LUT_RAM_A);
772
773 if (next_mode == LUT_RAM_A)
774 dpp3_program_blnd_luta_settings(dpp_base, params);
775 else
776 dpp3_program_blnd_lutb_settings(dpp_base, params);
777
778 dpp3_program_blnd_pwl(
779 dpp_base, params->rgb_resulted, params->hw_points_num);
780
781 REG_UPDATE_2(CM_BLNDGAM_CONTROL,
782 CM_BLNDGAM_MODE, 2,
783 CM_BLNDGAM_SELECT, next_mode == LUT_RAM_A ? 0 : 1);
784
785 return true;
786 }
787
788
dpp3_program_shaper_lut(struct dpp * dpp_base,const struct pwl_result_data * rgb,uint32_t num)789 static void dpp3_program_shaper_lut(
790 struct dpp *dpp_base,
791 const struct pwl_result_data *rgb,
792 uint32_t num)
793 {
794 uint32_t i, red, green, blue;
795 uint32_t red_delta, green_delta, blue_delta;
796 uint32_t red_value, green_value, blue_value;
797
798 struct dcn3_dpp *dpp = TO_DCN30_DPP(dpp_base);
799
800 for (i = 0 ; i < num; i++) {
801
802 red = rgb[i].red_reg;
803 green = rgb[i].green_reg;
804 blue = rgb[i].blue_reg;
805
806 red_delta = rgb[i].delta_red_reg;
807 green_delta = rgb[i].delta_green_reg;
808 blue_delta = rgb[i].delta_blue_reg;
809
810 red_value = ((red_delta & 0x3ff) << 14) | (red & 0x3fff);
811 green_value = ((green_delta & 0x3ff) << 14) | (green & 0x3fff);
812 blue_value = ((blue_delta & 0x3ff) << 14) | (blue & 0x3fff);
813
814 REG_SET(CM_SHAPER_LUT_DATA, 0, CM_SHAPER_LUT_DATA, red_value);
815 REG_SET(CM_SHAPER_LUT_DATA, 0, CM_SHAPER_LUT_DATA, green_value);
816 REG_SET(CM_SHAPER_LUT_DATA, 0, CM_SHAPER_LUT_DATA, blue_value);
817 }
818
819 }
820
dpp3_get_shaper_current(struct dpp * dpp_base)821 static enum dc_lut_mode dpp3_get_shaper_current(struct dpp *dpp_base)
822 {
823 enum dc_lut_mode mode;
824 uint32_t state_mode;
825 struct dcn3_dpp *dpp = TO_DCN30_DPP(dpp_base);
826
827 REG_GET(CM_SHAPER_CONTROL, CM_SHAPER_MODE_CURRENT, &state_mode);
828
829 switch (state_mode) {
830 case 0:
831 mode = LUT_BYPASS;
832 break;
833 case 1:
834 mode = LUT_RAM_A;
835 break;
836 case 2:
837 mode = LUT_RAM_B;
838 break;
839 default:
840 mode = LUT_BYPASS;
841 break;
842 }
843
844 return mode;
845 }
846
dpp3_configure_shaper_lut(struct dpp * dpp_base,bool is_ram_a)847 static void dpp3_configure_shaper_lut(
848 struct dpp *dpp_base,
849 bool is_ram_a)
850 {
851 struct dcn3_dpp *dpp = TO_DCN30_DPP(dpp_base);
852
853 REG_UPDATE(CM_SHAPER_LUT_WRITE_EN_MASK,
854 CM_SHAPER_LUT_WRITE_EN_MASK, 7);
855 REG_UPDATE(CM_SHAPER_LUT_WRITE_EN_MASK,
856 CM_SHAPER_LUT_WRITE_SEL, is_ram_a == true ? 0:1);
857 REG_SET(CM_SHAPER_LUT_INDEX, 0, CM_SHAPER_LUT_INDEX, 0);
858 }
859
860 /*program shaper RAM A*/
861
dpp3_program_shaper_luta_settings(struct dpp * dpp_base,const struct pwl_params * params)862 static void dpp3_program_shaper_luta_settings(
863 struct dpp *dpp_base,
864 const struct pwl_params *params)
865 {
866 const struct gamma_curve *curve;
867 struct dcn3_dpp *dpp = TO_DCN30_DPP(dpp_base);
868
869 REG_SET_2(CM_SHAPER_RAMA_START_CNTL_B, 0,
870 CM_SHAPER_RAMA_EXP_REGION_START_B, params->corner_points[0].blue.custom_float_x,
871 CM_SHAPER_RAMA_EXP_REGION_START_SEGMENT_B, 0);
872 REG_SET_2(CM_SHAPER_RAMA_START_CNTL_G, 0,
873 CM_SHAPER_RAMA_EXP_REGION_START_G, params->corner_points[0].green.custom_float_x,
874 CM_SHAPER_RAMA_EXP_REGION_START_SEGMENT_G, 0);
875 REG_SET_2(CM_SHAPER_RAMA_START_CNTL_R, 0,
876 CM_SHAPER_RAMA_EXP_REGION_START_R, params->corner_points[0].red.custom_float_x,
877 CM_SHAPER_RAMA_EXP_REGION_START_SEGMENT_R, 0);
878
879 REG_SET_2(CM_SHAPER_RAMA_END_CNTL_B, 0,
880 CM_SHAPER_RAMA_EXP_REGION_END_B, params->corner_points[1].blue.custom_float_x,
881 CM_SHAPER_RAMA_EXP_REGION_END_BASE_B, params->corner_points[1].blue.custom_float_y);
882
883 REG_SET_2(CM_SHAPER_RAMA_END_CNTL_G, 0,
884 CM_SHAPER_RAMA_EXP_REGION_END_G, params->corner_points[1].green.custom_float_x,
885 CM_SHAPER_RAMA_EXP_REGION_END_BASE_G, params->corner_points[1].green.custom_float_y);
886
887 REG_SET_2(CM_SHAPER_RAMA_END_CNTL_R, 0,
888 CM_SHAPER_RAMA_EXP_REGION_END_R, params->corner_points[1].red.custom_float_x,
889 CM_SHAPER_RAMA_EXP_REGION_END_BASE_R, params->corner_points[1].red.custom_float_y);
890
891 curve = params->arr_curve_points;
892 REG_SET_4(CM_SHAPER_RAMA_REGION_0_1, 0,
893 CM_SHAPER_RAMA_EXP_REGION0_LUT_OFFSET, curve[0].offset,
894 CM_SHAPER_RAMA_EXP_REGION0_NUM_SEGMENTS, curve[0].segments_num,
895 CM_SHAPER_RAMA_EXP_REGION1_LUT_OFFSET, curve[1].offset,
896 CM_SHAPER_RAMA_EXP_REGION1_NUM_SEGMENTS, curve[1].segments_num);
897
898 curve += 2;
899 REG_SET_4(CM_SHAPER_RAMA_REGION_2_3, 0,
900 CM_SHAPER_RAMA_EXP_REGION2_LUT_OFFSET, curve[0].offset,
901 CM_SHAPER_RAMA_EXP_REGION2_NUM_SEGMENTS, curve[0].segments_num,
902 CM_SHAPER_RAMA_EXP_REGION3_LUT_OFFSET, curve[1].offset,
903 CM_SHAPER_RAMA_EXP_REGION3_NUM_SEGMENTS, curve[1].segments_num);
904
905 curve += 2;
906 REG_SET_4(CM_SHAPER_RAMA_REGION_4_5, 0,
907 CM_SHAPER_RAMA_EXP_REGION4_LUT_OFFSET, curve[0].offset,
908 CM_SHAPER_RAMA_EXP_REGION4_NUM_SEGMENTS, curve[0].segments_num,
909 CM_SHAPER_RAMA_EXP_REGION5_LUT_OFFSET, curve[1].offset,
910 CM_SHAPER_RAMA_EXP_REGION5_NUM_SEGMENTS, curve[1].segments_num);
911
912 curve += 2;
913 REG_SET_4(CM_SHAPER_RAMA_REGION_6_7, 0,
914 CM_SHAPER_RAMA_EXP_REGION6_LUT_OFFSET, curve[0].offset,
915 CM_SHAPER_RAMA_EXP_REGION6_NUM_SEGMENTS, curve[0].segments_num,
916 CM_SHAPER_RAMA_EXP_REGION7_LUT_OFFSET, curve[1].offset,
917 CM_SHAPER_RAMA_EXP_REGION7_NUM_SEGMENTS, curve[1].segments_num);
918
919 curve += 2;
920 REG_SET_4(CM_SHAPER_RAMA_REGION_8_9, 0,
921 CM_SHAPER_RAMA_EXP_REGION8_LUT_OFFSET, curve[0].offset,
922 CM_SHAPER_RAMA_EXP_REGION8_NUM_SEGMENTS, curve[0].segments_num,
923 CM_SHAPER_RAMA_EXP_REGION9_LUT_OFFSET, curve[1].offset,
924 CM_SHAPER_RAMA_EXP_REGION9_NUM_SEGMENTS, curve[1].segments_num);
925
926 curve += 2;
927 REG_SET_4(CM_SHAPER_RAMA_REGION_10_11, 0,
928 CM_SHAPER_RAMA_EXP_REGION10_LUT_OFFSET, curve[0].offset,
929 CM_SHAPER_RAMA_EXP_REGION10_NUM_SEGMENTS, curve[0].segments_num,
930 CM_SHAPER_RAMA_EXP_REGION11_LUT_OFFSET, curve[1].offset,
931 CM_SHAPER_RAMA_EXP_REGION11_NUM_SEGMENTS, curve[1].segments_num);
932
933 curve += 2;
934 REG_SET_4(CM_SHAPER_RAMA_REGION_12_13, 0,
935 CM_SHAPER_RAMA_EXP_REGION12_LUT_OFFSET, curve[0].offset,
936 CM_SHAPER_RAMA_EXP_REGION12_NUM_SEGMENTS, curve[0].segments_num,
937 CM_SHAPER_RAMA_EXP_REGION13_LUT_OFFSET, curve[1].offset,
938 CM_SHAPER_RAMA_EXP_REGION13_NUM_SEGMENTS, curve[1].segments_num);
939
940 curve += 2;
941 REG_SET_4(CM_SHAPER_RAMA_REGION_14_15, 0,
942 CM_SHAPER_RAMA_EXP_REGION14_LUT_OFFSET, curve[0].offset,
943 CM_SHAPER_RAMA_EXP_REGION14_NUM_SEGMENTS, curve[0].segments_num,
944 CM_SHAPER_RAMA_EXP_REGION15_LUT_OFFSET, curve[1].offset,
945 CM_SHAPER_RAMA_EXP_REGION15_NUM_SEGMENTS, curve[1].segments_num);
946
947 curve += 2;
948 REG_SET_4(CM_SHAPER_RAMA_REGION_16_17, 0,
949 CM_SHAPER_RAMA_EXP_REGION16_LUT_OFFSET, curve[0].offset,
950 CM_SHAPER_RAMA_EXP_REGION16_NUM_SEGMENTS, curve[0].segments_num,
951 CM_SHAPER_RAMA_EXP_REGION17_LUT_OFFSET, curve[1].offset,
952 CM_SHAPER_RAMA_EXP_REGION17_NUM_SEGMENTS, curve[1].segments_num);
953
954 curve += 2;
955 REG_SET_4(CM_SHAPER_RAMA_REGION_18_19, 0,
956 CM_SHAPER_RAMA_EXP_REGION18_LUT_OFFSET, curve[0].offset,
957 CM_SHAPER_RAMA_EXP_REGION18_NUM_SEGMENTS, curve[0].segments_num,
958 CM_SHAPER_RAMA_EXP_REGION19_LUT_OFFSET, curve[1].offset,
959 CM_SHAPER_RAMA_EXP_REGION19_NUM_SEGMENTS, curve[1].segments_num);
960
961 curve += 2;
962 REG_SET_4(CM_SHAPER_RAMA_REGION_20_21, 0,
963 CM_SHAPER_RAMA_EXP_REGION20_LUT_OFFSET, curve[0].offset,
964 CM_SHAPER_RAMA_EXP_REGION20_NUM_SEGMENTS, curve[0].segments_num,
965 CM_SHAPER_RAMA_EXP_REGION21_LUT_OFFSET, curve[1].offset,
966 CM_SHAPER_RAMA_EXP_REGION21_NUM_SEGMENTS, curve[1].segments_num);
967
968 curve += 2;
969 REG_SET_4(CM_SHAPER_RAMA_REGION_22_23, 0,
970 CM_SHAPER_RAMA_EXP_REGION22_LUT_OFFSET, curve[0].offset,
971 CM_SHAPER_RAMA_EXP_REGION22_NUM_SEGMENTS, curve[0].segments_num,
972 CM_SHAPER_RAMA_EXP_REGION23_LUT_OFFSET, curve[1].offset,
973 CM_SHAPER_RAMA_EXP_REGION23_NUM_SEGMENTS, curve[1].segments_num);
974
975 curve += 2;
976 REG_SET_4(CM_SHAPER_RAMA_REGION_24_25, 0,
977 CM_SHAPER_RAMA_EXP_REGION24_LUT_OFFSET, curve[0].offset,
978 CM_SHAPER_RAMA_EXP_REGION24_NUM_SEGMENTS, curve[0].segments_num,
979 CM_SHAPER_RAMA_EXP_REGION25_LUT_OFFSET, curve[1].offset,
980 CM_SHAPER_RAMA_EXP_REGION25_NUM_SEGMENTS, curve[1].segments_num);
981
982 curve += 2;
983 REG_SET_4(CM_SHAPER_RAMA_REGION_26_27, 0,
984 CM_SHAPER_RAMA_EXP_REGION26_LUT_OFFSET, curve[0].offset,
985 CM_SHAPER_RAMA_EXP_REGION26_NUM_SEGMENTS, curve[0].segments_num,
986 CM_SHAPER_RAMA_EXP_REGION27_LUT_OFFSET, curve[1].offset,
987 CM_SHAPER_RAMA_EXP_REGION27_NUM_SEGMENTS, curve[1].segments_num);
988
989 curve += 2;
990 REG_SET_4(CM_SHAPER_RAMA_REGION_28_29, 0,
991 CM_SHAPER_RAMA_EXP_REGION28_LUT_OFFSET, curve[0].offset,
992 CM_SHAPER_RAMA_EXP_REGION28_NUM_SEGMENTS, curve[0].segments_num,
993 CM_SHAPER_RAMA_EXP_REGION29_LUT_OFFSET, curve[1].offset,
994 CM_SHAPER_RAMA_EXP_REGION29_NUM_SEGMENTS, curve[1].segments_num);
995
996 curve += 2;
997 REG_SET_4(CM_SHAPER_RAMA_REGION_30_31, 0,
998 CM_SHAPER_RAMA_EXP_REGION30_LUT_OFFSET, curve[0].offset,
999 CM_SHAPER_RAMA_EXP_REGION30_NUM_SEGMENTS, curve[0].segments_num,
1000 CM_SHAPER_RAMA_EXP_REGION31_LUT_OFFSET, curve[1].offset,
1001 CM_SHAPER_RAMA_EXP_REGION31_NUM_SEGMENTS, curve[1].segments_num);
1002
1003 curve += 2;
1004 REG_SET_4(CM_SHAPER_RAMA_REGION_32_33, 0,
1005 CM_SHAPER_RAMA_EXP_REGION32_LUT_OFFSET, curve[0].offset,
1006 CM_SHAPER_RAMA_EXP_REGION32_NUM_SEGMENTS, curve[0].segments_num,
1007 CM_SHAPER_RAMA_EXP_REGION33_LUT_OFFSET, curve[1].offset,
1008 CM_SHAPER_RAMA_EXP_REGION33_NUM_SEGMENTS, curve[1].segments_num);
1009 }
1010
1011 /*program shaper RAM B*/
dpp3_program_shaper_lutb_settings(struct dpp * dpp_base,const struct pwl_params * params)1012 static void dpp3_program_shaper_lutb_settings(
1013 struct dpp *dpp_base,
1014 const struct pwl_params *params)
1015 {
1016 const struct gamma_curve *curve;
1017 struct dcn3_dpp *dpp = TO_DCN30_DPP(dpp_base);
1018
1019 REG_SET_2(CM_SHAPER_RAMB_START_CNTL_B, 0,
1020 CM_SHAPER_RAMB_EXP_REGION_START_B, params->corner_points[0].blue.custom_float_x,
1021 CM_SHAPER_RAMB_EXP_REGION_START_SEGMENT_B, 0);
1022 REG_SET_2(CM_SHAPER_RAMB_START_CNTL_G, 0,
1023 CM_SHAPER_RAMB_EXP_REGION_START_G, params->corner_points[0].green.custom_float_x,
1024 CM_SHAPER_RAMB_EXP_REGION_START_SEGMENT_G, 0);
1025 REG_SET_2(CM_SHAPER_RAMB_START_CNTL_R, 0,
1026 CM_SHAPER_RAMB_EXP_REGION_START_R, params->corner_points[0].red.custom_float_x,
1027 CM_SHAPER_RAMB_EXP_REGION_START_SEGMENT_R, 0);
1028
1029 REG_SET_2(CM_SHAPER_RAMB_END_CNTL_B, 0,
1030 CM_SHAPER_RAMB_EXP_REGION_END_B, params->corner_points[1].blue.custom_float_x,
1031 CM_SHAPER_RAMB_EXP_REGION_END_BASE_B, params->corner_points[1].blue.custom_float_y);
1032
1033 REG_SET_2(CM_SHAPER_RAMB_END_CNTL_G, 0,
1034 CM_SHAPER_RAMB_EXP_REGION_END_G, params->corner_points[1].green.custom_float_x,
1035 CM_SHAPER_RAMB_EXP_REGION_END_BASE_G, params->corner_points[1].green.custom_float_y);
1036
1037 REG_SET_2(CM_SHAPER_RAMB_END_CNTL_R, 0,
1038 CM_SHAPER_RAMB_EXP_REGION_END_R, params->corner_points[1].red.custom_float_x,
1039 CM_SHAPER_RAMB_EXP_REGION_END_BASE_R, params->corner_points[1].red.custom_float_y);
1040
1041 curve = params->arr_curve_points;
1042 REG_SET_4(CM_SHAPER_RAMB_REGION_0_1, 0,
1043 CM_SHAPER_RAMB_EXP_REGION0_LUT_OFFSET, curve[0].offset,
1044 CM_SHAPER_RAMB_EXP_REGION0_NUM_SEGMENTS, curve[0].segments_num,
1045 CM_SHAPER_RAMB_EXP_REGION1_LUT_OFFSET, curve[1].offset,
1046 CM_SHAPER_RAMB_EXP_REGION1_NUM_SEGMENTS, curve[1].segments_num);
1047
1048 curve += 2;
1049 REG_SET_4(CM_SHAPER_RAMB_REGION_2_3, 0,
1050 CM_SHAPER_RAMB_EXP_REGION2_LUT_OFFSET, curve[0].offset,
1051 CM_SHAPER_RAMB_EXP_REGION2_NUM_SEGMENTS, curve[0].segments_num,
1052 CM_SHAPER_RAMB_EXP_REGION3_LUT_OFFSET, curve[1].offset,
1053 CM_SHAPER_RAMB_EXP_REGION3_NUM_SEGMENTS, curve[1].segments_num);
1054
1055 curve += 2;
1056 REG_SET_4(CM_SHAPER_RAMB_REGION_4_5, 0,
1057 CM_SHAPER_RAMB_EXP_REGION4_LUT_OFFSET, curve[0].offset,
1058 CM_SHAPER_RAMB_EXP_REGION4_NUM_SEGMENTS, curve[0].segments_num,
1059 CM_SHAPER_RAMB_EXP_REGION5_LUT_OFFSET, curve[1].offset,
1060 CM_SHAPER_RAMB_EXP_REGION5_NUM_SEGMENTS, curve[1].segments_num);
1061
1062 curve += 2;
1063 REG_SET_4(CM_SHAPER_RAMB_REGION_6_7, 0,
1064 CM_SHAPER_RAMB_EXP_REGION6_LUT_OFFSET, curve[0].offset,
1065 CM_SHAPER_RAMB_EXP_REGION6_NUM_SEGMENTS, curve[0].segments_num,
1066 CM_SHAPER_RAMB_EXP_REGION7_LUT_OFFSET, curve[1].offset,
1067 CM_SHAPER_RAMB_EXP_REGION7_NUM_SEGMENTS, curve[1].segments_num);
1068
1069 curve += 2;
1070 REG_SET_4(CM_SHAPER_RAMB_REGION_8_9, 0,
1071 CM_SHAPER_RAMB_EXP_REGION8_LUT_OFFSET, curve[0].offset,
1072 CM_SHAPER_RAMB_EXP_REGION8_NUM_SEGMENTS, curve[0].segments_num,
1073 CM_SHAPER_RAMB_EXP_REGION9_LUT_OFFSET, curve[1].offset,
1074 CM_SHAPER_RAMB_EXP_REGION9_NUM_SEGMENTS, curve[1].segments_num);
1075
1076 curve += 2;
1077 REG_SET_4(CM_SHAPER_RAMB_REGION_10_11, 0,
1078 CM_SHAPER_RAMB_EXP_REGION10_LUT_OFFSET, curve[0].offset,
1079 CM_SHAPER_RAMB_EXP_REGION10_NUM_SEGMENTS, curve[0].segments_num,
1080 CM_SHAPER_RAMB_EXP_REGION11_LUT_OFFSET, curve[1].offset,
1081 CM_SHAPER_RAMB_EXP_REGION11_NUM_SEGMENTS, curve[1].segments_num);
1082
1083 curve += 2;
1084 REG_SET_4(CM_SHAPER_RAMB_REGION_12_13, 0,
1085 CM_SHAPER_RAMB_EXP_REGION12_LUT_OFFSET, curve[0].offset,
1086 CM_SHAPER_RAMB_EXP_REGION12_NUM_SEGMENTS, curve[0].segments_num,
1087 CM_SHAPER_RAMB_EXP_REGION13_LUT_OFFSET, curve[1].offset,
1088 CM_SHAPER_RAMB_EXP_REGION13_NUM_SEGMENTS, curve[1].segments_num);
1089
1090 curve += 2;
1091 REG_SET_4(CM_SHAPER_RAMB_REGION_14_15, 0,
1092 CM_SHAPER_RAMB_EXP_REGION14_LUT_OFFSET, curve[0].offset,
1093 CM_SHAPER_RAMB_EXP_REGION14_NUM_SEGMENTS, curve[0].segments_num,
1094 CM_SHAPER_RAMB_EXP_REGION15_LUT_OFFSET, curve[1].offset,
1095 CM_SHAPER_RAMB_EXP_REGION15_NUM_SEGMENTS, curve[1].segments_num);
1096
1097 curve += 2;
1098 REG_SET_4(CM_SHAPER_RAMB_REGION_16_17, 0,
1099 CM_SHAPER_RAMB_EXP_REGION16_LUT_OFFSET, curve[0].offset,
1100 CM_SHAPER_RAMB_EXP_REGION16_NUM_SEGMENTS, curve[0].segments_num,
1101 CM_SHAPER_RAMB_EXP_REGION17_LUT_OFFSET, curve[1].offset,
1102 CM_SHAPER_RAMB_EXP_REGION17_NUM_SEGMENTS, curve[1].segments_num);
1103
1104 curve += 2;
1105 REG_SET_4(CM_SHAPER_RAMB_REGION_18_19, 0,
1106 CM_SHAPER_RAMB_EXP_REGION18_LUT_OFFSET, curve[0].offset,
1107 CM_SHAPER_RAMB_EXP_REGION18_NUM_SEGMENTS, curve[0].segments_num,
1108 CM_SHAPER_RAMB_EXP_REGION19_LUT_OFFSET, curve[1].offset,
1109 CM_SHAPER_RAMB_EXP_REGION19_NUM_SEGMENTS, curve[1].segments_num);
1110
1111 curve += 2;
1112 REG_SET_4(CM_SHAPER_RAMB_REGION_20_21, 0,
1113 CM_SHAPER_RAMB_EXP_REGION20_LUT_OFFSET, curve[0].offset,
1114 CM_SHAPER_RAMB_EXP_REGION20_NUM_SEGMENTS, curve[0].segments_num,
1115 CM_SHAPER_RAMB_EXP_REGION21_LUT_OFFSET, curve[1].offset,
1116 CM_SHAPER_RAMB_EXP_REGION21_NUM_SEGMENTS, curve[1].segments_num);
1117
1118 curve += 2;
1119 REG_SET_4(CM_SHAPER_RAMB_REGION_22_23, 0,
1120 CM_SHAPER_RAMB_EXP_REGION22_LUT_OFFSET, curve[0].offset,
1121 CM_SHAPER_RAMB_EXP_REGION22_NUM_SEGMENTS, curve[0].segments_num,
1122 CM_SHAPER_RAMB_EXP_REGION23_LUT_OFFSET, curve[1].offset,
1123 CM_SHAPER_RAMB_EXP_REGION23_NUM_SEGMENTS, curve[1].segments_num);
1124
1125 curve += 2;
1126 REG_SET_4(CM_SHAPER_RAMB_REGION_24_25, 0,
1127 CM_SHAPER_RAMB_EXP_REGION24_LUT_OFFSET, curve[0].offset,
1128 CM_SHAPER_RAMB_EXP_REGION24_NUM_SEGMENTS, curve[0].segments_num,
1129 CM_SHAPER_RAMB_EXP_REGION25_LUT_OFFSET, curve[1].offset,
1130 CM_SHAPER_RAMB_EXP_REGION25_NUM_SEGMENTS, curve[1].segments_num);
1131
1132 curve += 2;
1133 REG_SET_4(CM_SHAPER_RAMB_REGION_26_27, 0,
1134 CM_SHAPER_RAMB_EXP_REGION26_LUT_OFFSET, curve[0].offset,
1135 CM_SHAPER_RAMB_EXP_REGION26_NUM_SEGMENTS, curve[0].segments_num,
1136 CM_SHAPER_RAMB_EXP_REGION27_LUT_OFFSET, curve[1].offset,
1137 CM_SHAPER_RAMB_EXP_REGION27_NUM_SEGMENTS, curve[1].segments_num);
1138
1139 curve += 2;
1140 REG_SET_4(CM_SHAPER_RAMB_REGION_28_29, 0,
1141 CM_SHAPER_RAMB_EXP_REGION28_LUT_OFFSET, curve[0].offset,
1142 CM_SHAPER_RAMB_EXP_REGION28_NUM_SEGMENTS, curve[0].segments_num,
1143 CM_SHAPER_RAMB_EXP_REGION29_LUT_OFFSET, curve[1].offset,
1144 CM_SHAPER_RAMB_EXP_REGION29_NUM_SEGMENTS, curve[1].segments_num);
1145
1146 curve += 2;
1147 REG_SET_4(CM_SHAPER_RAMB_REGION_30_31, 0,
1148 CM_SHAPER_RAMB_EXP_REGION30_LUT_OFFSET, curve[0].offset,
1149 CM_SHAPER_RAMB_EXP_REGION30_NUM_SEGMENTS, curve[0].segments_num,
1150 CM_SHAPER_RAMB_EXP_REGION31_LUT_OFFSET, curve[1].offset,
1151 CM_SHAPER_RAMB_EXP_REGION31_NUM_SEGMENTS, curve[1].segments_num);
1152
1153 curve += 2;
1154 REG_SET_4(CM_SHAPER_RAMB_REGION_32_33, 0,
1155 CM_SHAPER_RAMB_EXP_REGION32_LUT_OFFSET, curve[0].offset,
1156 CM_SHAPER_RAMB_EXP_REGION32_NUM_SEGMENTS, curve[0].segments_num,
1157 CM_SHAPER_RAMB_EXP_REGION33_LUT_OFFSET, curve[1].offset,
1158 CM_SHAPER_RAMB_EXP_REGION33_NUM_SEGMENTS, curve[1].segments_num);
1159
1160 }
1161
1162
dpp3_program_shaper(struct dpp * dpp_base,const struct pwl_params * params)1163 static bool dpp3_program_shaper(struct dpp *dpp_base,
1164 const struct pwl_params *params)
1165 {
1166 enum dc_lut_mode current_mode;
1167 enum dc_lut_mode next_mode;
1168
1169 struct dcn3_dpp *dpp = TO_DCN30_DPP(dpp_base);
1170
1171 if (params == NULL) {
1172 REG_SET(CM_SHAPER_CONTROL, 0, CM_SHAPER_LUT_MODE, 0);
1173 if (dpp_base->ctx->dc->debug.enable_mem_low_power.bits.cm)
1174 dpp3_power_on_shaper(dpp_base, false);
1175 return false;
1176 }
1177
1178 if (dpp_base->ctx->dc->debug.enable_mem_low_power.bits.cm)
1179 dpp3_power_on_shaper(dpp_base, true);
1180
1181 current_mode = dpp3_get_shaper_current(dpp_base);
1182
1183 if (current_mode == LUT_BYPASS || current_mode == LUT_RAM_A)
1184 next_mode = LUT_RAM_B;
1185 else
1186 next_mode = LUT_RAM_A;
1187
1188 dpp3_configure_shaper_lut(dpp_base, next_mode == LUT_RAM_A);
1189
1190 if (next_mode == LUT_RAM_A)
1191 dpp3_program_shaper_luta_settings(dpp_base, params);
1192 else
1193 dpp3_program_shaper_lutb_settings(dpp_base, params);
1194
1195 dpp3_program_shaper_lut(
1196 dpp_base, params->rgb_resulted, params->hw_points_num);
1197
1198 REG_SET(CM_SHAPER_CONTROL, 0, CM_SHAPER_LUT_MODE, next_mode == LUT_RAM_A ? 1:2);
1199
1200 return true;
1201
1202 }
1203
get3dlut_config(struct dpp * dpp_base,bool * is_17x17x17,bool * is_12bits_color_channel)1204 static enum dc_lut_mode get3dlut_config(
1205 struct dpp *dpp_base,
1206 bool *is_17x17x17,
1207 bool *is_12bits_color_channel)
1208 {
1209 uint32_t i_mode, i_enable_10bits, lut_size;
1210 enum dc_lut_mode mode;
1211 struct dcn3_dpp *dpp = TO_DCN30_DPP(dpp_base);
1212
1213 REG_GET(CM_3DLUT_READ_WRITE_CONTROL,
1214 CM_3DLUT_30BIT_EN, &i_enable_10bits);
1215 REG_GET(CM_3DLUT_MODE,
1216 CM_3DLUT_MODE_CURRENT, &i_mode);
1217
1218 switch (i_mode) {
1219 case 0:
1220 mode = LUT_BYPASS;
1221 break;
1222 case 1:
1223 mode = LUT_RAM_A;
1224 break;
1225 case 2:
1226 mode = LUT_RAM_B;
1227 break;
1228 default:
1229 mode = LUT_BYPASS;
1230 break;
1231 }
1232 if (i_enable_10bits > 0)
1233 *is_12bits_color_channel = false;
1234 else
1235 *is_12bits_color_channel = true;
1236
1237 REG_GET(CM_3DLUT_MODE, CM_3DLUT_SIZE, &lut_size);
1238
1239 if (lut_size == 0)
1240 *is_17x17x17 = true;
1241 else
1242 *is_17x17x17 = false;
1243
1244 return mode;
1245 }
1246 /*
1247 * select ramA or ramB, or bypass
1248 * select color channel size 10 or 12 bits
1249 * select 3dlut size 17x17x17 or 9x9x9
1250 */
dpp3_set_3dlut_mode(struct dpp * dpp_base,enum dc_lut_mode mode,bool is_color_channel_12bits,bool is_lut_size17x17x17)1251 static void dpp3_set_3dlut_mode(
1252 struct dpp *dpp_base,
1253 enum dc_lut_mode mode,
1254 bool is_color_channel_12bits,
1255 bool is_lut_size17x17x17)
1256 {
1257 uint32_t lut_mode;
1258 struct dcn3_dpp *dpp = TO_DCN30_DPP(dpp_base);
1259
1260 if (mode == LUT_BYPASS)
1261 lut_mode = 0;
1262 else if (mode == LUT_RAM_A)
1263 lut_mode = 1;
1264 else
1265 lut_mode = 2;
1266
1267 REG_UPDATE_2(CM_3DLUT_MODE,
1268 CM_3DLUT_MODE, lut_mode,
1269 CM_3DLUT_SIZE, is_lut_size17x17x17 == true ? 0 : 1);
1270 }
1271
dpp3_select_3dlut_ram(struct dpp * dpp_base,enum dc_lut_mode mode,bool is_color_channel_12bits)1272 static void dpp3_select_3dlut_ram(
1273 struct dpp *dpp_base,
1274 enum dc_lut_mode mode,
1275 bool is_color_channel_12bits)
1276 {
1277 struct dcn3_dpp *dpp = TO_DCN30_DPP(dpp_base);
1278
1279 REG_UPDATE_2(CM_3DLUT_READ_WRITE_CONTROL,
1280 CM_3DLUT_RAM_SEL, mode == LUT_RAM_A ? 0 : 1,
1281 CM_3DLUT_30BIT_EN,
1282 is_color_channel_12bits == true ? 0:1);
1283 }
1284
1285
1286
dpp3_set3dlut_ram12(struct dpp * dpp_base,const struct dc_rgb * lut,uint32_t entries)1287 static void dpp3_set3dlut_ram12(
1288 struct dpp *dpp_base,
1289 const struct dc_rgb *lut,
1290 uint32_t entries)
1291 {
1292 uint32_t i, red, green, blue, red1, green1, blue1;
1293 struct dcn3_dpp *dpp = TO_DCN30_DPP(dpp_base);
1294
1295 for (i = 0 ; i < entries; i += 2) {
1296 red = lut[i].red<<4;
1297 green = lut[i].green<<4;
1298 blue = lut[i].blue<<4;
1299 red1 = lut[i+1].red<<4;
1300 green1 = lut[i+1].green<<4;
1301 blue1 = lut[i+1].blue<<4;
1302
1303 REG_SET_2(CM_3DLUT_DATA, 0,
1304 CM_3DLUT_DATA0, red,
1305 CM_3DLUT_DATA1, red1);
1306
1307 REG_SET_2(CM_3DLUT_DATA, 0,
1308 CM_3DLUT_DATA0, green,
1309 CM_3DLUT_DATA1, green1);
1310
1311 REG_SET_2(CM_3DLUT_DATA, 0,
1312 CM_3DLUT_DATA0, blue,
1313 CM_3DLUT_DATA1, blue1);
1314
1315 }
1316 }
1317
1318 /*
1319 * load selected lut with 10 bits color channels
1320 */
dpp3_set3dlut_ram10(struct dpp * dpp_base,const struct dc_rgb * lut,uint32_t entries)1321 static void dpp3_set3dlut_ram10(
1322 struct dpp *dpp_base,
1323 const struct dc_rgb *lut,
1324 uint32_t entries)
1325 {
1326 uint32_t i, red, green, blue, value;
1327 struct dcn3_dpp *dpp = TO_DCN30_DPP(dpp_base);
1328
1329 for (i = 0; i < entries; i++) {
1330 red = lut[i].red;
1331 green = lut[i].green;
1332 blue = lut[i].blue;
1333
1334 value = (red<<20) | (green<<10) | blue;
1335
1336 REG_SET(CM_3DLUT_DATA_30BIT, 0, CM_3DLUT_DATA_30BIT, value);
1337 }
1338
1339 }
1340
1341
dpp3_select_3dlut_ram_mask(struct dpp * dpp_base,uint32_t ram_selection_mask)1342 static void dpp3_select_3dlut_ram_mask(
1343 struct dpp *dpp_base,
1344 uint32_t ram_selection_mask)
1345 {
1346 struct dcn3_dpp *dpp = TO_DCN30_DPP(dpp_base);
1347
1348 REG_UPDATE(CM_3DLUT_READ_WRITE_CONTROL, CM_3DLUT_WRITE_EN_MASK,
1349 ram_selection_mask);
1350 REG_SET(CM_3DLUT_INDEX, 0, CM_3DLUT_INDEX, 0);
1351 }
1352
dpp3_program_3dlut(struct dpp * dpp_base,struct tetrahedral_params * params)1353 static bool dpp3_program_3dlut(struct dpp *dpp_base,
1354 struct tetrahedral_params *params)
1355 {
1356 enum dc_lut_mode mode;
1357 bool is_17x17x17;
1358 bool is_12bits_color_channel;
1359 struct dc_rgb *lut0;
1360 struct dc_rgb *lut1;
1361 struct dc_rgb *lut2;
1362 struct dc_rgb *lut3;
1363 int lut_size0;
1364 int lut_size;
1365
1366 if (params == NULL) {
1367 dpp3_set_3dlut_mode(dpp_base, LUT_BYPASS, false, false);
1368 if (dpp_base->ctx->dc->debug.enable_mem_low_power.bits.cm)
1369 dpp3_power_on_hdr3dlut(dpp_base, false);
1370 return false;
1371 }
1372
1373 if (dpp_base->ctx->dc->debug.enable_mem_low_power.bits.cm)
1374 dpp3_power_on_hdr3dlut(dpp_base, true);
1375
1376 mode = get3dlut_config(dpp_base, &is_17x17x17, &is_12bits_color_channel);
1377
1378 if (mode == LUT_BYPASS || mode == LUT_RAM_B)
1379 mode = LUT_RAM_A;
1380 else
1381 mode = LUT_RAM_B;
1382
1383 is_17x17x17 = !params->use_tetrahedral_9;
1384 is_12bits_color_channel = params->use_12bits;
1385 if (is_17x17x17) {
1386 lut0 = params->tetrahedral_17.lut0;
1387 lut1 = params->tetrahedral_17.lut1;
1388 lut2 = params->tetrahedral_17.lut2;
1389 lut3 = params->tetrahedral_17.lut3;
1390 lut_size0 = sizeof(params->tetrahedral_17.lut0)/
1391 sizeof(params->tetrahedral_17.lut0[0]);
1392 lut_size = sizeof(params->tetrahedral_17.lut1)/
1393 sizeof(params->tetrahedral_17.lut1[0]);
1394 } else {
1395 lut0 = params->tetrahedral_9.lut0;
1396 lut1 = params->tetrahedral_9.lut1;
1397 lut2 = params->tetrahedral_9.lut2;
1398 lut3 = params->tetrahedral_9.lut3;
1399 lut_size0 = sizeof(params->tetrahedral_9.lut0)/
1400 sizeof(params->tetrahedral_9.lut0[0]);
1401 lut_size = sizeof(params->tetrahedral_9.lut1)/
1402 sizeof(params->tetrahedral_9.lut1[0]);
1403 }
1404
1405 dpp3_select_3dlut_ram(dpp_base, mode,
1406 is_12bits_color_channel);
1407 dpp3_select_3dlut_ram_mask(dpp_base, 0x1);
1408 if (is_12bits_color_channel)
1409 dpp3_set3dlut_ram12(dpp_base, lut0, lut_size0);
1410 else
1411 dpp3_set3dlut_ram10(dpp_base, lut0, lut_size0);
1412
1413 dpp3_select_3dlut_ram_mask(dpp_base, 0x2);
1414 if (is_12bits_color_channel)
1415 dpp3_set3dlut_ram12(dpp_base, lut1, lut_size);
1416 else
1417 dpp3_set3dlut_ram10(dpp_base, lut1, lut_size);
1418
1419 dpp3_select_3dlut_ram_mask(dpp_base, 0x4);
1420 if (is_12bits_color_channel)
1421 dpp3_set3dlut_ram12(dpp_base, lut2, lut_size);
1422 else
1423 dpp3_set3dlut_ram10(dpp_base, lut2, lut_size);
1424
1425 dpp3_select_3dlut_ram_mask(dpp_base, 0x8);
1426 if (is_12bits_color_channel)
1427 dpp3_set3dlut_ram12(dpp_base, lut3, lut_size);
1428 else
1429 dpp3_set3dlut_ram10(dpp_base, lut3, lut_size);
1430
1431
1432 dpp3_set_3dlut_mode(dpp_base, mode, is_12bits_color_channel,
1433 is_17x17x17);
1434
1435 return true;
1436 }
1437 static struct dpp_funcs dcn30_dpp_funcs = {
1438 .dpp_program_gamcor_lut = dpp3_program_gamcor_lut,
1439 .dpp_read_state = dpp30_read_state,
1440 .dpp_reset = dpp_reset,
1441 .dpp_set_scaler = dpp1_dscl_set_scaler_manual_scale,
1442 .dpp_get_optimal_number_of_taps = dpp3_get_optimal_number_of_taps,
1443 .dpp_set_gamut_remap = dpp3_cm_set_gamut_remap,
1444 .dpp_set_csc_adjustment = NULL,
1445 .dpp_set_csc_default = NULL,
1446 .dpp_program_regamma_pwl = NULL,
1447 .dpp_set_pre_degam = dpp3_set_pre_degam,
1448 .dpp_program_input_lut = NULL,
1449 .dpp_full_bypass = dpp1_full_bypass,
1450 .dpp_setup = dpp3_cnv_setup,
1451 .dpp_program_degamma_pwl = NULL,
1452 .dpp_program_cm_dealpha = dpp3_program_cm_dealpha,
1453 .dpp_program_cm_bias = dpp3_program_cm_bias,
1454 .dpp_program_blnd_lut = dpp3_program_blnd_lut,
1455 .dpp_program_shaper_lut = dpp3_program_shaper,
1456 .dpp_program_3dlut = dpp3_program_3dlut,
1457 .dpp_deferred_update = dpp3_deferred_update,
1458 .dpp_program_bias_and_scale = NULL,
1459 .dpp_cnv_set_alpha_keyer = dpp2_cnv_set_alpha_keyer,
1460 .set_cursor_attributes = dpp3_set_cursor_attributes,
1461 .set_cursor_position = dpp1_set_cursor_position,
1462 .set_optional_cursor_attributes = dpp1_cnv_set_optional_cursor_attributes,
1463 .dpp_dppclk_control = dpp1_dppclk_control,
1464 .dpp_set_hdr_multiplier = dpp3_set_hdr_multiplier,
1465 };
1466
1467
1468 static struct dpp_caps dcn30_dpp_cap = {
1469 .dscl_data_proc_format = DSCL_DATA_PRCESSING_FLOAT_FORMAT,
1470 .dscl_calc_lb_num_partitions = dscl2_calc_lb_num_partitions,
1471 };
1472
dpp3_construct(struct dcn3_dpp * dpp,struct dc_context * ctx,uint32_t inst,const struct dcn3_dpp_registers * tf_regs,const struct dcn3_dpp_shift * tf_shift,const struct dcn3_dpp_mask * tf_mask)1473 bool dpp3_construct(
1474 struct dcn3_dpp *dpp,
1475 struct dc_context *ctx,
1476 uint32_t inst,
1477 const struct dcn3_dpp_registers *tf_regs,
1478 const struct dcn3_dpp_shift *tf_shift,
1479 const struct dcn3_dpp_mask *tf_mask)
1480 {
1481 dpp->base.ctx = ctx;
1482
1483 dpp->base.inst = inst;
1484 dpp->base.funcs = &dcn30_dpp_funcs;
1485 dpp->base.caps = &dcn30_dpp_cap;
1486
1487 dpp->tf_regs = tf_regs;
1488 dpp->tf_shift = tf_shift;
1489 dpp->tf_mask = tf_mask;
1490
1491 return true;
1492 }
1493
1494