1 // SPDX-License-Identifier: GPL-2.0
2 /*
3 * PCI Express Downstream Port Containment services driver
4 * Author: Keith Busch <keith.busch@intel.com>
5 *
6 * Copyright (C) 2016 Intel Corp.
7 */
8
9 #define dev_fmt(fmt) "DPC: " fmt
10
11 #include <linux/aer.h>
12 #include <linux/bitfield.h>
13 #include <linux/delay.h>
14 #include <linux/interrupt.h>
15 #include <linux/init.h>
16 #include <linux/pci.h>
17
18 #include "portdrv.h"
19 #include "../pci.h"
20
21 #define PCI_EXP_DPC_CTL_EN_MASK (PCI_EXP_DPC_CTL_EN_FATAL | \
22 PCI_EXP_DPC_CTL_EN_NONFATAL)
23
24 static const char * const rp_pio_error_string[] = {
25 "Configuration Request received UR Completion", /* Bit Position 0 */
26 "Configuration Request received CA Completion", /* Bit Position 1 */
27 "Configuration Request Completion Timeout", /* Bit Position 2 */
28 NULL,
29 NULL,
30 NULL,
31 NULL,
32 NULL,
33 "I/O Request received UR Completion", /* Bit Position 8 */
34 "I/O Request received CA Completion", /* Bit Position 9 */
35 "I/O Request Completion Timeout", /* Bit Position 10 */
36 NULL,
37 NULL,
38 NULL,
39 NULL,
40 NULL,
41 "Memory Request received UR Completion", /* Bit Position 16 */
42 "Memory Request received CA Completion", /* Bit Position 17 */
43 "Memory Request Completion Timeout", /* Bit Position 18 */
44 };
45
pci_save_dpc_state(struct pci_dev * dev)46 void pci_save_dpc_state(struct pci_dev *dev)
47 {
48 struct pci_cap_saved_state *save_state;
49 u16 *cap;
50
51 if (!pci_is_pcie(dev))
52 return;
53
54 save_state = pci_find_saved_ext_cap(dev, PCI_EXT_CAP_ID_DPC);
55 if (!save_state)
56 return;
57
58 cap = (u16 *)&save_state->cap.data[0];
59 pci_read_config_word(dev, dev->dpc_cap + PCI_EXP_DPC_CTL, cap);
60 }
61
pci_restore_dpc_state(struct pci_dev * dev)62 void pci_restore_dpc_state(struct pci_dev *dev)
63 {
64 struct pci_cap_saved_state *save_state;
65 u16 *cap;
66
67 if (!pci_is_pcie(dev))
68 return;
69
70 save_state = pci_find_saved_ext_cap(dev, PCI_EXT_CAP_ID_DPC);
71 if (!save_state)
72 return;
73
74 cap = (u16 *)&save_state->cap.data[0];
75 pci_write_config_word(dev, dev->dpc_cap + PCI_EXP_DPC_CTL, *cap);
76 }
77
78 static DECLARE_WAIT_QUEUE_HEAD(dpc_completed_waitqueue);
79
80 #ifdef CONFIG_HOTPLUG_PCI_PCIE
dpc_completed(struct pci_dev * pdev)81 static bool dpc_completed(struct pci_dev *pdev)
82 {
83 u16 status;
84
85 pci_read_config_word(pdev, pdev->dpc_cap + PCI_EXP_DPC_STATUS, &status);
86 if ((!PCI_POSSIBLE_ERROR(status)) && (status & PCI_EXP_DPC_STATUS_TRIGGER))
87 return false;
88
89 if (test_bit(PCI_DPC_RECOVERING, &pdev->priv_flags))
90 return false;
91
92 return true;
93 }
94
95 /**
96 * pci_dpc_recovered - whether DPC triggered and has recovered successfully
97 * @pdev: PCI device
98 *
99 * Return true if DPC was triggered for @pdev and has recovered successfully.
100 * Wait for recovery if it hasn't completed yet. Called from the PCIe hotplug
101 * driver to recognize and ignore Link Down/Up events caused by DPC.
102 */
pci_dpc_recovered(struct pci_dev * pdev)103 bool pci_dpc_recovered(struct pci_dev *pdev)
104 {
105 struct pci_host_bridge *host;
106
107 if (!pdev->dpc_cap)
108 return false;
109
110 /*
111 * Synchronization between hotplug and DPC is not supported
112 * if DPC is owned by firmware and EDR is not enabled.
113 */
114 host = pci_find_host_bridge(pdev->bus);
115 if (!host->native_dpc && !IS_ENABLED(CONFIG_PCIE_EDR))
116 return false;
117
118 /*
119 * Need a timeout in case DPC never completes due to failure of
120 * dpc_wait_rp_inactive(). The spec doesn't mandate a time limit,
121 * but reports indicate that DPC completes within 4 seconds.
122 */
123 wait_event_timeout(dpc_completed_waitqueue, dpc_completed(pdev),
124 msecs_to_jiffies(4000));
125
126 return test_and_clear_bit(PCI_DPC_RECOVERED, &pdev->priv_flags);
127 }
128 #endif /* CONFIG_HOTPLUG_PCI_PCIE */
129
dpc_wait_rp_inactive(struct pci_dev * pdev)130 static int dpc_wait_rp_inactive(struct pci_dev *pdev)
131 {
132 unsigned long timeout = jiffies + HZ;
133 u16 cap = pdev->dpc_cap, status;
134
135 pci_read_config_word(pdev, cap + PCI_EXP_DPC_STATUS, &status);
136 while (status & PCI_EXP_DPC_RP_BUSY &&
137 !time_after(jiffies, timeout)) {
138 msleep(10);
139 pci_read_config_word(pdev, cap + PCI_EXP_DPC_STATUS, &status);
140 }
141 if (status & PCI_EXP_DPC_RP_BUSY) {
142 pci_warn(pdev, "root port still busy\n");
143 return -EBUSY;
144 }
145 return 0;
146 }
147
dpc_reset_link(struct pci_dev * pdev)148 pci_ers_result_t dpc_reset_link(struct pci_dev *pdev)
149 {
150 pci_ers_result_t ret;
151 u16 cap;
152
153 set_bit(PCI_DPC_RECOVERING, &pdev->priv_flags);
154
155 /*
156 * DPC disables the Link automatically in hardware, so it has
157 * already been reset by the time we get here.
158 */
159 cap = pdev->dpc_cap;
160
161 /*
162 * Wait until the Link is inactive, then clear DPC Trigger Status
163 * to allow the Port to leave DPC.
164 */
165 if (!pcie_wait_for_link(pdev, false))
166 pci_info(pdev, "Data Link Layer Link Active not cleared in 1000 msec\n");
167
168 if (pdev->dpc_rp_extensions && dpc_wait_rp_inactive(pdev)) {
169 clear_bit(PCI_DPC_RECOVERED, &pdev->priv_flags);
170 ret = PCI_ERS_RESULT_DISCONNECT;
171 goto out;
172 }
173
174 pci_write_config_word(pdev, cap + PCI_EXP_DPC_STATUS,
175 PCI_EXP_DPC_STATUS_TRIGGER);
176
177 if (pci_bridge_wait_for_secondary_bus(pdev, "DPC")) {
178 clear_bit(PCI_DPC_RECOVERED, &pdev->priv_flags);
179 ret = PCI_ERS_RESULT_DISCONNECT;
180 } else {
181 set_bit(PCI_DPC_RECOVERED, &pdev->priv_flags);
182 ret = PCI_ERS_RESULT_RECOVERED;
183 }
184 out:
185 clear_bit(PCI_DPC_RECOVERING, &pdev->priv_flags);
186 wake_up_all(&dpc_completed_waitqueue);
187 return ret;
188 }
189
dpc_process_rp_pio_error(struct pci_dev * pdev)190 static void dpc_process_rp_pio_error(struct pci_dev *pdev)
191 {
192 u16 cap = pdev->dpc_cap, dpc_status, first_error;
193 u32 status, mask, sev, syserr, exc, log;
194 struct pcie_tlp_log tlp_log;
195 int i;
196
197 pci_read_config_dword(pdev, cap + PCI_EXP_DPC_RP_PIO_STATUS, &status);
198 pci_read_config_dword(pdev, cap + PCI_EXP_DPC_RP_PIO_MASK, &mask);
199 pci_err(pdev, "rp_pio_status: %#010x, rp_pio_mask: %#010x\n",
200 status, mask);
201
202 pci_read_config_dword(pdev, cap + PCI_EXP_DPC_RP_PIO_SEVERITY, &sev);
203 pci_read_config_dword(pdev, cap + PCI_EXP_DPC_RP_PIO_SYSERROR, &syserr);
204 pci_read_config_dword(pdev, cap + PCI_EXP_DPC_RP_PIO_EXCEPTION, &exc);
205 pci_err(pdev, "RP PIO severity=%#010x, syserror=%#010x, exception=%#010x\n",
206 sev, syserr, exc);
207
208 /* Get First Error Pointer */
209 pci_read_config_word(pdev, cap + PCI_EXP_DPC_STATUS, &dpc_status);
210 first_error = FIELD_GET(PCI_EXP_DPC_RP_PIO_FEP, dpc_status);
211
212 for (i = 0; i < ARRAY_SIZE(rp_pio_error_string); i++) {
213 if ((status & ~mask) & (1 << i))
214 pci_err(pdev, "[%2d] %s%s\n", i, rp_pio_error_string[i],
215 first_error == i ? " (First)" : "");
216 }
217
218 if (pdev->dpc_rp_log_size < PCIE_STD_NUM_TLP_HEADERLOG)
219 goto clear_status;
220 pcie_read_tlp_log(pdev, cap + PCI_EXP_DPC_RP_PIO_HEADER_LOG,
221 cap + PCI_EXP_DPC_RP_PIO_TLPPREFIX_LOG,
222 dpc_tlp_log_len(pdev),
223 pdev->subordinate->flit_mode,
224 &tlp_log);
225 pcie_print_tlp_log(pdev, &tlp_log, dev_fmt(""));
226
227 if (pdev->dpc_rp_log_size < PCIE_STD_NUM_TLP_HEADERLOG + 1)
228 goto clear_status;
229 pci_read_config_dword(pdev, cap + PCI_EXP_DPC_RP_PIO_IMPSPEC_LOG, &log);
230 pci_err(pdev, "RP PIO ImpSpec Log %#010x\n", log);
231
232 clear_status:
233 pci_write_config_dword(pdev, cap + PCI_EXP_DPC_RP_PIO_STATUS, status);
234 }
235
dpc_get_aer_uncorrect_severity(struct pci_dev * dev,struct aer_err_info * info)236 static int dpc_get_aer_uncorrect_severity(struct pci_dev *dev,
237 struct aer_err_info *info)
238 {
239 int pos = dev->aer_cap;
240 u32 status, mask, sev;
241
242 pci_read_config_dword(dev, pos + PCI_ERR_UNCOR_STATUS, &status);
243 pci_read_config_dword(dev, pos + PCI_ERR_UNCOR_MASK, &mask);
244 status &= ~mask;
245 if (!status)
246 return 0;
247
248 pci_read_config_dword(dev, pos + PCI_ERR_UNCOR_SEVER, &sev);
249 status &= sev;
250 if (status)
251 info->severity = AER_FATAL;
252 else
253 info->severity = AER_NONFATAL;
254
255 return 1;
256 }
257
dpc_process_error(struct pci_dev * pdev)258 void dpc_process_error(struct pci_dev *pdev)
259 {
260 u16 cap = pdev->dpc_cap, status, source, reason, ext_reason;
261 struct aer_err_info info;
262
263 pci_read_config_word(pdev, cap + PCI_EXP_DPC_STATUS, &status);
264 pci_read_config_word(pdev, cap + PCI_EXP_DPC_SOURCE_ID, &source);
265
266 pci_info(pdev, "containment event, status:%#06x source:%#06x\n",
267 status, source);
268
269 reason = status & PCI_EXP_DPC_STATUS_TRIGGER_RSN;
270 ext_reason = status & PCI_EXP_DPC_STATUS_TRIGGER_RSN_EXT;
271 pci_warn(pdev, "%s detected\n",
272 (reason == PCI_EXP_DPC_STATUS_TRIGGER_RSN_UNCOR) ?
273 "unmasked uncorrectable error" :
274 (reason == PCI_EXP_DPC_STATUS_TRIGGER_RSN_NFE) ?
275 "ERR_NONFATAL" :
276 (reason == PCI_EXP_DPC_STATUS_TRIGGER_RSN_FE) ?
277 "ERR_FATAL" :
278 (ext_reason == PCI_EXP_DPC_STATUS_TRIGGER_RSN_RP_PIO) ?
279 "RP PIO error" :
280 (ext_reason == PCI_EXP_DPC_STATUS_TRIGGER_RSN_SW_TRIGGER) ?
281 "software trigger" :
282 "reserved error");
283
284 /* show RP PIO error detail information */
285 if (pdev->dpc_rp_extensions &&
286 reason == PCI_EXP_DPC_STATUS_TRIGGER_RSN_IN_EXT &&
287 ext_reason == PCI_EXP_DPC_STATUS_TRIGGER_RSN_RP_PIO)
288 dpc_process_rp_pio_error(pdev);
289 else if (reason == PCI_EXP_DPC_STATUS_TRIGGER_RSN_UNCOR &&
290 dpc_get_aer_uncorrect_severity(pdev, &info) &&
291 aer_get_device_error_info(pdev, &info)) {
292 aer_print_error(pdev, &info);
293 pci_aer_clear_nonfatal_status(pdev);
294 pci_aer_clear_fatal_status(pdev);
295 }
296 }
297
pci_clear_surpdn_errors(struct pci_dev * pdev)298 static void pci_clear_surpdn_errors(struct pci_dev *pdev)
299 {
300 if (pdev->dpc_rp_extensions)
301 pci_write_config_dword(pdev, pdev->dpc_cap +
302 PCI_EXP_DPC_RP_PIO_STATUS, ~0);
303
304 /*
305 * In practice, Surprise Down errors have been observed to also set
306 * error bits in the Status Register as well as the Fatal Error
307 * Detected bit in the Device Status Register.
308 */
309 pci_write_config_word(pdev, PCI_STATUS, 0xffff);
310
311 pcie_capability_write_word(pdev, PCI_EXP_DEVSTA, PCI_EXP_DEVSTA_FED);
312 }
313
dpc_handle_surprise_removal(struct pci_dev * pdev)314 static void dpc_handle_surprise_removal(struct pci_dev *pdev)
315 {
316 if (!pcie_wait_for_link(pdev, false)) {
317 pci_info(pdev, "Data Link Layer Link Active not cleared in 1000 msec\n");
318 goto out;
319 }
320
321 if (pdev->dpc_rp_extensions && dpc_wait_rp_inactive(pdev))
322 goto out;
323
324 pci_aer_raw_clear_status(pdev);
325 pci_clear_surpdn_errors(pdev);
326
327 pci_write_config_word(pdev, pdev->dpc_cap + PCI_EXP_DPC_STATUS,
328 PCI_EXP_DPC_STATUS_TRIGGER);
329
330 out:
331 clear_bit(PCI_DPC_RECOVERED, &pdev->priv_flags);
332 wake_up_all(&dpc_completed_waitqueue);
333 }
334
dpc_is_surprise_removal(struct pci_dev * pdev)335 static bool dpc_is_surprise_removal(struct pci_dev *pdev)
336 {
337 u16 status;
338
339 if (!pdev->is_hotplug_bridge)
340 return false;
341
342 if (pci_read_config_word(pdev, pdev->aer_cap + PCI_ERR_UNCOR_STATUS,
343 &status))
344 return false;
345
346 return status & PCI_ERR_UNC_SURPDN;
347 }
348
dpc_handler(int irq,void * context)349 static irqreturn_t dpc_handler(int irq, void *context)
350 {
351 struct pci_dev *pdev = context;
352
353 /*
354 * According to PCIe r6.0 sec 6.7.6, errors are an expected side effect
355 * of async removal and should be ignored by software.
356 */
357 if (dpc_is_surprise_removal(pdev)) {
358 dpc_handle_surprise_removal(pdev);
359 return IRQ_HANDLED;
360 }
361
362 dpc_process_error(pdev);
363
364 /* We configure DPC so it only triggers on ERR_FATAL */
365 pcie_do_recovery(pdev, pci_channel_io_frozen, dpc_reset_link);
366
367 return IRQ_HANDLED;
368 }
369
dpc_irq(int irq,void * context)370 static irqreturn_t dpc_irq(int irq, void *context)
371 {
372 struct pci_dev *pdev = context;
373 u16 cap = pdev->dpc_cap, status;
374
375 pci_read_config_word(pdev, cap + PCI_EXP_DPC_STATUS, &status);
376
377 if (!(status & PCI_EXP_DPC_STATUS_INTERRUPT) || PCI_POSSIBLE_ERROR(status))
378 return IRQ_NONE;
379
380 pci_write_config_word(pdev, cap + PCI_EXP_DPC_STATUS,
381 PCI_EXP_DPC_STATUS_INTERRUPT);
382 if (status & PCI_EXP_DPC_STATUS_TRIGGER)
383 return IRQ_WAKE_THREAD;
384 return IRQ_HANDLED;
385 }
386
pci_dpc_init(struct pci_dev * pdev)387 void pci_dpc_init(struct pci_dev *pdev)
388 {
389 u16 cap;
390
391 pdev->dpc_cap = pci_find_ext_capability(pdev, PCI_EXT_CAP_ID_DPC);
392 if (!pdev->dpc_cap)
393 return;
394
395 pci_read_config_word(pdev, pdev->dpc_cap + PCI_EXP_DPC_CAP, &cap);
396 if (!(cap & PCI_EXP_DPC_CAP_RP_EXT))
397 return;
398
399 pdev->dpc_rp_extensions = true;
400
401 /* Quirks may set dpc_rp_log_size if device or firmware is buggy */
402 if (!pdev->dpc_rp_log_size) {
403 u16 flags;
404 int ret;
405
406 ret = pcie_capability_read_word(pdev, PCI_EXP_FLAGS, &flags);
407 if (ret)
408 return;
409
410 pdev->dpc_rp_log_size =
411 FIELD_GET(PCI_EXP_DPC_RP_PIO_LOG_SIZE, cap);
412 if (FIELD_GET(PCI_EXP_FLAGS_FLIT, flags))
413 pdev->dpc_rp_log_size += FIELD_GET(PCI_EXP_DPC_RP_PIO_LOG_SIZE4,
414 cap) << 4;
415
416 if (pdev->dpc_rp_log_size < PCIE_STD_NUM_TLP_HEADERLOG ||
417 pdev->dpc_rp_log_size > PCIE_STD_MAX_TLP_HEADERLOG + 1) {
418 pci_err(pdev, "RP PIO log size %u is invalid\n",
419 pdev->dpc_rp_log_size);
420 pdev->dpc_rp_log_size = 0;
421 }
422 }
423 }
424
dpc_enable(struct pcie_device * dev)425 static void dpc_enable(struct pcie_device *dev)
426 {
427 struct pci_dev *pdev = dev->port;
428 int dpc = pdev->dpc_cap;
429 u16 ctl;
430
431 /*
432 * Clear DPC Interrupt Status so we don't get an interrupt for an
433 * old event when setting DPC Interrupt Enable.
434 */
435 pci_write_config_word(pdev, dpc + PCI_EXP_DPC_STATUS,
436 PCI_EXP_DPC_STATUS_INTERRUPT);
437
438 pci_read_config_word(pdev, dpc + PCI_EXP_DPC_CTL, &ctl);
439 ctl &= ~PCI_EXP_DPC_CTL_EN_MASK;
440 ctl |= PCI_EXP_DPC_CTL_EN_FATAL | PCI_EXP_DPC_CTL_INT_EN;
441 pci_write_config_word(pdev, dpc + PCI_EXP_DPC_CTL, ctl);
442 }
443
dpc_disable(struct pcie_device * dev)444 static void dpc_disable(struct pcie_device *dev)
445 {
446 struct pci_dev *pdev = dev->port;
447 int dpc = pdev->dpc_cap;
448 u16 ctl;
449
450 /* Disable DPC triggering and DPC interrupts */
451 pci_read_config_word(pdev, dpc + PCI_EXP_DPC_CTL, &ctl);
452 ctl &= ~(PCI_EXP_DPC_CTL_EN_FATAL | PCI_EXP_DPC_CTL_INT_EN);
453 pci_write_config_word(pdev, dpc + PCI_EXP_DPC_CTL, ctl);
454 }
455
456 #define FLAG(x, y) (((x) & (y)) ? '+' : '-')
dpc_probe(struct pcie_device * dev)457 static int dpc_probe(struct pcie_device *dev)
458 {
459 struct pci_dev *pdev = dev->port;
460 struct device *device = &dev->device;
461 int status;
462 u16 cap;
463
464 if (!pcie_aer_is_native(pdev) && !pcie_ports_dpc_native)
465 return -ENOTSUPP;
466
467 status = devm_request_threaded_irq(device, dev->irq, dpc_irq,
468 dpc_handler, IRQF_SHARED,
469 "pcie-dpc", pdev);
470 if (status) {
471 pci_warn(pdev, "request IRQ%d failed: %d\n", dev->irq,
472 status);
473 return status;
474 }
475
476 pci_read_config_word(pdev, pdev->dpc_cap + PCI_EXP_DPC_CAP, &cap);
477 dpc_enable(dev);
478
479 pci_info(pdev, "enabled with IRQ %d\n", dev->irq);
480 pci_info(pdev, "error containment capabilities: Int Msg #%d, RPExt%c PoisonedTLP%c SwTrigger%c RP PIO Log %d, DL_ActiveErr%c\n",
481 cap & PCI_EXP_DPC_IRQ, FLAG(cap, PCI_EXP_DPC_CAP_RP_EXT),
482 FLAG(cap, PCI_EXP_DPC_CAP_POISONED_TLP),
483 FLAG(cap, PCI_EXP_DPC_CAP_SW_TRIGGER), pdev->dpc_rp_log_size,
484 FLAG(cap, PCI_EXP_DPC_CAP_DL_ACTIVE));
485
486 pci_add_ext_cap_save_buffer(pdev, PCI_EXT_CAP_ID_DPC, sizeof(u16));
487 return status;
488 }
489
dpc_suspend(struct pcie_device * dev)490 static int dpc_suspend(struct pcie_device *dev)
491 {
492 dpc_disable(dev);
493 return 0;
494 }
495
dpc_resume(struct pcie_device * dev)496 static int dpc_resume(struct pcie_device *dev)
497 {
498 dpc_enable(dev);
499 return 0;
500 }
501
dpc_remove(struct pcie_device * dev)502 static void dpc_remove(struct pcie_device *dev)
503 {
504 dpc_disable(dev);
505 }
506
507 static struct pcie_port_service_driver dpcdriver = {
508 .name = "dpc",
509 .port_type = PCIE_ANY_PORT,
510 .service = PCIE_PORT_SERVICE_DPC,
511 .probe = dpc_probe,
512 .suspend = dpc_suspend,
513 .resume = dpc_resume,
514 .remove = dpc_remove,
515 };
516
pcie_dpc_init(void)517 int __init pcie_dpc_init(void)
518 {
519 return pcie_port_service_register(&dpcdriver);
520 }
521