1 /* 2 * Copyright 2000 ATI Technologies Inc., Markham, Ontario, and 3 * VA Linux Systems Inc., Fremont, California. 4 * Copyright 2008 Red Hat Inc. 5 * 6 * Permission is hereby granted, free of charge, to any person obtaining a 7 * copy of this software and associated documentation files (the "Software"), 8 * to deal in the Software without restriction, including without limitation 9 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 10 * and/or sell copies of the Software, and to permit persons to whom the 11 * Software is furnished to do so, subject to the following conditions: 12 * 13 * The above copyright notice and this permission notice shall be included in 14 * all copies or substantial portions of the Software. 15 * 16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 19 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 22 * OTHER DEALINGS IN THE SOFTWARE. 23 * 24 * Original Authors: 25 * Kevin E. Martin, Rickard E. Faith, Alan Hourihane 26 * 27 * Kernel port Author: Dave Airlie 28 */ 29 30 #ifndef AMDGPU_MODE_H 31 #define AMDGPU_MODE_H 32 33 #include <drm/display/drm_dp_helper.h> 34 #include <drm/drm_crtc.h> 35 #include <drm/drm_encoder.h> 36 #include <drm/drm_fixed.h> 37 #include <drm/drm_framebuffer.h> 38 #include <drm/drm_probe_helper.h> 39 #include <linux/i2c.h> 40 #include <linux/i2c-algo-bit.h> 41 #include <linux/hrtimer.h> 42 #include "amdgpu_irq.h" 43 44 #include <drm/display/drm_dp_mst_helper.h> 45 #include "modules/inc/mod_freesync.h" 46 #include "amdgpu_dm_irq_params.h" 47 #include "amdgpu_dm_ism.h" 48 49 struct amdgpu_bo; 50 struct amdgpu_device; 51 struct amdgpu_encoder; 52 struct amdgpu_router; 53 struct amdgpu_hpd; 54 struct edid; 55 struct drm_edid; 56 57 #define to_amdgpu_crtc(x) container_of(x, struct amdgpu_crtc, base) 58 #define to_amdgpu_connector(x) container_of(x, struct amdgpu_connector, base) 59 #define to_amdgpu_encoder(x) container_of(x, struct amdgpu_encoder, base) 60 #define to_amdgpu_framebuffer(x) container_of(x, struct amdgpu_framebuffer, base) 61 62 #define to_dm_plane_state(x) container_of(x, struct dm_plane_state, base) 63 64 #define AMDGPU_MAX_HPD_PINS 6 65 #define AMDGPU_MAX_CRTCS 6 66 #define AMDGPU_MAX_PLANES 6 67 #define AMDGPU_MAX_AFMT_BLOCKS 9 68 69 enum amdgpu_rmx_type { 70 RMX_OFF, 71 RMX_FULL, 72 RMX_CENTER, 73 RMX_ASPECT 74 }; 75 76 enum amdgpu_underscan_type { 77 UNDERSCAN_OFF, 78 UNDERSCAN_ON, 79 UNDERSCAN_AUTO, 80 }; 81 82 #define AMDGPU_HPD_CONNECT_INT_DELAY_IN_MS 50 83 #define AMDGPU_HPD_DISCONNECT_INT_DELAY_IN_MS 10 84 85 enum amdgpu_hpd_id { 86 AMDGPU_HPD_1 = 0, 87 AMDGPU_HPD_2, 88 AMDGPU_HPD_3, 89 AMDGPU_HPD_4, 90 AMDGPU_HPD_5, 91 AMDGPU_HPD_6, 92 AMDGPU_HPD_NONE = 0xff, 93 }; 94 95 enum amdgpu_crtc_irq { 96 AMDGPU_CRTC_IRQ_VBLANK1 = 0, 97 AMDGPU_CRTC_IRQ_VBLANK2, 98 AMDGPU_CRTC_IRQ_VBLANK3, 99 AMDGPU_CRTC_IRQ_VBLANK4, 100 AMDGPU_CRTC_IRQ_VBLANK5, 101 AMDGPU_CRTC_IRQ_VBLANK6, 102 AMDGPU_CRTC_IRQ_VLINE1, 103 AMDGPU_CRTC_IRQ_VLINE2, 104 AMDGPU_CRTC_IRQ_VLINE3, 105 AMDGPU_CRTC_IRQ_VLINE4, 106 AMDGPU_CRTC_IRQ_VLINE5, 107 AMDGPU_CRTC_IRQ_VLINE6, 108 AMDGPU_CRTC_IRQ_NONE = 0xff 109 }; 110 111 enum amdgpu_pageflip_irq { 112 AMDGPU_PAGEFLIP_IRQ_D1 = 0, 113 AMDGPU_PAGEFLIP_IRQ_D2, 114 AMDGPU_PAGEFLIP_IRQ_D3, 115 AMDGPU_PAGEFLIP_IRQ_D4, 116 AMDGPU_PAGEFLIP_IRQ_D5, 117 AMDGPU_PAGEFLIP_IRQ_D6, 118 AMDGPU_PAGEFLIP_IRQ_NONE = 0xff 119 }; 120 121 enum amdgpu_flip_status { 122 AMDGPU_FLIP_NONE, 123 AMDGPU_FLIP_PENDING, 124 AMDGPU_FLIP_SUBMITTED 125 }; 126 127 #define AMDGPU_MAX_I2C_BUS 16 128 129 /* amdgpu gpio-based i2c 130 * 1. "mask" reg and bits 131 * grabs the gpio pins for software use 132 * 0=not held 1=held 133 * 2. "a" reg and bits 134 * output pin value 135 * 0=low 1=high 136 * 3. "en" reg and bits 137 * sets the pin direction 138 * 0=input 1=output 139 * 4. "y" reg and bits 140 * input pin value 141 * 0=low 1=high 142 */ 143 struct amdgpu_i2c_bus_rec { 144 bool valid; 145 /* id used by atom */ 146 uint8_t i2c_id; 147 /* id used by atom */ 148 enum amdgpu_hpd_id hpd; 149 /* can be used with hw i2c engine */ 150 bool hw_capable; 151 /* uses multi-media i2c engine */ 152 bool mm_i2c; 153 /* regs and bits */ 154 uint32_t mask_clk_reg; 155 uint32_t mask_data_reg; 156 uint32_t a_clk_reg; 157 uint32_t a_data_reg; 158 uint32_t en_clk_reg; 159 uint32_t en_data_reg; 160 uint32_t y_clk_reg; 161 uint32_t y_data_reg; 162 uint32_t mask_clk_mask; 163 uint32_t mask_data_mask; 164 uint32_t a_clk_mask; 165 uint32_t a_data_mask; 166 uint32_t en_clk_mask; 167 uint32_t en_data_mask; 168 uint32_t y_clk_mask; 169 uint32_t y_data_mask; 170 }; 171 172 #define AMDGPU_MAX_BIOS_CONNECTOR 16 173 174 /* pll flags */ 175 #define AMDGPU_PLL_USE_BIOS_DIVS (1 << 0) 176 #define AMDGPU_PLL_NO_ODD_POST_DIV (1 << 1) 177 #define AMDGPU_PLL_USE_REF_DIV (1 << 2) 178 #define AMDGPU_PLL_LEGACY (1 << 3) 179 #define AMDGPU_PLL_PREFER_LOW_REF_DIV (1 << 4) 180 #define AMDGPU_PLL_PREFER_HIGH_REF_DIV (1 << 5) 181 #define AMDGPU_PLL_PREFER_LOW_FB_DIV (1 << 6) 182 #define AMDGPU_PLL_PREFER_HIGH_FB_DIV (1 << 7) 183 #define AMDGPU_PLL_PREFER_LOW_POST_DIV (1 << 8) 184 #define AMDGPU_PLL_PREFER_HIGH_POST_DIV (1 << 9) 185 #define AMDGPU_PLL_USE_FRAC_FB_DIV (1 << 10) 186 #define AMDGPU_PLL_PREFER_CLOSEST_LOWER (1 << 11) 187 #define AMDGPU_PLL_USE_POST_DIV (1 << 12) 188 #define AMDGPU_PLL_IS_LCD (1 << 13) 189 #define AMDGPU_PLL_PREFER_MINM_OVER_MAXP (1 << 14) 190 191 struct amdgpu_pll { 192 /* reference frequency */ 193 uint32_t reference_freq; 194 195 /* fixed dividers */ 196 uint32_t reference_div; 197 uint32_t post_div; 198 199 /* pll in/out limits */ 200 uint32_t pll_in_min; 201 uint32_t pll_in_max; 202 uint32_t pll_out_min; 203 uint32_t pll_out_max; 204 uint32_t lcd_pll_out_min; 205 uint32_t lcd_pll_out_max; 206 uint32_t best_vco; 207 208 /* divider limits */ 209 uint32_t min_ref_div; 210 uint32_t max_ref_div; 211 uint32_t min_post_div; 212 uint32_t max_post_div; 213 uint32_t min_feedback_div; 214 uint32_t max_feedback_div; 215 uint32_t min_frac_feedback_div; 216 uint32_t max_frac_feedback_div; 217 218 /* flags for the current clock */ 219 uint32_t flags; 220 221 /* pll id */ 222 uint32_t id; 223 }; 224 225 struct amdgpu_i2c_chan { 226 struct i2c_adapter adapter; 227 struct drm_device *dev; 228 struct i2c_algo_bit_data bit; 229 struct amdgpu_i2c_bus_rec rec; 230 struct drm_dp_aux aux; 231 bool has_aux; 232 struct mutex mutex; 233 }; 234 235 struct amdgpu_afmt { 236 bool enabled; 237 int offset; 238 bool last_buffer_filled_status; 239 int id; 240 struct amdgpu_audio_pin *pin; 241 }; 242 243 /* 244 * Audio 245 */ 246 struct amdgpu_audio_pin { 247 int channels; 248 int rate; 249 int bits_per_sample; 250 u8 status_bits; 251 u8 category_code; 252 u32 offset; 253 bool connected; 254 u32 id; 255 }; 256 257 struct amdgpu_audio { 258 bool enabled; 259 struct amdgpu_audio_pin pin[AMDGPU_MAX_AFMT_BLOCKS]; 260 int num_pins; 261 }; 262 263 struct amdgpu_display_funcs { 264 /* display watermarks */ 265 void (*bandwidth_update)(struct amdgpu_device *adev); 266 /* get frame count */ 267 u32 (*vblank_get_counter)(struct amdgpu_device *adev, int crtc); 268 /* set backlight level */ 269 void (*backlight_set_level)(struct amdgpu_encoder *amdgpu_encoder, 270 u8 level); 271 /* get backlight level */ 272 u8 (*backlight_get_level)(struct amdgpu_encoder *amdgpu_encoder); 273 /* hotplug detect */ 274 bool (*hpd_sense)(struct amdgpu_device *adev, enum amdgpu_hpd_id hpd); 275 void (*hpd_set_polarity)(struct amdgpu_device *adev, 276 enum amdgpu_hpd_id hpd); 277 u32 (*hpd_get_gpio_reg)(struct amdgpu_device *adev); 278 /* pageflipping */ 279 void (*page_flip)(struct amdgpu_device *adev, 280 int crtc_id, u64 crtc_base, bool async); 281 int (*page_flip_get_scanoutpos)(struct amdgpu_device *adev, int crtc, 282 u32 *vbl, u32 *position); 283 /* display topology setup */ 284 void (*add_encoder)(struct amdgpu_device *adev, 285 uint32_t encoder_enum, 286 uint32_t supported_device, 287 u16 caps); 288 void (*add_connector)(struct amdgpu_device *adev, 289 uint32_t connector_id, 290 uint32_t supported_device, 291 int connector_type, 292 struct amdgpu_i2c_bus_rec *i2c_bus, 293 uint16_t connector_object_id, 294 struct amdgpu_hpd *hpd, 295 struct amdgpu_router *router); 296 297 298 }; 299 300 struct amdgpu_framebuffer { 301 struct drm_framebuffer base; 302 303 uint64_t tiling_flags; 304 bool tmz_surface; 305 bool gfx12_dcc; 306 307 /* caching for later use */ 308 uint64_t address; 309 }; 310 311 struct amdgpu_mode_info { 312 struct atom_context *atom_context; 313 struct card_info *atom_card_info; 314 bool mode_config_initialized; 315 struct amdgpu_crtc *crtcs[AMDGPU_MAX_CRTCS]; 316 struct drm_plane *planes[AMDGPU_MAX_PLANES]; 317 struct amdgpu_afmt *afmt[AMDGPU_MAX_AFMT_BLOCKS]; 318 /* DVI-I properties */ 319 struct drm_property *coherent_mode_property; 320 /* DAC enable load detect */ 321 struct drm_property *load_detect_property; 322 /* underscan */ 323 struct drm_property *underscan_property; 324 struct drm_property *underscan_hborder_property; 325 struct drm_property *underscan_vborder_property; 326 /* audio */ 327 struct drm_property *audio_property; 328 /* FMT dithering */ 329 struct drm_property *dither_property; 330 /* Adaptive Backlight Modulation (power feature) */ 331 struct drm_property *abm_level_property; 332 /* hardcoded DFP edid from BIOS */ 333 const struct drm_edid *bios_hardcoded_edid; 334 335 /* firmware flags */ 336 u32 firmware_flags; 337 /* pointer to backlight encoder */ 338 struct amdgpu_encoder *bl_encoder; 339 u8 bl_level; /* saved backlight level */ 340 struct amdgpu_audio audio; /* audio stuff */ 341 int num_crtc; /* number of crtcs */ 342 int num_hpd; /* number of hpd pins */ 343 int num_dig; /* number of dig blocks */ 344 bool gpu_vm_support; /* supports display from GTT */ 345 int disp_priority; 346 const struct amdgpu_display_funcs *funcs; 347 const enum drm_plane_type *plane_type; 348 349 /* Driver-private color mgmt props */ 350 351 /* @plane_degamma_lut_property: Plane property to set a degamma LUT to 352 * convert encoded values to light linear values before sampling or 353 * blending. 354 */ 355 struct drm_property *plane_degamma_lut_property; 356 /* @plane_degamma_lut_size_property: Plane property to define the max 357 * size of degamma LUT as supported by the driver (read-only). 358 */ 359 struct drm_property *plane_degamma_lut_size_property; 360 /** 361 * @plane_degamma_tf_property: Plane pre-defined transfer function to 362 * to go from scanout/encoded values to linear values. 363 */ 364 struct drm_property *plane_degamma_tf_property; 365 /** 366 * @plane_hdr_mult_property: 367 */ 368 struct drm_property *plane_hdr_mult_property; 369 370 struct drm_property *plane_ctm_property; 371 /** 372 * @plane_shaper_lut_property: Plane property to set pre-blending 373 * shaper LUT that converts color content before 3D LUT. 374 * If plane_shaper_tf_property != Identity TF, AMD color module will 375 * combine the user LUT values with pre-defined TF into the LUT 376 * parameters to be programmed. 377 */ 378 struct drm_property *plane_shaper_lut_property; 379 /** 380 * @plane_shaper_lut_size_property: Plane property for the size of 381 * pre-blending shaper LUT as supported by the driver (read-only). 382 */ 383 struct drm_property *plane_shaper_lut_size_property; 384 /** 385 * @plane_shaper_tf_property: Plane property to set a predefined 386 * transfer function for pre-blending shaper (before applying 3D LUT) 387 * with or without LUT. There is no shaper ROM, but we can use AMD 388 * color modules to program LUT parameters from predefined TF (or 389 * from a combination of pre-defined TF and the custom 1D LUT). 390 */ 391 struct drm_property *plane_shaper_tf_property; 392 /** 393 * @plane_lut3d_property: Plane property for color transformation using 394 * a 3D LUT (pre-blending), a three-dimensional array where each 395 * element is an RGB triplet. Each dimension has the size of 396 * lut3d_size. The array contains samples from the approximated 397 * function. On AMD, values between samples are estimated by 398 * tetrahedral interpolation. The array is accessed with three indices, 399 * one for each input dimension (color channel), blue being the 400 * outermost dimension, red the innermost. 401 */ 402 struct drm_property *plane_lut3d_property; 403 /** 404 * @plane_lut3d_size_property: Plane property to define the max size 405 * of 3D LUT as supported by the driver (read-only). The max size is 406 * the max size of one dimension and, therefore, the max number of 407 * entries for 3D LUT array is the 3D LUT size cubed. 408 */ 409 struct drm_property *plane_lut3d_size_property; 410 /** 411 * @plane_blend_lut_property: Plane property for output gamma before 412 * blending. Userspace set a blend LUT to convert colors after 3D LUT 413 * conversion. It works as a post-3DLUT 1D LUT. With shaper LUT, they 414 * are sandwiching 3D LUT with two 1D LUT. If plane_blend_tf_property 415 * != Identity TF, AMD color module will combine the user LUT values 416 * with pre-defined TF into the LUT parameters to be programmed. 417 */ 418 struct drm_property *plane_blend_lut_property; 419 /** 420 * @plane_blend_lut_size_property: Plane property to define the max 421 * size of blend LUT as supported by the driver (read-only). 422 */ 423 struct drm_property *plane_blend_lut_size_property; 424 /** 425 * @plane_blend_tf_property: Plane property to set a predefined 426 * transfer function for pre-blending blend/out_gamma (after applying 427 * 3D LUT) with or without LUT. There is no blend ROM, but we can use 428 * AMD color modules to program LUT parameters from predefined TF (or 429 * from a combination of pre-defined TF and the custom 1D LUT). 430 */ 431 struct drm_property *plane_blend_tf_property; 432 /* @regamma_tf_property: Transfer function for CRTC regamma 433 * (post-blending). Possible values are defined by `enum 434 * amdgpu_transfer_function`. There is no regamma ROM, but we can use 435 * AMD color modules to program LUT parameters from predefined TF (or 436 * from a combination of pre-defined TF and the custom 1D LUT). 437 */ 438 struct drm_property *regamma_tf_property; 439 }; 440 441 #define AMDGPU_MAX_BL_LEVEL 0xFF 442 443 struct amdgpu_backlight_privdata { 444 struct amdgpu_encoder *encoder; 445 uint8_t negative; 446 }; 447 448 struct amdgpu_atom_ss { 449 uint16_t percentage; 450 uint16_t percentage_divider; 451 uint8_t type; 452 uint16_t step; 453 uint8_t delay; 454 uint8_t range; 455 uint8_t refdiv; 456 /* asic_ss */ 457 uint16_t rate; 458 uint16_t amount; 459 }; 460 461 struct amdgpu_crtc { 462 struct drm_crtc base; 463 int crtc_id; 464 bool enabled; 465 bool can_tile; 466 uint32_t crtc_offset; 467 struct drm_gem_object *cursor_bo; 468 uint64_t cursor_addr; 469 int cursor_x; 470 int cursor_y; 471 int cursor_hot_x; 472 int cursor_hot_y; 473 int cursor_width; 474 int cursor_height; 475 int max_cursor_width; 476 int max_cursor_height; 477 enum amdgpu_rmx_type rmx_type; 478 u8 h_border; 479 u8 v_border; 480 fixed20_12 vsc; 481 fixed20_12 hsc; 482 struct drm_display_mode native_mode; 483 u32 pll_id; 484 /* page flipping */ 485 struct amdgpu_flip_work *pflip_works; 486 enum amdgpu_flip_status pflip_status; 487 int deferred_flip_completion; 488 /* parameters access from DM IRQ handler */ 489 struct dm_irq_params dm_irq_params; 490 491 /* DM idle state manager */ 492 struct amdgpu_dm_ism ism; 493 494 /* pll sharing */ 495 struct amdgpu_atom_ss ss; 496 bool ss_enabled; 497 u32 adjusted_clock; 498 int bpc; 499 u32 pll_reference_div; 500 u32 pll_post_div; 501 u32 pll_flags; 502 struct drm_encoder *encoder; 503 struct drm_connector *connector; 504 /* for dpm */ 505 u32 line_time; 506 u32 lb_vblank_lead_lines; 507 struct drm_display_mode hw_mode; 508 /* for virtual dce */ 509 struct hrtimer vblank_timer; 510 enum amdgpu_interrupt_state vsync_timer_enabled; 511 512 int otg_inst; 513 struct drm_pending_vblank_event *event; 514 515 bool wb_pending; 516 bool wb_enabled; 517 struct drm_writeback_connector *wb_conn; 518 }; 519 520 struct amdgpu_encoder_atom_dig { 521 bool linkb; 522 /* atom dig */ 523 bool coherent_mode; 524 int dig_encoder; /* -1 disabled, 0 DIGA, 1 DIGB, etc. */ 525 /* atom lvds/edp */ 526 uint32_t lcd_misc; 527 uint16_t panel_pwr_delay; 528 uint32_t lcd_ss_id; 529 /* panel mode */ 530 struct drm_display_mode native_mode; 531 struct backlight_device *bl_dev; 532 int dpms_mode; 533 uint8_t backlight_level; 534 int panel_mode; 535 struct amdgpu_afmt *afmt; 536 }; 537 538 struct amdgpu_encoder { 539 struct drm_encoder base; 540 uint32_t encoder_enum; 541 uint32_t encoder_id; 542 uint32_t devices; 543 uint32_t active_device; 544 uint32_t flags; 545 uint32_t pixel_clock; 546 enum amdgpu_rmx_type rmx_type; 547 enum amdgpu_underscan_type underscan_type; 548 uint32_t underscan_hborder; 549 uint32_t underscan_vborder; 550 struct drm_display_mode native_mode; 551 void *enc_priv; 552 int audio_polling_active; 553 bool is_ext_encoder; 554 u16 caps; 555 }; 556 557 struct amdgpu_connector_atom_dig { 558 /* displayport */ 559 u8 dpcd[DP_RECEIVER_CAP_SIZE]; 560 u8 downstream_ports[DP_MAX_DOWNSTREAM_PORTS]; 561 u8 dp_sink_type; 562 int dp_clock; 563 int dp_lane_count; 564 bool edp_on; 565 }; 566 567 struct amdgpu_gpio_rec { 568 bool valid; 569 u8 id; 570 u32 reg; 571 u32 mask; 572 u32 shift; 573 }; 574 575 struct amdgpu_hpd { 576 enum amdgpu_hpd_id hpd; 577 u8 plugged_state; 578 struct amdgpu_gpio_rec gpio; 579 }; 580 581 struct amdgpu_router { 582 u32 router_id; 583 struct amdgpu_i2c_bus_rec i2c_info; 584 u8 i2c_addr; 585 /* i2c mux */ 586 bool ddc_valid; 587 u8 ddc_mux_type; 588 u8 ddc_mux_control_pin; 589 u8 ddc_mux_state; 590 /* clock/data mux */ 591 bool cd_valid; 592 u8 cd_mux_type; 593 u8 cd_mux_control_pin; 594 u8 cd_mux_state; 595 }; 596 597 enum amdgpu_connector_audio { 598 AMDGPU_AUDIO_DISABLE = 0, 599 AMDGPU_AUDIO_ENABLE = 1, 600 AMDGPU_AUDIO_AUTO = 2 601 }; 602 603 enum amdgpu_connector_dither { 604 AMDGPU_FMT_DITHER_DISABLE = 0, 605 AMDGPU_FMT_DITHER_ENABLE = 1, 606 }; 607 608 struct amdgpu_dm_dp_aux { 609 struct drm_dp_aux aux; 610 struct ddc_service *ddc_service; 611 }; 612 613 struct amdgpu_i2c_adapter { 614 struct i2c_adapter base; 615 616 struct ddc_service *ddc_service; 617 bool oem; 618 }; 619 620 #define TO_DM_AUX(x) container_of((x), struct amdgpu_dm_dp_aux, aux) 621 622 struct amdgpu_connector { 623 struct drm_connector base; 624 uint32_t connector_id; 625 uint32_t devices; 626 struct amdgpu_i2c_chan *ddc_bus; 627 /* some systems have an hdmi and vga port with a shared ddc line */ 628 bool shared_ddc; 629 bool use_digital; 630 /* we need to mind the EDID between detect 631 and get modes due to analog/digital/tvencoder */ 632 const struct drm_edid *edid; 633 void *con_priv; 634 bool dac_load_detect; 635 bool detected_by_load; /* if the connection status was determined by load */ 636 bool detected_hpd_without_ddc; /* if an HPD signal was detected on DVI, but ddc probing failed */ 637 uint16_t connector_object_id; 638 struct amdgpu_hpd hpd; 639 struct amdgpu_router router; 640 struct amdgpu_i2c_chan *router_bus; 641 enum amdgpu_connector_audio audio; 642 enum amdgpu_connector_dither dither; 643 unsigned pixelclock_for_modeset; 644 }; 645 646 /* TODO: start to use this struct and remove same field from base one */ 647 struct amdgpu_mst_connector { 648 struct amdgpu_connector base; 649 650 struct drm_dp_mst_topology_mgr mst_mgr; 651 struct amdgpu_dm_dp_aux dm_dp_aux; 652 struct drm_dp_mst_port *mst_output_port; 653 struct amdgpu_connector *mst_root; 654 bool is_mst_connector; 655 struct amdgpu_encoder *mst_encoder; 656 }; 657 658 #define ENCODER_MODE_IS_DP(em) (((em) == ATOM_ENCODER_MODE_DP) || \ 659 ((em) == ATOM_ENCODER_MODE_DP_MST)) 660 661 /* Driver internal use only flags of amdgpu_display_get_crtc_scanoutpos() */ 662 #define DRM_SCANOUTPOS_VALID (1 << 0) 663 #define DRM_SCANOUTPOS_IN_VBLANK (1 << 1) 664 #define DRM_SCANOUTPOS_ACCURATE (1 << 2) 665 #define USE_REAL_VBLANKSTART (1 << 30) 666 #define GET_DISTANCE_TO_VBLANKSTART (1 << 31) 667 668 void amdgpu_link_encoder_connector(struct drm_device *dev); 669 670 struct drm_connector * 671 amdgpu_get_connector_for_encoder(struct drm_encoder *encoder); 672 struct drm_connector * 673 amdgpu_get_connector_for_encoder_init(struct drm_encoder *encoder); 674 bool amdgpu_dig_monitor_is_duallink(struct drm_encoder *encoder, 675 u32 pixel_clock); 676 677 u16 amdgpu_encoder_get_dp_bridge_encoder_id(struct drm_encoder *encoder); 678 struct drm_encoder *amdgpu_get_external_encoder(struct drm_encoder *encoder); 679 680 bool amdgpu_display_ddc_probe(struct amdgpu_connector *amdgpu_connector, 681 bool use_aux); 682 683 void amdgpu_encoder_set_active_device(struct drm_encoder *encoder); 684 685 int amdgpu_display_get_crtc_scanoutpos(struct drm_device *dev, 686 unsigned int pipe, unsigned int flags, int *vpos, 687 int *hpos, ktime_t *stime, ktime_t *etime, 688 const struct drm_display_mode *mode); 689 690 int amdgpufb_remove(struct drm_device *dev, struct drm_framebuffer *fb); 691 692 void amdgpu_enc_destroy(struct drm_encoder *encoder); 693 void amdgpu_copy_fb(struct drm_device *dev, struct drm_gem_object *dst_obj); 694 bool amdgpu_display_crtc_scaling_mode_fixup(struct drm_crtc *crtc, 695 const struct drm_display_mode *mode, 696 struct drm_display_mode *adjusted_mode); 697 void amdgpu_panel_mode_fixup(struct drm_encoder *encoder, 698 struct drm_display_mode *adjusted_mode); 699 int amdgpu_display_crtc_idx_to_irq_type(struct amdgpu_device *adev, int crtc); 700 701 bool amdgpu_crtc_get_scanout_position(struct drm_crtc *crtc, 702 bool in_vblank_irq, int *vpos, 703 int *hpos, ktime_t *stime, ktime_t *etime, 704 const struct drm_display_mode *mode); 705 706 /* amdgpu_display.c */ 707 void amdgpu_display_print_display_setup(struct drm_device *dev); 708 int amdgpu_display_modeset_create_props(struct amdgpu_device *adev); 709 int amdgpu_display_crtc_set_config(struct drm_mode_set *set, 710 struct drm_modeset_acquire_ctx *ctx); 711 int amdgpu_display_crtc_page_flip_target(struct drm_crtc *crtc, 712 struct drm_framebuffer *fb, 713 struct drm_pending_vblank_event *event, 714 uint32_t page_flip_flags, uint32_t target, 715 struct drm_modeset_acquire_ctx *ctx); 716 extern const struct drm_mode_config_funcs amdgpu_mode_funcs; 717 718 #endif 719