1 // SPDX-License-Identifier: MIT
2 //
3 // Copyright 2024 Advanced Micro Devices, Inc.
4
5 #include "../dmub_srv.h"
6 #include "dmub_reg.h"
7 #include "dmub_dcn401.h"
8
9 #include "dcn/dcn_4_1_0_offset.h"
10 #include "dcn/dcn_4_1_0_sh_mask.h"
11
12 #define DCN_BASE__INST0_SEG2 0x000034C0
13
14 #define BASE_INNER(seg) DCN_BASE__INST0_SEG##seg
15 #define CTX dmub
16 #define REGS dmub->regs_dcn401
17 #define REG_OFFSET_EXP(reg_name) (BASE(reg##reg_name##_BASE_IDX) + reg##reg_name)
18
19 const struct dmub_srv_dcn401_regs dmub_srv_dcn401_regs = {
20 #define DMUB_SR(reg) REG_OFFSET_EXP(reg),
21 {
22 DMUB_DCN401_REGS()
23 DMCUB_INTERNAL_REGS()
24 },
25 #undef DMUB_SR
26
27 #define DMUB_SF(reg, field) FD_MASK(reg, field),
28 { DMUB_DCN401_FIELDS() },
29 #undef DMUB_SF
30
31 #define DMUB_SF(reg, field) FD_SHIFT(reg, field),
32 { DMUB_DCN401_FIELDS() },
33 #undef DMUB_SF
34 };
35
dmub_dcn401_get_fb_base_offset(struct dmub_srv * dmub,uint64_t * fb_base,uint64_t * fb_offset)36 static void dmub_dcn401_get_fb_base_offset(struct dmub_srv *dmub,
37 uint64_t *fb_base,
38 uint64_t *fb_offset)
39 {
40 uint32_t tmp;
41
42 if (dmub->fb_base || dmub->fb_offset) {
43 *fb_base = dmub->fb_base;
44 *fb_offset = dmub->fb_offset;
45 return;
46 }
47
48 REG_GET(DCN_VM_FB_LOCATION_BASE, FB_BASE, &tmp);
49 *fb_base = (uint64_t)tmp << 24;
50
51 REG_GET(DCN_VM_FB_OFFSET, FB_OFFSET, &tmp);
52 *fb_offset = (uint64_t)tmp << 24;
53 }
54
dmub_dcn401_translate_addr(const union dmub_addr * addr_in,uint64_t fb_base,uint64_t fb_offset,union dmub_addr * addr_out)55 static inline void dmub_dcn401_translate_addr(const union dmub_addr *addr_in,
56 uint64_t fb_base,
57 uint64_t fb_offset,
58 union dmub_addr *addr_out)
59 {
60 addr_out->quad_part = addr_in->quad_part - fb_base + fb_offset;
61 }
62
dmub_dcn401_reset(struct dmub_srv * dmub)63 void dmub_dcn401_reset(struct dmub_srv *dmub)
64 {
65 union dmub_gpint_data_register cmd;
66 const uint32_t timeout_us = 1 * 1000 * 1000; //1s
67 const uint32_t poll_delay_us = 1; //1us
68 uint32_t i = 0;
69 uint32_t enabled, in_reset, scratch, pwait_mode;
70
71 REG_GET(DMCUB_CNTL,
72 DMCUB_ENABLE, &enabled);
73 REG_GET(DMCUB_CNTL2,
74 DMCUB_SOFT_RESET, &in_reset);
75
76 if (enabled && in_reset == 0) {
77 cmd.bits.status = 1;
78 cmd.bits.command_code = DMUB_GPINT__STOP_FW;
79 cmd.bits.param = 0;
80
81 dmub->hw_funcs.set_gpint(dmub, cmd);
82
83 for (; i < timeout_us; i++) {
84 scratch = dmub->hw_funcs.get_gpint_response(dmub);
85 if (scratch == DMUB_GPINT__STOP_FW_RESPONSE)
86 break;
87
88 udelay(poll_delay_us);
89 }
90
91 for (; i < timeout_us; i++) {
92 REG_GET(DMCUB_CNTL, DMCUB_PWAIT_MODE_STATUS, &pwait_mode);
93 if (pwait_mode & (1 << 0))
94 break;
95
96 udelay(poll_delay_us);
97 }
98 }
99
100 if (i >= timeout_us) {
101 /* timeout should never occur */
102 BREAK_TO_DEBUGGER();
103 }
104
105 REG_WRITE(DMCUB_INBOX1_RPTR, 0);
106 REG_WRITE(DMCUB_INBOX1_WPTR, 0);
107 REG_WRITE(DMCUB_OUTBOX1_RPTR, 0);
108 REG_WRITE(DMCUB_OUTBOX1_WPTR, 0);
109 REG_WRITE(DMCUB_OUTBOX0_RPTR, 0);
110 REG_WRITE(DMCUB_OUTBOX0_WPTR, 0);
111 REG_WRITE(DMCUB_SCRATCH0, 0);
112
113 /* Clear the GPINT command manually so we don't reset again. */
114 cmd.all = 0;
115 dmub->hw_funcs.set_gpint(dmub, cmd);
116 }
117
dmub_dcn401_reset_release(struct dmub_srv * dmub)118 void dmub_dcn401_reset_release(struct dmub_srv *dmub)
119 {
120 REG_UPDATE(MMHUBBUB_SOFT_RESET, DMUIF_SOFT_RESET, 0);
121 REG_WRITE(DMCUB_SCRATCH15, dmub->psp_version & 0x001100FF);
122 REG_UPDATE_2(DMCUB_CNTL, DMCUB_ENABLE, 1, DMCUB_TRACEPORT_EN, 1);
123 REG_UPDATE(DMCUB_CNTL2, DMCUB_SOFT_RESET, 0);
124 }
125
dmub_dcn401_backdoor_load(struct dmub_srv * dmub,const struct dmub_window * cw0,const struct dmub_window * cw1)126 void dmub_dcn401_backdoor_load(struct dmub_srv *dmub,
127 const struct dmub_window *cw0,
128 const struct dmub_window *cw1)
129 {
130 union dmub_addr offset;
131 uint64_t fb_base, fb_offset;
132
133 dmub_dcn401_get_fb_base_offset(dmub, &fb_base, &fb_offset);
134
135 /* reset and disable DMCUB and MMHUBBUB DMUIF */
136 REG_UPDATE(DMCUB_SEC_CNTL, DMCUB_SEC_RESET, 1);
137 REG_UPDATE(MMHUBBUB_SOFT_RESET, DMUIF_SOFT_RESET, 1);
138 REG_UPDATE(DMCUB_CNTL, DMCUB_ENABLE, 0);
139
140 dmub_dcn401_translate_addr(&cw0->offset, fb_base, fb_offset, &offset);
141
142 REG_WRITE(DMCUB_REGION3_CW0_OFFSET, offset.u.low_part);
143 REG_WRITE(DMCUB_REGION3_CW0_OFFSET_HIGH, offset.u.high_part);
144 REG_WRITE(DMCUB_REGION3_CW0_BASE_ADDRESS, cw0->region.base);
145 REG_SET_2(DMCUB_REGION3_CW0_TOP_ADDRESS, 0,
146 DMCUB_REGION3_CW0_TOP_ADDRESS, cw0->region.top,
147 DMCUB_REGION3_CW0_ENABLE, 1);
148
149 dmub_dcn401_translate_addr(&cw1->offset, fb_base, fb_offset, &offset);
150
151 REG_WRITE(DMCUB_REGION3_CW1_OFFSET, offset.u.low_part);
152 REG_WRITE(DMCUB_REGION3_CW1_OFFSET_HIGH, offset.u.high_part);
153 REG_WRITE(DMCUB_REGION3_CW1_BASE_ADDRESS, cw1->region.base);
154 REG_SET_2(DMCUB_REGION3_CW1_TOP_ADDRESS, 0,
155 DMCUB_REGION3_CW1_TOP_ADDRESS, cw1->region.top,
156 DMCUB_REGION3_CW1_ENABLE, 1);
157
158 /* release DMCUB reset only to prevent premature execution */
159 REG_UPDATE_2(DMCUB_SEC_CNTL, DMCUB_SEC_RESET, 0, DMCUB_MEM_UNIT_ID,
160 0x20);
161 }
162
dmub_dcn401_backdoor_load_zfb_mode(struct dmub_srv * dmub,const struct dmub_window * cw0,const struct dmub_window * cw1)163 void dmub_dcn401_backdoor_load_zfb_mode(struct dmub_srv *dmub,
164 const struct dmub_window *cw0,
165 const struct dmub_window *cw1)
166 {
167 union dmub_addr offset;
168
169 /* reset and disable DMCUB and MMHUBBUB DMUIF */
170 REG_UPDATE(DMCUB_SEC_CNTL, DMCUB_SEC_RESET, 1);
171 REG_UPDATE(MMHUBBUB_SOFT_RESET, DMUIF_SOFT_RESET, 1);
172 REG_UPDATE(DMCUB_CNTL, DMCUB_ENABLE, 0);
173
174 offset = cw0->offset;
175
176 REG_WRITE(DMCUB_REGION3_CW0_OFFSET, offset.u.low_part);
177 REG_WRITE(DMCUB_REGION3_CW0_OFFSET_HIGH, offset.u.high_part);
178 REG_WRITE(DMCUB_REGION3_CW0_BASE_ADDRESS, cw0->region.base);
179 REG_SET_2(DMCUB_REGION3_CW0_TOP_ADDRESS, 0,
180 DMCUB_REGION3_CW0_TOP_ADDRESS, cw0->region.top,
181 DMCUB_REGION3_CW0_ENABLE, 1);
182
183 offset = cw1->offset;
184
185 REG_WRITE(DMCUB_REGION3_CW1_OFFSET, offset.u.low_part);
186 REG_WRITE(DMCUB_REGION3_CW1_OFFSET_HIGH, offset.u.high_part);
187 REG_WRITE(DMCUB_REGION3_CW1_BASE_ADDRESS, cw1->region.base);
188 REG_SET_2(DMCUB_REGION3_CW1_TOP_ADDRESS, 0,
189 DMCUB_REGION3_CW1_TOP_ADDRESS, cw1->region.top,
190 DMCUB_REGION3_CW1_ENABLE, 1);
191
192 /* release DMCUB reset only to prevent premature execution */
193 REG_UPDATE_2(DMCUB_SEC_CNTL, DMCUB_SEC_RESET, 0, DMCUB_MEM_UNIT_ID,
194 0x20);
195 }
196
dmub_dcn401_setup_windows(struct dmub_srv * dmub,const struct dmub_window * cw2,const struct dmub_window * cw3,const struct dmub_window * cw4,const struct dmub_window * cw5,const struct dmub_window * cw6,const struct dmub_window * region6)197 void dmub_dcn401_setup_windows(struct dmub_srv *dmub,
198 const struct dmub_window *cw2,
199 const struct dmub_window *cw3,
200 const struct dmub_window *cw4,
201 const struct dmub_window *cw5,
202 const struct dmub_window *cw6,
203 const struct dmub_window *region6)
204 {
205 union dmub_addr offset;
206
207 offset = cw3->offset;
208
209 REG_WRITE(DMCUB_REGION3_CW3_OFFSET, offset.u.low_part);
210 REG_WRITE(DMCUB_REGION3_CW3_OFFSET_HIGH, offset.u.high_part);
211 REG_WRITE(DMCUB_REGION3_CW3_BASE_ADDRESS, cw3->region.base);
212 REG_SET_2(DMCUB_REGION3_CW3_TOP_ADDRESS, 0,
213 DMCUB_REGION3_CW3_TOP_ADDRESS, cw3->region.top,
214 DMCUB_REGION3_CW3_ENABLE, 1);
215
216 offset = cw4->offset;
217
218 REG_WRITE(DMCUB_REGION3_CW4_OFFSET, offset.u.low_part);
219 REG_WRITE(DMCUB_REGION3_CW4_OFFSET_HIGH, offset.u.high_part);
220 REG_WRITE(DMCUB_REGION3_CW4_BASE_ADDRESS, cw4->region.base);
221 REG_SET_2(DMCUB_REGION3_CW4_TOP_ADDRESS, 0,
222 DMCUB_REGION3_CW4_TOP_ADDRESS, cw4->region.top,
223 DMCUB_REGION3_CW4_ENABLE, 1);
224
225 offset = cw5->offset;
226
227 REG_WRITE(DMCUB_REGION3_CW5_OFFSET, offset.u.low_part);
228 REG_WRITE(DMCUB_REGION3_CW5_OFFSET_HIGH, offset.u.high_part);
229 REG_WRITE(DMCUB_REGION3_CW5_BASE_ADDRESS, cw5->region.base);
230 REG_SET_2(DMCUB_REGION3_CW5_TOP_ADDRESS, 0,
231 DMCUB_REGION3_CW5_TOP_ADDRESS, cw5->region.top,
232 DMCUB_REGION3_CW5_ENABLE, 1);
233
234 REG_WRITE(DMCUB_REGION5_OFFSET, offset.u.low_part);
235 REG_WRITE(DMCUB_REGION5_OFFSET_HIGH, offset.u.high_part);
236 REG_SET_2(DMCUB_REGION5_TOP_ADDRESS, 0,
237 DMCUB_REGION5_TOP_ADDRESS,
238 cw5->region.top - cw5->region.base - 1,
239 DMCUB_REGION5_ENABLE, 1);
240
241 offset = cw6->offset;
242
243 REG_WRITE(DMCUB_REGION3_CW6_OFFSET, offset.u.low_part);
244 REG_WRITE(DMCUB_REGION3_CW6_OFFSET_HIGH, offset.u.high_part);
245 REG_WRITE(DMCUB_REGION3_CW6_BASE_ADDRESS, cw6->region.base);
246 REG_SET_2(DMCUB_REGION3_CW6_TOP_ADDRESS, 0,
247 DMCUB_REGION3_CW6_TOP_ADDRESS, cw6->region.top,
248 DMCUB_REGION3_CW6_ENABLE, 1);
249
250 offset = region6->offset;
251
252 REG_WRITE(DMCUB_REGION6_OFFSET, offset.u.low_part);
253 REG_WRITE(DMCUB_REGION6_OFFSET_HIGH, offset.u.high_part);
254 REG_SET_2(DMCUB_REGION6_TOP_ADDRESS, 0,
255 DMCUB_REGION6_TOP_ADDRESS,
256 region6->region.top - region6->region.base - 1,
257 DMCUB_REGION6_ENABLE, 1);
258 }
259
dmub_dcn401_setup_mailbox(struct dmub_srv * dmub,const struct dmub_region * inbox1)260 void dmub_dcn401_setup_mailbox(struct dmub_srv *dmub,
261 const struct dmub_region *inbox1)
262 {
263 REG_WRITE(DMCUB_INBOX1_BASE_ADDRESS, inbox1->base);
264 REG_WRITE(DMCUB_INBOX1_SIZE, inbox1->top - inbox1->base);
265 }
266
dmub_dcn401_get_inbox1_wptr(struct dmub_srv * dmub)267 uint32_t dmub_dcn401_get_inbox1_wptr(struct dmub_srv *dmub)
268 {
269 return REG_READ(DMCUB_INBOX1_WPTR);
270 }
271
dmub_dcn401_get_inbox1_rptr(struct dmub_srv * dmub)272 uint32_t dmub_dcn401_get_inbox1_rptr(struct dmub_srv *dmub)
273 {
274 return REG_READ(DMCUB_INBOX1_RPTR);
275 }
276
dmub_dcn401_set_inbox1_wptr(struct dmub_srv * dmub,uint32_t wptr_offset)277 void dmub_dcn401_set_inbox1_wptr(struct dmub_srv *dmub, uint32_t wptr_offset)
278 {
279 REG_WRITE(DMCUB_INBOX1_WPTR, wptr_offset);
280 }
281
dmub_dcn401_setup_out_mailbox(struct dmub_srv * dmub,const struct dmub_region * outbox1)282 void dmub_dcn401_setup_out_mailbox(struct dmub_srv *dmub,
283 const struct dmub_region *outbox1)
284 {
285 REG_WRITE(DMCUB_OUTBOX1_BASE_ADDRESS, outbox1->base);
286 REG_WRITE(DMCUB_OUTBOX1_SIZE, outbox1->top - outbox1->base);
287 }
288
dmub_dcn401_get_outbox1_wptr(struct dmub_srv * dmub)289 uint32_t dmub_dcn401_get_outbox1_wptr(struct dmub_srv *dmub)
290 {
291 /**
292 * outbox1 wptr register is accessed without locks (dal & dc)
293 * and to be called only by dmub_srv_stat_get_notification()
294 */
295 return REG_READ(DMCUB_OUTBOX1_WPTR);
296 }
297
dmub_dcn401_set_outbox1_rptr(struct dmub_srv * dmub,uint32_t rptr_offset)298 void dmub_dcn401_set_outbox1_rptr(struct dmub_srv *dmub, uint32_t rptr_offset)
299 {
300 /**
301 * outbox1 rptr register is accessed without locks (dal & dc)
302 * and to be called only by dmub_srv_stat_get_notification()
303 */
304 REG_WRITE(DMCUB_OUTBOX1_RPTR, rptr_offset);
305 }
306
dmub_dcn401_is_hw_init(struct dmub_srv * dmub)307 bool dmub_dcn401_is_hw_init(struct dmub_srv *dmub)
308 {
309 union dmub_fw_boot_status status;
310 uint32_t is_hw_init;
311
312 status.all = REG_READ(DMCUB_SCRATCH0);
313 REG_GET(DMCUB_CNTL, DMCUB_ENABLE, &is_hw_init);
314
315 return is_hw_init != 0 && status.bits.dal_fw;
316 }
317
dmub_dcn401_is_supported(struct dmub_srv * dmub)318 bool dmub_dcn401_is_supported(struct dmub_srv *dmub)
319 {
320 uint32_t supported = 0;
321
322 REG_GET(CC_DC_PIPE_DIS, DC_DMCUB_ENABLE, &supported);
323
324 return supported;
325 }
326
dmub_dcn401_set_gpint(struct dmub_srv * dmub,union dmub_gpint_data_register reg)327 void dmub_dcn401_set_gpint(struct dmub_srv *dmub,
328 union dmub_gpint_data_register reg)
329 {
330 REG_WRITE(DMCUB_GPINT_DATAIN1, reg.all);
331 }
332
dmub_dcn401_is_gpint_acked(struct dmub_srv * dmub,union dmub_gpint_data_register reg)333 bool dmub_dcn401_is_gpint_acked(struct dmub_srv *dmub,
334 union dmub_gpint_data_register reg)
335 {
336 union dmub_gpint_data_register test;
337
338 reg.bits.status = 0;
339 test.all = REG_READ(DMCUB_GPINT_DATAIN1);
340
341 return test.all == reg.all;
342 }
343
dmub_dcn401_get_gpint_response(struct dmub_srv * dmub)344 uint32_t dmub_dcn401_get_gpint_response(struct dmub_srv *dmub)
345 {
346 return REG_READ(DMCUB_SCRATCH7);
347 }
348
dmub_dcn401_get_gpint_dataout(struct dmub_srv * dmub)349 uint32_t dmub_dcn401_get_gpint_dataout(struct dmub_srv *dmub)
350 {
351 uint32_t dataout = REG_READ(DMCUB_GPINT_DATAOUT);
352
353 REG_UPDATE(DMCUB_INTERRUPT_ENABLE, DMCUB_GPINT_IH_INT_EN, 0);
354
355 REG_WRITE(DMCUB_GPINT_DATAOUT, 0);
356 REG_UPDATE(DMCUB_INTERRUPT_ACK, DMCUB_GPINT_IH_INT_ACK, 1);
357 REG_UPDATE(DMCUB_INTERRUPT_ACK, DMCUB_GPINT_IH_INT_ACK, 0);
358
359 REG_UPDATE(DMCUB_INTERRUPT_ENABLE, DMCUB_GPINT_IH_INT_EN, 1);
360
361 return dataout;
362 }
363
dmub_dcn401_get_fw_boot_status(struct dmub_srv * dmub)364 union dmub_fw_boot_status dmub_dcn401_get_fw_boot_status(struct dmub_srv *dmub)
365 {
366 union dmub_fw_boot_status status;
367
368 status.all = REG_READ(DMCUB_SCRATCH0);
369 return status;
370 }
371
dmub_dcn401_enable_dmub_boot_options(struct dmub_srv * dmub,const struct dmub_srv_hw_params * params)372 void dmub_dcn401_enable_dmub_boot_options(struct dmub_srv *dmub, const struct dmub_srv_hw_params *params)
373 {
374 union dmub_fw_boot_options boot_options = {0};
375
376 boot_options.bits.z10_disable = params->disable_z10;
377
378 boot_options.bits.skip_phy_access = params->disallow_phy_access;
379
380 REG_WRITE(DMCUB_SCRATCH14, boot_options.all);
381 }
382
dmub_dcn401_skip_dmub_panel_power_sequence(struct dmub_srv * dmub,bool skip)383 void dmub_dcn401_skip_dmub_panel_power_sequence(struct dmub_srv *dmub, bool skip)
384 {
385 union dmub_fw_boot_options boot_options;
386 boot_options.all = REG_READ(DMCUB_SCRATCH14);
387 boot_options.bits.skip_phy_init_panel_sequence = skip;
388 REG_WRITE(DMCUB_SCRATCH14, boot_options.all);
389 }
390
dmub_dcn401_setup_outbox0(struct dmub_srv * dmub,const struct dmub_region * outbox0)391 void dmub_dcn401_setup_outbox0(struct dmub_srv *dmub,
392 const struct dmub_region *outbox0)
393 {
394 REG_WRITE(DMCUB_OUTBOX0_BASE_ADDRESS, outbox0->base);
395
396 REG_WRITE(DMCUB_OUTBOX0_SIZE, outbox0->top - outbox0->base);
397 }
398
dmub_dcn401_get_outbox0_wptr(struct dmub_srv * dmub)399 uint32_t dmub_dcn401_get_outbox0_wptr(struct dmub_srv *dmub)
400 {
401 return REG_READ(DMCUB_OUTBOX0_WPTR);
402 }
403
dmub_dcn401_set_outbox0_rptr(struct dmub_srv * dmub,uint32_t rptr_offset)404 void dmub_dcn401_set_outbox0_rptr(struct dmub_srv *dmub, uint32_t rptr_offset)
405 {
406 REG_WRITE(DMCUB_OUTBOX0_RPTR, rptr_offset);
407 }
408
dmub_dcn401_get_current_time(struct dmub_srv * dmub)409 uint32_t dmub_dcn401_get_current_time(struct dmub_srv *dmub)
410 {
411 return REG_READ(DMCUB_TIMER_CURRENT);
412 }
413
dmub_dcn401_get_diagnostic_data(struct dmub_srv * dmub)414 void dmub_dcn401_get_diagnostic_data(struct dmub_srv *dmub)
415 {
416 uint32_t is_dmub_enabled, is_soft_reset, is_sec_reset, is_pwait;
417 uint32_t is_traceport_enabled, is_cw0_enabled, is_cw6_enabled;
418 struct dmub_timeout_info timeout = {0};
419
420 if (!dmub)
421 return;
422
423 /* timeout data filled externally, cache before resetting memory */
424 timeout = dmub->debug.timeout_info;
425 memset(&dmub->debug, 0, sizeof(dmub->debug));
426 dmub->debug.timeout_info = timeout;
427
428 dmub->debug.dmcub_version = dmub->fw_version;
429
430 dmub->debug.scratch[0] = REG_READ(DMCUB_SCRATCH0);
431 dmub->debug.scratch[1] = REG_READ(DMCUB_SCRATCH1);
432 dmub->debug.scratch[2] = REG_READ(DMCUB_SCRATCH2);
433 dmub->debug.scratch[3] = REG_READ(DMCUB_SCRATCH3);
434 dmub->debug.scratch[4] = REG_READ(DMCUB_SCRATCH4);
435 dmub->debug.scratch[5] = REG_READ(DMCUB_SCRATCH5);
436 dmub->debug.scratch[6] = REG_READ(DMCUB_SCRATCH6);
437 dmub->debug.scratch[7] = REG_READ(DMCUB_SCRATCH7);
438 dmub->debug.scratch[8] = REG_READ(DMCUB_SCRATCH8);
439 dmub->debug.scratch[9] = REG_READ(DMCUB_SCRATCH9);
440 dmub->debug.scratch[10] = REG_READ(DMCUB_SCRATCH10);
441 dmub->debug.scratch[11] = REG_READ(DMCUB_SCRATCH11);
442 dmub->debug.scratch[12] = REG_READ(DMCUB_SCRATCH12);
443 dmub->debug.scratch[13] = REG_READ(DMCUB_SCRATCH13);
444 dmub->debug.scratch[14] = REG_READ(DMCUB_SCRATCH14);
445 dmub->debug.scratch[15] = REG_READ(DMCUB_SCRATCH15);
446 dmub->debug.scratch[16] = REG_READ(DMCUB_SCRATCH16);
447
448 dmub->debug.undefined_address_fault_addr = REG_READ(DMCUB_UNDEFINED_ADDRESS_FAULT_ADDR);
449 dmub->debug.inst_fetch_fault_addr = REG_READ(DMCUB_INST_FETCH_FAULT_ADDR);
450 dmub->debug.data_write_fault_addr = REG_READ(DMCUB_DATA_WRITE_FAULT_ADDR);
451
452 dmub->debug.inbox1_rptr = REG_READ(DMCUB_INBOX1_RPTR);
453 dmub->debug.inbox1_wptr = REG_READ(DMCUB_INBOX1_WPTR);
454 dmub->debug.inbox1_size = REG_READ(DMCUB_INBOX1_SIZE);
455
456 dmub->debug.inbox0_rptr = REG_READ(DMCUB_INBOX0_RPTR);
457 dmub->debug.inbox0_wptr = REG_READ(DMCUB_INBOX0_WPTR);
458 dmub->debug.inbox0_size = REG_READ(DMCUB_INBOX0_SIZE);
459
460 dmub->debug.outbox1_rptr = REG_READ(DMCUB_OUTBOX1_RPTR);
461 dmub->debug.outbox1_wptr = REG_READ(DMCUB_OUTBOX1_WPTR);
462 dmub->debug.outbox1_size = REG_READ(DMCUB_OUTBOX1_SIZE);
463
464 REG_GET(DMCUB_CNTL, DMCUB_ENABLE, &is_dmub_enabled);
465 dmub->debug.is_dmcub_enabled = is_dmub_enabled;
466
467 REG_GET(DMCUB_CNTL, DMCUB_PWAIT_MODE_STATUS, &is_pwait);
468 dmub->debug.is_pwait = is_pwait;
469
470 REG_GET(DMCUB_CNTL2, DMCUB_SOFT_RESET, &is_soft_reset);
471 dmub->debug.is_dmcub_soft_reset = is_soft_reset;
472
473 REG_GET(DMCUB_SEC_CNTL, DMCUB_SEC_RESET_STATUS, &is_sec_reset);
474 dmub->debug.is_dmcub_secure_reset = is_sec_reset;
475
476 REG_GET(DMCUB_CNTL, DMCUB_TRACEPORT_EN, &is_traceport_enabled);
477 dmub->debug.is_traceport_en = is_traceport_enabled;
478
479 REG_GET(DMCUB_REGION3_CW0_TOP_ADDRESS, DMCUB_REGION3_CW0_ENABLE, &is_cw0_enabled);
480 dmub->debug.is_cw0_enabled = is_cw0_enabled;
481
482 REG_GET(DMCUB_REGION3_CW6_TOP_ADDRESS, DMCUB_REGION3_CW6_ENABLE, &is_cw6_enabled);
483 dmub->debug.is_cw6_enabled = is_cw6_enabled;
484
485 dmub->debug.gpint_datain0 = REG_READ(DMCUB_GPINT_DATAIN0);
486 }
dmub_dcn401_configure_dmub_in_system_memory(struct dmub_srv * dmub)487 void dmub_dcn401_configure_dmub_in_system_memory(struct dmub_srv *dmub)
488 {
489 /* DMCUB_REGION3_TMR_AXI_SPACE values:
490 * 0b011 (0x3) - FB physical address
491 * 0b100 (0x4) - GPU virtual address
492 *
493 * Default value is 0x3 (FB Physical address for TMR). When programming
494 * DMUB to be in system memory, change to 0x4. The system memory allocated
495 * is accessible by both GPU and CPU, so we use GPU virtual address.
496 */
497 REG_WRITE(DMCUB_REGION3_TMR_AXI_SPACE, 0x4);
498 }
499
dmub_dcn401_send_inbox0_cmd(struct dmub_srv * dmub,union dmub_inbox0_data_register data)500 void dmub_dcn401_send_inbox0_cmd(struct dmub_srv *dmub, union dmub_inbox0_data_register data)
501 {
502 REG_WRITE(DMCUB_INBOX0_WPTR, data.inbox0_cmd_common.all);
503 }
504
dmub_dcn401_clear_inbox0_ack_register(struct dmub_srv * dmub)505 void dmub_dcn401_clear_inbox0_ack_register(struct dmub_srv *dmub)
506 {
507 REG_WRITE(DMCUB_SCRATCH17, 0);
508 }
509
dmub_dcn401_read_inbox0_ack_register(struct dmub_srv * dmub)510 uint32_t dmub_dcn401_read_inbox0_ack_register(struct dmub_srv *dmub)
511 {
512 return REG_READ(DMCUB_SCRATCH17);
513 }
514
dmub_dcn401_send_reg_inbox0_cmd_msg(struct dmub_srv * dmub,union dmub_rb_cmd * cmd)515 void dmub_dcn401_send_reg_inbox0_cmd_msg(struct dmub_srv *dmub,
516 union dmub_rb_cmd *cmd)
517 {
518 uint32_t *dwords = (uint32_t *)cmd;
519 int32_t payload_size_bytes = cmd->cmd_common.header.payload_bytes;
520 uint32_t msg_index;
521 static_assert(sizeof(*cmd) == 64, "DMUB command size mismatch");
522
523 /* read remaining data based on payload size */
524 for (msg_index = 0; msg_index < 15; msg_index++) {
525 if (payload_size_bytes <= msg_index * 4) {
526 break;
527 }
528
529 switch (msg_index) {
530 case 0:
531 REG_WRITE(DMCUB_REG_INBOX0_MSG0, dwords[msg_index + 1]);
532 break;
533 case 1:
534 REG_WRITE(DMCUB_REG_INBOX0_MSG1, dwords[msg_index + 1]);
535 break;
536 case 2:
537 REG_WRITE(DMCUB_REG_INBOX0_MSG2, dwords[msg_index + 1]);
538 break;
539 case 3:
540 REG_WRITE(DMCUB_REG_INBOX0_MSG3, dwords[msg_index + 1]);
541 break;
542 case 4:
543 REG_WRITE(DMCUB_REG_INBOX0_MSG4, dwords[msg_index + 1]);
544 break;
545 case 5:
546 REG_WRITE(DMCUB_REG_INBOX0_MSG5, dwords[msg_index + 1]);
547 break;
548 case 6:
549 REG_WRITE(DMCUB_REG_INBOX0_MSG6, dwords[msg_index + 1]);
550 break;
551 case 7:
552 REG_WRITE(DMCUB_REG_INBOX0_MSG7, dwords[msg_index + 1]);
553 break;
554 case 8:
555 REG_WRITE(DMCUB_REG_INBOX0_MSG8, dwords[msg_index + 1]);
556 break;
557 case 9:
558 REG_WRITE(DMCUB_REG_INBOX0_MSG9, dwords[msg_index + 1]);
559 break;
560 case 10:
561 REG_WRITE(DMCUB_REG_INBOX0_MSG10, dwords[msg_index + 1]);
562 break;
563 case 11:
564 REG_WRITE(DMCUB_REG_INBOX0_MSG11, dwords[msg_index + 1]);
565 break;
566 case 12:
567 REG_WRITE(DMCUB_REG_INBOX0_MSG12, dwords[msg_index + 1]);
568 break;
569 case 13:
570 REG_WRITE(DMCUB_REG_INBOX0_MSG13, dwords[msg_index + 1]);
571 break;
572 case 14:
573 REG_WRITE(DMCUB_REG_INBOX0_MSG14, dwords[msg_index + 1]);
574 break;
575 }
576 }
577
578 /* writing to INBOX RDY register will trigger DMUB REG INBOX0 RDY
579 * interrupt.
580 */
581 REG_WRITE(DMCUB_REG_INBOX0_RDY, dwords[0]);
582 }
583
dmub_dcn401_read_reg_inbox0_rsp_int_status(struct dmub_srv * dmub)584 uint32_t dmub_dcn401_read_reg_inbox0_rsp_int_status(struct dmub_srv *dmub)
585 {
586 uint32_t status;
587
588 REG_GET(HOST_INTERRUPT_CSR, HOST_REG_INBOX0_RSP_INT_STAT, &status);
589 return status;
590 }
591
dmub_dcn401_read_reg_inbox0_cmd_rsp(struct dmub_srv * dmub,union dmub_rb_cmd * cmd)592 void dmub_dcn401_read_reg_inbox0_cmd_rsp(struct dmub_srv *dmub,
593 union dmub_rb_cmd *cmd)
594 {
595 uint32_t *dwords = (uint32_t *)cmd;
596
597 static_assert(sizeof(*cmd) == 64, "DMUB command size mismatch");
598
599 dwords[0] = REG_READ(DMCUB_REG_INBOX0_RSP);
600 dwords[1] = REG_READ(DMCUB_REG_INBOX0_MSG0);
601 dwords[2] = REG_READ(DMCUB_REG_INBOX0_MSG1);
602 dwords[3] = REG_READ(DMCUB_REG_INBOX0_MSG2);
603 dwords[4] = REG_READ(DMCUB_REG_INBOX0_MSG3);
604 dwords[5] = REG_READ(DMCUB_REG_INBOX0_MSG4);
605 dwords[6] = REG_READ(DMCUB_REG_INBOX0_MSG5);
606 dwords[7] = REG_READ(DMCUB_REG_INBOX0_MSG6);
607 dwords[8] = REG_READ(DMCUB_REG_INBOX0_MSG7);
608 dwords[9] = REG_READ(DMCUB_REG_INBOX0_MSG8);
609 dwords[10] = REG_READ(DMCUB_REG_INBOX0_MSG9);
610 dwords[11] = REG_READ(DMCUB_REG_INBOX0_MSG10);
611 dwords[12] = REG_READ(DMCUB_REG_INBOX0_MSG11);
612 dwords[13] = REG_READ(DMCUB_REG_INBOX0_MSG12);
613 dwords[14] = REG_READ(DMCUB_REG_INBOX0_MSG13);
614 dwords[15] = REG_READ(DMCUB_REG_INBOX0_MSG14);
615 }
616
dmub_dcn401_write_reg_inbox0_rsp_int_ack(struct dmub_srv * dmub)617 void dmub_dcn401_write_reg_inbox0_rsp_int_ack(struct dmub_srv *dmub)
618 {
619 REG_UPDATE(HOST_INTERRUPT_CSR, HOST_REG_INBOX0_RSP_INT_ACK, 1);
620 }
621
dmub_dcn401_clear_reg_inbox0_rsp_int_ack(struct dmub_srv * dmub)622 void dmub_dcn401_clear_reg_inbox0_rsp_int_ack(struct dmub_srv *dmub)
623 {
624 REG_UPDATE(HOST_INTERRUPT_CSR, HOST_REG_INBOX0_RSP_INT_ACK, 0);
625 }
626
dmub_dcn401_enable_reg_inbox0_rsp_int(struct dmub_srv * dmub,bool enable)627 void dmub_dcn401_enable_reg_inbox0_rsp_int(struct dmub_srv *dmub, bool enable)
628 {
629 REG_UPDATE(HOST_INTERRUPT_CSR, HOST_REG_INBOX0_RSP_INT_EN, enable ? 1:0);
630 }
631
dmub_dcn401_write_reg_outbox0_rdy_int_ack(struct dmub_srv * dmub)632 void dmub_dcn401_write_reg_outbox0_rdy_int_ack(struct dmub_srv *dmub)
633 {
634 REG_UPDATE(HOST_INTERRUPT_CSR, HOST_REG_OUTBOX0_RDY_INT_ACK, 1);
635 REG_UPDATE(HOST_INTERRUPT_CSR, HOST_REG_OUTBOX0_RDY_INT_ACK, 0);
636 }
637
dmub_dcn401_read_reg_outbox0_msg(struct dmub_srv * dmub,uint32_t * msg)638 void dmub_dcn401_read_reg_outbox0_msg(struct dmub_srv *dmub, uint32_t *msg)
639 {
640 *msg = REG_READ(DMCUB_REG_OUTBOX0_MSG0);
641 }
642
dmub_dcn401_write_reg_outbox0_rsp(struct dmub_srv * dmub,uint32_t * rsp)643 void dmub_dcn401_write_reg_outbox0_rsp(struct dmub_srv *dmub, uint32_t *rsp)
644 {
645 REG_WRITE(DMCUB_REG_OUTBOX0_RSP, *rsp);
646 }
647
dmub_dcn401_read_reg_outbox0_rsp_int_status(struct dmub_srv * dmub)648 uint32_t dmub_dcn401_read_reg_outbox0_rsp_int_status(struct dmub_srv *dmub)
649 {
650 uint32_t status;
651
652 REG_GET(DMCUB_INTERRUPT_STATUS, DMCUB_REG_OUTBOX0_RSP_INT_STAT, &status);
653 return status;
654 }
655
dmub_dcn401_enable_reg_outbox0_rdy_int(struct dmub_srv * dmub,bool enable)656 void dmub_dcn401_enable_reg_outbox0_rdy_int(struct dmub_srv *dmub, bool enable)
657 {
658 REG_UPDATE(HOST_INTERRUPT_CSR, HOST_REG_OUTBOX0_RDY_INT_EN, enable ? 1:0);
659 }
660
dmub_dcn401_read_reg_outbox0_rdy_int_status(struct dmub_srv * dmub)661 uint32_t dmub_dcn401_read_reg_outbox0_rdy_int_status(struct dmub_srv *dmub)
662 {
663 uint32_t status;
664
665 REG_GET(HOST_INTERRUPT_CSR, HOST_REG_OUTBOX0_RDY_INT_STAT, &status);
666 return status;
667 }
668