1 // SPDX-License-Identifier: MIT
2 //
3 // Copyright 2024 Advanced Micro Devices, Inc.
4
5 #include "../dmub_srv.h"
6 #include "dmub_reg.h"
7 #include "dmub_dcn401.h"
8
9 #include "dcn/dcn_4_1_0_offset.h"
10 #include "dcn/dcn_4_1_0_sh_mask.h"
11
12 #define DCN_BASE__INST0_SEG2 0x000034C0
13
14 #define BASE_INNER(seg) DCN_BASE__INST0_SEG##seg
15 #define CTX dmub
16 #define REGS dmub->regs_dcn401
17 #define REG_OFFSET_EXP(reg_name) (BASE(reg##reg_name##_BASE_IDX) + reg##reg_name)
18
19 const struct dmub_srv_dcn401_regs dmub_srv_dcn401_regs = {
20 #define DMUB_SR(reg) REG_OFFSET_EXP(reg),
21 {
22 DMUB_DCN401_REGS()
23 DMCUB_INTERNAL_REGS()
24 },
25 #undef DMUB_SR
26
27 #define DMUB_SF(reg, field) FD_MASK(reg, field),
28 { DMUB_DCN401_FIELDS() },
29 #undef DMUB_SF
30
31 #define DMUB_SF(reg, field) FD_SHIFT(reg, field),
32 { DMUB_DCN401_FIELDS() },
33 #undef DMUB_SF
34 };
35
dmub_dcn401_get_fb_base_offset(struct dmub_srv * dmub,uint64_t * fb_base,uint64_t * fb_offset)36 static void dmub_dcn401_get_fb_base_offset(struct dmub_srv *dmub,
37 uint64_t *fb_base,
38 uint64_t *fb_offset)
39 {
40 uint32_t tmp;
41
42 if (dmub->fb_base || dmub->fb_offset) {
43 *fb_base = dmub->fb_base;
44 *fb_offset = dmub->fb_offset;
45 return;
46 }
47
48 REG_GET(DCN_VM_FB_LOCATION_BASE, FB_BASE, &tmp);
49 *fb_base = (uint64_t)tmp << 24;
50
51 REG_GET(DCN_VM_FB_OFFSET, FB_OFFSET, &tmp);
52 *fb_offset = (uint64_t)tmp << 24;
53 }
54
dmub_dcn401_translate_addr(const union dmub_addr * addr_in,uint64_t fb_base,uint64_t fb_offset,union dmub_addr * addr_out)55 static inline void dmub_dcn401_translate_addr(const union dmub_addr *addr_in,
56 uint64_t fb_base,
57 uint64_t fb_offset,
58 union dmub_addr *addr_out)
59 {
60 addr_out->quad_part = addr_in->quad_part - fb_base + fb_offset;
61 }
62
dmub_dcn401_reset(struct dmub_srv * dmub)63 void dmub_dcn401_reset(struct dmub_srv *dmub)
64 {
65 union dmub_gpint_data_register cmd;
66 const uint32_t timeout_us = 1 * 1000 * 1000; //1s
67 const uint32_t poll_delay_us = 1; //1us
68 uint32_t i = 0;
69 uint32_t in_reset, scratch, pwait_mode;
70
71 REG_GET(DMCUB_CNTL2, DMCUB_SOFT_RESET, &in_reset);
72
73 if (in_reset == 0) {
74 cmd.bits.status = 1;
75 cmd.bits.command_code = DMUB_GPINT__STOP_FW;
76 cmd.bits.param = 0;
77
78 dmub->hw_funcs.set_gpint(dmub, cmd);
79
80 for (i = 0; i < timeout_us; i++) {
81 if (dmub->hw_funcs.is_gpint_acked(dmub, cmd))
82 break;
83
84 udelay(poll_delay_us);
85 }
86
87 for (; i < timeout_us; i++) {
88 scratch = dmub->hw_funcs.get_gpint_response(dmub);
89 if (scratch == DMUB_GPINT__STOP_FW_RESPONSE)
90 break;
91
92 udelay(poll_delay_us);
93 }
94
95 for (; i < timeout_us; i++) {
96 REG_GET(DMCUB_CNTL, DMCUB_PWAIT_MODE_STATUS, &pwait_mode);
97 if (pwait_mode & (1 << 0))
98 break;
99
100 udelay(poll_delay_us);
101 }
102 }
103
104 if (i >= timeout_us) {
105 /* timeout should never occur */
106 BREAK_TO_DEBUGGER();
107 }
108
109 REG_WRITE(DMCUB_INBOX1_RPTR, 0);
110 REG_WRITE(DMCUB_INBOX1_WPTR, 0);
111 REG_WRITE(DMCUB_OUTBOX1_RPTR, 0);
112 REG_WRITE(DMCUB_OUTBOX1_WPTR, 0);
113 REG_WRITE(DMCUB_OUTBOX0_RPTR, 0);
114 REG_WRITE(DMCUB_OUTBOX0_WPTR, 0);
115 REG_WRITE(DMCUB_SCRATCH0, 0);
116
117 /* Clear the GPINT command manually so we don't reset again. */
118 cmd.all = 0;
119 dmub->hw_funcs.set_gpint(dmub, cmd);
120 }
121
dmub_dcn401_reset_release(struct dmub_srv * dmub)122 void dmub_dcn401_reset_release(struct dmub_srv *dmub)
123 {
124 REG_UPDATE(MMHUBBUB_SOFT_RESET, DMUIF_SOFT_RESET, 0);
125 REG_WRITE(DMCUB_SCRATCH15, dmub->psp_version & 0x001100FF);
126 REG_UPDATE_2(DMCUB_CNTL, DMCUB_ENABLE, 1, DMCUB_TRACEPORT_EN, 1);
127 REG_UPDATE(DMCUB_CNTL2, DMCUB_SOFT_RESET, 0);
128 }
129
dmub_dcn401_backdoor_load(struct dmub_srv * dmub,const struct dmub_window * cw0,const struct dmub_window * cw1)130 void dmub_dcn401_backdoor_load(struct dmub_srv *dmub,
131 const struct dmub_window *cw0,
132 const struct dmub_window *cw1)
133 {
134 union dmub_addr offset;
135 uint64_t fb_base, fb_offset;
136
137 dmub_dcn401_get_fb_base_offset(dmub, &fb_base, &fb_offset);
138
139 /* reset and disable DMCUB and MMHUBBUB DMUIF */
140 REG_UPDATE(DMCUB_SEC_CNTL, DMCUB_SEC_RESET, 1);
141 REG_UPDATE(MMHUBBUB_SOFT_RESET, DMUIF_SOFT_RESET, 1);
142 REG_UPDATE(DMCUB_CNTL, DMCUB_ENABLE, 0);
143
144 dmub_dcn401_translate_addr(&cw0->offset, fb_base, fb_offset, &offset);
145
146 REG_WRITE(DMCUB_REGION3_CW0_OFFSET, offset.u.low_part);
147 REG_WRITE(DMCUB_REGION3_CW0_OFFSET_HIGH, offset.u.high_part);
148 REG_WRITE(DMCUB_REGION3_CW0_BASE_ADDRESS, cw0->region.base);
149 REG_SET_2(DMCUB_REGION3_CW0_TOP_ADDRESS, 0,
150 DMCUB_REGION3_CW0_TOP_ADDRESS, cw0->region.top,
151 DMCUB_REGION3_CW0_ENABLE, 1);
152
153 dmub_dcn401_translate_addr(&cw1->offset, fb_base, fb_offset, &offset);
154
155 REG_WRITE(DMCUB_REGION3_CW1_OFFSET, offset.u.low_part);
156 REG_WRITE(DMCUB_REGION3_CW1_OFFSET_HIGH, offset.u.high_part);
157 REG_WRITE(DMCUB_REGION3_CW1_BASE_ADDRESS, cw1->region.base);
158 REG_SET_2(DMCUB_REGION3_CW1_TOP_ADDRESS, 0,
159 DMCUB_REGION3_CW1_TOP_ADDRESS, cw1->region.top,
160 DMCUB_REGION3_CW1_ENABLE, 1);
161
162 /* release DMCUB reset only to prevent premature execution */
163 REG_UPDATE_2(DMCUB_SEC_CNTL, DMCUB_SEC_RESET, 0, DMCUB_MEM_UNIT_ID,
164 0x20);
165 }
166
dmub_dcn401_backdoor_load_zfb_mode(struct dmub_srv * dmub,const struct dmub_window * cw0,const struct dmub_window * cw1)167 void dmub_dcn401_backdoor_load_zfb_mode(struct dmub_srv *dmub,
168 const struct dmub_window *cw0,
169 const struct dmub_window *cw1)
170 {
171 union dmub_addr offset;
172
173 /* reset and disable DMCUB and MMHUBBUB DMUIF */
174 REG_UPDATE(DMCUB_SEC_CNTL, DMCUB_SEC_RESET, 1);
175 REG_UPDATE(MMHUBBUB_SOFT_RESET, DMUIF_SOFT_RESET, 1);
176 REG_UPDATE(DMCUB_CNTL, DMCUB_ENABLE, 0);
177
178 offset = cw0->offset;
179
180 REG_WRITE(DMCUB_REGION3_CW0_OFFSET, offset.u.low_part);
181 REG_WRITE(DMCUB_REGION3_CW0_OFFSET_HIGH, offset.u.high_part);
182 REG_WRITE(DMCUB_REGION3_CW0_BASE_ADDRESS, cw0->region.base);
183 REG_SET_2(DMCUB_REGION3_CW0_TOP_ADDRESS, 0,
184 DMCUB_REGION3_CW0_TOP_ADDRESS, cw0->region.top,
185 DMCUB_REGION3_CW0_ENABLE, 1);
186
187 offset = cw1->offset;
188
189 REG_WRITE(DMCUB_REGION3_CW1_OFFSET, offset.u.low_part);
190 REG_WRITE(DMCUB_REGION3_CW1_OFFSET_HIGH, offset.u.high_part);
191 REG_WRITE(DMCUB_REGION3_CW1_BASE_ADDRESS, cw1->region.base);
192 REG_SET_2(DMCUB_REGION3_CW1_TOP_ADDRESS, 0,
193 DMCUB_REGION3_CW1_TOP_ADDRESS, cw1->region.top,
194 DMCUB_REGION3_CW1_ENABLE, 1);
195
196 /* release DMCUB reset only to prevent premature execution */
197 REG_UPDATE_2(DMCUB_SEC_CNTL, DMCUB_SEC_RESET, 0, DMCUB_MEM_UNIT_ID,
198 0x20);
199 }
200
dmub_dcn401_setup_windows(struct dmub_srv * dmub,const struct dmub_window * cw2,const struct dmub_window * cw3,const struct dmub_window * cw4,const struct dmub_window * cw5,const struct dmub_window * cw6,const struct dmub_window * region6)201 void dmub_dcn401_setup_windows(struct dmub_srv *dmub,
202 const struct dmub_window *cw2,
203 const struct dmub_window *cw3,
204 const struct dmub_window *cw4,
205 const struct dmub_window *cw5,
206 const struct dmub_window *cw6,
207 const struct dmub_window *region6)
208 {
209 union dmub_addr offset;
210
211 offset = cw3->offset;
212
213 REG_WRITE(DMCUB_REGION3_CW3_OFFSET, offset.u.low_part);
214 REG_WRITE(DMCUB_REGION3_CW3_OFFSET_HIGH, offset.u.high_part);
215 REG_WRITE(DMCUB_REGION3_CW3_BASE_ADDRESS, cw3->region.base);
216 REG_SET_2(DMCUB_REGION3_CW3_TOP_ADDRESS, 0,
217 DMCUB_REGION3_CW3_TOP_ADDRESS, cw3->region.top,
218 DMCUB_REGION3_CW3_ENABLE, 1);
219
220 offset = cw4->offset;
221
222 REG_WRITE(DMCUB_REGION3_CW4_OFFSET, offset.u.low_part);
223 REG_WRITE(DMCUB_REGION3_CW4_OFFSET_HIGH, offset.u.high_part);
224 REG_WRITE(DMCUB_REGION3_CW4_BASE_ADDRESS, cw4->region.base);
225 REG_SET_2(DMCUB_REGION3_CW4_TOP_ADDRESS, 0,
226 DMCUB_REGION3_CW4_TOP_ADDRESS, cw4->region.top,
227 DMCUB_REGION3_CW4_ENABLE, 1);
228
229 offset = cw5->offset;
230
231 REG_WRITE(DMCUB_REGION3_CW5_OFFSET, offset.u.low_part);
232 REG_WRITE(DMCUB_REGION3_CW5_OFFSET_HIGH, offset.u.high_part);
233 REG_WRITE(DMCUB_REGION3_CW5_BASE_ADDRESS, cw5->region.base);
234 REG_SET_2(DMCUB_REGION3_CW5_TOP_ADDRESS, 0,
235 DMCUB_REGION3_CW5_TOP_ADDRESS, cw5->region.top,
236 DMCUB_REGION3_CW5_ENABLE, 1);
237
238 REG_WRITE(DMCUB_REGION5_OFFSET, offset.u.low_part);
239 REG_WRITE(DMCUB_REGION5_OFFSET_HIGH, offset.u.high_part);
240 REG_SET_2(DMCUB_REGION5_TOP_ADDRESS, 0,
241 DMCUB_REGION5_TOP_ADDRESS,
242 cw5->region.top - cw5->region.base - 1,
243 DMCUB_REGION5_ENABLE, 1);
244
245 offset = cw6->offset;
246
247 REG_WRITE(DMCUB_REGION3_CW6_OFFSET, offset.u.low_part);
248 REG_WRITE(DMCUB_REGION3_CW6_OFFSET_HIGH, offset.u.high_part);
249 REG_WRITE(DMCUB_REGION3_CW6_BASE_ADDRESS, cw6->region.base);
250 REG_SET_2(DMCUB_REGION3_CW6_TOP_ADDRESS, 0,
251 DMCUB_REGION3_CW6_TOP_ADDRESS, cw6->region.top,
252 DMCUB_REGION3_CW6_ENABLE, 1);
253
254 offset = region6->offset;
255
256 REG_WRITE(DMCUB_REGION6_OFFSET, offset.u.low_part);
257 REG_WRITE(DMCUB_REGION6_OFFSET_HIGH, offset.u.high_part);
258 REG_SET_2(DMCUB_REGION6_TOP_ADDRESS, 0,
259 DMCUB_REGION6_TOP_ADDRESS,
260 region6->region.top - region6->region.base - 1,
261 DMCUB_REGION6_ENABLE, 1);
262 }
263
dmub_dcn401_setup_mailbox(struct dmub_srv * dmub,const struct dmub_region * inbox1)264 void dmub_dcn401_setup_mailbox(struct dmub_srv *dmub,
265 const struct dmub_region *inbox1)
266 {
267 REG_WRITE(DMCUB_INBOX1_BASE_ADDRESS, inbox1->base);
268 REG_WRITE(DMCUB_INBOX1_SIZE, inbox1->top - inbox1->base);
269 }
270
dmub_dcn401_get_inbox1_wptr(struct dmub_srv * dmub)271 uint32_t dmub_dcn401_get_inbox1_wptr(struct dmub_srv *dmub)
272 {
273 return REG_READ(DMCUB_INBOX1_WPTR);
274 }
275
dmub_dcn401_get_inbox1_rptr(struct dmub_srv * dmub)276 uint32_t dmub_dcn401_get_inbox1_rptr(struct dmub_srv *dmub)
277 {
278 return REG_READ(DMCUB_INBOX1_RPTR);
279 }
280
dmub_dcn401_set_inbox1_wptr(struct dmub_srv * dmub,uint32_t wptr_offset)281 void dmub_dcn401_set_inbox1_wptr(struct dmub_srv *dmub, uint32_t wptr_offset)
282 {
283 REG_WRITE(DMCUB_INBOX1_WPTR, wptr_offset);
284 }
285
dmub_dcn401_setup_out_mailbox(struct dmub_srv * dmub,const struct dmub_region * outbox1)286 void dmub_dcn401_setup_out_mailbox(struct dmub_srv *dmub,
287 const struct dmub_region *outbox1)
288 {
289 REG_WRITE(DMCUB_OUTBOX1_BASE_ADDRESS, outbox1->base);
290 REG_WRITE(DMCUB_OUTBOX1_SIZE, outbox1->top - outbox1->base);
291 }
292
dmub_dcn401_get_outbox1_wptr(struct dmub_srv * dmub)293 uint32_t dmub_dcn401_get_outbox1_wptr(struct dmub_srv *dmub)
294 {
295 /**
296 * outbox1 wptr register is accessed without locks (dal & dc)
297 * and to be called only by dmub_srv_stat_get_notification()
298 */
299 return REG_READ(DMCUB_OUTBOX1_WPTR);
300 }
301
dmub_dcn401_set_outbox1_rptr(struct dmub_srv * dmub,uint32_t rptr_offset)302 void dmub_dcn401_set_outbox1_rptr(struct dmub_srv *dmub, uint32_t rptr_offset)
303 {
304 /**
305 * outbox1 rptr register is accessed without locks (dal & dc)
306 * and to be called only by dmub_srv_stat_get_notification()
307 */
308 REG_WRITE(DMCUB_OUTBOX1_RPTR, rptr_offset);
309 }
310
dmub_dcn401_is_hw_init(struct dmub_srv * dmub)311 bool dmub_dcn401_is_hw_init(struct dmub_srv *dmub)
312 {
313 union dmub_fw_boot_status status;
314 uint32_t is_hw_init;
315
316 status.all = REG_READ(DMCUB_SCRATCH0);
317 REG_GET(DMCUB_CNTL, DMCUB_ENABLE, &is_hw_init);
318
319 return is_hw_init != 0 && status.bits.dal_fw;
320 }
321
dmub_dcn401_is_supported(struct dmub_srv * dmub)322 bool dmub_dcn401_is_supported(struct dmub_srv *dmub)
323 {
324 uint32_t supported = 0;
325
326 REG_GET(CC_DC_PIPE_DIS, DC_DMCUB_ENABLE, &supported);
327
328 return supported;
329 }
330
dmub_dcn401_set_gpint(struct dmub_srv * dmub,union dmub_gpint_data_register reg)331 void dmub_dcn401_set_gpint(struct dmub_srv *dmub,
332 union dmub_gpint_data_register reg)
333 {
334 REG_WRITE(DMCUB_GPINT_DATAIN1, reg.all);
335 }
336
dmub_dcn401_is_gpint_acked(struct dmub_srv * dmub,union dmub_gpint_data_register reg)337 bool dmub_dcn401_is_gpint_acked(struct dmub_srv *dmub,
338 union dmub_gpint_data_register reg)
339 {
340 union dmub_gpint_data_register test;
341
342 reg.bits.status = 0;
343 test.all = REG_READ(DMCUB_GPINT_DATAIN1);
344
345 return test.all == reg.all;
346 }
347
dmub_dcn401_get_gpint_response(struct dmub_srv * dmub)348 uint32_t dmub_dcn401_get_gpint_response(struct dmub_srv *dmub)
349 {
350 return REG_READ(DMCUB_SCRATCH7);
351 }
352
dmub_dcn401_get_gpint_dataout(struct dmub_srv * dmub)353 uint32_t dmub_dcn401_get_gpint_dataout(struct dmub_srv *dmub)
354 {
355 uint32_t dataout = REG_READ(DMCUB_GPINT_DATAOUT);
356
357 REG_UPDATE(DMCUB_INTERRUPT_ENABLE, DMCUB_GPINT_IH_INT_EN, 0);
358
359 REG_WRITE(DMCUB_GPINT_DATAOUT, 0);
360 REG_UPDATE(DMCUB_INTERRUPT_ACK, DMCUB_GPINT_IH_INT_ACK, 1);
361 REG_UPDATE(DMCUB_INTERRUPT_ACK, DMCUB_GPINT_IH_INT_ACK, 0);
362
363 REG_UPDATE(DMCUB_INTERRUPT_ENABLE, DMCUB_GPINT_IH_INT_EN, 1);
364
365 return dataout;
366 }
367
dmub_dcn401_get_fw_boot_status(struct dmub_srv * dmub)368 union dmub_fw_boot_status dmub_dcn401_get_fw_boot_status(struct dmub_srv *dmub)
369 {
370 union dmub_fw_boot_status status;
371
372 status.all = REG_READ(DMCUB_SCRATCH0);
373 return status;
374 }
375
dmub_dcn401_enable_dmub_boot_options(struct dmub_srv * dmub,const struct dmub_srv_hw_params * params)376 void dmub_dcn401_enable_dmub_boot_options(struct dmub_srv *dmub, const struct dmub_srv_hw_params *params)
377 {
378 union dmub_fw_boot_options boot_options = {0};
379
380 boot_options.bits.z10_disable = params->disable_z10;
381
382 boot_options.bits.skip_phy_access = params->disallow_phy_access;
383
384 REG_WRITE(DMCUB_SCRATCH14, boot_options.all);
385 }
386
dmub_dcn401_skip_dmub_panel_power_sequence(struct dmub_srv * dmub,bool skip)387 void dmub_dcn401_skip_dmub_panel_power_sequence(struct dmub_srv *dmub, bool skip)
388 {
389 union dmub_fw_boot_options boot_options;
390 boot_options.all = REG_READ(DMCUB_SCRATCH14);
391 boot_options.bits.skip_phy_init_panel_sequence = skip;
392 REG_WRITE(DMCUB_SCRATCH14, boot_options.all);
393 }
394
dmub_dcn401_setup_outbox0(struct dmub_srv * dmub,const struct dmub_region * outbox0)395 void dmub_dcn401_setup_outbox0(struct dmub_srv *dmub,
396 const struct dmub_region *outbox0)
397 {
398 REG_WRITE(DMCUB_OUTBOX0_BASE_ADDRESS, outbox0->base);
399
400 REG_WRITE(DMCUB_OUTBOX0_SIZE, outbox0->top - outbox0->base);
401 }
402
dmub_dcn401_get_outbox0_wptr(struct dmub_srv * dmub)403 uint32_t dmub_dcn401_get_outbox0_wptr(struct dmub_srv *dmub)
404 {
405 return REG_READ(DMCUB_OUTBOX0_WPTR);
406 }
407
dmub_dcn401_set_outbox0_rptr(struct dmub_srv * dmub,uint32_t rptr_offset)408 void dmub_dcn401_set_outbox0_rptr(struct dmub_srv *dmub, uint32_t rptr_offset)
409 {
410 REG_WRITE(DMCUB_OUTBOX0_RPTR, rptr_offset);
411 }
412
dmub_dcn401_get_current_time(struct dmub_srv * dmub)413 uint32_t dmub_dcn401_get_current_time(struct dmub_srv *dmub)
414 {
415 return REG_READ(DMCUB_TIMER_CURRENT);
416 }
417
dmub_dcn401_get_diagnostic_data(struct dmub_srv * dmub)418 void dmub_dcn401_get_diagnostic_data(struct dmub_srv *dmub)
419 {
420 uint32_t is_dmub_enabled, is_soft_reset, is_sec_reset;
421 uint32_t is_traceport_enabled, is_cw0_enabled, is_cw6_enabled;
422 struct dmub_timeout_info timeout = {0};
423
424 if (!dmub)
425 return;
426
427 /* timeout data filled externally, cache before resetting memory */
428 timeout = dmub->debug.timeout_info;
429 memset(&dmub->debug, 0, sizeof(dmub->debug));
430 dmub->debug.timeout_info = timeout;
431
432 dmub->debug.dmcub_version = dmub->fw_version;
433
434 dmub->debug.scratch[0] = REG_READ(DMCUB_SCRATCH0);
435 dmub->debug.scratch[1] = REG_READ(DMCUB_SCRATCH1);
436 dmub->debug.scratch[2] = REG_READ(DMCUB_SCRATCH2);
437 dmub->debug.scratch[3] = REG_READ(DMCUB_SCRATCH3);
438 dmub->debug.scratch[4] = REG_READ(DMCUB_SCRATCH4);
439 dmub->debug.scratch[5] = REG_READ(DMCUB_SCRATCH5);
440 dmub->debug.scratch[6] = REG_READ(DMCUB_SCRATCH6);
441 dmub->debug.scratch[7] = REG_READ(DMCUB_SCRATCH7);
442 dmub->debug.scratch[8] = REG_READ(DMCUB_SCRATCH8);
443 dmub->debug.scratch[9] = REG_READ(DMCUB_SCRATCH9);
444 dmub->debug.scratch[10] = REG_READ(DMCUB_SCRATCH10);
445 dmub->debug.scratch[11] = REG_READ(DMCUB_SCRATCH11);
446 dmub->debug.scratch[12] = REG_READ(DMCUB_SCRATCH12);
447 dmub->debug.scratch[13] = REG_READ(DMCUB_SCRATCH13);
448 dmub->debug.scratch[14] = REG_READ(DMCUB_SCRATCH14);
449 dmub->debug.scratch[15] = REG_READ(DMCUB_SCRATCH15);
450 dmub->debug.scratch[16] = REG_READ(DMCUB_SCRATCH16);
451
452 dmub->debug.undefined_address_fault_addr = REG_READ(DMCUB_UNDEFINED_ADDRESS_FAULT_ADDR);
453 dmub->debug.inst_fetch_fault_addr = REG_READ(DMCUB_INST_FETCH_FAULT_ADDR);
454 dmub->debug.data_write_fault_addr = REG_READ(DMCUB_DATA_WRITE_FAULT_ADDR);
455
456 dmub->debug.inbox1_rptr = REG_READ(DMCUB_INBOX1_RPTR);
457 dmub->debug.inbox1_wptr = REG_READ(DMCUB_INBOX1_WPTR);
458 dmub->debug.inbox1_size = REG_READ(DMCUB_INBOX1_SIZE);
459
460 dmub->debug.inbox0_rptr = REG_READ(DMCUB_INBOX0_RPTR);
461 dmub->debug.inbox0_wptr = REG_READ(DMCUB_INBOX0_WPTR);
462 dmub->debug.inbox0_size = REG_READ(DMCUB_INBOX0_SIZE);
463
464 dmub->debug.outbox1_rptr = REG_READ(DMCUB_OUTBOX1_RPTR);
465 dmub->debug.outbox1_wptr = REG_READ(DMCUB_OUTBOX1_WPTR);
466 dmub->debug.outbox1_size = REG_READ(DMCUB_OUTBOX1_SIZE);
467
468 REG_GET(DMCUB_CNTL, DMCUB_ENABLE, &is_dmub_enabled);
469 dmub->debug.is_dmcub_enabled = is_dmub_enabled;
470
471 REG_GET(DMCUB_CNTL2, DMCUB_SOFT_RESET, &is_soft_reset);
472 dmub->debug.is_dmcub_soft_reset = is_soft_reset;
473
474 REG_GET(DMCUB_SEC_CNTL, DMCUB_SEC_RESET_STATUS, &is_sec_reset);
475 dmub->debug.is_dmcub_secure_reset = is_sec_reset;
476
477 REG_GET(DMCUB_CNTL, DMCUB_TRACEPORT_EN, &is_traceport_enabled);
478 dmub->debug.is_traceport_en = is_traceport_enabled;
479
480 REG_GET(DMCUB_REGION3_CW0_TOP_ADDRESS, DMCUB_REGION3_CW0_ENABLE, &is_cw0_enabled);
481 dmub->debug.is_cw0_enabled = is_cw0_enabled;
482
483 REG_GET(DMCUB_REGION3_CW6_TOP_ADDRESS, DMCUB_REGION3_CW6_ENABLE, &is_cw6_enabled);
484 dmub->debug.is_cw6_enabled = is_cw6_enabled;
485
486 dmub->debug.gpint_datain0 = REG_READ(DMCUB_GPINT_DATAIN0);
487 }
dmub_dcn401_configure_dmub_in_system_memory(struct dmub_srv * dmub)488 void dmub_dcn401_configure_dmub_in_system_memory(struct dmub_srv *dmub)
489 {
490 /* DMCUB_REGION3_TMR_AXI_SPACE values:
491 * 0b011 (0x3) - FB physical address
492 * 0b100 (0x4) - GPU virtual address
493 *
494 * Default value is 0x3 (FB Physical address for TMR). When programming
495 * DMUB to be in system memory, change to 0x4. The system memory allocated
496 * is accessible by both GPU and CPU, so we use GPU virtual address.
497 */
498 REG_WRITE(DMCUB_REGION3_TMR_AXI_SPACE, 0x4);
499 }
500
dmub_dcn401_send_inbox0_cmd(struct dmub_srv * dmub,union dmub_inbox0_data_register data)501 void dmub_dcn401_send_inbox0_cmd(struct dmub_srv *dmub, union dmub_inbox0_data_register data)
502 {
503 REG_WRITE(DMCUB_INBOX0_WPTR, data.inbox0_cmd_common.all);
504 }
505
dmub_dcn401_clear_inbox0_ack_register(struct dmub_srv * dmub)506 void dmub_dcn401_clear_inbox0_ack_register(struct dmub_srv *dmub)
507 {
508 REG_WRITE(DMCUB_SCRATCH17, 0);
509 }
510
dmub_dcn401_read_inbox0_ack_register(struct dmub_srv * dmub)511 uint32_t dmub_dcn401_read_inbox0_ack_register(struct dmub_srv *dmub)
512 {
513 return REG_READ(DMCUB_SCRATCH17);
514 }
515
dmub_dcn401_send_reg_inbox0_cmd_msg(struct dmub_srv * dmub,union dmub_rb_cmd * cmd)516 void dmub_dcn401_send_reg_inbox0_cmd_msg(struct dmub_srv *dmub,
517 union dmub_rb_cmd *cmd)
518 {
519 uint32_t *dwords = (uint32_t *)cmd;
520
521 static_assert(sizeof(*cmd) == 64, "DMUB command size mismatch");
522
523 REG_WRITE(DMCUB_REG_INBOX0_MSG0, dwords[0]);
524 REG_WRITE(DMCUB_REG_INBOX0_MSG1, dwords[1]);
525 REG_WRITE(DMCUB_REG_INBOX0_MSG2, dwords[2]);
526 REG_WRITE(DMCUB_REG_INBOX0_MSG3, dwords[3]);
527 REG_WRITE(DMCUB_REG_INBOX0_MSG4, dwords[4]);
528 REG_WRITE(DMCUB_REG_INBOX0_MSG5, dwords[5]);
529 REG_WRITE(DMCUB_REG_INBOX0_MSG6, dwords[6]);
530 REG_WRITE(DMCUB_REG_INBOX0_MSG7, dwords[7]);
531 REG_WRITE(DMCUB_REG_INBOX0_MSG8, dwords[8]);
532 REG_WRITE(DMCUB_REG_INBOX0_MSG9, dwords[9]);
533 REG_WRITE(DMCUB_REG_INBOX0_MSG10, dwords[10]);
534 REG_WRITE(DMCUB_REG_INBOX0_MSG11, dwords[11]);
535 REG_WRITE(DMCUB_REG_INBOX0_MSG12, dwords[12]);
536 REG_WRITE(DMCUB_REG_INBOX0_MSG13, dwords[13]);
537 REG_WRITE(DMCUB_REG_INBOX0_MSG14, dwords[14]);
538 /* writing to INBOX RDY register will trigger DMUB REG INBOX0 RDY
539 * interrupt.
540 */
541 REG_WRITE(DMCUB_REG_INBOX0_RDY, dwords[15]);
542 }
543
dmub_dcn401_read_reg_inbox0_rsp_int_status(struct dmub_srv * dmub)544 uint32_t dmub_dcn401_read_reg_inbox0_rsp_int_status(struct dmub_srv *dmub)
545 {
546 uint32_t status;
547
548 REG_GET(HOST_INTERRUPT_CSR, HOST_REG_INBOX0_RSP_INT_STAT, &status);
549 return status;
550 }
551
dmub_dcn401_read_reg_inbox0_cmd_rsp(struct dmub_srv * dmub,union dmub_rb_cmd * cmd)552 void dmub_dcn401_read_reg_inbox0_cmd_rsp(struct dmub_srv *dmub,
553 union dmub_rb_cmd *cmd)
554 {
555 uint32_t *dwords = (uint32_t *)cmd;
556
557 static_assert(sizeof(*cmd) == 64, "DMUB command size mismatch");
558
559 dwords[0] = REG_READ(DMCUB_REG_INBOX0_MSG0);
560 dwords[1] = REG_READ(DMCUB_REG_INBOX0_MSG1);
561 dwords[2] = REG_READ(DMCUB_REG_INBOX0_MSG2);
562 dwords[3] = REG_READ(DMCUB_REG_INBOX0_MSG3);
563 dwords[4] = REG_READ(DMCUB_REG_INBOX0_MSG4);
564 dwords[5] = REG_READ(DMCUB_REG_INBOX0_MSG5);
565 dwords[6] = REG_READ(DMCUB_REG_INBOX0_MSG6);
566 dwords[7] = REG_READ(DMCUB_REG_INBOX0_MSG7);
567 dwords[8] = REG_READ(DMCUB_REG_INBOX0_MSG8);
568 dwords[9] = REG_READ(DMCUB_REG_INBOX0_MSG9);
569 dwords[10] = REG_READ(DMCUB_REG_INBOX0_MSG10);
570 dwords[11] = REG_READ(DMCUB_REG_INBOX0_MSG11);
571 dwords[12] = REG_READ(DMCUB_REG_INBOX0_MSG12);
572 dwords[13] = REG_READ(DMCUB_REG_INBOX0_MSG13);
573 dwords[14] = REG_READ(DMCUB_REG_INBOX0_MSG14);
574 dwords[15] = REG_READ(DMCUB_REG_INBOX0_RSP);
575 }
576
dmub_dcn401_write_reg_inbox0_rsp_int_ack(struct dmub_srv * dmub)577 void dmub_dcn401_write_reg_inbox0_rsp_int_ack(struct dmub_srv *dmub)
578 {
579 REG_UPDATE(HOST_INTERRUPT_CSR, HOST_REG_INBOX0_RSP_INT_ACK, 1);
580 REG_UPDATE(HOST_INTERRUPT_CSR, HOST_REG_INBOX0_RSP_INT_ACK, 0);
581 }
582
dmub_dcn401_write_reg_outbox0_rdy_int_ack(struct dmub_srv * dmub)583 void dmub_dcn401_write_reg_outbox0_rdy_int_ack(struct dmub_srv *dmub)
584 {
585 REG_UPDATE(HOST_INTERRUPT_CSR, HOST_REG_OUTBOX0_RDY_INT_ACK, 1);
586 REG_UPDATE(HOST_INTERRUPT_CSR, HOST_REG_OUTBOX0_RDY_INT_ACK, 0);
587 }
588
dmub_dcn401_read_reg_outbox0_msg(struct dmub_srv * dmub,uint32_t * msg)589 void dmub_dcn401_read_reg_outbox0_msg(struct dmub_srv *dmub, uint32_t *msg)
590 {
591 *msg = REG_READ(DMCUB_REG_OUTBOX0_MSG0);
592 }
593
dmub_dcn401_write_reg_outbox0_rsp(struct dmub_srv * dmub,uint32_t * rsp)594 void dmub_dcn401_write_reg_outbox0_rsp(struct dmub_srv *dmub, uint32_t *rsp)
595 {
596 REG_WRITE(DMCUB_REG_OUTBOX0_RSP, *rsp);
597 }
598
dmub_dcn401_read_reg_outbox0_rsp_int_status(struct dmub_srv * dmub)599 uint32_t dmub_dcn401_read_reg_outbox0_rsp_int_status(struct dmub_srv *dmub)
600 {
601 uint32_t status;
602
603 REG_GET(DMCUB_INTERRUPT_STATUS, DMCUB_REG_OUTBOX0_RSP_INT_STAT, &status);
604 return status;
605 }
606
dmub_dcn401_enable_reg_inbox0_rsp_int(struct dmub_srv * dmub,bool enable)607 void dmub_dcn401_enable_reg_inbox0_rsp_int(struct dmub_srv *dmub, bool enable)
608 {
609 REG_UPDATE(HOST_INTERRUPT_CSR, HOST_REG_INBOX0_RSP_INT_EN, enable ? 1:0);
610 }
611
dmub_dcn401_enable_reg_outbox0_rdy_int(struct dmub_srv * dmub,bool enable)612 void dmub_dcn401_enable_reg_outbox0_rdy_int(struct dmub_srv *dmub, bool enable)
613 {
614 REG_UPDATE(HOST_INTERRUPT_CSR, HOST_REG_OUTBOX0_RDY_INT_EN, enable ? 1:0);
615 }
616
dmub_dcn401_read_reg_outbox0_rdy_int_status(struct dmub_srv * dmub)617 uint32_t dmub_dcn401_read_reg_outbox0_rdy_int_status(struct dmub_srv *dmub)
618 {
619 uint32_t status;
620
621 REG_GET(HOST_INTERRUPT_CSR, HOST_REG_OUTBOX0_RDY_INT_STAT, &status);
622 return status;
623 }
624