1 /*
2 * Copyright 2022 Advanced Micro Devices, Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
21 *
22 * Authors: AMD
23 *
24 */
25
26 #include "../dmub_srv.h"
27 #include "dc_types.h"
28 #include "dmub_reg.h"
29 #include "dmub_dcn35.h"
30 #include "dc/dc_types.h"
31
32 #include "dcn/dcn_3_5_0_offset.h"
33 #include "dcn/dcn_3_5_0_sh_mask.h"
34
35 #define BASE_INNER(seg) ctx->dcn_reg_offsets[seg]
36 #define CTX dmub
37 #define REGS dmub->regs_dcn35
38 #define REG_OFFSET_EXP(reg_name) BASE(reg##reg_name##_BASE_IDX) + reg##reg_name
39
dmub_srv_dcn35_regs_init(struct dmub_srv * dmub,struct dc_context * ctx)40 void dmub_srv_dcn35_regs_init(struct dmub_srv *dmub, struct dc_context *ctx) {
41 struct dmub_srv_dcn35_regs *regs = dmub->regs_dcn35;
42 #define REG_STRUCT regs
43
44 #define DMUB_SR(reg) REG_STRUCT->offset.reg = REG_OFFSET_EXP(reg);
45 DMUB_DCN35_REGS()
46 DMCUB_INTERNAL_REGS()
47 #undef DMUB_SR
48
49 #define DMUB_SF(reg, field) REG_STRUCT->mask.reg##__##field = FD_MASK(reg, field);
50 DMUB_DCN35_FIELDS()
51 #undef DMUB_SF
52
53 #define DMUB_SF(reg, field) REG_STRUCT->shift.reg##__##field = FD_SHIFT(reg, field);
54 DMUB_DCN35_FIELDS()
55 #undef DMUB_SF
56 #undef REG_STRUCT
57 }
58
dmub_dcn35_get_fb_base_offset(struct dmub_srv * dmub,uint64_t * fb_base,uint64_t * fb_offset)59 static void dmub_dcn35_get_fb_base_offset(struct dmub_srv *dmub,
60 uint64_t *fb_base,
61 uint64_t *fb_offset)
62 {
63 uint32_t tmp;
64
65 /*
66 if (dmub->fb_base || dmub->fb_offset) {
67 *fb_base = dmub->fb_base;
68 *fb_offset = dmub->fb_offset;
69 return;
70 }
71 */
72
73 REG_GET(DCN_VM_FB_LOCATION_BASE, FB_BASE, &tmp);
74 *fb_base = (uint64_t)tmp << 24;
75
76 REG_GET(DCN_VM_FB_OFFSET, FB_OFFSET, &tmp);
77 *fb_offset = (uint64_t)tmp << 24;
78 }
79
dmub_dcn35_translate_addr(const union dmub_addr * addr_in,uint64_t fb_base,uint64_t fb_offset,union dmub_addr * addr_out)80 static inline void dmub_dcn35_translate_addr(const union dmub_addr *addr_in,
81 uint64_t fb_base,
82 uint64_t fb_offset,
83 union dmub_addr *addr_out)
84 {
85 addr_out->quad_part = addr_in->quad_part - fb_base + fb_offset;
86 }
87
dmub_dcn35_reset(struct dmub_srv * dmub)88 void dmub_dcn35_reset(struct dmub_srv *dmub)
89 {
90 union dmub_gpint_data_register cmd;
91 const uint32_t timeout = 100;
92 uint32_t in_reset, is_enabled, scratch, i, pwait_mode;
93
94 REG_GET(DMCUB_CNTL2, DMCUB_SOFT_RESET, &in_reset);
95
96 if (in_reset == 0) {
97 cmd.bits.status = 1;
98 cmd.bits.command_code = DMUB_GPINT__STOP_FW;
99 cmd.bits.param = 0;
100
101 dmub->hw_funcs.set_gpint(dmub, cmd);
102
103 /**
104 * Timeout covers both the ACK and the wait
105 * for remaining work to finish.
106 */
107
108 for (i = 0; i < timeout; ++i) {
109 if (dmub->hw_funcs.is_gpint_acked(dmub, cmd))
110 break;
111
112 udelay(1);
113 }
114
115 for (i = 0; i < timeout; ++i) {
116 scratch = dmub->hw_funcs.get_gpint_response(dmub);
117 if (scratch == DMUB_GPINT__STOP_FW_RESPONSE)
118 break;
119
120 udelay(1);
121 }
122
123 for (i = 0; i < timeout; ++i) {
124 REG_GET(DMCUB_CNTL, DMCUB_PWAIT_MODE_STATUS, &pwait_mode);
125 if (pwait_mode & (1 << 0))
126 break;
127
128 udelay(1);
129 }
130 /* Force reset in case we timed out, DMCUB is likely hung. */
131 }
132
133 REG_GET(DMCUB_CNTL, DMCUB_ENABLE, &is_enabled);
134
135 if (is_enabled) {
136 REG_UPDATE(DMCUB_CNTL2, DMCUB_SOFT_RESET, 1);
137 REG_UPDATE(MMHUBBUB_SOFT_RESET, DMUIF_SOFT_RESET, 1);
138 REG_UPDATE(DMCUB_CNTL, DMCUB_ENABLE, 0);
139 }
140
141 REG_WRITE(DMCUB_INBOX1_RPTR, 0);
142 REG_WRITE(DMCUB_INBOX1_WPTR, 0);
143 REG_WRITE(DMCUB_OUTBOX1_RPTR, 0);
144 REG_WRITE(DMCUB_OUTBOX1_WPTR, 0);
145 REG_WRITE(DMCUB_OUTBOX0_RPTR, 0);
146 REG_WRITE(DMCUB_OUTBOX0_WPTR, 0);
147 REG_WRITE(DMCUB_SCRATCH0, 0);
148
149 /* Clear the GPINT command manually so we don't send anything during boot. */
150 cmd.all = 0;
151 dmub->hw_funcs.set_gpint(dmub, cmd);
152 }
153
dmub_dcn35_reset_release(struct dmub_srv * dmub)154 void dmub_dcn35_reset_release(struct dmub_srv *dmub)
155 {
156 REG_WRITE(DMCUB_SCRATCH15, dmub->psp_version & 0x001100FF);
157
158 REG_UPDATE_3(DMU_CLK_CNTL,
159 LONO_DISPCLK_GATE_DISABLE, 1,
160 LONO_SOCCLK_GATE_DISABLE, 1,
161 LONO_DMCUBCLK_GATE_DISABLE, 1);
162
163 REG_UPDATE(MMHUBBUB_SOFT_RESET, DMUIF_SOFT_RESET, 1);
164 udelay(1);
165 REG_UPDATE_2(DMCUB_CNTL, DMCUB_ENABLE, 1, DMCUB_TRACEPORT_EN, 1);
166 REG_UPDATE(DMCUB_CNTL2, DMCUB_SOFT_RESET, 1);
167 udelay(1);
168 REG_UPDATE(MMHUBBUB_SOFT_RESET, DMUIF_SOFT_RESET, 0);
169 REG_UPDATE(DMCUB_CNTL2, DMCUB_SOFT_RESET, 0);
170 }
171
dmub_dcn35_backdoor_load(struct dmub_srv * dmub,const struct dmub_window * cw0,const struct dmub_window * cw1)172 void dmub_dcn35_backdoor_load(struct dmub_srv *dmub,
173 const struct dmub_window *cw0,
174 const struct dmub_window *cw1)
175 {
176 union dmub_addr offset;
177 uint64_t fb_base, fb_offset;
178
179 dmub_dcn35_get_fb_base_offset(dmub, &fb_base, &fb_offset);
180
181 dmub_dcn35_translate_addr(&cw0->offset, fb_base, fb_offset, &offset);
182
183 REG_WRITE(DMCUB_REGION3_CW0_OFFSET, offset.u.low_part);
184 REG_WRITE(DMCUB_REGION3_CW0_OFFSET_HIGH, offset.u.high_part);
185 REG_WRITE(DMCUB_REGION3_CW0_BASE_ADDRESS, cw0->region.base);
186 REG_SET_2(DMCUB_REGION3_CW0_TOP_ADDRESS, 0,
187 DMCUB_REGION3_CW0_TOP_ADDRESS, cw0->region.top,
188 DMCUB_REGION3_CW0_ENABLE, 1);
189
190 dmub_dcn35_translate_addr(&cw1->offset, fb_base, fb_offset, &offset);
191
192 REG_WRITE(DMCUB_REGION3_CW1_OFFSET, offset.u.low_part);
193 REG_WRITE(DMCUB_REGION3_CW1_OFFSET_HIGH, offset.u.high_part);
194 REG_WRITE(DMCUB_REGION3_CW1_BASE_ADDRESS, cw1->region.base);
195 REG_SET_2(DMCUB_REGION3_CW1_TOP_ADDRESS, 0,
196 DMCUB_REGION3_CW1_TOP_ADDRESS, cw1->region.top,
197 DMCUB_REGION3_CW1_ENABLE, 1);
198
199 /* TODO: Do we need to set DMCUB_MEM_UNIT_ID? */
200 REG_UPDATE(DMCUB_SEC_CNTL, DMCUB_SEC_RESET, 0);
201 }
202
dmub_dcn35_backdoor_load_zfb_mode(struct dmub_srv * dmub,const struct dmub_window * cw0,const struct dmub_window * cw1)203 void dmub_dcn35_backdoor_load_zfb_mode(struct dmub_srv *dmub,
204 const struct dmub_window *cw0,
205 const struct dmub_window *cw1)
206 {
207 union dmub_addr offset;
208
209 REG_UPDATE(DMCUB_SEC_CNTL, DMCUB_SEC_RESET, 1);
210 offset = cw0->offset;
211 REG_WRITE(DMCUB_REGION3_CW0_OFFSET, offset.u.low_part);
212 REG_WRITE(DMCUB_REGION3_CW0_OFFSET_HIGH, offset.u.high_part);
213 REG_WRITE(DMCUB_REGION3_CW0_BASE_ADDRESS, cw0->region.base);
214 REG_SET_2(DMCUB_REGION3_CW0_TOP_ADDRESS, 0,
215 DMCUB_REGION3_CW0_TOP_ADDRESS, cw0->region.top,
216 DMCUB_REGION3_CW0_ENABLE, 1);
217 offset = cw1->offset;
218 REG_WRITE(DMCUB_REGION3_CW1_OFFSET, offset.u.low_part);
219 REG_WRITE(DMCUB_REGION3_CW1_OFFSET_HIGH, offset.u.high_part);
220 REG_WRITE(DMCUB_REGION3_CW1_BASE_ADDRESS, cw1->region.base);
221 REG_SET_2(DMCUB_REGION3_CW1_TOP_ADDRESS, 0,
222 DMCUB_REGION3_CW1_TOP_ADDRESS, cw1->region.top,
223 DMCUB_REGION3_CW1_ENABLE, 1);
224 REG_UPDATE_2(DMCUB_SEC_CNTL, DMCUB_SEC_RESET, 0, DMCUB_MEM_UNIT_ID,
225 0x20);
226 }
dmub_dcn35_setup_windows(struct dmub_srv * dmub,const struct dmub_window * cw2,const struct dmub_window * cw3,const struct dmub_window * cw4,const struct dmub_window * cw5,const struct dmub_window * cw6)227 void dmub_dcn35_setup_windows(struct dmub_srv *dmub,
228 const struct dmub_window *cw2,
229 const struct dmub_window *cw3,
230 const struct dmub_window *cw4,
231 const struct dmub_window *cw5,
232 const struct dmub_window *cw6)
233 {
234 union dmub_addr offset;
235
236 offset = cw3->offset;
237
238 REG_WRITE(DMCUB_REGION3_CW3_OFFSET, offset.u.low_part);
239 REG_WRITE(DMCUB_REGION3_CW3_OFFSET_HIGH, offset.u.high_part);
240 REG_WRITE(DMCUB_REGION3_CW3_BASE_ADDRESS, cw3->region.base);
241 REG_SET_2(DMCUB_REGION3_CW3_TOP_ADDRESS, 0,
242 DMCUB_REGION3_CW3_TOP_ADDRESS, cw3->region.top,
243 DMCUB_REGION3_CW3_ENABLE, 1);
244
245 offset = cw4->offset;
246
247 REG_WRITE(DMCUB_REGION3_CW4_OFFSET, offset.u.low_part);
248 REG_WRITE(DMCUB_REGION3_CW4_OFFSET_HIGH, offset.u.high_part);
249 REG_WRITE(DMCUB_REGION3_CW4_BASE_ADDRESS, cw4->region.base);
250 REG_SET_2(DMCUB_REGION3_CW4_TOP_ADDRESS, 0,
251 DMCUB_REGION3_CW4_TOP_ADDRESS, cw4->region.top,
252 DMCUB_REGION3_CW4_ENABLE, 1);
253
254 offset = cw5->offset;
255
256 REG_WRITE(DMCUB_REGION3_CW5_OFFSET, offset.u.low_part);
257 REG_WRITE(DMCUB_REGION3_CW5_OFFSET_HIGH, offset.u.high_part);
258 REG_WRITE(DMCUB_REGION3_CW5_BASE_ADDRESS, cw5->region.base);
259 REG_SET_2(DMCUB_REGION3_CW5_TOP_ADDRESS, 0,
260 DMCUB_REGION3_CW5_TOP_ADDRESS, cw5->region.top,
261 DMCUB_REGION3_CW5_ENABLE, 1);
262
263 REG_WRITE(DMCUB_REGION5_OFFSET, offset.u.low_part);
264 REG_WRITE(DMCUB_REGION5_OFFSET_HIGH, offset.u.high_part);
265 REG_SET_2(DMCUB_REGION5_TOP_ADDRESS, 0,
266 DMCUB_REGION5_TOP_ADDRESS,
267 cw5->region.top - cw5->region.base - 1,
268 DMCUB_REGION5_ENABLE, 1);
269
270 offset = cw6->offset;
271
272 REG_WRITE(DMCUB_REGION3_CW6_OFFSET, offset.u.low_part);
273 REG_WRITE(DMCUB_REGION3_CW6_OFFSET_HIGH, offset.u.high_part);
274 REG_WRITE(DMCUB_REGION3_CW6_BASE_ADDRESS, cw6->region.base);
275 REG_SET_2(DMCUB_REGION3_CW6_TOP_ADDRESS, 0,
276 DMCUB_REGION3_CW6_TOP_ADDRESS, cw6->region.top,
277 DMCUB_REGION3_CW6_ENABLE, 1);
278 }
279
dmub_dcn35_setup_mailbox(struct dmub_srv * dmub,const struct dmub_region * inbox1)280 void dmub_dcn35_setup_mailbox(struct dmub_srv *dmub,
281 const struct dmub_region *inbox1)
282 {
283 REG_WRITE(DMCUB_INBOX1_BASE_ADDRESS, inbox1->base);
284 REG_WRITE(DMCUB_INBOX1_SIZE, inbox1->top - inbox1->base);
285 }
286
dmub_dcn35_get_inbox1_wptr(struct dmub_srv * dmub)287 uint32_t dmub_dcn35_get_inbox1_wptr(struct dmub_srv *dmub)
288 {
289 return REG_READ(DMCUB_INBOX1_WPTR);
290 }
291
dmub_dcn35_get_inbox1_rptr(struct dmub_srv * dmub)292 uint32_t dmub_dcn35_get_inbox1_rptr(struct dmub_srv *dmub)
293 {
294 return REG_READ(DMCUB_INBOX1_RPTR);
295 }
296
dmub_dcn35_set_inbox1_wptr(struct dmub_srv * dmub,uint32_t wptr_offset)297 void dmub_dcn35_set_inbox1_wptr(struct dmub_srv *dmub, uint32_t wptr_offset)
298 {
299 REG_WRITE(DMCUB_INBOX1_WPTR, wptr_offset);
300 }
301
dmub_dcn35_setup_out_mailbox(struct dmub_srv * dmub,const struct dmub_region * outbox1)302 void dmub_dcn35_setup_out_mailbox(struct dmub_srv *dmub,
303 const struct dmub_region *outbox1)
304 {
305 REG_WRITE(DMCUB_OUTBOX1_BASE_ADDRESS, outbox1->base);
306 REG_WRITE(DMCUB_OUTBOX1_SIZE, outbox1->top - outbox1->base);
307 }
308
dmub_dcn35_get_outbox1_wptr(struct dmub_srv * dmub)309 uint32_t dmub_dcn35_get_outbox1_wptr(struct dmub_srv *dmub)
310 {
311 /**
312 * outbox1 wptr register is accessed without locks (dal & dc)
313 * and to be called only by dmub_srv_stat_get_notification()
314 */
315 return REG_READ(DMCUB_OUTBOX1_WPTR);
316 }
317
dmub_dcn35_set_outbox1_rptr(struct dmub_srv * dmub,uint32_t rptr_offset)318 void dmub_dcn35_set_outbox1_rptr(struct dmub_srv *dmub, uint32_t rptr_offset)
319 {
320 /**
321 * outbox1 rptr register is accessed without locks (dal & dc)
322 * and to be called only by dmub_srv_stat_get_notification()
323 */
324 REG_WRITE(DMCUB_OUTBOX1_RPTR, rptr_offset);
325 }
326
dmub_dcn35_is_hw_init(struct dmub_srv * dmub)327 bool dmub_dcn35_is_hw_init(struct dmub_srv *dmub)
328 {
329 union dmub_fw_boot_status status;
330 uint32_t is_enable;
331
332 status.all = REG_READ(DMCUB_SCRATCH0);
333 REG_GET(DMCUB_CNTL, DMCUB_ENABLE, &is_enable);
334
335 return is_enable != 0 && status.bits.dal_fw;
336 }
337
dmub_dcn35_is_supported(struct dmub_srv * dmub)338 bool dmub_dcn35_is_supported(struct dmub_srv *dmub)
339 {
340 uint32_t supported = 0;
341
342 REG_GET(CC_DC_PIPE_DIS, DC_DMCUB_ENABLE, &supported);
343
344 return supported;
345 }
346
dmub_dcn35_set_gpint(struct dmub_srv * dmub,union dmub_gpint_data_register reg)347 void dmub_dcn35_set_gpint(struct dmub_srv *dmub,
348 union dmub_gpint_data_register reg)
349 {
350 REG_WRITE(DMCUB_GPINT_DATAIN1, reg.all);
351 }
352
dmub_dcn35_is_gpint_acked(struct dmub_srv * dmub,union dmub_gpint_data_register reg)353 bool dmub_dcn35_is_gpint_acked(struct dmub_srv *dmub,
354 union dmub_gpint_data_register reg)
355 {
356 union dmub_gpint_data_register test;
357
358 reg.bits.status = 0;
359 test.all = REG_READ(DMCUB_GPINT_DATAIN1);
360
361 return test.all == reg.all;
362 }
363
dmub_dcn35_get_gpint_response(struct dmub_srv * dmub)364 uint32_t dmub_dcn35_get_gpint_response(struct dmub_srv *dmub)
365 {
366 return REG_READ(DMCUB_SCRATCH7);
367 }
368
dmub_dcn35_get_gpint_dataout(struct dmub_srv * dmub)369 uint32_t dmub_dcn35_get_gpint_dataout(struct dmub_srv *dmub)
370 {
371 uint32_t dataout = REG_READ(DMCUB_GPINT_DATAOUT);
372
373 REG_UPDATE(DMCUB_INTERRUPT_ENABLE, DMCUB_GPINT_IH_INT_EN, 0);
374
375 REG_WRITE(DMCUB_GPINT_DATAOUT, 0);
376 REG_UPDATE(DMCUB_INTERRUPT_ACK, DMCUB_GPINT_IH_INT_ACK, 1);
377 REG_UPDATE(DMCUB_INTERRUPT_ACK, DMCUB_GPINT_IH_INT_ACK, 0);
378
379 REG_UPDATE(DMCUB_INTERRUPT_ENABLE, DMCUB_GPINT_IH_INT_EN, 1);
380
381 return dataout;
382 }
383
dmub_dcn35_get_fw_boot_status(struct dmub_srv * dmub)384 union dmub_fw_boot_status dmub_dcn35_get_fw_boot_status(struct dmub_srv *dmub)
385 {
386 union dmub_fw_boot_status status;
387
388 status.all = REG_READ(DMCUB_SCRATCH0);
389 return status;
390 }
391
dmub_dcn35_get_fw_boot_option(struct dmub_srv * dmub)392 union dmub_fw_boot_options dmub_dcn35_get_fw_boot_option(struct dmub_srv *dmub)
393 {
394 union dmub_fw_boot_options option;
395
396 option.all = REG_READ(DMCUB_SCRATCH14);
397 return option;
398 }
399
dmub_dcn35_enable_dmub_boot_options(struct dmub_srv * dmub,const struct dmub_srv_hw_params * params)400 void dmub_dcn35_enable_dmub_boot_options(struct dmub_srv *dmub, const struct dmub_srv_hw_params *params)
401 {
402 union dmub_fw_boot_options boot_options = {0};
403
404 boot_options.bits.z10_disable = params->disable_z10;
405 boot_options.bits.dpia_supported = params->dpia_supported;
406 boot_options.bits.enable_dpia = params->disable_dpia == true ? 0:1;
407 boot_options.bits.usb4_cm_version = params->usb4_cm_version;
408 boot_options.bits.dpia_hpd_int_enable_supported = params->dpia_hpd_int_enable_supported;
409 boot_options.bits.power_optimization = params->power_optimization;
410 boot_options.bits.disable_clk_ds = params->disallow_dispclk_dppclk_ds;
411 boot_options.bits.disable_clk_gate = params->disable_clock_gate;
412 boot_options.bits.ips_disable = params->disable_ips;
413
414 REG_WRITE(DMCUB_SCRATCH14, boot_options.all);
415 }
416
dmub_dcn35_skip_dmub_panel_power_sequence(struct dmub_srv * dmub,bool skip)417 void dmub_dcn35_skip_dmub_panel_power_sequence(struct dmub_srv *dmub, bool skip)
418 {
419 union dmub_fw_boot_options boot_options;
420 boot_options.all = REG_READ(DMCUB_SCRATCH14);
421 boot_options.bits.skip_phy_init_panel_sequence = skip;
422 REG_WRITE(DMCUB_SCRATCH14, boot_options.all);
423 }
424
dmub_dcn35_setup_outbox0(struct dmub_srv * dmub,const struct dmub_region * outbox0)425 void dmub_dcn35_setup_outbox0(struct dmub_srv *dmub,
426 const struct dmub_region *outbox0)
427 {
428 REG_WRITE(DMCUB_OUTBOX0_BASE_ADDRESS, outbox0->base);
429
430 REG_WRITE(DMCUB_OUTBOX0_SIZE, outbox0->top - outbox0->base);
431 }
432
dmub_dcn35_get_outbox0_wptr(struct dmub_srv * dmub)433 uint32_t dmub_dcn35_get_outbox0_wptr(struct dmub_srv *dmub)
434 {
435 return REG_READ(DMCUB_OUTBOX0_WPTR);
436 }
437
dmub_dcn35_set_outbox0_rptr(struct dmub_srv * dmub,uint32_t rptr_offset)438 void dmub_dcn35_set_outbox0_rptr(struct dmub_srv *dmub, uint32_t rptr_offset)
439 {
440 REG_WRITE(DMCUB_OUTBOX0_RPTR, rptr_offset);
441 }
442
dmub_dcn35_get_current_time(struct dmub_srv * dmub)443 uint32_t dmub_dcn35_get_current_time(struct dmub_srv *dmub)
444 {
445 return REG_READ(DMCUB_TIMER_CURRENT);
446 }
447
dmub_dcn35_get_diagnostic_data(struct dmub_srv * dmub,struct dmub_diagnostic_data * diag_data)448 void dmub_dcn35_get_diagnostic_data(struct dmub_srv *dmub, struct dmub_diagnostic_data *diag_data)
449 {
450 uint32_t is_dmub_enabled, is_soft_reset, is_sec_reset;
451 uint32_t is_traceport_enabled, is_cw0_enabled, is_cw6_enabled;
452
453 if (!dmub || !diag_data)
454 return;
455
456 memset(diag_data, 0, sizeof(*diag_data));
457
458 diag_data->dmcub_version = dmub->fw_version;
459
460 diag_data->scratch[0] = REG_READ(DMCUB_SCRATCH0);
461 diag_data->scratch[1] = REG_READ(DMCUB_SCRATCH1);
462 diag_data->scratch[2] = REG_READ(DMCUB_SCRATCH2);
463 diag_data->scratch[3] = REG_READ(DMCUB_SCRATCH3);
464 diag_data->scratch[4] = REG_READ(DMCUB_SCRATCH4);
465 diag_data->scratch[5] = REG_READ(DMCUB_SCRATCH5);
466 diag_data->scratch[6] = REG_READ(DMCUB_SCRATCH6);
467 diag_data->scratch[7] = REG_READ(DMCUB_SCRATCH7);
468 diag_data->scratch[8] = REG_READ(DMCUB_SCRATCH8);
469 diag_data->scratch[9] = REG_READ(DMCUB_SCRATCH9);
470 diag_data->scratch[10] = REG_READ(DMCUB_SCRATCH10);
471 diag_data->scratch[11] = REG_READ(DMCUB_SCRATCH11);
472 diag_data->scratch[12] = REG_READ(DMCUB_SCRATCH12);
473 diag_data->scratch[13] = REG_READ(DMCUB_SCRATCH13);
474 diag_data->scratch[14] = REG_READ(DMCUB_SCRATCH14);
475 diag_data->scratch[15] = REG_READ(DMCUB_SCRATCH15);
476 diag_data->scratch[16] = REG_READ(DMCUB_SCRATCH16);
477
478 diag_data->undefined_address_fault_addr = REG_READ(DMCUB_UNDEFINED_ADDRESS_FAULT_ADDR);
479 diag_data->inst_fetch_fault_addr = REG_READ(DMCUB_INST_FETCH_FAULT_ADDR);
480 diag_data->data_write_fault_addr = REG_READ(DMCUB_DATA_WRITE_FAULT_ADDR);
481
482 diag_data->inbox1_rptr = REG_READ(DMCUB_INBOX1_RPTR);
483 diag_data->inbox1_wptr = REG_READ(DMCUB_INBOX1_WPTR);
484 diag_data->inbox1_size = REG_READ(DMCUB_INBOX1_SIZE);
485
486 diag_data->inbox0_rptr = REG_READ(DMCUB_INBOX0_RPTR);
487 diag_data->inbox0_wptr = REG_READ(DMCUB_INBOX0_WPTR);
488 diag_data->inbox0_size = REG_READ(DMCUB_INBOX0_SIZE);
489
490 REG_GET(DMCUB_CNTL, DMCUB_ENABLE, &is_dmub_enabled);
491 diag_data->is_dmcub_enabled = is_dmub_enabled;
492
493 REG_GET(DMCUB_CNTL2, DMCUB_SOFT_RESET, &is_soft_reset);
494 diag_data->is_dmcub_soft_reset = is_soft_reset;
495
496 REG_GET(DMCUB_SEC_CNTL, DMCUB_SEC_RESET_STATUS, &is_sec_reset);
497 diag_data->is_dmcub_secure_reset = is_sec_reset;
498
499 REG_GET(DMCUB_CNTL, DMCUB_TRACEPORT_EN, &is_traceport_enabled);
500 diag_data->is_traceport_en = is_traceport_enabled;
501
502 REG_GET(DMCUB_REGION3_CW0_TOP_ADDRESS, DMCUB_REGION3_CW0_ENABLE, &is_cw0_enabled);
503 diag_data->is_cw0_enabled = is_cw0_enabled;
504
505 REG_GET(DMCUB_REGION3_CW6_TOP_ADDRESS, DMCUB_REGION3_CW6_ENABLE, &is_cw6_enabled);
506 diag_data->is_cw6_enabled = is_cw6_enabled;
507
508 diag_data->gpint_datain0 = REG_READ(DMCUB_GPINT_DATAIN0);
509 }
dmub_dcn35_configure_dmub_in_system_memory(struct dmub_srv * dmub)510 void dmub_dcn35_configure_dmub_in_system_memory(struct dmub_srv *dmub)
511 {
512 /* DMCUB_REGION3_TMR_AXI_SPACE values:
513 * 0b011 (0x3) - FB physical address
514 * 0b100 (0x4) - GPU virtual address
515 *
516 * Default value is 0x3 (FB Physical address for TMR). When programming
517 * DMUB to be in system memory, change to 0x4. The system memory allocated
518 * is accessible by both GPU and CPU, so we use GPU virtual address.
519 */
520 REG_WRITE(DMCUB_REGION3_TMR_AXI_SPACE, 0x4);
521 }
522
dmub_dcn35_should_detect(struct dmub_srv * dmub)523 bool dmub_dcn35_should_detect(struct dmub_srv *dmub)
524 {
525 uint32_t fw_boot_status = REG_READ(DMCUB_SCRATCH0);
526 bool should_detect = (fw_boot_status & DMUB_FW_BOOT_STATUS_BIT_DETECTION_REQUIRED) != 0;
527 return should_detect;
528 }
529
dmub_dcn35_send_inbox0_cmd(struct dmub_srv * dmub,union dmub_inbox0_data_register data)530 void dmub_dcn35_send_inbox0_cmd(struct dmub_srv *dmub, union dmub_inbox0_data_register data)
531 {
532 REG_WRITE(DMCUB_INBOX0_WPTR, data.inbox0_cmd_common.all);
533 }
534
dmub_dcn35_clear_inbox0_ack_register(struct dmub_srv * dmub)535 void dmub_dcn35_clear_inbox0_ack_register(struct dmub_srv *dmub)
536 {
537 REG_WRITE(DMCUB_SCRATCH17, 0);
538 }
539
dmub_dcn35_read_inbox0_ack_register(struct dmub_srv * dmub)540 uint32_t dmub_dcn35_read_inbox0_ack_register(struct dmub_srv *dmub)
541 {
542 return REG_READ(DMCUB_SCRATCH17);
543 }
544
dmub_dcn35_is_hw_powered_up(struct dmub_srv * dmub)545 bool dmub_dcn35_is_hw_powered_up(struct dmub_srv *dmub)
546 {
547 union dmub_fw_boot_status status;
548
549 status.all = REG_READ(DMCUB_SCRATCH0);
550
551 return status.bits.hw_power_init_done;
552 }
553