1 /*
2 * Copyright 2017 Advanced Micro Devices, Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
21 *
22 * Authors: AMD
23 *
24 */
25
26 #include "../display_mode_lib.h"
27 #include "../display_mode_vba.h"
28 #include "../dml_inline_defs.h"
29 #include "display_rq_dlg_calc_31.h"
30 #include "../dcn30/display_mode_vba_30.h"
31
is_dual_plane(enum source_format_class source_format)32 static bool is_dual_plane(enum source_format_class source_format)
33 {
34 bool ret_val = 0;
35
36 if ((source_format == dm_420_12) || (source_format == dm_420_8) || (source_format == dm_420_10) || (source_format == dm_rgbe_alpha))
37 ret_val = 1;
38
39 return ret_val;
40 }
41
get_refcyc_per_delivery(struct display_mode_lib * mode_lib,double refclk_freq_in_mhz,double pclk_freq_in_mhz,unsigned int odm_combine,unsigned int recout_width,unsigned int hactive,double vratio,double hscale_pixel_rate,unsigned int delivery_width,unsigned int req_per_swath_ub)42 static double get_refcyc_per_delivery(
43 struct display_mode_lib *mode_lib,
44 double refclk_freq_in_mhz,
45 double pclk_freq_in_mhz,
46 unsigned int odm_combine,
47 unsigned int recout_width,
48 unsigned int hactive,
49 double vratio,
50 double hscale_pixel_rate,
51 unsigned int delivery_width,
52 unsigned int req_per_swath_ub)
53 {
54 double refcyc_per_delivery = 0.0;
55
56 if (vratio <= 1.0) {
57 if (odm_combine)
58 refcyc_per_delivery = (double) refclk_freq_in_mhz * (double) ((unsigned int) odm_combine * 2)
59 * dml_min((double) recout_width, (double) hactive / ((unsigned int) odm_combine * 2)) / pclk_freq_in_mhz / (double) req_per_swath_ub;
60 else
61 refcyc_per_delivery = (double) refclk_freq_in_mhz * (double) recout_width / pclk_freq_in_mhz / (double) req_per_swath_ub;
62 } else {
63 refcyc_per_delivery = (double) refclk_freq_in_mhz * (double) delivery_width / (double) hscale_pixel_rate / (double) req_per_swath_ub;
64 }
65
66 #ifdef __DML_RQ_DLG_CALC_DEBUG__
67 dml_print("DML_DLG: %s: refclk_freq_in_mhz = %3.2f\n", __func__, refclk_freq_in_mhz);
68 dml_print("DML_DLG: %s: pclk_freq_in_mhz = %3.2f\n", __func__, pclk_freq_in_mhz);
69 dml_print("DML_DLG: %s: recout_width = %d\n", __func__, recout_width);
70 dml_print("DML_DLG: %s: vratio = %3.2f\n", __func__, vratio);
71 dml_print("DML_DLG: %s: req_per_swath_ub = %d\n", __func__, req_per_swath_ub);
72 dml_print("DML_DLG: %s: hscale_pixel_rate = %3.2f\n", __func__, hscale_pixel_rate);
73 dml_print("DML_DLG: %s: delivery_width = %d\n", __func__, delivery_width);
74 dml_print("DML_DLG: %s: refcyc_per_delivery= %3.2f\n", __func__, refcyc_per_delivery);
75 #endif
76
77 return refcyc_per_delivery;
78
79 }
80
get_blk_size_bytes(const enum source_macro_tile_size tile_size)81 static unsigned int get_blk_size_bytes(const enum source_macro_tile_size tile_size)
82 {
83 if (tile_size == dm_256k_tile)
84 return (256 * 1024);
85 else if (tile_size == dm_64k_tile)
86 return (64 * 1024);
87 else
88 return (4 * 1024);
89 }
90
extract_rq_sizing_regs(struct display_mode_lib * mode_lib,display_data_rq_regs_st * rq_regs,const display_data_rq_sizing_params_st * rq_sizing)91 static void extract_rq_sizing_regs(struct display_mode_lib *mode_lib, display_data_rq_regs_st *rq_regs, const display_data_rq_sizing_params_st *rq_sizing)
92 {
93 print__data_rq_sizing_params_st(mode_lib, rq_sizing);
94
95 rq_regs->chunk_size = dml_log2(rq_sizing->chunk_bytes) - 10;
96
97 if (rq_sizing->min_chunk_bytes == 0)
98 rq_regs->min_chunk_size = 0;
99 else
100 rq_regs->min_chunk_size = dml_log2(rq_sizing->min_chunk_bytes) - 8 + 1;
101
102 rq_regs->meta_chunk_size = dml_log2(rq_sizing->meta_chunk_bytes) - 10;
103 if (rq_sizing->min_meta_chunk_bytes == 0)
104 rq_regs->min_meta_chunk_size = 0;
105 else
106 rq_regs->min_meta_chunk_size = dml_log2(rq_sizing->min_meta_chunk_bytes) - 6 + 1;
107
108 rq_regs->dpte_group_size = dml_log2(rq_sizing->dpte_group_bytes) - 6;
109 rq_regs->mpte_group_size = dml_log2(rq_sizing->mpte_group_bytes) - 6;
110 }
111
extract_rq_regs(struct display_mode_lib * mode_lib,display_rq_regs_st * rq_regs,const display_rq_params_st * rq_param)112 static void extract_rq_regs(struct display_mode_lib *mode_lib, display_rq_regs_st *rq_regs, const display_rq_params_st *rq_param)
113 {
114 unsigned int detile_buf_size_in_bytes = mode_lib->ip.det_buffer_size_kbytes * 1024;
115 unsigned int detile_buf_plane1_addr = 0;
116
117 extract_rq_sizing_regs(mode_lib, &(rq_regs->rq_regs_l), &rq_param->sizing.rq_l);
118
119 rq_regs->rq_regs_l.pte_row_height_linear = dml_floor(dml_log2(rq_param->dlg.rq_l.dpte_row_height), 1) - 3;
120
121 if (rq_param->yuv420) {
122 extract_rq_sizing_regs(mode_lib, &(rq_regs->rq_regs_c), &rq_param->sizing.rq_c);
123 rq_regs->rq_regs_c.pte_row_height_linear = dml_floor(dml_log2(rq_param->dlg.rq_c.dpte_row_height), 1) - 3;
124 }
125
126 rq_regs->rq_regs_l.swath_height = dml_log2(rq_param->dlg.rq_l.swath_height);
127 rq_regs->rq_regs_c.swath_height = dml_log2(rq_param->dlg.rq_c.swath_height);
128
129 // FIXME: take the max between luma, chroma chunk size?
130 // okay for now, as we are setting chunk_bytes to 8kb anyways
131 if (rq_param->sizing.rq_l.chunk_bytes >= 32 * 1024 || (rq_param->yuv420 && rq_param->sizing.rq_c.chunk_bytes >= 32 * 1024)) { //32kb
132 rq_regs->drq_expansion_mode = 0;
133 } else {
134 rq_regs->drq_expansion_mode = 2;
135 }
136 rq_regs->prq_expansion_mode = 1;
137 rq_regs->mrq_expansion_mode = 1;
138 rq_regs->crq_expansion_mode = 1;
139
140 // Note: detile_buf_plane1_addr is in unit of 1KB
141 if (rq_param->yuv420) {
142 if ((double) rq_param->misc.rq_l.stored_swath_bytes / (double) rq_param->misc.rq_c.stored_swath_bytes <= 1.5) {
143 detile_buf_plane1_addr = (detile_buf_size_in_bytes / 2.0 / 1024.0); // half to chroma
144 #ifdef __DML_RQ_DLG_CALC_DEBUG__
145 dml_print("DML_DLG: %s: detile_buf_plane1_addr = %0d (1/2 to chroma)\n", __func__, detile_buf_plane1_addr);
146 #endif
147 } else {
148 detile_buf_plane1_addr = dml_round_to_multiple((unsigned int) ((2.0 * detile_buf_size_in_bytes) / 3.0), 1024, 0) / 1024.0; // 2/3 to luma
149 #ifdef __DML_RQ_DLG_CALC_DEBUG__
150 dml_print("DML_DLG: %s: detile_buf_plane1_addr = %0d (1/3 chroma)\n", __func__, detile_buf_plane1_addr);
151 #endif
152 }
153 }
154 rq_regs->plane1_base_address = detile_buf_plane1_addr;
155
156 #ifdef __DML_RQ_DLG_CALC_DEBUG__
157 dml_print("DML_DLG: %s: detile_buf_size_in_bytes = %0d\n", __func__, detile_buf_size_in_bytes);
158 dml_print("DML_DLG: %s: detile_buf_plane1_addr = %0d\n", __func__, detile_buf_plane1_addr);
159 dml_print("DML_DLG: %s: plane1_base_address = %0d\n", __func__, rq_regs->plane1_base_address);
160 dml_print("DML_DLG: %s: rq_l.stored_swath_bytes = %0d\n", __func__, rq_param->misc.rq_l.stored_swath_bytes);
161 dml_print("DML_DLG: %s: rq_c.stored_swath_bytes = %0d\n", __func__, rq_param->misc.rq_c.stored_swath_bytes);
162 dml_print("DML_DLG: %s: rq_l.swath_height = %0d\n", __func__, rq_param->dlg.rq_l.swath_height);
163 dml_print("DML_DLG: %s: rq_c.swath_height = %0d\n", __func__, rq_param->dlg.rq_c.swath_height);
164 #endif
165 }
166
handle_det_buf_split(struct display_mode_lib * mode_lib,display_rq_params_st * rq_param,const display_pipe_source_params_st * pipe_src_param)167 static void handle_det_buf_split(struct display_mode_lib *mode_lib, display_rq_params_st *rq_param, const display_pipe_source_params_st *pipe_src_param)
168 {
169 unsigned int total_swath_bytes = 0;
170 unsigned int swath_bytes_l = 0;
171 unsigned int swath_bytes_c = 0;
172 unsigned int full_swath_bytes_packed_l = 0;
173 unsigned int full_swath_bytes_packed_c = 0;
174 bool req128_l = 0;
175 bool req128_c = 0;
176 bool surf_linear = (pipe_src_param->sw_mode == dm_sw_linear);
177 bool surf_vert = (pipe_src_param->source_scan == dm_vert);
178 unsigned int log2_swath_height_l = 0;
179 unsigned int log2_swath_height_c = 0;
180 unsigned int detile_buf_size_in_bytes = mode_lib->ip.det_buffer_size_kbytes * 1024;
181
182 full_swath_bytes_packed_l = rq_param->misc.rq_l.full_swath_bytes;
183 full_swath_bytes_packed_c = rq_param->misc.rq_c.full_swath_bytes;
184
185 #ifdef __DML_RQ_DLG_CALC_DEBUG__
186 dml_print("DML_DLG: %s: full_swath_bytes_packed_l = %0d\n", __func__, full_swath_bytes_packed_l);
187 dml_print("DML_DLG: %s: full_swath_bytes_packed_c = %0d\n", __func__, full_swath_bytes_packed_c);
188 #endif
189
190 if (rq_param->yuv420_10bpc) {
191 full_swath_bytes_packed_l = dml_round_to_multiple(rq_param->misc.rq_l.full_swath_bytes * 2.0 / 3.0, 256, 1) + 256;
192 full_swath_bytes_packed_c = dml_round_to_multiple(rq_param->misc.rq_c.full_swath_bytes * 2.0 / 3.0, 256, 1) + 256;
193 #ifdef __DML_RQ_DLG_CALC_DEBUG__
194 dml_print("DML_DLG: %s: full_swath_bytes_packed_l = %0d (3-2 packing)\n", __func__, full_swath_bytes_packed_l);
195 dml_print("DML_DLG: %s: full_swath_bytes_packed_c = %0d (3-2 packing)\n", __func__, full_swath_bytes_packed_c);
196 #endif
197 }
198
199 if (rq_param->yuv420)
200 total_swath_bytes = 2 * full_swath_bytes_packed_l + 2 * full_swath_bytes_packed_c;
201 else
202 total_swath_bytes = 2 * full_swath_bytes_packed_l;
203
204 #ifdef __DML_RQ_DLG_CALC_DEBUG__
205 dml_print("DML_DLG: %s: total_swath_bytes = %0d\n", __func__, total_swath_bytes);
206 dml_print("DML_DLG: %s: detile_buf_size_in_bytes = %0d\n", __func__, detile_buf_size_in_bytes);
207 #endif
208
209 if (total_swath_bytes <= detile_buf_size_in_bytes) { //full 256b request
210 req128_l = 0;
211 req128_c = 0;
212 swath_bytes_l = full_swath_bytes_packed_l;
213 swath_bytes_c = full_swath_bytes_packed_c;
214 } else if (!rq_param->yuv420) {
215 req128_l = 1;
216 req128_c = 0;
217 swath_bytes_c = full_swath_bytes_packed_c;
218 swath_bytes_l = full_swath_bytes_packed_l / 2;
219 } else if ((double) full_swath_bytes_packed_l / (double) full_swath_bytes_packed_c < 1.5) {
220 req128_l = 0;
221 req128_c = 1;
222 swath_bytes_l = full_swath_bytes_packed_l;
223 swath_bytes_c = full_swath_bytes_packed_c / 2;
224
225 total_swath_bytes = 2 * swath_bytes_l + 2 * swath_bytes_c;
226
227 if (total_swath_bytes > detile_buf_size_in_bytes) {
228 req128_l = 1;
229 swath_bytes_l = full_swath_bytes_packed_l / 2;
230 }
231 } else {
232 req128_l = 1;
233 req128_c = 0;
234 swath_bytes_l = full_swath_bytes_packed_l / 2;
235 swath_bytes_c = full_swath_bytes_packed_c;
236
237 total_swath_bytes = 2 * swath_bytes_l + 2 * swath_bytes_c;
238
239 if (total_swath_bytes > detile_buf_size_in_bytes) {
240 req128_c = 1;
241 swath_bytes_c = full_swath_bytes_packed_c / 2;
242 }
243 }
244
245 if (rq_param->yuv420)
246 total_swath_bytes = 2 * swath_bytes_l + 2 * swath_bytes_c;
247 else
248 total_swath_bytes = 2 * swath_bytes_l;
249
250 rq_param->misc.rq_l.stored_swath_bytes = swath_bytes_l;
251 rq_param->misc.rq_c.stored_swath_bytes = swath_bytes_c;
252
253 #ifdef __DML_RQ_DLG_CALC_DEBUG__
254 dml_print("DML_DLG: %s: total_swath_bytes = %0d\n", __func__, total_swath_bytes);
255 dml_print("DML_DLG: %s: rq_l.stored_swath_bytes = %0d\n", __func__, rq_param->misc.rq_l.stored_swath_bytes);
256 dml_print("DML_DLG: %s: rq_c.stored_swath_bytes = %0d\n", __func__, rq_param->misc.rq_c.stored_swath_bytes);
257 #endif
258 if (surf_linear) {
259 log2_swath_height_l = 0;
260 log2_swath_height_c = 0;
261 } else {
262 unsigned int swath_height_l;
263 unsigned int swath_height_c;
264
265 if (!surf_vert) {
266 swath_height_l = rq_param->misc.rq_l.blk256_height;
267 swath_height_c = rq_param->misc.rq_c.blk256_height;
268 } else {
269 swath_height_l = rq_param->misc.rq_l.blk256_width;
270 swath_height_c = rq_param->misc.rq_c.blk256_width;
271 }
272
273 if (swath_height_l > 0)
274 log2_swath_height_l = dml_log2(swath_height_l);
275
276 if (req128_l && log2_swath_height_l > 0)
277 log2_swath_height_l -= 1;
278
279 if (swath_height_c > 0)
280 log2_swath_height_c = dml_log2(swath_height_c);
281
282 if (req128_c && log2_swath_height_c > 0)
283 log2_swath_height_c -= 1;
284 }
285
286 rq_param->dlg.rq_l.swath_height = 1 << log2_swath_height_l;
287 rq_param->dlg.rq_c.swath_height = 1 << log2_swath_height_c;
288
289 #ifdef __DML_RQ_DLG_CALC_DEBUG__
290 dml_print("DML_DLG: %s: req128_l = %0d\n", __func__, req128_l);
291 dml_print("DML_DLG: %s: req128_c = %0d\n", __func__, req128_c);
292 dml_print("DML_DLG: %s: full_swath_bytes_packed_l = %0d\n", __func__, full_swath_bytes_packed_l);
293 dml_print("DML_DLG: %s: full_swath_bytes_packed_c = %0d\n", __func__, full_swath_bytes_packed_c);
294 dml_print("DML_DLG: %s: swath_height luma = %0d\n", __func__, rq_param->dlg.rq_l.swath_height);
295 dml_print("DML_DLG: %s: swath_height chroma = %0d\n", __func__, rq_param->dlg.rq_c.swath_height);
296 #endif
297 }
298
get_meta_and_pte_attr(struct display_mode_lib * mode_lib,display_data_rq_dlg_params_st * rq_dlg_param,display_data_rq_misc_params_st * rq_misc_param,display_data_rq_sizing_params_st * rq_sizing_param,unsigned int vp_width,unsigned int vp_height,unsigned int data_pitch,unsigned int meta_pitch,unsigned int source_format,unsigned int tiling,unsigned int macro_tile_size,unsigned int source_scan,unsigned int hostvm_enable,unsigned int is_chroma,unsigned int surface_height)299 static void get_meta_and_pte_attr(
300 struct display_mode_lib *mode_lib,
301 display_data_rq_dlg_params_st *rq_dlg_param,
302 display_data_rq_misc_params_st *rq_misc_param,
303 display_data_rq_sizing_params_st *rq_sizing_param,
304 unsigned int vp_width,
305 unsigned int vp_height,
306 unsigned int data_pitch,
307 unsigned int meta_pitch,
308 unsigned int source_format,
309 unsigned int tiling,
310 unsigned int macro_tile_size,
311 unsigned int source_scan,
312 unsigned int hostvm_enable,
313 unsigned int is_chroma,
314 unsigned int surface_height)
315 {
316 bool surf_linear = (tiling == dm_sw_linear);
317 bool surf_vert = (source_scan == dm_vert);
318
319 unsigned int bytes_per_element;
320 unsigned int bytes_per_element_y;
321 unsigned int bytes_per_element_c;
322
323 unsigned int blk256_width = 0;
324 unsigned int blk256_height = 0;
325
326 unsigned int blk256_width_y = 0;
327 unsigned int blk256_height_y = 0;
328 unsigned int blk256_width_c = 0;
329 unsigned int blk256_height_c = 0;
330 unsigned int log2_bytes_per_element;
331 unsigned int log2_blk256_width;
332 unsigned int log2_blk256_height;
333 unsigned int blk_bytes;
334 unsigned int log2_blk_bytes;
335 unsigned int log2_blk_height;
336 unsigned int log2_blk_width;
337 unsigned int log2_meta_req_bytes;
338 unsigned int log2_meta_req_height;
339 unsigned int log2_meta_req_width;
340 unsigned int meta_req_width;
341 unsigned int meta_req_height;
342 unsigned int log2_meta_row_height;
343 unsigned int meta_row_width_ub;
344 unsigned int log2_meta_chunk_bytes;
345 unsigned int log2_meta_chunk_height;
346
347 //full sized meta chunk width in unit of data elements
348 unsigned int log2_meta_chunk_width;
349 unsigned int log2_min_meta_chunk_bytes;
350 unsigned int min_meta_chunk_width;
351 unsigned int meta_chunk_width;
352 unsigned int meta_chunk_per_row_int;
353 unsigned int meta_row_remainder;
354 unsigned int meta_chunk_threshold;
355 unsigned int meta_blk_height;
356 unsigned int meta_surface_bytes;
357 unsigned int vmpg_bytes;
358 unsigned int meta_pte_req_per_frame_ub;
359 unsigned int meta_pte_bytes_per_frame_ub;
360 const unsigned int log2_vmpg_bytes = dml_log2(mode_lib->soc.gpuvm_min_page_size_bytes);
361 const bool dual_plane_en = is_dual_plane((enum source_format_class) (source_format));
362 const unsigned int dpte_buf_in_pte_reqs =
363 dual_plane_en ? (is_chroma ? mode_lib->ip.dpte_buffer_size_in_pte_reqs_chroma : mode_lib->ip.dpte_buffer_size_in_pte_reqs_luma) : (mode_lib->ip.dpte_buffer_size_in_pte_reqs_luma
364 + mode_lib->ip.dpte_buffer_size_in_pte_reqs_chroma);
365
366 unsigned int log2_vmpg_height = 0;
367 unsigned int log2_vmpg_width = 0;
368 unsigned int log2_dpte_req_height_ptes = 0;
369 unsigned int log2_dpte_req_height = 0;
370 unsigned int log2_dpte_req_width = 0;
371 unsigned int log2_dpte_row_height_linear = 0;
372 unsigned int log2_dpte_row_height = 0;
373 unsigned int log2_dpte_group_width = 0;
374 unsigned int dpte_row_width_ub = 0;
375 unsigned int dpte_req_height = 0;
376 unsigned int dpte_req_width = 0;
377 unsigned int dpte_group_width = 0;
378 unsigned int log2_dpte_group_bytes = 0;
379 unsigned int log2_dpte_group_length = 0;
380 double byte_per_pixel_det_y;
381 double byte_per_pixel_det_c;
382
383 dml30_CalculateBytePerPixelAnd256BBlockSizes(
384 (enum source_format_class) (source_format),
385 (enum dm_swizzle_mode) (tiling),
386 &bytes_per_element_y,
387 &bytes_per_element_c,
388 &byte_per_pixel_det_y,
389 &byte_per_pixel_det_c,
390 &blk256_height_y,
391 &blk256_height_c,
392 &blk256_width_y,
393 &blk256_width_c);
394
395 if (!is_chroma) {
396 blk256_width = blk256_width_y;
397 blk256_height = blk256_height_y;
398 bytes_per_element = bytes_per_element_y;
399 } else {
400 blk256_width = blk256_width_c;
401 blk256_height = blk256_height_c;
402 bytes_per_element = bytes_per_element_c;
403 }
404
405 log2_bytes_per_element = dml_log2(bytes_per_element);
406
407 dml_print("DML_DLG: %s: surf_linear = %d\n", __func__, surf_linear);
408 dml_print("DML_DLG: %s: surf_vert = %d\n", __func__, surf_vert);
409 dml_print("DML_DLG: %s: blk256_width = %d\n", __func__, blk256_width);
410 dml_print("DML_DLG: %s: blk256_height = %d\n", __func__, blk256_height);
411
412 log2_blk256_width = dml_log2((double) blk256_width);
413 log2_blk256_height = dml_log2((double) blk256_height);
414 blk_bytes = surf_linear ? 256 : get_blk_size_bytes((enum source_macro_tile_size) macro_tile_size);
415 log2_blk_bytes = dml_log2((double) blk_bytes);
416
417 // remember log rule
418 // "+" in log is multiply
419 // "-" in log is divide
420 // "/2" is like square root
421 // blk is vertical biased
422 if (tiling != dm_sw_linear)
423 log2_blk_height = log2_blk256_height + dml_ceil((double) (log2_blk_bytes - 8) / 2.0, 1);
424 else
425 log2_blk_height = 0; // blk height of 1
426
427 log2_blk_width = log2_blk_bytes - log2_bytes_per_element - log2_blk_height;
428
429 if (!surf_vert) {
430 int unsigned temp;
431
432 temp = dml_round_to_multiple(vp_width - 1, blk256_width, 1) + blk256_width;
433 if (data_pitch < blk256_width) {
434 dml_print("WARNING: DML_DLG: %s: swath_size calculation ignoring data_pitch=%u < blk256_width=%u\n", __func__, data_pitch, blk256_width);
435 } else {
436 if (temp > data_pitch) {
437 if (data_pitch >= vp_width)
438 temp = data_pitch;
439 else
440 dml_print("WARNING: DML_DLG: %s: swath_size calculation ignoring data_pitch=%u < vp_width=%u\n", __func__, data_pitch, vp_width);
441 }
442 }
443 rq_dlg_param->swath_width_ub = temp;
444 rq_dlg_param->req_per_swath_ub = temp >> log2_blk256_width;
445 } else {
446 int unsigned temp;
447
448 temp = dml_round_to_multiple(vp_height - 1, blk256_height, 1) + blk256_height;
449 if (surface_height < blk256_height) {
450 dml_print("WARNING: DML_DLG: %s swath_size calculation ignored surface_height=%u < blk256_height=%u\n", __func__, surface_height, blk256_height);
451 } else {
452 if (temp > surface_height) {
453 if (surface_height >= vp_height)
454 temp = surface_height;
455 else
456 dml_print("WARNING: DML_DLG: %s swath_size calculation ignored surface_height=%u < vp_height=%u\n", __func__, surface_height, vp_height);
457 }
458 }
459 rq_dlg_param->swath_width_ub = temp;
460 rq_dlg_param->req_per_swath_ub = temp >> log2_blk256_height;
461 }
462
463 if (!surf_vert)
464 rq_misc_param->full_swath_bytes = rq_dlg_param->swath_width_ub * blk256_height * bytes_per_element;
465 else
466 rq_misc_param->full_swath_bytes = rq_dlg_param->swath_width_ub * blk256_width * bytes_per_element;
467
468 rq_misc_param->blk256_height = blk256_height;
469 rq_misc_param->blk256_width = blk256_width;
470
471 // -------
472 // meta
473 // -------
474 log2_meta_req_bytes = 6; // meta request is 64b and is 8x8byte meta element
475
476 // each 64b meta request for dcn is 8x8 meta elements and
477 // a meta element covers one 256b block of the data surface.
478 log2_meta_req_height = log2_blk256_height + 3; // meta req is 8x8 byte, each byte represent 1 blk256
479 log2_meta_req_width = log2_meta_req_bytes + 8 - log2_bytes_per_element - log2_meta_req_height;
480 meta_req_width = 1 << log2_meta_req_width;
481 meta_req_height = 1 << log2_meta_req_height;
482
483 // the dimensions of a meta row are meta_row_width x meta_row_height in elements.
484 // calculate upper bound of the meta_row_width
485 if (!surf_vert) {
486 log2_meta_row_height = log2_meta_req_height;
487 meta_row_width_ub = dml_round_to_multiple(vp_width - 1, meta_req_width, 1) + meta_req_width;
488 rq_dlg_param->meta_req_per_row_ub = meta_row_width_ub / meta_req_width;
489 } else {
490 log2_meta_row_height = log2_meta_req_width;
491 meta_row_width_ub = dml_round_to_multiple(vp_height - 1, meta_req_height, 1) + meta_req_height;
492 rq_dlg_param->meta_req_per_row_ub = meta_row_width_ub / meta_req_height;
493 }
494 rq_dlg_param->meta_bytes_per_row_ub = rq_dlg_param->meta_req_per_row_ub * 64;
495
496 rq_dlg_param->meta_row_height = 1 << log2_meta_row_height;
497
498 log2_meta_chunk_bytes = dml_log2(rq_sizing_param->meta_chunk_bytes);
499 log2_meta_chunk_height = log2_meta_row_height;
500
501 //full sized meta chunk width in unit of data elements
502 log2_meta_chunk_width = log2_meta_chunk_bytes + 8 - log2_bytes_per_element - log2_meta_chunk_height;
503 log2_min_meta_chunk_bytes = dml_log2(rq_sizing_param->min_meta_chunk_bytes);
504 min_meta_chunk_width = 1 << (log2_min_meta_chunk_bytes + 8 - log2_bytes_per_element - log2_meta_chunk_height);
505 meta_chunk_width = 1 << log2_meta_chunk_width;
506 meta_chunk_per_row_int = (unsigned int) (meta_row_width_ub / meta_chunk_width);
507 meta_row_remainder = meta_row_width_ub % meta_chunk_width;
508 meta_chunk_threshold = 0;
509 meta_blk_height = blk256_height * 64;
510 meta_surface_bytes = meta_pitch * (dml_round_to_multiple(vp_height - 1, meta_blk_height, 1) + meta_blk_height) * bytes_per_element / 256;
511 vmpg_bytes = mode_lib->soc.gpuvm_min_page_size_bytes;
512 meta_pte_req_per_frame_ub = (dml_round_to_multiple(meta_surface_bytes - vmpg_bytes, 8 * vmpg_bytes, 1) + 8 * vmpg_bytes) / (8 * vmpg_bytes);
513 meta_pte_bytes_per_frame_ub = meta_pte_req_per_frame_ub * 64; //64B mpte request
514 rq_dlg_param->meta_pte_bytes_per_frame_ub = meta_pte_bytes_per_frame_ub;
515
516 dml_print("DML_DLG: %s: meta_blk_height = %d\n", __func__, meta_blk_height);
517 dml_print("DML_DLG: %s: meta_surface_bytes = %d\n", __func__, meta_surface_bytes);
518 dml_print("DML_DLG: %s: meta_pte_req_per_frame_ub = %d\n", __func__, meta_pte_req_per_frame_ub);
519 dml_print("DML_DLG: %s: meta_pte_bytes_per_frame_ub = %d\n", __func__, meta_pte_bytes_per_frame_ub);
520
521 if (!surf_vert)
522 meta_chunk_threshold = 2 * min_meta_chunk_width - meta_req_width;
523 else
524 meta_chunk_threshold = 2 * min_meta_chunk_width - meta_req_height;
525
526 if (meta_row_remainder <= meta_chunk_threshold)
527 rq_dlg_param->meta_chunks_per_row_ub = meta_chunk_per_row_int + 1;
528 else
529 rq_dlg_param->meta_chunks_per_row_ub = meta_chunk_per_row_int + 2;
530
531 // ------
532 // dpte
533 // ------
534 if (surf_linear) {
535 log2_vmpg_height = 0; // one line high
536 } else {
537 log2_vmpg_height = (log2_vmpg_bytes - 8) / 2 + log2_blk256_height;
538 }
539 log2_vmpg_width = log2_vmpg_bytes - log2_bytes_per_element - log2_vmpg_height;
540
541 // only 3 possible shapes for dpte request in dimensions of ptes: 8x1, 4x2, 2x4.
542 if (surf_linear) { //one 64B PTE request returns 8 PTEs
543 log2_dpte_req_height_ptes = 0;
544 log2_dpte_req_width = log2_vmpg_width + 3;
545 log2_dpte_req_height = 0;
546 } else if (log2_blk_bytes == 12) { //4KB tile means 4kB page size
547 //one 64B req gives 8x1 PTEs for 4KB tile
548 log2_dpte_req_height_ptes = 0;
549 log2_dpte_req_width = log2_blk_width + 3;
550 log2_dpte_req_height = log2_blk_height + 0;
551 } else if ((log2_blk_bytes >= 16) && (log2_vmpg_bytes == 12)) { // tile block >= 64KB
552 //two 64B reqs of 2x4 PTEs give 16 PTEs to cover 64KB
553 log2_dpte_req_height_ptes = 4;
554 log2_dpte_req_width = log2_blk256_width + 4; // log2_64KB_width
555 log2_dpte_req_height = log2_blk256_height + 4; // log2_64KB_height
556 } else { //64KB page size and must 64KB tile block
557 //one 64B req gives 8x1 PTEs for 64KB tile
558 log2_dpte_req_height_ptes = 0;
559 log2_dpte_req_width = log2_blk_width + 3;
560 log2_dpte_req_height = log2_blk_height + 0;
561 }
562
563 // The dpte request dimensions in data elements is dpte_req_width x dpte_req_height
564 // log2_vmpg_width is how much 1 pte represent, now calculating how much a 64b pte req represent
565 // That depends on the pte shape (i.e. 8x1, 4x2, 2x4)
566 //log2_dpte_req_height = log2_vmpg_height + log2_dpte_req_height_ptes;
567 //log2_dpte_req_width = log2_vmpg_width + log2_dpte_req_width_ptes;
568 dpte_req_height = 1 << log2_dpte_req_height;
569 dpte_req_width = 1 << log2_dpte_req_width;
570
571 // calculate pitch dpte row buffer can hold
572 // round the result down to a power of two.
573 if (surf_linear) {
574 unsigned int dpte_row_height;
575
576 log2_dpte_row_height_linear = dml_floor(dml_log2(dpte_buf_in_pte_reqs * dpte_req_width / data_pitch), 1);
577
578 dml_print("DML_DLG: %s: is_chroma = %d\n", __func__, is_chroma);
579 dml_print("DML_DLG: %s: dpte_buf_in_pte_reqs = %d\n", __func__, dpte_buf_in_pte_reqs);
580 dml_print("DML_DLG: %s: log2_dpte_row_height_linear = %d\n", __func__, log2_dpte_row_height_linear);
581
582 ASSERT(log2_dpte_row_height_linear >= 3);
583
584 if (log2_dpte_row_height_linear > 7)
585 log2_dpte_row_height_linear = 7;
586
587 log2_dpte_row_height = log2_dpte_row_height_linear;
588 // For linear, the dpte row is pitch dependent and the pte requests wrap at the pitch boundary.
589 // the dpte_row_width_ub is the upper bound of data_pitch*dpte_row_height in elements with this unique buffering.
590 dpte_row_height = 1 << log2_dpte_row_height;
591 dpte_row_width_ub = dml_round_to_multiple(data_pitch * dpte_row_height - 1, dpte_req_width, 1) + dpte_req_width;
592 rq_dlg_param->dpte_req_per_row_ub = dpte_row_width_ub / dpte_req_width;
593 } else {
594 // the upper bound of the dpte_row_width without dependency on viewport position follows.
595 // for tiled mode, row height is the same as req height and row store up to vp size upper bound
596 if (!surf_vert) {
597 log2_dpte_row_height = log2_dpte_req_height;
598 dpte_row_width_ub = dml_round_to_multiple(vp_width - 1, dpte_req_width, 1) + dpte_req_width;
599 rq_dlg_param->dpte_req_per_row_ub = dpte_row_width_ub / dpte_req_width;
600 } else {
601 log2_dpte_row_height = (log2_blk_width < log2_dpte_req_width) ? log2_blk_width : log2_dpte_req_width;
602 dpte_row_width_ub = dml_round_to_multiple(vp_height - 1, dpte_req_height, 1) + dpte_req_height;
603 rq_dlg_param->dpte_req_per_row_ub = dpte_row_width_ub / dpte_req_height;
604 }
605 }
606 if (log2_blk_bytes >= 16 && log2_vmpg_bytes == 12) // tile block >= 64KB
607 rq_dlg_param->dpte_bytes_per_row_ub = rq_dlg_param->dpte_req_per_row_ub * 128; //2*64B dpte request
608 else
609 rq_dlg_param->dpte_bytes_per_row_ub = rq_dlg_param->dpte_req_per_row_ub * 64; //64B dpte request
610
611 rq_dlg_param->dpte_row_height = 1 << log2_dpte_row_height;
612
613 // the dpte_group_bytes is reduced for the specific case of vertical
614 // access of a tile surface that has dpte request of 8x1 ptes.
615 if (hostvm_enable)
616 rq_sizing_param->dpte_group_bytes = 512;
617 else {
618 if (!surf_linear & (log2_dpte_req_height_ptes == 0) & surf_vert) //reduced, in this case, will have page fault within a group
619 rq_sizing_param->dpte_group_bytes = 512;
620 else
621 rq_sizing_param->dpte_group_bytes = 2048;
622 }
623
624 //since pte request size is 64byte, the number of data pte requests per full sized group is as follows.
625 log2_dpte_group_bytes = dml_log2(rq_sizing_param->dpte_group_bytes);
626 log2_dpte_group_length = log2_dpte_group_bytes - 6; //length in 64b requests
627
628 // full sized data pte group width in elements
629 if (!surf_vert)
630 log2_dpte_group_width = log2_dpte_group_length + log2_dpte_req_width;
631 else
632 log2_dpte_group_width = log2_dpte_group_length + log2_dpte_req_height;
633
634 //But if the tile block >=64KB and the page size is 4KB, then each dPTE request is 2*64B
635 if ((log2_blk_bytes >= 16) && (log2_vmpg_bytes == 12)) // tile block >= 64KB
636 log2_dpte_group_width = log2_dpte_group_width - 1;
637
638 dpte_group_width = 1 << log2_dpte_group_width;
639
640 // since dpte groups are only aligned to dpte_req_width and not dpte_group_width,
641 // the upper bound for the dpte groups per row is as follows.
642 rq_dlg_param->dpte_groups_per_row_ub = dml_ceil((double) dpte_row_width_ub / dpte_group_width, 1);
643 }
644
get_surf_rq_param(struct display_mode_lib * mode_lib,display_data_rq_sizing_params_st * rq_sizing_param,display_data_rq_dlg_params_st * rq_dlg_param,display_data_rq_misc_params_st * rq_misc_param,const display_pipe_params_st * pipe_param,bool is_chroma,bool is_alpha)645 static void get_surf_rq_param(
646 struct display_mode_lib *mode_lib,
647 display_data_rq_sizing_params_st *rq_sizing_param,
648 display_data_rq_dlg_params_st *rq_dlg_param,
649 display_data_rq_misc_params_st *rq_misc_param,
650 const display_pipe_params_st *pipe_param,
651 bool is_chroma,
652 bool is_alpha)
653 {
654 unsigned int vp_width = 0;
655 unsigned int vp_height = 0;
656 unsigned int data_pitch = 0;
657 unsigned int meta_pitch = 0;
658 unsigned int surface_height = 0;
659 unsigned int ppe = 1;
660
661 // FIXME check if ppe apply for both luma and chroma in 422 case
662 if (is_chroma | is_alpha) {
663 vp_width = pipe_param->src.viewport_width_c / ppe;
664 vp_height = pipe_param->src.viewport_height_c;
665 data_pitch = pipe_param->src.data_pitch_c;
666 meta_pitch = pipe_param->src.meta_pitch_c;
667 surface_height = pipe_param->src.surface_height_y / 2.0;
668 } else {
669 vp_width = pipe_param->src.viewport_width / ppe;
670 vp_height = pipe_param->src.viewport_height;
671 data_pitch = pipe_param->src.data_pitch;
672 meta_pitch = pipe_param->src.meta_pitch;
673 surface_height = pipe_param->src.surface_height_y;
674 }
675
676 if (pipe_param->dest.odm_combine) {
677 unsigned int access_dir;
678 unsigned int full_src_vp_width;
679 unsigned int hactive_odm;
680 unsigned int src_hactive_odm;
681
682 access_dir = (pipe_param->src.source_scan == dm_vert); // vp access direction: horizontal or vertical accessed
683 hactive_odm = pipe_param->dest.hactive / ((unsigned int) pipe_param->dest.odm_combine * 2);
684 if (is_chroma) {
685 full_src_vp_width = pipe_param->scale_ratio_depth.hscl_ratio_c * pipe_param->dest.full_recout_width;
686 src_hactive_odm = pipe_param->scale_ratio_depth.hscl_ratio_c * hactive_odm;
687 } else {
688 full_src_vp_width = pipe_param->scale_ratio_depth.hscl_ratio * pipe_param->dest.full_recout_width;
689 src_hactive_odm = pipe_param->scale_ratio_depth.hscl_ratio * hactive_odm;
690 }
691
692 if (access_dir == 0) {
693 vp_width = dml_min(full_src_vp_width, src_hactive_odm);
694 dml_print("DML_DLG: %s: vp_width = %d\n", __func__, vp_width);
695 } else {
696 vp_height = dml_min(full_src_vp_width, src_hactive_odm);
697 dml_print("DML_DLG: %s: vp_height = %d\n", __func__, vp_height);
698
699 }
700 dml_print("DML_DLG: %s: full_src_vp_width = %d\n", __func__, full_src_vp_width);
701 dml_print("DML_DLG: %s: hactive_odm = %d\n", __func__, hactive_odm);
702 dml_print("DML_DLG: %s: src_hactive_odm = %d\n", __func__, src_hactive_odm);
703 }
704
705 rq_sizing_param->chunk_bytes = 8192;
706
707 if (is_alpha) {
708 rq_sizing_param->chunk_bytes = 4096;
709 }
710
711 if (rq_sizing_param->chunk_bytes == 64 * 1024)
712 rq_sizing_param->min_chunk_bytes = 0;
713 else
714 rq_sizing_param->min_chunk_bytes = 1024;
715
716 rq_sizing_param->meta_chunk_bytes = 2048;
717 rq_sizing_param->min_meta_chunk_bytes = 256;
718
719 if (pipe_param->src.hostvm)
720 rq_sizing_param->mpte_group_bytes = 512;
721 else
722 rq_sizing_param->mpte_group_bytes = 2048;
723
724 get_meta_and_pte_attr(
725 mode_lib,
726 rq_dlg_param,
727 rq_misc_param,
728 rq_sizing_param,
729 vp_width,
730 vp_height,
731 data_pitch,
732 meta_pitch,
733 pipe_param->src.source_format,
734 pipe_param->src.sw_mode,
735 pipe_param->src.macro_tile_size,
736 pipe_param->src.source_scan,
737 pipe_param->src.hostvm,
738 is_chroma,
739 surface_height);
740 }
741
dml_rq_dlg_get_rq_params(struct display_mode_lib * mode_lib,display_rq_params_st * rq_param,const display_pipe_params_st * pipe_param)742 static void dml_rq_dlg_get_rq_params(struct display_mode_lib *mode_lib, display_rq_params_st *rq_param, const display_pipe_params_st *pipe_param)
743 {
744 // get param for luma surface
745 rq_param->yuv420 = pipe_param->src.source_format == dm_420_8 || pipe_param->src.source_format == dm_420_10 || pipe_param->src.source_format == dm_rgbe_alpha
746 || pipe_param->src.source_format == dm_420_12;
747
748 rq_param->yuv420_10bpc = pipe_param->src.source_format == dm_420_10;
749
750 rq_param->rgbe_alpha = (pipe_param->src.source_format == dm_rgbe_alpha) ? 1 : 0;
751
752 get_surf_rq_param(mode_lib, &(rq_param->sizing.rq_l), &(rq_param->dlg.rq_l), &(rq_param->misc.rq_l), pipe_param, 0, 0);
753
754 if (is_dual_plane((enum source_format_class) (pipe_param->src.source_format))) {
755 // get param for chroma surface
756 get_surf_rq_param(mode_lib, &(rq_param->sizing.rq_c), &(rq_param->dlg.rq_c), &(rq_param->misc.rq_c), pipe_param, 1, rq_param->rgbe_alpha);
757 }
758
759 // calculate how to split the det buffer space between luma and chroma
760 handle_det_buf_split(mode_lib, rq_param, &pipe_param->src);
761 print__rq_params_st(mode_lib, rq_param);
762 }
763
dml31_rq_dlg_get_rq_reg(struct display_mode_lib * mode_lib,display_rq_regs_st * rq_regs,const display_pipe_params_st * pipe_param)764 void dml31_rq_dlg_get_rq_reg(struct display_mode_lib *mode_lib, display_rq_regs_st *rq_regs, const display_pipe_params_st *pipe_param)
765 {
766 display_rq_params_st rq_param = {0};
767
768 memset(rq_regs, 0, sizeof(*rq_regs));
769 dml_rq_dlg_get_rq_params(mode_lib, &rq_param, pipe_param);
770 extract_rq_regs(mode_lib, rq_regs, &rq_param);
771
772 print__rq_regs_st(mode_lib, rq_regs);
773 }
774
calculate_ttu_cursor(struct display_mode_lib * mode_lib,double * refcyc_per_req_delivery_pre_cur,double * refcyc_per_req_delivery_cur,double refclk_freq_in_mhz,double ref_freq_to_pix_freq,double hscale_pixel_rate_l,double hscl_ratio,double vratio_pre_l,double vratio_l,unsigned int cur_width,enum cursor_bpp cur_bpp)775 static void calculate_ttu_cursor(
776 struct display_mode_lib *mode_lib,
777 double *refcyc_per_req_delivery_pre_cur,
778 double *refcyc_per_req_delivery_cur,
779 double refclk_freq_in_mhz,
780 double ref_freq_to_pix_freq,
781 double hscale_pixel_rate_l,
782 double hscl_ratio,
783 double vratio_pre_l,
784 double vratio_l,
785 unsigned int cur_width,
786 enum cursor_bpp cur_bpp)
787 {
788 unsigned int cur_src_width = cur_width;
789 unsigned int cur_req_size = 0;
790 unsigned int cur_req_width = 0;
791 double cur_width_ub = 0.0;
792 double cur_req_per_width = 0.0;
793 double hactive_cur = 0.0;
794
795 ASSERT(cur_src_width <= 256);
796
797 *refcyc_per_req_delivery_pre_cur = 0.0;
798 *refcyc_per_req_delivery_cur = 0.0;
799 if (cur_src_width > 0) {
800 unsigned int cur_bit_per_pixel = 0;
801
802 if (cur_bpp == dm_cur_2bit) {
803 cur_req_size = 64; // byte
804 cur_bit_per_pixel = 2;
805 } else { // 32bit
806 cur_bit_per_pixel = 32;
807 if (cur_src_width >= 1 && cur_src_width <= 16)
808 cur_req_size = 64;
809 else if (cur_src_width >= 17 && cur_src_width <= 31)
810 cur_req_size = 128;
811 else
812 cur_req_size = 256;
813 }
814
815 cur_req_width = (double) cur_req_size / ((double) cur_bit_per_pixel / 8.0);
816 cur_width_ub = dml_ceil((double) cur_src_width / (double) cur_req_width, 1) * (double) cur_req_width;
817 cur_req_per_width = cur_width_ub / (double) cur_req_width;
818 hactive_cur = (double) cur_src_width / hscl_ratio; // FIXME: oswin to think about what to do for cursor
819
820 if (vratio_pre_l <= 1.0) {
821 *refcyc_per_req_delivery_pre_cur = hactive_cur * ref_freq_to_pix_freq / (double) cur_req_per_width;
822 } else {
823 *refcyc_per_req_delivery_pre_cur = (double) refclk_freq_in_mhz * (double) cur_src_width / hscale_pixel_rate_l / (double) cur_req_per_width;
824 }
825
826 ASSERT(*refcyc_per_req_delivery_pre_cur < dml_pow(2, 13));
827
828 if (vratio_l <= 1.0) {
829 *refcyc_per_req_delivery_cur = hactive_cur * ref_freq_to_pix_freq / (double) cur_req_per_width;
830 } else {
831 *refcyc_per_req_delivery_cur = (double) refclk_freq_in_mhz * (double) cur_src_width / hscale_pixel_rate_l / (double) cur_req_per_width;
832 }
833
834 dml_print("DML_DLG: %s: cur_req_width = %d\n", __func__, cur_req_width);
835 dml_print("DML_DLG: %s: cur_width_ub = %3.2f\n", __func__, cur_width_ub);
836 dml_print("DML_DLG: %s: cur_req_per_width = %3.2f\n", __func__, cur_req_per_width);
837 dml_print("DML_DLG: %s: hactive_cur = %3.2f\n", __func__, hactive_cur);
838 dml_print("DML_DLG: %s: refcyc_per_req_delivery_pre_cur = %3.2f\n", __func__, *refcyc_per_req_delivery_pre_cur);
839 dml_print("DML_DLG: %s: refcyc_per_req_delivery_cur = %3.2f\n", __func__, *refcyc_per_req_delivery_cur);
840
841 ASSERT(*refcyc_per_req_delivery_cur < dml_pow(2, 13));
842 }
843 }
844
845 // Note: currently taken in as is.
846 // Nice to decouple code from hw register implement and extract code that are repeated for luma and chroma.
dml_rq_dlg_get_dlg_params(struct display_mode_lib * mode_lib,const display_e2e_pipe_params_st * e2e_pipe_param,const unsigned int num_pipes,const unsigned int pipe_idx,display_dlg_regs_st * disp_dlg_regs,display_ttu_regs_st * disp_ttu_regs,const display_rq_dlg_params_st * rq_dlg_param,const display_dlg_sys_params_st * dlg_sys_param,const bool cstate_en,const bool pstate_en,const bool vm_en,const bool ignore_viewport_pos,const bool immediate_flip_support)847 static void dml_rq_dlg_get_dlg_params(
848 struct display_mode_lib *mode_lib,
849 const display_e2e_pipe_params_st *e2e_pipe_param,
850 const unsigned int num_pipes,
851 const unsigned int pipe_idx,
852 display_dlg_regs_st *disp_dlg_regs,
853 display_ttu_regs_st *disp_ttu_regs,
854 const display_rq_dlg_params_st *rq_dlg_param,
855 const display_dlg_sys_params_st *dlg_sys_param,
856 const bool cstate_en,
857 const bool pstate_en,
858 const bool vm_en,
859 const bool ignore_viewport_pos,
860 const bool immediate_flip_support)
861 {
862 const display_pipe_source_params_st *src = &e2e_pipe_param[pipe_idx].pipe.src;
863 const display_pipe_dest_params_st *dst = &e2e_pipe_param[pipe_idx].pipe.dest;
864 const display_clocks_and_cfg_st *clks = &e2e_pipe_param[pipe_idx].clks_cfg;
865 const scaler_ratio_depth_st *scl = &e2e_pipe_param[pipe_idx].pipe.scale_ratio_depth;
866 const scaler_taps_st *taps = &e2e_pipe_param[pipe_idx].pipe.scale_taps;
867 unsigned int pipe_index_in_combine[DC__NUM_PIPES__MAX];
868
869 // -------------------------
870 // Section 1.15.2.1: OTG dependent Params
871 // -------------------------
872 // Timing
873 unsigned int htotal = dst->htotal;
874 unsigned int hblank_end = dst->hblank_end;
875 unsigned int vblank_start = dst->vblank_start;
876 unsigned int vblank_end = dst->vblank_end;
877
878 double dppclk_freq_in_mhz = clks->dppclk_mhz;
879 double refclk_freq_in_mhz = clks->refclk_mhz;
880 double pclk_freq_in_mhz = dst->pixel_rate_mhz;
881 bool interlaced = dst->interlaced;
882 double ref_freq_to_pix_freq = refclk_freq_in_mhz / pclk_freq_in_mhz;
883 double min_ttu_vblank;
884 unsigned int dlg_vblank_start;
885 bool dual_plane;
886 unsigned int access_dir;
887 unsigned int vp_height_l;
888 unsigned int vp_width_l;
889 unsigned int vp_height_c;
890 unsigned int vp_width_c;
891
892 // Scaling
893 unsigned int htaps_l;
894 unsigned int htaps_c;
895 double hratio_l;
896 double hratio_c;
897 double vratio_l;
898 double vratio_c;
899
900 unsigned int swath_width_ub_l;
901 unsigned int dpte_groups_per_row_ub_l;
902 unsigned int swath_width_ub_c;
903 unsigned int dpte_groups_per_row_ub_c;
904
905 unsigned int meta_chunks_per_row_ub_l;
906 unsigned int meta_chunks_per_row_ub_c;
907 unsigned int vupdate_offset;
908 unsigned int vupdate_width;
909 unsigned int vready_offset;
910
911 unsigned int vstartup_start;
912 unsigned int dst_x_after_scaler;
913 unsigned int dst_y_after_scaler;
914 double dst_y_prefetch;
915 double dst_y_per_vm_vblank;
916 double dst_y_per_row_vblank;
917 double dst_y_per_vm_flip;
918 double dst_y_per_row_flip;
919 double max_dst_y_per_vm_vblank;
920 double max_dst_y_per_row_vblank;
921 double vratio_pre_l;
922 double vratio_pre_c;
923 unsigned int req_per_swath_ub_l;
924 unsigned int req_per_swath_ub_c;
925 unsigned int meta_row_height_l;
926 unsigned int meta_row_height_c;
927 unsigned int swath_width_pixels_ub_l;
928 unsigned int swath_width_pixels_ub_c;
929 unsigned int scaler_rec_in_width_l;
930 unsigned int scaler_rec_in_width_c;
931 unsigned int dpte_row_height_l;
932 unsigned int dpte_row_height_c;
933 double hscale_pixel_rate_l;
934 double hscale_pixel_rate_c;
935 double min_hratio_fact_l;
936 double min_hratio_fact_c;
937 double refcyc_per_line_delivery_pre_l;
938 double refcyc_per_line_delivery_pre_c;
939 double refcyc_per_line_delivery_l;
940 double refcyc_per_line_delivery_c;
941
942 double refcyc_per_req_delivery_pre_l;
943 double refcyc_per_req_delivery_pre_c;
944 double refcyc_per_req_delivery_l;
945 double refcyc_per_req_delivery_c;
946
947 unsigned int full_recout_width;
948 double refcyc_per_req_delivery_pre_cur0;
949 double refcyc_per_req_delivery_cur0;
950 double refcyc_per_req_delivery_pre_cur1;
951 double refcyc_per_req_delivery_cur1;
952 int unsigned vba__min_dst_y_next_start = get_min_dst_y_next_start(mode_lib, e2e_pipe_param, num_pipes, pipe_idx); // FROM VBA
953 int unsigned vba__vready_after_vcount0 = get_vready_at_or_after_vsync(mode_lib, e2e_pipe_param, num_pipes, pipe_idx); // From VBA
954
955 float vba__refcyc_per_line_delivery_pre_l = get_refcyc_per_line_delivery_pre_l_in_us(mode_lib, e2e_pipe_param, num_pipes, pipe_idx) * refclk_freq_in_mhz; // From VBA
956 float vba__refcyc_per_line_delivery_l = get_refcyc_per_line_delivery_l_in_us(mode_lib, e2e_pipe_param, num_pipes, pipe_idx) * refclk_freq_in_mhz; // From VBA
957
958 float vba__refcyc_per_req_delivery_pre_l = get_refcyc_per_req_delivery_pre_l_in_us(mode_lib, e2e_pipe_param, num_pipes, pipe_idx) * refclk_freq_in_mhz; // From VBA
959 float vba__refcyc_per_req_delivery_l = get_refcyc_per_req_delivery_l_in_us(mode_lib, e2e_pipe_param, num_pipes, pipe_idx) * refclk_freq_in_mhz; // From VBA
960
961 memset(disp_dlg_regs, 0, sizeof(*disp_dlg_regs));
962 memset(disp_ttu_regs, 0, sizeof(*disp_ttu_regs));
963
964 dml_print("DML_DLG: %s: cstate_en = %d\n", __func__, cstate_en);
965 dml_print("DML_DLG: %s: pstate_en = %d\n", __func__, pstate_en);
966 dml_print("DML_DLG: %s: vm_en = %d\n", __func__, vm_en);
967 dml_print("DML_DLG: %s: ignore_viewport_pos = %d\n", __func__, ignore_viewport_pos);
968 dml_print("DML_DLG: %s: immediate_flip_support = %d\n", __func__, immediate_flip_support);
969
970 dml_print("DML_DLG: %s: dppclk_freq_in_mhz = %3.2f\n", __func__, dppclk_freq_in_mhz);
971 dml_print("DML_DLG: %s: refclk_freq_in_mhz = %3.2f\n", __func__, refclk_freq_in_mhz);
972 dml_print("DML_DLG: %s: pclk_freq_in_mhz = %3.2f\n", __func__, pclk_freq_in_mhz);
973 dml_print("DML_DLG: %s: interlaced = %d\n", __func__, interlaced); ASSERT(ref_freq_to_pix_freq < 4.0);
974
975 disp_dlg_regs->ref_freq_to_pix_freq = (unsigned int) (ref_freq_to_pix_freq * dml_pow(2, 19));
976 disp_dlg_regs->refcyc_per_htotal = (unsigned int) (ref_freq_to_pix_freq * (double) htotal * dml_pow(2, 8));
977 disp_dlg_regs->dlg_vblank_end = interlaced ? (vblank_end / 2) : vblank_end; // 15 bits
978
979 //set_prefetch_mode(mode_lib, cstate_en, pstate_en, ignore_viewport_pos, immediate_flip_support);
980 min_ttu_vblank = get_min_ttu_vblank_in_us(mode_lib, e2e_pipe_param, num_pipes, pipe_idx); // From VBA
981
982 dlg_vblank_start = interlaced ? (vblank_start / 2) : vblank_start;
983 disp_dlg_regs->min_dst_y_next_start = (unsigned int) (((double) dlg_vblank_start) * dml_pow(2, 2));
984 disp_dlg_regs->min_dst_y_next_start_us = 0;
985 ASSERT(disp_dlg_regs->min_dst_y_next_start < (unsigned int)dml_pow(2, 18));
986
987 dml_print("DML_DLG: %s: min_ttu_vblank (us) = %3.2f\n", __func__, min_ttu_vblank);
988 dml_print("DML_DLG: %s: min_dst_y_next_start = 0x%0x\n", __func__, disp_dlg_regs->min_dst_y_next_start);
989 dml_print("DML_DLG: %s: dlg_vblank_start = 0x%0x\n", __func__, dlg_vblank_start);
990 dml_print("DML_DLG: %s: ref_freq_to_pix_freq = %3.2f\n", __func__, ref_freq_to_pix_freq);
991 dml_print("DML_DLG: %s: vba__min_dst_y_next_start = 0x%0x\n", __func__, vba__min_dst_y_next_start);
992
993 //old_impl_vs_vba_impl("min_dst_y_next_start", dlg_vblank_start, vba__min_dst_y_next_start);
994
995 // -------------------------
996 // Section 1.15.2.2: Prefetch, Active and TTU
997 // -------------------------
998 // Prefetch Calc
999 // Source
1000 dual_plane = is_dual_plane((enum source_format_class) (src->source_format));
1001 access_dir = (src->source_scan == dm_vert); // vp access direction: horizontal or vertical accessed
1002 vp_height_l = src->viewport_height;
1003 vp_width_l = src->viewport_width;
1004 vp_height_c = src->viewport_height_c;
1005 vp_width_c = src->viewport_width_c;
1006
1007 // Scaling
1008 htaps_l = taps->htaps;
1009 htaps_c = taps->htaps_c;
1010 hratio_l = scl->hscl_ratio;
1011 hratio_c = scl->hscl_ratio_c;
1012 vratio_l = scl->vscl_ratio;
1013 vratio_c = scl->vscl_ratio_c;
1014
1015 swath_width_ub_l = rq_dlg_param->rq_l.swath_width_ub;
1016 dpte_groups_per_row_ub_l = rq_dlg_param->rq_l.dpte_groups_per_row_ub;
1017 swath_width_ub_c = rq_dlg_param->rq_c.swath_width_ub;
1018 dpte_groups_per_row_ub_c = rq_dlg_param->rq_c.dpte_groups_per_row_ub;
1019
1020 meta_chunks_per_row_ub_l = rq_dlg_param->rq_l.meta_chunks_per_row_ub;
1021 meta_chunks_per_row_ub_c = rq_dlg_param->rq_c.meta_chunks_per_row_ub;
1022 vupdate_offset = dst->vupdate_offset;
1023 vupdate_width = dst->vupdate_width;
1024 vready_offset = dst->vready_offset;
1025
1026 vstartup_start = dst->vstartup_start;
1027 if (interlaced) {
1028 if (vstartup_start / 2.0 - (double) (vready_offset + vupdate_width + vupdate_offset) / htotal <= vblank_end / 2.0)
1029 disp_dlg_regs->vready_after_vcount0 = 1;
1030 else
1031 disp_dlg_regs->vready_after_vcount0 = 0;
1032 } else {
1033 if (vstartup_start - (double) (vready_offset + vupdate_width + vupdate_offset) / htotal <= vblank_end)
1034 disp_dlg_regs->vready_after_vcount0 = 1;
1035 else
1036 disp_dlg_regs->vready_after_vcount0 = 0;
1037 }
1038
1039 dml_print("DML_DLG: %s: vready_after_vcount0 = %d\n", __func__, disp_dlg_regs->vready_after_vcount0);
1040 dml_print("DML_DLG: %s: vba__vready_after_vcount0 = %d\n", __func__, vba__vready_after_vcount0);
1041 //old_impl_vs_vba_impl("vready_after_vcount0", disp_dlg_regs->vready_after_vcount0, vba__vready_after_vcount0);
1042
1043 if (interlaced)
1044 vstartup_start = vstartup_start / 2;
1045
1046 dst_x_after_scaler = get_dst_x_after_scaler(mode_lib, e2e_pipe_param, num_pipes, pipe_idx); // From VBA
1047 dst_y_after_scaler = get_dst_y_after_scaler(mode_lib, e2e_pipe_param, num_pipes, pipe_idx); // From VBA
1048
1049 // do some adjustment on the dst_after scaler to account for odm combine mode
1050 dml_print("DML_DLG: %s: input dst_x_after_scaler = %d\n", __func__, dst_x_after_scaler);
1051 dml_print("DML_DLG: %s: input dst_y_after_scaler = %d\n", __func__, dst_y_after_scaler);
1052
1053 // need to figure out which side of odm combine we're in
1054 if (dst->odm_combine) {
1055 // figure out which pipes go together
1056 bool visited[DC__NUM_PIPES__MAX];
1057 unsigned int i, j, k;
1058
1059 for (k = 0; k < num_pipes; ++k) {
1060 visited[k] = false;
1061 pipe_index_in_combine[k] = 0;
1062 }
1063
1064 for (i = 0; i < num_pipes; i++) {
1065 if (e2e_pipe_param[i].pipe.src.is_hsplit && !visited[i]) {
1066
1067 unsigned int grp = e2e_pipe_param[i].pipe.src.hsplit_grp;
1068 unsigned int grp_idx = 0;
1069
1070 for (j = i; j < num_pipes; j++) {
1071 if (e2e_pipe_param[j].pipe.src.hsplit_grp == grp && e2e_pipe_param[j].pipe.src.is_hsplit && !visited[j]) {
1072 pipe_index_in_combine[j] = grp_idx;
1073 dml_print("DML_DLG: %s: pipe[%d] is in grp %d idx %d\n", __func__, j, grp, grp_idx);
1074 grp_idx++;
1075 visited[j] = true;
1076 }
1077 }
1078 }
1079 }
1080
1081 }
1082
1083 if (dst->odm_combine == dm_odm_combine_mode_disabled) {
1084 disp_dlg_regs->refcyc_h_blank_end = (unsigned int) ((double) hblank_end * ref_freq_to_pix_freq);
1085 } else {
1086 unsigned int odm_combine_factor = (dst->odm_combine == dm_odm_combine_mode_2to1 ? 2 : 4); // TODO: We should really check that 4to1 is supported before setting it to 4
1087 unsigned int odm_pipe_index = pipe_index_in_combine[pipe_idx];
1088 disp_dlg_regs->refcyc_h_blank_end = (unsigned int) (((double) hblank_end + odm_pipe_index * (double) dst->hactive / odm_combine_factor) * ref_freq_to_pix_freq);
1089 } ASSERT(disp_dlg_regs->refcyc_h_blank_end < (unsigned int)dml_pow(2, 13));
1090
1091 dml_print("DML_DLG: %s: htotal = %d\n", __func__, htotal);
1092 dml_print("DML_DLG: %s: dst_x_after_scaler[%d] = %d\n", __func__, pipe_idx, dst_x_after_scaler);
1093 dml_print("DML_DLG: %s: dst_y_after_scaler[%d] = %d\n", __func__, pipe_idx, dst_y_after_scaler);
1094
1095 dst_y_prefetch = get_dst_y_prefetch(mode_lib, e2e_pipe_param, num_pipes, pipe_idx); // From VBA
1096 dst_y_per_vm_vblank = get_dst_y_per_vm_vblank(mode_lib, e2e_pipe_param, num_pipes, pipe_idx); // From VBA
1097 dst_y_per_row_vblank = get_dst_y_per_row_vblank(mode_lib, e2e_pipe_param, num_pipes, pipe_idx); // From VBA
1098 dst_y_per_vm_flip = get_dst_y_per_vm_flip(mode_lib, e2e_pipe_param, num_pipes, pipe_idx); // From VBA
1099 dst_y_per_row_flip = get_dst_y_per_row_flip(mode_lib, e2e_pipe_param, num_pipes, pipe_idx); // From VBA
1100
1101 max_dst_y_per_vm_vblank = 32.0; //U5.2
1102 max_dst_y_per_row_vblank = 16.0; //U4.2
1103
1104 // magic!
1105 if (htotal <= 75) {
1106 max_dst_y_per_vm_vblank = 100.0;
1107 max_dst_y_per_row_vblank = 100.0;
1108 }
1109
1110 dml_print("DML_DLG: %s: dst_y_prefetch (after rnd) = %3.2f\n", __func__, dst_y_prefetch);
1111 dml_print("DML_DLG: %s: dst_y_per_vm_flip = %3.2f\n", __func__, dst_y_per_vm_flip);
1112 dml_print("DML_DLG: %s: dst_y_per_row_flip = %3.2f\n", __func__, dst_y_per_row_flip);
1113 dml_print("DML_DLG: %s: dst_y_per_vm_vblank = %3.2f\n", __func__, dst_y_per_vm_vblank);
1114 dml_print("DML_DLG: %s: dst_y_per_row_vblank = %3.2f\n", __func__, dst_y_per_row_vblank);
1115
1116 ASSERT(dst_y_per_vm_vblank < max_dst_y_per_vm_vblank); ASSERT(dst_y_per_row_vblank < max_dst_y_per_row_vblank);
1117
1118 ASSERT(dst_y_prefetch > (dst_y_per_vm_vblank + dst_y_per_row_vblank));
1119
1120 vratio_pre_l = get_vratio_prefetch_l(mode_lib, e2e_pipe_param, num_pipes, pipe_idx); // From VBA
1121 vratio_pre_c = get_vratio_prefetch_c(mode_lib, e2e_pipe_param, num_pipes, pipe_idx); // From VBA
1122
1123 dml_print("DML_DLG: %s: vratio_pre_l = %3.2f\n", __func__, vratio_pre_l);
1124 dml_print("DML_DLG: %s: vratio_pre_c = %3.2f\n", __func__, vratio_pre_c);
1125
1126 // Active
1127 req_per_swath_ub_l = rq_dlg_param->rq_l.req_per_swath_ub;
1128 req_per_swath_ub_c = rq_dlg_param->rq_c.req_per_swath_ub;
1129 meta_row_height_l = rq_dlg_param->rq_l.meta_row_height;
1130 meta_row_height_c = rq_dlg_param->rq_c.meta_row_height;
1131 swath_width_pixels_ub_l = 0;
1132 swath_width_pixels_ub_c = 0;
1133 scaler_rec_in_width_l = 0;
1134 scaler_rec_in_width_c = 0;
1135 dpte_row_height_l = rq_dlg_param->rq_l.dpte_row_height;
1136 dpte_row_height_c = rq_dlg_param->rq_c.dpte_row_height;
1137
1138 swath_width_pixels_ub_l = swath_width_ub_l;
1139 swath_width_pixels_ub_c = swath_width_ub_c;
1140
1141 if (hratio_l <= 1)
1142 min_hratio_fact_l = 2.0;
1143 else if (htaps_l <= 6) {
1144 if ((hratio_l * 2.0) > 4.0)
1145 min_hratio_fact_l = 4.0;
1146 else
1147 min_hratio_fact_l = hratio_l * 2.0;
1148 } else {
1149 if (hratio_l > 4.0)
1150 min_hratio_fact_l = 4.0;
1151 else
1152 min_hratio_fact_l = hratio_l;
1153 }
1154
1155 hscale_pixel_rate_l = min_hratio_fact_l * dppclk_freq_in_mhz;
1156
1157 dml_print("DML_DLG: %s: hratio_l = %3.2f\n", __func__, hratio_l);
1158 dml_print("DML_DLG: %s: min_hratio_fact_l = %3.2f\n", __func__, min_hratio_fact_l);
1159 dml_print("DML_DLG: %s: hscale_pixel_rate_l = %3.2f\n", __func__, hscale_pixel_rate_l);
1160
1161 if (hratio_c <= 1)
1162 min_hratio_fact_c = 2.0;
1163 else if (htaps_c <= 6) {
1164 if ((hratio_c * 2.0) > 4.0)
1165 min_hratio_fact_c = 4.0;
1166 else
1167 min_hratio_fact_c = hratio_c * 2.0;
1168 } else {
1169 if (hratio_c > 4.0)
1170 min_hratio_fact_c = 4.0;
1171 else
1172 min_hratio_fact_c = hratio_c;
1173 }
1174
1175 hscale_pixel_rate_c = min_hratio_fact_c * dppclk_freq_in_mhz;
1176
1177 refcyc_per_line_delivery_pre_l = 0.;
1178 refcyc_per_line_delivery_pre_c = 0.;
1179 refcyc_per_line_delivery_l = 0.;
1180 refcyc_per_line_delivery_c = 0.;
1181
1182 refcyc_per_req_delivery_pre_l = 0.;
1183 refcyc_per_req_delivery_pre_c = 0.;
1184 refcyc_per_req_delivery_l = 0.;
1185 refcyc_per_req_delivery_c = 0.;
1186
1187 full_recout_width = 0;
1188 // In ODM
1189 if (src->is_hsplit) {
1190 // This "hack" is only allowed (and valid) for MPC combine. In ODM
1191 // combine, you MUST specify the full_recout_width...according to Oswin
1192 if (dst->full_recout_width == 0 && !dst->odm_combine) {
1193 dml_print("DML_DLG: %s: Warning: full_recout_width not set in hsplit mode\n", __func__);
1194 full_recout_width = dst->recout_width * 2; // assume half split for dcn1
1195 } else
1196 full_recout_width = dst->full_recout_width;
1197 } else
1198 full_recout_width = dst->recout_width;
1199
1200 // As of DCN2, mpc_combine and odm_combine are mutually exclusive
1201 refcyc_per_line_delivery_pre_l = get_refcyc_per_delivery(
1202 mode_lib,
1203 refclk_freq_in_mhz,
1204 pclk_freq_in_mhz,
1205 dst->odm_combine,
1206 full_recout_width,
1207 dst->hactive,
1208 vratio_pre_l,
1209 hscale_pixel_rate_l,
1210 swath_width_pixels_ub_l,
1211 1); // per line
1212
1213 refcyc_per_line_delivery_l = get_refcyc_per_delivery(
1214 mode_lib,
1215 refclk_freq_in_mhz,
1216 pclk_freq_in_mhz,
1217 dst->odm_combine,
1218 full_recout_width,
1219 dst->hactive,
1220 vratio_l,
1221 hscale_pixel_rate_l,
1222 swath_width_pixels_ub_l,
1223 1); // per line
1224
1225 dml_print("DML_DLG: %s: full_recout_width = %d\n", __func__, full_recout_width);
1226 dml_print("DML_DLG: %s: hscale_pixel_rate_l = %3.2f\n", __func__, hscale_pixel_rate_l);
1227 dml_print("DML_DLG: %s: refcyc_per_line_delivery_pre_l = %3.2f\n", __func__, refcyc_per_line_delivery_pre_l);
1228 dml_print("DML_DLG: %s: refcyc_per_line_delivery_l = %3.2f\n", __func__, refcyc_per_line_delivery_l);
1229 dml_print("DML_DLG: %s: vba__refcyc_per_line_delivery_pre_l = %3.2f\n", __func__, vba__refcyc_per_line_delivery_pre_l);
1230 dml_print("DML_DLG: %s: vba__refcyc_per_line_delivery_l = %3.2f\n", __func__, vba__refcyc_per_line_delivery_l);
1231
1232 //old_impl_vs_vba_impl("refcyc_per_line_delivery_pre_l", refcyc_per_line_delivery_pre_l, vba__refcyc_per_line_delivery_pre_l);
1233 //old_impl_vs_vba_impl("refcyc_per_line_delivery_l", refcyc_per_line_delivery_l, vba__refcyc_per_line_delivery_l);
1234
1235 if (dual_plane) {
1236 float vba__refcyc_per_line_delivery_pre_c = get_refcyc_per_line_delivery_pre_c_in_us(mode_lib, e2e_pipe_param, num_pipes, pipe_idx) * refclk_freq_in_mhz; // From VBA
1237 float vba__refcyc_per_line_delivery_c = get_refcyc_per_line_delivery_c_in_us(mode_lib, e2e_pipe_param, num_pipes, pipe_idx) * refclk_freq_in_mhz; // From VBA
1238
1239 refcyc_per_line_delivery_pre_c = get_refcyc_per_delivery(
1240 mode_lib,
1241 refclk_freq_in_mhz,
1242 pclk_freq_in_mhz,
1243 dst->odm_combine,
1244 full_recout_width,
1245 dst->hactive,
1246 vratio_pre_c,
1247 hscale_pixel_rate_c,
1248 swath_width_pixels_ub_c,
1249 1); // per line
1250
1251 refcyc_per_line_delivery_c = get_refcyc_per_delivery(
1252 mode_lib,
1253 refclk_freq_in_mhz,
1254 pclk_freq_in_mhz,
1255 dst->odm_combine,
1256 full_recout_width,
1257 dst->hactive,
1258 vratio_c,
1259 hscale_pixel_rate_c,
1260 swath_width_pixels_ub_c,
1261 1); // per line
1262
1263 dml_print("DML_DLG: %s: refcyc_per_line_delivery_pre_c = %3.2f\n", __func__, refcyc_per_line_delivery_pre_c);
1264 dml_print("DML_DLG: %s: refcyc_per_line_delivery_c = %3.2f\n", __func__, refcyc_per_line_delivery_c);
1265 dml_print("DML_DLG: %s: vba__refcyc_per_line_delivery_pre_c = %3.2f\n", __func__, vba__refcyc_per_line_delivery_pre_c);
1266 dml_print("DML_DLG: %s: vba__refcyc_per_line_delivery_c = %3.2f\n", __func__, vba__refcyc_per_line_delivery_c);
1267
1268 //old_impl_vs_vba_impl("refcyc_per_line_delivery_pre_c", refcyc_per_line_delivery_pre_c, vba__refcyc_per_line_delivery_pre_c);
1269 //old_impl_vs_vba_impl("refcyc_per_line_delivery_c", refcyc_per_line_delivery_c, vba__refcyc_per_line_delivery_c);
1270 }
1271
1272 if (src->dynamic_metadata_enable && src->gpuvm)
1273 disp_dlg_regs->refcyc_per_vm_dmdata = get_refcyc_per_vm_dmdata_in_us(mode_lib, e2e_pipe_param, num_pipes, pipe_idx) * refclk_freq_in_mhz; // From VBA
1274
1275 disp_dlg_regs->dmdata_dl_delta = get_dmdata_dl_delta_in_us(mode_lib, e2e_pipe_param, num_pipes, pipe_idx) * refclk_freq_in_mhz; // From VBA
1276
1277 // TTU - Luma / Chroma
1278 if (access_dir) { // vertical access
1279 scaler_rec_in_width_l = vp_height_l;
1280 scaler_rec_in_width_c = vp_height_c;
1281 } else {
1282 scaler_rec_in_width_l = vp_width_l;
1283 scaler_rec_in_width_c = vp_width_c;
1284 }
1285
1286 refcyc_per_req_delivery_pre_l = get_refcyc_per_delivery(
1287 mode_lib,
1288 refclk_freq_in_mhz,
1289 pclk_freq_in_mhz,
1290 dst->odm_combine,
1291 full_recout_width,
1292 dst->hactive,
1293 vratio_pre_l,
1294 hscale_pixel_rate_l,
1295 scaler_rec_in_width_l,
1296 req_per_swath_ub_l); // per req
1297
1298 refcyc_per_req_delivery_l = get_refcyc_per_delivery(
1299 mode_lib,
1300 refclk_freq_in_mhz,
1301 pclk_freq_in_mhz,
1302 dst->odm_combine,
1303 full_recout_width,
1304 dst->hactive,
1305 vratio_l,
1306 hscale_pixel_rate_l,
1307 scaler_rec_in_width_l,
1308 req_per_swath_ub_l); // per req
1309
1310 dml_print("DML_DLG: %s: refcyc_per_req_delivery_pre_l = %3.2f\n", __func__, refcyc_per_req_delivery_pre_l);
1311 dml_print("DML_DLG: %s: refcyc_per_req_delivery_l = %3.2f\n", __func__, refcyc_per_req_delivery_l);
1312 dml_print("DML_DLG: %s: vba__refcyc_per_req_delivery_pre_l = %3.2f\n", __func__, vba__refcyc_per_req_delivery_pre_l);
1313 dml_print("DML_DLG: %s: vba__refcyc_per_req_delivery_l = %3.2f\n", __func__, vba__refcyc_per_req_delivery_l);
1314
1315 //old_impl_vs_vba_impl("refcyc_per_req_delivery_pre_l", refcyc_per_req_delivery_pre_l, vba__refcyc_per_req_delivery_pre_l);
1316 //old_impl_vs_vba_impl("refcyc_per_req_delivery_l", refcyc_per_req_delivery_l, vba__refcyc_per_req_delivery_l);
1317
1318 ASSERT(refcyc_per_req_delivery_pre_l < dml_pow(2, 13)); ASSERT(refcyc_per_req_delivery_l < dml_pow(2, 13));
1319
1320 if (dual_plane) {
1321 float vba__refcyc_per_req_delivery_pre_c = get_refcyc_per_req_delivery_pre_c_in_us(mode_lib, e2e_pipe_param, num_pipes, pipe_idx) * refclk_freq_in_mhz; // From VBA
1322 float vba__refcyc_per_req_delivery_c = get_refcyc_per_req_delivery_c_in_us(mode_lib, e2e_pipe_param, num_pipes, pipe_idx) * refclk_freq_in_mhz; // From VBA
1323
1324 refcyc_per_req_delivery_pre_c = get_refcyc_per_delivery(
1325 mode_lib,
1326 refclk_freq_in_mhz,
1327 pclk_freq_in_mhz,
1328 dst->odm_combine,
1329 full_recout_width,
1330 dst->hactive,
1331 vratio_pre_c,
1332 hscale_pixel_rate_c,
1333 scaler_rec_in_width_c,
1334 req_per_swath_ub_c); // per req
1335 refcyc_per_req_delivery_c = get_refcyc_per_delivery(
1336 mode_lib,
1337 refclk_freq_in_mhz,
1338 pclk_freq_in_mhz,
1339 dst->odm_combine,
1340 full_recout_width,
1341 dst->hactive,
1342 vratio_c,
1343 hscale_pixel_rate_c,
1344 scaler_rec_in_width_c,
1345 req_per_swath_ub_c); // per req
1346
1347 dml_print("DML_DLG: %s: refcyc_per_req_delivery_pre_c = %3.2f\n", __func__, refcyc_per_req_delivery_pre_c);
1348 dml_print("DML_DLG: %s: refcyc_per_req_delivery_c = %3.2f\n", __func__, refcyc_per_req_delivery_c);
1349 dml_print("DML_DLG: %s: vba__refcyc_per_req_delivery_pre_c = %3.2f\n", __func__, vba__refcyc_per_req_delivery_pre_c);
1350 dml_print("DML_DLG: %s: vba__refcyc_per_req_delivery_c = %3.2f\n", __func__, vba__refcyc_per_req_delivery_c);
1351
1352 //old_impl_vs_vba_impl("refcyc_per_req_delivery_pre_c", refcyc_per_req_delivery_pre_c, vba__refcyc_per_req_delivery_pre_c);
1353 //old_impl_vs_vba_impl("refcyc_per_req_delivery_c", refcyc_per_req_delivery_c, vba__refcyc_per_req_delivery_c);
1354
1355 ASSERT(refcyc_per_req_delivery_pre_c < dml_pow(2, 13)); ASSERT(refcyc_per_req_delivery_c < dml_pow(2, 13));
1356 }
1357
1358 // TTU - Cursor
1359 refcyc_per_req_delivery_pre_cur0 = 0.0;
1360 refcyc_per_req_delivery_cur0 = 0.0;
1361
1362 ASSERT(src->num_cursors <= 1);
1363
1364 if (src->num_cursors > 0) {
1365 float vba__refcyc_per_req_delivery_pre_cur0;
1366 float vba__refcyc_per_req_delivery_cur0;
1367
1368 calculate_ttu_cursor(
1369 mode_lib,
1370 &refcyc_per_req_delivery_pre_cur0,
1371 &refcyc_per_req_delivery_cur0,
1372 refclk_freq_in_mhz,
1373 ref_freq_to_pix_freq,
1374 hscale_pixel_rate_l,
1375 scl->hscl_ratio,
1376 vratio_pre_l,
1377 vratio_l,
1378 src->cur0_src_width,
1379 (enum cursor_bpp) (src->cur0_bpp));
1380
1381 vba__refcyc_per_req_delivery_pre_cur0 = get_refcyc_per_cursor_req_delivery_pre_in_us(mode_lib, e2e_pipe_param, num_pipes, pipe_idx) * refclk_freq_in_mhz; // From VBA
1382 vba__refcyc_per_req_delivery_cur0 = get_refcyc_per_cursor_req_delivery_in_us(mode_lib, e2e_pipe_param, num_pipes, pipe_idx) * refclk_freq_in_mhz; // From VBA
1383
1384 dml_print("DML_DLG: %s: refcyc_per_req_delivery_pre_cur0 = %3.2f\n", __func__, refcyc_per_req_delivery_pre_cur0);
1385 dml_print("DML_DLG: %s: refcyc_per_req_delivery_cur0 = %3.2f\n", __func__, refcyc_per_req_delivery_cur0);
1386 dml_print("DML_DLG: %s: vba__refcyc_per_req_delivery_pre_cur0 = %3.2f\n", __func__, vba__refcyc_per_req_delivery_pre_cur0);
1387 dml_print("DML_DLG: %s: vba__refcyc_per_req_delivery_cur0 = %3.2f\n", __func__, vba__refcyc_per_req_delivery_cur0);
1388
1389 //old_impl_vs_vba_impl("refcyc_per_req_delivery_pre_cur0", refcyc_per_req_delivery_pre_cur0, vba__refcyc_per_req_delivery_pre_cur0);
1390 //old_impl_vs_vba_impl("refcyc_per_req_delivery_cur0", refcyc_per_req_delivery_cur0, vba__refcyc_per_req_delivery_cur0);
1391 }
1392
1393 refcyc_per_req_delivery_pre_cur1 = 0.0;
1394 refcyc_per_req_delivery_cur1 = 0.0;
1395
1396 // TTU - Misc
1397 // all hard-coded
1398
1399 // Assignment to register structures
1400 disp_dlg_regs->dst_y_after_scaler = dst_y_after_scaler; // in terms of line
1401 ASSERT(disp_dlg_regs->dst_y_after_scaler < (unsigned int)8);
1402 disp_dlg_regs->refcyc_x_after_scaler = dst_x_after_scaler * ref_freq_to_pix_freq; // in terms of refclk
1403 ASSERT(disp_dlg_regs->refcyc_x_after_scaler < (unsigned int)dml_pow(2, 13));
1404 disp_dlg_regs->dst_y_prefetch = (unsigned int) (dst_y_prefetch * dml_pow(2, 2));
1405 disp_dlg_regs->dst_y_per_vm_vblank = (unsigned int) (dst_y_per_vm_vblank * dml_pow(2, 2));
1406 disp_dlg_regs->dst_y_per_row_vblank = (unsigned int) (dst_y_per_row_vblank * dml_pow(2, 2));
1407 disp_dlg_regs->dst_y_per_vm_flip = (unsigned int) (dst_y_per_vm_flip * dml_pow(2, 2));
1408 disp_dlg_regs->dst_y_per_row_flip = (unsigned int) (dst_y_per_row_flip * dml_pow(2, 2));
1409
1410 disp_dlg_regs->vratio_prefetch = (unsigned int) (vratio_pre_l * dml_pow(2, 19));
1411 disp_dlg_regs->vratio_prefetch_c = (unsigned int) (vratio_pre_c * dml_pow(2, 19));
1412
1413 dml_print("DML_DLG: %s: disp_dlg_regs->dst_y_per_vm_vblank = 0x%x\n", __func__, disp_dlg_regs->dst_y_per_vm_vblank);
1414 dml_print("DML_DLG: %s: disp_dlg_regs->dst_y_per_row_vblank = 0x%x\n", __func__, disp_dlg_regs->dst_y_per_row_vblank);
1415 dml_print("DML_DLG: %s: disp_dlg_regs->dst_y_per_vm_flip = 0x%x\n", __func__, disp_dlg_regs->dst_y_per_vm_flip);
1416 dml_print("DML_DLG: %s: disp_dlg_regs->dst_y_per_row_flip = 0x%x\n", __func__, disp_dlg_regs->dst_y_per_row_flip);
1417
1418 disp_dlg_regs->refcyc_per_pte_group_vblank_l = (unsigned int) (dst_y_per_row_vblank * (double) htotal * ref_freq_to_pix_freq / (double) dpte_groups_per_row_ub_l);
1419 ASSERT(disp_dlg_regs->refcyc_per_pte_group_vblank_l < (unsigned int)dml_pow(2, 13));
1420
1421 if (dual_plane) {
1422 disp_dlg_regs->refcyc_per_pte_group_vblank_c = (unsigned int) (dst_y_per_row_vblank * (double) htotal * ref_freq_to_pix_freq / (double) dpte_groups_per_row_ub_c);
1423 ASSERT(disp_dlg_regs->refcyc_per_pte_group_vblank_c < (unsigned int)dml_pow(2, 13));
1424 }
1425
1426 disp_dlg_regs->refcyc_per_meta_chunk_vblank_l = (unsigned int) (dst_y_per_row_vblank * (double) htotal * ref_freq_to_pix_freq / (double) meta_chunks_per_row_ub_l);
1427 ASSERT(disp_dlg_regs->refcyc_per_meta_chunk_vblank_l < (unsigned int)dml_pow(2, 13));
1428
1429 disp_dlg_regs->refcyc_per_meta_chunk_vblank_c = disp_dlg_regs->refcyc_per_meta_chunk_vblank_l; // dcc for 4:2:0 is not supported in dcn1.0. assigned to be the same as _l for now
1430
1431 disp_dlg_regs->refcyc_per_pte_group_flip_l = (unsigned int) (dst_y_per_row_flip * htotal * ref_freq_to_pix_freq) / dpte_groups_per_row_ub_l;
1432 disp_dlg_regs->refcyc_per_meta_chunk_flip_l = (unsigned int) (dst_y_per_row_flip * htotal * ref_freq_to_pix_freq) / meta_chunks_per_row_ub_l;
1433
1434 if (dual_plane) {
1435 disp_dlg_regs->refcyc_per_pte_group_flip_c = (unsigned int) (dst_y_per_row_flip * htotal * ref_freq_to_pix_freq) / dpte_groups_per_row_ub_c;
1436 disp_dlg_regs->refcyc_per_meta_chunk_flip_c = (unsigned int) (dst_y_per_row_flip * htotal * ref_freq_to_pix_freq) / meta_chunks_per_row_ub_c;
1437 }
1438
1439 disp_dlg_regs->refcyc_per_vm_group_vblank = get_refcyc_per_vm_group_vblank_in_us(mode_lib, e2e_pipe_param, num_pipes, pipe_idx) * refclk_freq_in_mhz; // From VBA
1440 disp_dlg_regs->refcyc_per_vm_group_flip = get_refcyc_per_vm_group_flip_in_us(mode_lib, e2e_pipe_param, num_pipes, pipe_idx) * refclk_freq_in_mhz; // From VBA
1441 disp_dlg_regs->refcyc_per_vm_req_vblank = get_refcyc_per_vm_req_vblank_in_us(mode_lib, e2e_pipe_param, num_pipes, pipe_idx) * refclk_freq_in_mhz * dml_pow(2, 10); // From VBA
1442 disp_dlg_regs->refcyc_per_vm_req_flip = get_refcyc_per_vm_req_flip_in_us(mode_lib, e2e_pipe_param, num_pipes, pipe_idx) * refclk_freq_in_mhz * dml_pow(2, 10); // From VBA
1443
1444 // Clamp to max for now
1445 if (disp_dlg_regs->refcyc_per_vm_group_vblank >= (unsigned int) dml_pow(2, 23))
1446 disp_dlg_regs->refcyc_per_vm_group_vblank = dml_pow(2, 23) - 1;
1447
1448 if (disp_dlg_regs->refcyc_per_vm_group_flip >= (unsigned int) dml_pow(2, 23))
1449 disp_dlg_regs->refcyc_per_vm_group_flip = dml_pow(2, 23) - 1;
1450
1451 if (disp_dlg_regs->refcyc_per_vm_req_vblank >= (unsigned int) dml_pow(2, 23))
1452 disp_dlg_regs->refcyc_per_vm_req_vblank = dml_pow(2, 23) - 1;
1453
1454 if (disp_dlg_regs->refcyc_per_vm_req_flip >= (unsigned int) dml_pow(2, 23))
1455 disp_dlg_regs->refcyc_per_vm_req_flip = dml_pow(2, 23) - 1;
1456
1457 disp_dlg_regs->dst_y_per_pte_row_nom_l = (unsigned int) ((double) dpte_row_height_l / (double) vratio_l * dml_pow(2, 2));
1458 ASSERT(disp_dlg_regs->dst_y_per_pte_row_nom_l < (unsigned int)dml_pow(2, 17));
1459 if (dual_plane) {
1460 disp_dlg_regs->dst_y_per_pte_row_nom_c = (unsigned int) ((double) dpte_row_height_c / (double) vratio_c * dml_pow(2, 2));
1461 if (disp_dlg_regs->dst_y_per_pte_row_nom_c >= (unsigned int) dml_pow(2, 17)) {
1462 dml_print(
1463 "DML_DLG: %s: Warning dst_y_per_pte_row_nom_c %u larger than supported by register format U15.2 %u\n",
1464 __func__,
1465 disp_dlg_regs->dst_y_per_pte_row_nom_c,
1466 (unsigned int) dml_pow(2, 17) - 1);
1467 }
1468 }
1469
1470 disp_dlg_regs->dst_y_per_meta_row_nom_l = (unsigned int) ((double) meta_row_height_l / (double) vratio_l * dml_pow(2, 2));
1471 ASSERT(disp_dlg_regs->dst_y_per_meta_row_nom_l < (unsigned int)dml_pow(2, 17));
1472
1473 disp_dlg_regs->dst_y_per_meta_row_nom_c = (unsigned int) ((double) meta_row_height_c / (double) vratio_c * dml_pow(2, 2));
1474 ASSERT(disp_dlg_regs->dst_y_per_meta_row_nom_c < (unsigned int)dml_pow(2, 17));
1475
1476 disp_dlg_regs->refcyc_per_pte_group_nom_l = (unsigned int) ((double) dpte_row_height_l / (double) vratio_l * (double) htotal * ref_freq_to_pix_freq
1477 / (double) dpte_groups_per_row_ub_l);
1478 if (disp_dlg_regs->refcyc_per_pte_group_nom_l >= (unsigned int) dml_pow(2, 23))
1479 disp_dlg_regs->refcyc_per_pte_group_nom_l = dml_pow(2, 23) - 1;
1480 disp_dlg_regs->refcyc_per_meta_chunk_nom_l = (unsigned int) ((double) meta_row_height_l / (double) vratio_l * (double) htotal * ref_freq_to_pix_freq
1481 / (double) meta_chunks_per_row_ub_l);
1482 if (disp_dlg_regs->refcyc_per_meta_chunk_nom_l >= (unsigned int) dml_pow(2, 23))
1483 disp_dlg_regs->refcyc_per_meta_chunk_nom_l = dml_pow(2, 23) - 1;
1484
1485 if (dual_plane) {
1486 disp_dlg_regs->refcyc_per_pte_group_nom_c = (unsigned int) ((double) dpte_row_height_c / (double) vratio_c * (double) htotal * ref_freq_to_pix_freq
1487 / (double) dpte_groups_per_row_ub_c);
1488 if (disp_dlg_regs->refcyc_per_pte_group_nom_c >= (unsigned int) dml_pow(2, 23))
1489 disp_dlg_regs->refcyc_per_pte_group_nom_c = dml_pow(2, 23) - 1;
1490
1491 // TODO: Is this the right calculation? Does htotal need to be halved?
1492 disp_dlg_regs->refcyc_per_meta_chunk_nom_c = (unsigned int) ((double) meta_row_height_c / (double) vratio_c * (double) htotal * ref_freq_to_pix_freq
1493 / (double) meta_chunks_per_row_ub_c);
1494 if (disp_dlg_regs->refcyc_per_meta_chunk_nom_c >= (unsigned int) dml_pow(2, 23))
1495 disp_dlg_regs->refcyc_per_meta_chunk_nom_c = dml_pow(2, 23) - 1;
1496 }
1497
1498 disp_dlg_regs->refcyc_per_line_delivery_pre_l = (unsigned int) dml_floor(refcyc_per_line_delivery_pre_l, 1);
1499 disp_dlg_regs->refcyc_per_line_delivery_l = (unsigned int) dml_floor(refcyc_per_line_delivery_l, 1);
1500 ASSERT(disp_dlg_regs->refcyc_per_line_delivery_pre_l < (unsigned int)dml_pow(2, 13)); ASSERT(disp_dlg_regs->refcyc_per_line_delivery_l < (unsigned int)dml_pow(2, 13));
1501
1502 disp_dlg_regs->refcyc_per_line_delivery_pre_c = (unsigned int) dml_floor(refcyc_per_line_delivery_pre_c, 1);
1503 disp_dlg_regs->refcyc_per_line_delivery_c = (unsigned int) dml_floor(refcyc_per_line_delivery_c, 1);
1504 ASSERT(disp_dlg_regs->refcyc_per_line_delivery_pre_c < (unsigned int)dml_pow(2, 13)); ASSERT(disp_dlg_regs->refcyc_per_line_delivery_c < (unsigned int)dml_pow(2, 13));
1505
1506 disp_dlg_regs->chunk_hdl_adjust_cur0 = 3;
1507 disp_dlg_regs->dst_y_offset_cur0 = 0;
1508 disp_dlg_regs->chunk_hdl_adjust_cur1 = 3;
1509 disp_dlg_regs->dst_y_offset_cur1 = 0;
1510
1511 disp_dlg_regs->dst_y_delta_drq_limit = 0x7fff; // off
1512
1513 disp_ttu_regs->refcyc_per_req_delivery_pre_l = (unsigned int) (refcyc_per_req_delivery_pre_l * dml_pow(2, 10));
1514 disp_ttu_regs->refcyc_per_req_delivery_l = (unsigned int) (refcyc_per_req_delivery_l * dml_pow(2, 10));
1515 disp_ttu_regs->refcyc_per_req_delivery_pre_c = (unsigned int) (refcyc_per_req_delivery_pre_c * dml_pow(2, 10));
1516 disp_ttu_regs->refcyc_per_req_delivery_c = (unsigned int) (refcyc_per_req_delivery_c * dml_pow(2, 10));
1517 disp_ttu_regs->refcyc_per_req_delivery_pre_cur0 = (unsigned int) (refcyc_per_req_delivery_pre_cur0 * dml_pow(2, 10));
1518 disp_ttu_regs->refcyc_per_req_delivery_cur0 = (unsigned int) (refcyc_per_req_delivery_cur0 * dml_pow(2, 10));
1519 disp_ttu_regs->refcyc_per_req_delivery_pre_cur1 = (unsigned int) (refcyc_per_req_delivery_pre_cur1 * dml_pow(2, 10));
1520 disp_ttu_regs->refcyc_per_req_delivery_cur1 = (unsigned int) (refcyc_per_req_delivery_cur1 * dml_pow(2, 10));
1521
1522 disp_ttu_regs->qos_level_low_wm = 0;
1523 ASSERT(disp_ttu_regs->qos_level_low_wm < dml_pow(2, 14));
1524
1525 disp_ttu_regs->qos_level_high_wm = (unsigned int) (4.0 * (double) htotal * ref_freq_to_pix_freq);
1526 ASSERT(disp_ttu_regs->qos_level_high_wm < dml_pow(2, 14));
1527
1528 disp_ttu_regs->qos_level_flip = 14;
1529 disp_ttu_regs->qos_level_fixed_l = 8;
1530 disp_ttu_regs->qos_level_fixed_c = 8;
1531 disp_ttu_regs->qos_level_fixed_cur0 = 8;
1532 disp_ttu_regs->qos_ramp_disable_l = 0;
1533 disp_ttu_regs->qos_ramp_disable_c = 0;
1534 disp_ttu_regs->qos_ramp_disable_cur0 = 0;
1535
1536 disp_ttu_regs->min_ttu_vblank = min_ttu_vblank * refclk_freq_in_mhz;
1537 ASSERT(disp_ttu_regs->min_ttu_vblank < dml_pow(2, 24));
1538
1539 print__ttu_regs_st(mode_lib, disp_ttu_regs);
1540 print__dlg_regs_st(mode_lib, disp_dlg_regs);
1541 }
1542
dml31_rq_dlg_get_dlg_reg(struct display_mode_lib * mode_lib,display_dlg_regs_st * dlg_regs,display_ttu_regs_st * ttu_regs,const display_e2e_pipe_params_st * e2e_pipe_param,const unsigned int num_pipes,const unsigned int pipe_idx,const bool cstate_en,const bool pstate_en,const bool vm_en,const bool ignore_viewport_pos,const bool immediate_flip_support)1543 void dml31_rq_dlg_get_dlg_reg(
1544 struct display_mode_lib *mode_lib,
1545 display_dlg_regs_st *dlg_regs,
1546 display_ttu_regs_st *ttu_regs,
1547 const display_e2e_pipe_params_st *e2e_pipe_param,
1548 const unsigned int num_pipes,
1549 const unsigned int pipe_idx,
1550 const bool cstate_en,
1551 const bool pstate_en,
1552 const bool vm_en,
1553 const bool ignore_viewport_pos,
1554 const bool immediate_flip_support)
1555 {
1556 display_rq_params_st rq_param = {0};
1557 display_dlg_sys_params_st dlg_sys_param = {0};
1558
1559 // Get watermark and Tex.
1560 dlg_sys_param.t_urg_wm_us = get_wm_urgent(mode_lib, e2e_pipe_param, num_pipes);
1561 dlg_sys_param.deepsleep_dcfclk_mhz = get_clk_dcf_deepsleep(mode_lib, e2e_pipe_param, num_pipes);
1562 dlg_sys_param.t_extra_us = get_urgent_extra_latency(mode_lib, e2e_pipe_param, num_pipes);
1563 dlg_sys_param.mem_trip_us = get_wm_memory_trip(mode_lib, e2e_pipe_param, num_pipes);
1564 dlg_sys_param.t_mclk_wm_us = get_wm_dram_clock_change(mode_lib, e2e_pipe_param, num_pipes);
1565 dlg_sys_param.t_sr_wm_us = get_wm_stutter_enter_exit(mode_lib, e2e_pipe_param, num_pipes);
1566 dlg_sys_param.total_flip_bw = get_total_immediate_flip_bw(mode_lib, e2e_pipe_param, num_pipes);
1567 dlg_sys_param.total_flip_bytes = get_total_immediate_flip_bytes(mode_lib, e2e_pipe_param, num_pipes);
1568
1569 print__dlg_sys_params_st(mode_lib, &dlg_sys_param);
1570
1571 // system parameter calculation done
1572
1573 dml_print("DML_DLG: Calculation for pipe[%d] start\n\n", pipe_idx);
1574 dml_rq_dlg_get_rq_params(mode_lib, &rq_param, &e2e_pipe_param[pipe_idx].pipe);
1575 dml_rq_dlg_get_dlg_params(
1576 mode_lib,
1577 e2e_pipe_param,
1578 num_pipes,
1579 pipe_idx,
1580 dlg_regs,
1581 ttu_regs,
1582 &rq_param.dlg,
1583 &dlg_sys_param,
1584 cstate_en,
1585 pstate_en,
1586 vm_en,
1587 ignore_viewport_pos,
1588 immediate_flip_support);
1589 dml_print("DML_DLG: Calculation for pipe[%d] end\n", pipe_idx);
1590 }
1591
1592