1 // SPDX-License-Identifier: MIT 2 // 3 // Copyright 2024 Advanced Micro Devices, Inc. 4 5 #ifndef __DML_TOP_TYPES_H__ 6 #define __DML_TOP_TYPES_H__ 7 8 #include "dml_top_display_cfg_types.h" 9 #include "dml_top_soc_parameter_types.h" 10 #include "dml_top_policy_types.h" 11 #include "dml_top_dchub_registers.h" 12 13 #include "dmub_cmd.h" 14 15 struct dml2_instance; 16 17 enum dml2_project_id { 18 dml2_project_invalid = 0, 19 dml2_project_dcn4x_stage1 = 1, 20 dml2_project_dcn4x_stage2 = 2, 21 dml2_project_dcn4x_stage2_auto_drr_svp = 3, 22 }; 23 24 enum dml2_pstate_change_support { 25 dml2_pstate_change_vactive = 0, 26 dml2_pstate_change_vblank = 1, 27 dml2_pstate_change_vblank_and_vactive = 2, 28 dml2_pstate_change_drr = 3, 29 dml2_pstate_change_mall_svp = 4, 30 dml2_pstate_change_mall_full_frame = 6, 31 dml2_pstate_change_unsupported = 7 32 }; 33 34 enum dml2_output_type_and_rate__type { 35 dml2_output_type_unknown = 0, 36 dml2_output_type_dp = 1, 37 dml2_output_type_edp = 2, 38 dml2_output_type_dp2p0 = 3, 39 dml2_output_type_hdmi = 4, 40 dml2_output_type_hdmifrl = 5 41 }; 42 43 enum dml2_output_type_and_rate__rate { 44 dml2_output_rate_unknown = 0, 45 dml2_output_rate_dp_rate_hbr = 1, 46 dml2_output_rate_dp_rate_hbr2 = 2, 47 dml2_output_rate_dp_rate_hbr3 = 3, 48 dml2_output_rate_dp_rate_uhbr10 = 4, 49 dml2_output_rate_dp_rate_uhbr13p5 = 5, 50 dml2_output_rate_dp_rate_uhbr20 = 6, 51 dml2_output_rate_hdmi_rate_3x3 = 7, 52 dml2_output_rate_hdmi_rate_6x3 = 8, 53 dml2_output_rate_hdmi_rate_6x4 = 9, 54 dml2_output_rate_hdmi_rate_8x4 = 10, 55 dml2_output_rate_hdmi_rate_10x4 = 11, 56 dml2_output_rate_hdmi_rate_12x4 = 12, 57 dml2_output_rate_hdmi_rate_16x4 = 13, 58 dml2_output_rate_hdmi_rate_20x4 = 14 59 }; 60 61 struct dml2_pmo_options { 62 bool disable_vblank; 63 bool disable_svp; 64 bool disable_drr_var; 65 bool disable_drr_clamped; 66 bool disable_drr_var_when_var_active; 67 bool disable_drr_clamped_when_var_active; 68 bool disable_fams2; 69 bool disable_vactive_det_fill_bw_pad; /* dml2_project_dcn4x_stage2_auto_drr_svp and above only */ 70 bool disable_dyn_odm; 71 bool disable_dyn_odm_for_multi_stream; 72 bool disable_dyn_odm_for_stream_with_svp; 73 }; 74 75 struct dml2_options { 76 enum dml2_project_id project_id; 77 struct dml2_pmo_options pmo_options; 78 }; 79 80 struct dml2_initialize_instance_in_out { 81 struct dml2_instance *dml2_instance; 82 struct dml2_options options; 83 struct dml2_soc_bb soc_bb; 84 struct dml2_ip_capabilities ip_caps; 85 86 struct { 87 void *explicit_ip_bb; 88 unsigned int explicit_ip_bb_size; 89 } overrides; 90 }; 91 92 struct dml2_reset_instance_in_out { 93 struct dml2_instance *dml2_instance; 94 }; 95 96 struct dml2_check_mode_supported_in_out { 97 /* 98 * Inputs 99 */ 100 struct dml2_instance *dml2_instance; 101 const struct dml2_display_cfg *display_config; 102 103 /* 104 * Outputs 105 */ 106 bool is_supported; 107 }; 108 109 struct dml2_mcache_surface_allocation { 110 bool valid; 111 /* 112 * For iMALL, dedicated mall mcaches are required (sharing of last 113 * slice possible), for legacy phantom or phantom without return 114 * the only mall mcaches need to be valid. 115 */ 116 bool requires_dedicated_mall_mcache; 117 118 unsigned int num_mcaches_plane0; 119 unsigned int num_mcaches_plane1; 120 /* 121 * A plane is divided into vertical slices of mcaches, 122 * which wrap on the surface width. 123 * 124 * For example, if the surface width is 7680, and split into 125 * three slices of equal width, the boundary array would contain 126 * [2560, 5120, 7680] 127 * 128 * The assignments are 129 * 0 = [0 .. 2559] 130 * 1 = [2560 .. 5119] 131 * 2 = [5120 .. 7679] 132 * 0 = [7680 .. INF] 133 * The final element implicitly is the same as the first, and 134 * at first seems invalid since it is never referenced (since) 135 * it is outside the surface. However, its useful when shifting 136 * (see below). 137 * 138 * For any given valid mcache assignment, a shifted version, wrapped 139 * on the surface width boundary is also assumed to be valid. 140 * 141 * For example, shifting [2560, 5120, 7680] by -50 results in 142 * [2510, 5170, 7630]. 143 * 144 * The assignments are now: 145 * 0 = [0 .. 2509] 146 * 1 = [2510 .. 5169] 147 * 2 = [5170 .. 7629] 148 * 0 = [7630 .. INF] 149 */ 150 int mcache_x_offsets_plane0[DML2_MAX_MCACHES + 1]; 151 int mcache_x_offsets_plane1[DML2_MAX_MCACHES + 1]; 152 153 /* 154 * Shift grainularity is not necessarily 1 155 */ 156 struct { 157 int p0; 158 int p1; 159 } shift_granularity; 160 161 /* 162 * MCacheIDs have global scope in the SoC, and they are stored here. 163 * These IDs are generally not valid until all planes in a display 164 * configuration have had their mcache requirements calculated. 165 */ 166 int global_mcache_ids_plane0[DML2_MAX_MCACHES + 1]; 167 int global_mcache_ids_plane1[DML2_MAX_MCACHES + 1]; 168 int global_mcache_ids_mall_plane0[DML2_MAX_MCACHES + 1]; 169 int global_mcache_ids_mall_plane1[DML2_MAX_MCACHES + 1]; 170 171 /* 172 * Generally, plane0/1 slices must use a disjoint set of caches 173 * but in some cases the final segement of the two planes can 174 * use the same cache. If plane0_plane1 is set, then this is 175 * allowed. 176 * 177 * Similarly, the caches allocated to MALL prefetcher are generally 178 * disjoint, but if mall_prefetch is set, then the final segment 179 * between the main and the mall pixel requestor can use the same 180 * cache. 181 * 182 * Note that both bits may be set at the same time. 183 */ 184 struct { 185 bool mall_comb_mcache_p0; 186 bool mall_comb_mcache_p1; 187 bool plane0_plane1; 188 } last_slice_sharing; 189 190 struct { 191 int meta_row_bytes_plane0; 192 int meta_row_bytes_plane1; 193 } informative; 194 }; 195 196 enum dml2_pstate_method { 197 dml2_pstate_method_na = 0, 198 /* hw exclusive modes */ 199 dml2_pstate_method_vactive = 1, 200 dml2_pstate_method_vblank = 2, 201 dml2_pstate_method_reserved_hw = 5, 202 /* fw assisted exclusive modes */ 203 dml2_pstate_method_fw_svp = 6, 204 dml2_pstate_method_reserved_fw = 10, 205 /* fw assisted modes requiring drr modulation */ 206 dml2_pstate_method_fw_vactive_drr = 11, 207 dml2_pstate_method_fw_vblank_drr = 12, 208 dml2_pstate_method_fw_svp_drr = 13, 209 dml2_pstate_method_reserved_fw_drr_clamped = 20, 210 dml2_pstate_method_fw_drr = 21, 211 dml2_pstate_method_reserved_fw_drr_var = 22, 212 dml2_pstate_method_count 213 }; 214 215 struct dml2_per_plane_programming { 216 const struct dml2_plane_parameters *plane_descriptor; 217 218 union { 219 struct { 220 unsigned long dppclk_khz; 221 } dcn4x; 222 } min_clocks; 223 224 struct dml2_mcache_surface_allocation mcache_allocation; 225 226 // If a stream is using automatic or forced odm combine 227 // and the stream for this plane has num_odms_required > 1 228 // num_dpps_required is always equal to num_odms_required for 229 // ALL planes of the stream 230 231 // If a stream is using odm split, then this value is always 1 232 unsigned int num_dpps_required; 233 234 enum dml2_pstate_method uclk_pstate_support_method; 235 236 // MALL size requirements for MALL SS and SubVP 237 unsigned int surface_size_mall_bytes; 238 unsigned int svp_size_mall_bytes; 239 240 struct dml2_dchub_per_pipe_register_set *pipe_regs[DML2_MAX_PLANES]; 241 242 struct { 243 bool valid; 244 struct dml2_plane_parameters descriptor; 245 struct dml2_mcache_surface_allocation mcache_allocation; 246 struct dml2_dchub_per_pipe_register_set *pipe_regs[DML2_MAX_PLANES]; 247 } phantom_plane; 248 }; 249 250 union dml2_global_sync_programming { 251 struct { 252 unsigned int vstartup_lines; 253 unsigned int vupdate_offset_pixels; 254 unsigned int vupdate_vupdate_width_pixels; 255 unsigned int vready_offset_pixels; 256 unsigned int pstate_keepout_start_lines; 257 } dcn4x; 258 }; 259 260 struct dml2_per_stream_programming { 261 const struct dml2_stream_parameters *stream_descriptor; 262 263 union { 264 struct { 265 unsigned long dscclk_khz; 266 unsigned long dtbclk_khz; 267 unsigned long phyclk_khz; 268 } dcn4x; 269 } min_clocks; 270 271 union dml2_global_sync_programming global_sync; 272 273 unsigned int num_odms_required; 274 275 enum dml2_pstate_method uclk_pstate_method; 276 277 struct { 278 bool enabled; 279 struct dml2_stream_parameters descriptor; 280 union dml2_global_sync_programming global_sync; 281 } phantom_stream; 282 283 union dmub_cmd_fams2_config fams2_base_params; 284 union { 285 union dmub_cmd_fams2_config fams2_sub_params; 286 union dmub_fams2_stream_static_sub_state_v2 fams2_sub_params_v2; 287 }; 288 }; 289 290 //----------------- 291 // Mode Support Information 292 //----------------- 293 294 struct dml2_mode_support_info { 295 bool ModeIsSupported; //<brief Is the mode support any voltage and combine setting 296 bool ImmediateFlipSupport; //<brief Means mode support immediate flip at the max combine setting; determine in mode support and used in mode programming 297 // Mode Support Reason 298 bool WritebackLatencySupport; 299 bool ScaleRatioAndTapsSupport; 300 bool SourceFormatPixelAndScanSupport; 301 bool P2IWith420; 302 bool DSCOnlyIfNecessaryWithBPP; 303 bool DSC422NativeNotSupported; 304 bool LinkRateDoesNotMatchDPVersion; 305 bool LinkRateForMultistreamNotIndicated; 306 bool BPPForMultistreamNotIndicated; 307 bool MultistreamWithHDMIOreDP; 308 bool MSOOrODMSplitWithNonDPLink; 309 bool NotEnoughLanesForMSO; 310 bool NumberOfOTGSupport; 311 bool NumberOfHDMIFRLSupport; 312 bool NumberOfDP2p0Support; 313 bool WritebackScaleRatioAndTapsSupport; 314 bool CursorSupport; 315 bool PitchSupport; 316 bool ViewportExceedsSurface; 317 bool ImmediateFlipRequiredButTheRequirementForEachSurfaceIsNotSpecified; 318 bool ImmediateFlipOrHostVMAndPStateWithMALLFullFrameOrPhantomPipe; 319 bool InvalidCombinationOfMALLUseForPStateAndStaticScreen; 320 bool InvalidCombinationOfMALLUseForPState; 321 bool ExceededMALLSize; 322 bool EnoughWritebackUnits; 323 bool ExceededMultistreamSlots; 324 bool NotEnoughDSCUnits; 325 bool NotEnoughDSCSlices; 326 bool PixelsPerLinePerDSCUnitSupport; 327 bool DSCCLKRequiredMoreThanSupported; 328 bool DTBCLKRequiredMoreThanSupported; 329 bool LinkCapacitySupport; 330 bool ROBSupport; 331 bool OutstandingRequestsSupport; 332 bool OutstandingRequestsUrgencyAvoidance; 333 bool PTEBufferSizeNotExceeded; 334 bool DCCMetaBufferSizeNotExceeded; 335 bool TotalVerticalActiveBandwidthSupport; 336 bool VActiveBandwidthSupport; 337 enum dml2_pstate_change_support FCLKChangeSupport[DML2_MAX_PLANES]; 338 bool USRRetrainingSupport; 339 bool PrefetchSupported; 340 bool DynamicMetadataSupported; 341 bool VRatioInPrefetchSupported; 342 bool DISPCLK_DPPCLK_Support; 343 bool TotalAvailablePipesSupport; 344 bool ViewportSizeSupport; 345 bool ImmediateFlipSupportedForState; 346 double MaxTotalVerticalActiveAvailableBandwidth; 347 bool MPCCombineEnable[DML2_MAX_PLANES]; /// <brief Indicate if the MPC Combine enable in the given state and optimize mpc combine setting 348 enum dml2_odm_mode ODMMode[DML2_MAX_PLANES]; /// <brief ODM mode that is chosen in the mode check stage and will be used in mode programming stage 349 unsigned int DPPPerSurface[DML2_MAX_PLANES]; /// <brief How many DPPs are needed drive the surface to output. If MPCC or ODMC could be 2 or 4. 350 bool DSCEnabled[DML2_MAX_PLANES]; /// <brief Indicate if the DSC is actually required; used in mode_programming 351 bool FECEnabled[DML2_MAX_PLANES]; /// <brief Indicate if the FEC is actually required 352 unsigned int NumberOfDSCSlices[DML2_MAX_PLANES]; /// <brief Indicate how many slices needed to support the given mode 353 double OutputBpp[DML2_MAX_PLANES]; 354 enum dml2_output_type_and_rate__type OutputType[DML2_MAX_PLANES]; 355 enum dml2_output_type_and_rate__rate OutputRate[DML2_MAX_PLANES]; 356 unsigned int AlignedYPitch[DML2_MAX_PLANES]; 357 unsigned int AlignedCPitch[DML2_MAX_PLANES]; 358 bool g6_temp_read_support; 359 bool temp_read_or_ppt_support; 360 }; // dml2_mode_support_info 361 362 struct dml2_display_cfg_programming { 363 struct dml2_display_cfg display_config; 364 365 union { 366 struct { 367 unsigned long dcfclk_khz; 368 unsigned long fclk_khz; 369 unsigned long uclk_khz; 370 unsigned long socclk_khz; 371 unsigned long dispclk_khz; 372 unsigned long dcfclk_deepsleep_khz; 373 unsigned long dpp_ref_khz; 374 } dcn32x; 375 struct { 376 struct { 377 unsigned long uclk_khz; 378 unsigned long fclk_khz; 379 unsigned long dcfclk_khz; 380 } active; 381 struct { 382 unsigned long uclk_khz; 383 unsigned long fclk_khz; 384 unsigned long dcfclk_khz; 385 } idle; 386 struct { 387 unsigned long uclk_khz; 388 unsigned long fclk_khz; 389 unsigned long dcfclk_khz; 390 } svp_prefetch; 391 struct { 392 unsigned long uclk_khz; 393 unsigned long fclk_khz; 394 unsigned long dcfclk_khz; 395 } svp_prefetch_no_throttle; 396 397 unsigned long deepsleep_dcfclk_khz; 398 unsigned long dispclk_khz; 399 unsigned long dpprefclk_khz; 400 unsigned long dtbrefclk_khz; 401 unsigned long socclk_khz; 402 403 struct { 404 uint32_t dispclk_did; 405 uint32_t dpprefclk_did; 406 uint32_t dtbrefclk_did; 407 } divider_ids; 408 } dcn4x; 409 } min_clocks; 410 411 bool uclk_pstate_supported; 412 bool fclk_pstate_supported; 413 414 /* indicates this configuration requires FW to support */ 415 bool fams2_required; 416 struct dmub_cmd_fams2_global_config fams2_global_config; 417 418 struct { 419 bool supported_in_blank; // Changing to configurations where this is false requires stutter to be disabled during the transition 420 } stutter; 421 422 struct { 423 bool meets_eco; // Stutter cycles will meet Z8 ECO criteria 424 bool supported_in_blank; // Changing to configurations where this is false requires Z8 to be disabled during the transition 425 } z8_stutter; 426 427 struct dml2_dchub_global_register_set global_regs; 428 429 struct dml2_per_plane_programming plane_programming[DML2_MAX_PLANES]; 430 struct dml2_per_stream_programming stream_programming[DML2_MAX_PLANES]; 431 432 // Don't access this structure directly, access it through plane_programming.pipe_regs 433 struct dml2_dchub_per_pipe_register_set pipe_regs[DML2_MAX_PLANES]; 434 435 struct { 436 struct { 437 double urgent_us; 438 double writeback_urgent_us; 439 double writeback_pstate_us; 440 double writeback_fclk_pstate_us; 441 double cstate_exit_us; 442 double cstate_enter_plus_exit_us; 443 double z8_cstate_exit_us; 444 double z8_cstate_enter_plus_exit_us; 445 double pstate_change_us; 446 double fclk_pstate_change_us; 447 double usr_retraining_us; 448 double temp_read_or_ppt_watermark_us; 449 } watermarks; 450 451 struct { 452 unsigned int swath_width_plane0; 453 unsigned int swath_height_plane0; 454 unsigned int swath_height_plane1; 455 unsigned int dpte_row_height_plane0; 456 unsigned int dpte_row_height_plane1; 457 unsigned int meta_row_height_plane0; 458 unsigned int meta_row_height_plane1; 459 } plane_info[DML2_MAX_PLANES]; 460 461 struct { 462 unsigned int total_num_dpps_required; 463 } dpp; 464 465 struct { 466 unsigned long long total_surface_size_in_mall_bytes; 467 unsigned int subviewport_lines_needed_in_mall[DML2_MAX_PLANES]; 468 } mall; 469 470 struct { 471 double urgent_latency_us; // urgent ramp latency 472 double max_non_urgent_latency_us; 473 double max_urgent_latency_us; 474 double avg_non_urgent_latency_us; 475 double avg_urgent_latency_us; 476 double wm_memory_trip_us; 477 double meta_trip_memory_us; 478 double fraction_of_urgent_bandwidth; // nom 479 double fraction_of_urgent_bandwidth_immediate_flip; 480 double fraction_of_urgent_bandwidth_mall; 481 double max_active_fclk_change_latency_supported; 482 unsigned int min_return_latency_in_dcfclk; 483 484 struct { 485 struct { 486 double sdp_bw_mbps; 487 double dram_bw_mbps; 488 double dram_vm_only_bw_mbps; 489 } svp_prefetch; 490 491 struct { 492 double sdp_bw_mbps; 493 double dram_bw_mbps; 494 double dram_vm_only_bw_mbps; 495 } sys_active; 496 } urg_bw_available; 497 498 struct { 499 struct { 500 double sdp_bw_mbps; 501 double dram_bw_mbps; 502 } svp_prefetch; 503 504 struct { 505 double sdp_bw_mbps; 506 double dram_bw_mbps; 507 } sys_active; 508 } avg_bw_available; 509 510 struct { 511 struct { 512 double sdp_bw_mbps; 513 double dram_bw_mbps; 514 } svp_prefetch; 515 516 struct { 517 double sdp_bw_mbps; 518 double dram_bw_mbps; 519 } sys_active; 520 } non_urg_bw_required; 521 522 struct { 523 struct { 524 double sdp_bw_mbps; 525 double dram_bw_mbps; 526 } svp_prefetch; 527 528 struct { 529 double sdp_bw_mbps; 530 double dram_bw_mbps; 531 } sys_active; 532 } non_urg_bw_required_with_flip; 533 534 struct { 535 struct { 536 double sdp_bw_mbps; 537 double dram_bw_mbps; 538 } svp_prefetch; 539 540 struct { 541 double sdp_bw_mbps; 542 double dram_bw_mbps; 543 } sys_active; 544 545 } urg_bw_required; 546 547 struct { 548 struct { 549 double sdp_bw_mbps; 550 double dram_bw_mbps; 551 } svp_prefetch; 552 553 struct { 554 double sdp_bw_mbps; 555 double dram_bw_mbps; 556 } sys_active; 557 } urg_bw_required_with_flip; 558 559 struct { 560 struct { 561 double sdp_bw_mbps; 562 double dram_bw_mbps; 563 } svp_prefetch; 564 565 struct { 566 double sdp_bw_mbps; 567 double dram_bw_mbps; 568 } sys_active; 569 } avg_bw_required; 570 } qos; 571 572 struct { 573 unsigned long long det_size_in_kbytes[DML2_MAX_PLANES]; 574 unsigned long long DETBufferSizeY[DML2_MAX_PLANES]; 575 unsigned long long comp_buffer_size_kbytes; 576 bool UnboundedRequestEnabled; 577 unsigned int compbuf_reserved_space_64b; 578 } crb; 579 580 struct { 581 unsigned int max_uncompressed_block_plane0; 582 unsigned int max_compressed_block_plane0; 583 unsigned int independent_block_plane0; 584 unsigned int max_uncompressed_block_plane1; 585 unsigned int max_compressed_block_plane1; 586 unsigned int independent_block_plane1; 587 } dcc_control[DML2_MAX_PLANES]; 588 589 struct { 590 double stutter_efficiency; 591 double stutter_efficiency_with_vblank; 592 double stutter_num_bursts; 593 594 struct { 595 double stutter_efficiency; 596 double stutter_efficiency_with_vblank; 597 double stutter_num_bursts; 598 double stutter_period; 599 600 struct { 601 double stutter_efficiency; 602 double stutter_num_bursts; 603 double stutter_period; 604 } bestcase; 605 } z8; 606 } power_management; 607 608 struct { 609 double min_ttu_vblank_us[DML2_MAX_PLANES]; 610 bool vready_at_or_after_vsync[DML2_MAX_PLANES]; 611 double min_dst_y_next_start[DML2_MAX_PLANES]; 612 bool cstate_max_cap_mode; 613 bool hw_debug5; 614 unsigned int dcfclk_deep_sleep_hysteresis; 615 unsigned int dst_x_after_scaler[DML2_MAX_PLANES]; 616 unsigned int dst_y_after_scaler[DML2_MAX_PLANES]; 617 unsigned int prefetch_source_lines_plane0[DML2_MAX_PLANES]; 618 unsigned int prefetch_source_lines_plane1[DML2_MAX_PLANES]; 619 bool ImmediateFlipSupportedForPipe[DML2_MAX_PLANES]; 620 bool UsesMALLForStaticScreen[DML2_MAX_PLANES]; 621 unsigned int CursorDstXOffset[DML2_MAX_PLANES]; 622 unsigned int CursorDstYOffset[DML2_MAX_PLANES]; 623 unsigned int CursorChunkHDLAdjust[DML2_MAX_PLANES]; 624 unsigned int dpte_group_bytes[DML2_MAX_PLANES]; 625 unsigned int vm_group_bytes[DML2_MAX_PLANES]; 626 double DisplayPipeRequestDeliveryTimeLuma[DML2_MAX_PLANES]; 627 double DisplayPipeRequestDeliveryTimeChroma[DML2_MAX_PLANES]; 628 double DisplayPipeRequestDeliveryTimeLumaPrefetch[DML2_MAX_PLANES]; 629 double DisplayPipeRequestDeliveryTimeChromaPrefetch[DML2_MAX_PLANES]; 630 double TimePerVMGroupVBlank[DML2_MAX_PLANES]; 631 double TimePerVMGroupFlip[DML2_MAX_PLANES]; 632 double TimePerVMRequestVBlank[DML2_MAX_PLANES]; 633 double TimePerVMRequestFlip[DML2_MAX_PLANES]; 634 double Tdmdl_vm[DML2_MAX_PLANES]; 635 double Tdmdl[DML2_MAX_PLANES]; 636 unsigned int VStartup[DML2_MAX_PLANES]; 637 unsigned int VUpdateOffsetPix[DML2_MAX_PLANES]; 638 unsigned int VUpdateWidthPix[DML2_MAX_PLANES]; 639 unsigned int VReadyOffsetPix[DML2_MAX_PLANES]; 640 641 double DST_Y_PER_PTE_ROW_NOM_L[DML2_MAX_PLANES]; 642 double DST_Y_PER_PTE_ROW_NOM_C[DML2_MAX_PLANES]; 643 double time_per_pte_group_nom_luma[DML2_MAX_PLANES]; 644 double time_per_pte_group_nom_chroma[DML2_MAX_PLANES]; 645 double time_per_pte_group_vblank_luma[DML2_MAX_PLANES]; 646 double time_per_pte_group_vblank_chroma[DML2_MAX_PLANES]; 647 double time_per_pte_group_flip_luma[DML2_MAX_PLANES]; 648 double time_per_pte_group_flip_chroma[DML2_MAX_PLANES]; 649 double VRatioPrefetchY[DML2_MAX_PLANES]; 650 double VRatioPrefetchC[DML2_MAX_PLANES]; 651 double DestinationLinesForPrefetch[DML2_MAX_PLANES]; 652 double DestinationLinesToRequestVMInVBlank[DML2_MAX_PLANES]; 653 double DestinationLinesToRequestRowInVBlank[DML2_MAX_PLANES]; 654 double DestinationLinesToRequestVMInImmediateFlip[DML2_MAX_PLANES]; 655 double DestinationLinesToRequestRowInImmediateFlip[DML2_MAX_PLANES]; 656 double DisplayPipeLineDeliveryTimeLuma[DML2_MAX_PLANES]; 657 double DisplayPipeLineDeliveryTimeChroma[DML2_MAX_PLANES]; 658 double DisplayPipeLineDeliveryTimeLumaPrefetch[DML2_MAX_PLANES]; 659 double DisplayPipeLineDeliveryTimeChromaPrefetch[DML2_MAX_PLANES]; 660 661 double WritebackRequiredBandwidth; 662 double WritebackAllowDRAMClockChangeEndPosition[DML2_MAX_PLANES]; 663 double WritebackAllowFCLKChangeEndPosition[DML2_MAX_PLANES]; 664 double DSCCLK_calculated[DML2_MAX_PLANES]; 665 unsigned int BIGK_FRAGMENT_SIZE[DML2_MAX_PLANES]; 666 bool PTE_BUFFER_MODE[DML2_MAX_PLANES]; 667 double DSCDelay[DML2_MAX_PLANES]; 668 double MaxActiveDRAMClockChangeLatencySupported[DML2_MAX_PLANES]; 669 unsigned int PrefetchMode[DML2_MAX_PLANES]; // LEGACY_ONLY 670 bool ROBUrgencyAvoidance; 671 double LowestPrefetchMargin; 672 } misc; 673 674 struct dml2_mode_support_info mode_support_info; 675 unsigned int voltage_level; // LEGACY_ONLY 676 677 // For DV only 678 // This is what dml core calculated, only on the full_vp width and assume we have 679 // unlimited # of mcache 680 struct dml2_mcache_surface_allocation non_optimized_mcache_allocation[DML2_MAX_PLANES]; 681 682 bool failed_prefetch; 683 bool failed_uclk_pstate; 684 bool failed_mcache_validation; 685 bool failed_dpmm; 686 bool failed_mode_programming; 687 bool failed_mode_programming_dcfclk; 688 bool failed_mode_programming_prefetch; 689 bool failed_mode_programming_flip; 690 bool failed_map_watermarks; 691 } informative; 692 }; 693 694 struct dml2_build_mode_programming_in_out { 695 /* 696 * Inputs 697 */ 698 struct dml2_instance *dml2_instance; 699 const struct dml2_display_cfg *display_config; 700 701 /* 702 * Outputs 703 */ 704 struct dml2_display_cfg_programming *programming; 705 }; 706 707 struct dml2_build_mcache_programming_in_out { 708 /* 709 * Inputs 710 */ 711 struct dml2_instance *dml2_instance; 712 713 struct dml2_plane_mcache_configuration_descriptor mcache_configurations[DML2_MAX_PLANES]; 714 char num_configurations; 715 716 /* 717 * Outputs 718 */ 719 // per_plane_pipe_mcache_regs[i][j] refers to the proper programming for the j-th pipe of the 720 // i-th plane (from mcache_configurations) 721 struct dml2_hubp_pipe_mcache_regs *per_plane_pipe_mcache_regs[DML2_MAX_PLANES][DML2_MAX_DCN_PIPES]; 722 723 // It's not a good idea to reference this directly, better to use the pointer structure above instead 724 struct dml2_hubp_pipe_mcache_regs mcache_regs_set[DML2_MAX_DCN_PIPES]; 725 }; 726 727 struct dml2_unit_test_in_out { 728 /* 729 * Inputs 730 */ 731 struct dml2_instance *dml2_instance; 732 }; 733 734 735 #endif 736