1 // SPDX-License-Identifier: MIT 2 // 3 // Copyright 2024 Advanced Micro Devices, Inc. 4 5 #ifndef __DML_TOP_TYPES_H__ 6 #define __DML_TOP_TYPES_H__ 7 8 #include "dml_top_display_cfg_types.h" 9 #include "dml_top_soc_parameter_types.h" 10 #include "dml_top_policy_types.h" 11 #include "dml_top_dchub_registers.h" 12 13 #include "dmub_cmd.h" 14 15 struct dml2_instance; 16 17 enum dml2_project_id { 18 dml2_project_invalid = 0, 19 dml2_project_dcn4x_stage1 = 1, 20 dml2_project_dcn4x_stage2 = 2, 21 dml2_project_dcn4x_stage2_auto_drr_svp = 3, 22 }; 23 24 enum dml2_pstate_change_support { 25 dml2_pstate_change_vactive = 0, 26 dml2_pstate_change_vblank = 1, 27 dml2_pstate_change_vblank_and_vactive = 2, 28 dml2_pstate_change_drr = 3, 29 dml2_pstate_change_mall_svp = 4, 30 dml2_pstate_change_mall_full_frame = 6, 31 dml2_pstate_change_unsupported = 7 32 }; 33 34 enum dml2_output_type_and_rate__type { 35 dml2_output_type_unknown = 0, 36 dml2_output_type_dp = 1, 37 dml2_output_type_edp = 2, 38 dml2_output_type_dp2p0 = 3, 39 dml2_output_type_hdmi = 4, 40 dml2_output_type_hdmifrl = 5 41 }; 42 43 enum dml2_output_type_and_rate__rate { 44 dml2_output_rate_unknown = 0, 45 dml2_output_rate_dp_rate_hbr = 1, 46 dml2_output_rate_dp_rate_hbr2 = 2, 47 dml2_output_rate_dp_rate_hbr3 = 3, 48 dml2_output_rate_dp_rate_uhbr10 = 4, 49 dml2_output_rate_dp_rate_uhbr13p5 = 5, 50 dml2_output_rate_dp_rate_uhbr20 = 6, 51 dml2_output_rate_hdmi_rate_3x3 = 7, 52 dml2_output_rate_hdmi_rate_6x3 = 8, 53 dml2_output_rate_hdmi_rate_6x4 = 9, 54 dml2_output_rate_hdmi_rate_8x4 = 10, 55 dml2_output_rate_hdmi_rate_10x4 = 11, 56 dml2_output_rate_hdmi_rate_12x4 = 12 57 }; 58 59 struct dml2_pmo_options { 60 bool disable_vblank; 61 bool disable_svp; 62 bool disable_drr_var; 63 bool disable_drr_clamped; 64 bool disable_drr_var_when_var_active; 65 bool disable_drr_clamped_when_var_active; 66 bool disable_fams2; 67 bool disable_vactive_det_fill_bw_pad; /* dml2_project_dcn4x_stage2_auto_drr_svp and above only */ 68 bool disable_dyn_odm; 69 bool disable_dyn_odm_for_multi_stream; 70 bool disable_dyn_odm_for_stream_with_svp; 71 }; 72 73 struct dml2_options { 74 enum dml2_project_id project_id; 75 struct dml2_pmo_options pmo_options; 76 }; 77 78 struct dml2_initialize_instance_in_out { 79 struct dml2_instance *dml2_instance; 80 struct dml2_options options; 81 struct dml2_soc_bb soc_bb; 82 struct dml2_ip_capabilities ip_caps; 83 84 struct { 85 void *explicit_ip_bb; 86 unsigned int explicit_ip_bb_size; 87 } overrides; 88 }; 89 90 struct dml2_reset_instance_in_out { 91 struct dml2_instance *dml2_instance; 92 }; 93 94 struct dml2_check_mode_supported_in_out { 95 /* 96 * Inputs 97 */ 98 struct dml2_instance *dml2_instance; 99 const struct dml2_display_cfg *display_config; 100 101 /* 102 * Outputs 103 */ 104 bool is_supported; 105 }; 106 107 struct dml2_mcache_surface_allocation { 108 bool valid; 109 /* 110 * For iMALL, dedicated mall mcaches are required (sharing of last 111 * slice possible), for legacy phantom or phantom without return 112 * the only mall mcaches need to be valid. 113 */ 114 bool requires_dedicated_mall_mcache; 115 116 unsigned int num_mcaches_plane0; 117 unsigned int num_mcaches_plane1; 118 /* 119 * A plane is divided into vertical slices of mcaches, 120 * which wrap on the surface width. 121 * 122 * For example, if the surface width is 7680, and split into 123 * three slices of equal width, the boundary array would contain 124 * [2560, 5120, 7680] 125 * 126 * The assignments are 127 * 0 = [0 .. 2559] 128 * 1 = [2560 .. 5119] 129 * 2 = [5120 .. 7679] 130 * 0 = [7680 .. INF] 131 * The final element implicitly is the same as the first, and 132 * at first seems invalid since it is never referenced (since) 133 * it is outside the surface. However, its useful when shifting 134 * (see below). 135 * 136 * For any given valid mcache assignment, a shifted version, wrapped 137 * on the surface width boundary is also assumed to be valid. 138 * 139 * For example, shifting [2560, 5120, 7680] by -50 results in 140 * [2510, 5170, 7630]. 141 * 142 * The assignments are now: 143 * 0 = [0 .. 2509] 144 * 1 = [2510 .. 5169] 145 * 2 = [5170 .. 7629] 146 * 0 = [7630 .. INF] 147 */ 148 int mcache_x_offsets_plane0[DML2_MAX_MCACHES + 1]; 149 int mcache_x_offsets_plane1[DML2_MAX_MCACHES + 1]; 150 151 /* 152 * Shift grainularity is not necessarily 1 153 */ 154 struct { 155 int p0; 156 int p1; 157 } shift_granularity; 158 159 /* 160 * MCacheIDs have global scope in the SoC, and they are stored here. 161 * These IDs are generally not valid until all planes in a display 162 * configuration have had their mcache requirements calculated. 163 */ 164 int global_mcache_ids_plane0[DML2_MAX_MCACHES + 1]; 165 int global_mcache_ids_plane1[DML2_MAX_MCACHES + 1]; 166 int global_mcache_ids_mall_plane0[DML2_MAX_MCACHES + 1]; 167 int global_mcache_ids_mall_plane1[DML2_MAX_MCACHES + 1]; 168 169 /* 170 * Generally, plane0/1 slices must use a disjoint set of caches 171 * but in some cases the final segement of the two planes can 172 * use the same cache. If plane0_plane1 is set, then this is 173 * allowed. 174 * 175 * Similarly, the caches allocated to MALL prefetcher are generally 176 * disjoint, but if mall_prefetch is set, then the final segment 177 * between the main and the mall pixel requestor can use the same 178 * cache. 179 * 180 * Note that both bits may be set at the same time. 181 */ 182 struct { 183 bool mall_comb_mcache_p0; 184 bool mall_comb_mcache_p1; 185 bool plane0_plane1; 186 } last_slice_sharing; 187 188 struct { 189 int meta_row_bytes_plane0; 190 int meta_row_bytes_plane1; 191 } informative; 192 }; 193 194 enum dml2_pstate_method { 195 dml2_pstate_method_na = 0, 196 /* hw exclusive modes */ 197 dml2_pstate_method_vactive = 1, 198 dml2_pstate_method_vblank = 2, 199 dml2_pstate_method_reserved_hw = 5, 200 /* fw assisted exclusive modes */ 201 dml2_pstate_method_fw_svp = 6, 202 dml2_pstate_method_reserved_fw = 10, 203 /* fw assisted modes requiring drr modulation */ 204 dml2_pstate_method_fw_vactive_drr = 11, 205 dml2_pstate_method_fw_vblank_drr = 12, 206 dml2_pstate_method_fw_svp_drr = 13, 207 dml2_pstate_method_reserved_fw_drr_clamped = 20, 208 dml2_pstate_method_fw_drr = 21, 209 dml2_pstate_method_reserved_fw_drr_var = 22, 210 dml2_pstate_method_count 211 }; 212 213 struct dml2_per_plane_programming { 214 const struct dml2_plane_parameters *plane_descriptor; 215 216 union { 217 struct { 218 unsigned long dppclk_khz; 219 } dcn4x; 220 } min_clocks; 221 222 struct dml2_mcache_surface_allocation mcache_allocation; 223 224 // If a stream is using automatic or forced odm combine 225 // and the stream for this plane has num_odms_required > 1 226 // num_dpps_required is always equal to num_odms_required for 227 // ALL planes of the stream 228 229 // If a stream is using odm split, then this value is always 1 230 unsigned int num_dpps_required; 231 232 enum dml2_pstate_method uclk_pstate_support_method; 233 234 // MALL size requirements for MALL SS and SubVP 235 unsigned int surface_size_mall_bytes; 236 unsigned int svp_size_mall_bytes; 237 238 struct dml2_dchub_per_pipe_register_set *pipe_regs[DML2_MAX_PLANES]; 239 240 struct { 241 bool valid; 242 struct dml2_plane_parameters descriptor; 243 struct dml2_mcache_surface_allocation mcache_allocation; 244 struct dml2_dchub_per_pipe_register_set *pipe_regs[DML2_MAX_PLANES]; 245 } phantom_plane; 246 }; 247 248 union dml2_global_sync_programming { 249 struct { 250 unsigned int vstartup_lines; 251 unsigned int vupdate_offset_pixels; 252 unsigned int vupdate_vupdate_width_pixels; 253 unsigned int vready_offset_pixels; 254 unsigned int pstate_keepout_start_lines; 255 } dcn4x; 256 }; 257 258 struct dml2_per_stream_programming { 259 const struct dml2_stream_parameters *stream_descriptor; 260 261 union { 262 struct { 263 unsigned long dscclk_khz; 264 unsigned long dtbclk_khz; 265 unsigned long phyclk_khz; 266 } dcn4x; 267 } min_clocks; 268 269 union dml2_global_sync_programming global_sync; 270 271 unsigned int num_odms_required; 272 273 enum dml2_pstate_method uclk_pstate_method; 274 275 struct { 276 bool enabled; 277 struct dml2_stream_parameters descriptor; 278 union dml2_global_sync_programming global_sync; 279 } phantom_stream; 280 281 union dmub_cmd_fams2_config fams2_base_params; 282 union dmub_cmd_fams2_config fams2_sub_params; 283 }; 284 285 //----------------- 286 // Mode Support Information 287 //----------------- 288 289 struct dml2_mode_support_info { 290 bool ModeIsSupported; //<brief Is the mode support any voltage and combine setting 291 bool ImmediateFlipSupport; //<brief Means mode support immediate flip at the max combine setting; determine in mode support and used in mode programming 292 // Mode Support Reason 293 bool WritebackLatencySupport; 294 bool ScaleRatioAndTapsSupport; 295 bool SourceFormatPixelAndScanSupport; 296 bool P2IWith420; 297 bool DSCOnlyIfNecessaryWithBPP; 298 bool DSC422NativeNotSupported; 299 bool LinkRateDoesNotMatchDPVersion; 300 bool LinkRateForMultistreamNotIndicated; 301 bool BPPForMultistreamNotIndicated; 302 bool MultistreamWithHDMIOreDP; 303 bool MSOOrODMSplitWithNonDPLink; 304 bool NotEnoughLanesForMSO; 305 bool NumberOfOTGSupport; 306 bool NumberOfHDMIFRLSupport; 307 bool NumberOfDP2p0Support; 308 bool WritebackScaleRatioAndTapsSupport; 309 bool CursorSupport; 310 bool PitchSupport; 311 bool ViewportExceedsSurface; 312 bool ImmediateFlipRequiredButTheRequirementForEachSurfaceIsNotSpecified; 313 bool ImmediateFlipOrHostVMAndPStateWithMALLFullFrameOrPhantomPipe; 314 bool InvalidCombinationOfMALLUseForPStateAndStaticScreen; 315 bool InvalidCombinationOfMALLUseForPState; 316 bool ExceededMALLSize; 317 bool EnoughWritebackUnits; 318 bool ExceededMultistreamSlots; 319 bool NotEnoughDSCUnits; 320 bool NotEnoughDSCSlices; 321 bool PixelsPerLinePerDSCUnitSupport; 322 bool DSCCLKRequiredMoreThanSupported; 323 bool DTBCLKRequiredMoreThanSupported; 324 bool LinkCapacitySupport; 325 bool ROBSupport; 326 bool OutstandingRequestsSupport; 327 bool OutstandingRequestsUrgencyAvoidance; 328 bool PTEBufferSizeNotExceeded; 329 bool DCCMetaBufferSizeNotExceeded; 330 bool TotalVerticalActiveBandwidthSupport; 331 bool VActiveBandwidthSupport; 332 enum dml2_pstate_change_support FCLKChangeSupport[DML2_MAX_PLANES]; 333 bool USRRetrainingSupport; 334 bool PrefetchSupported; 335 bool DynamicMetadataSupported; 336 bool VRatioInPrefetchSupported; 337 bool DISPCLK_DPPCLK_Support; 338 bool TotalAvailablePipesSupport; 339 bool ViewportSizeSupport; 340 bool ImmediateFlipSupportedForState; 341 double MaxTotalVerticalActiveAvailableBandwidth; 342 bool MPCCombineEnable[DML2_MAX_PLANES]; /// <brief Indicate if the MPC Combine enable in the given state and optimize mpc combine setting 343 enum dml2_odm_mode ODMMode[DML2_MAX_PLANES]; /// <brief ODM mode that is chosen in the mode check stage and will be used in mode programming stage 344 unsigned int DPPPerSurface[DML2_MAX_PLANES]; /// <brief How many DPPs are needed drive the surface to output. If MPCC or ODMC could be 2 or 4. 345 bool DSCEnabled[DML2_MAX_PLANES]; /// <brief Indicate if the DSC is actually required; used in mode_programming 346 bool FECEnabled[DML2_MAX_PLANES]; /// <brief Indicate if the FEC is actually required 347 unsigned int NumberOfDSCSlices[DML2_MAX_PLANES]; /// <brief Indicate how many slices needed to support the given mode 348 double OutputBpp[DML2_MAX_PLANES]; 349 enum dml2_output_type_and_rate__type OutputType[DML2_MAX_PLANES]; 350 enum dml2_output_type_and_rate__rate OutputRate[DML2_MAX_PLANES]; 351 unsigned int AlignedYPitch[DML2_MAX_PLANES]; 352 unsigned int AlignedCPitch[DML2_MAX_PLANES]; 353 bool g6_temp_read_support; 354 bool temp_read_or_ppt_support; 355 }; // dml2_mode_support_info 356 357 struct dml2_display_cfg_programming { 358 struct dml2_display_cfg display_config; 359 360 union { 361 struct { 362 unsigned long dcfclk_khz; 363 unsigned long fclk_khz; 364 unsigned long uclk_khz; 365 unsigned long socclk_khz; 366 unsigned long dispclk_khz; 367 unsigned long dcfclk_deepsleep_khz; 368 unsigned long dpp_ref_khz; 369 } dcn32x; 370 struct { 371 struct { 372 unsigned long uclk_khz; 373 unsigned long fclk_khz; 374 unsigned long dcfclk_khz; 375 } active; 376 struct { 377 unsigned long uclk_khz; 378 unsigned long fclk_khz; 379 unsigned long dcfclk_khz; 380 } idle; 381 struct { 382 unsigned long uclk_khz; 383 unsigned long fclk_khz; 384 unsigned long dcfclk_khz; 385 } svp_prefetch; 386 struct { 387 unsigned long uclk_khz; 388 unsigned long fclk_khz; 389 unsigned long dcfclk_khz; 390 } svp_prefetch_no_throttle; 391 392 unsigned long deepsleep_dcfclk_khz; 393 unsigned long dispclk_khz; 394 unsigned long dpprefclk_khz; 395 unsigned long dtbrefclk_khz; 396 unsigned long socclk_khz; 397 398 struct { 399 uint32_t dispclk_did; 400 uint32_t dpprefclk_did; 401 uint32_t dtbrefclk_did; 402 } divider_ids; 403 } dcn4x; 404 } min_clocks; 405 406 bool uclk_pstate_supported; 407 bool fclk_pstate_supported; 408 409 /* indicates this configuration requires FW to support */ 410 bool fams2_required; 411 struct dmub_cmd_fams2_global_config fams2_global_config; 412 413 struct { 414 bool supported_in_blank; // Changing to configurations where this is false requires stutter to be disabled during the transition 415 } stutter; 416 417 struct { 418 bool meets_eco; // Stutter cycles will meet Z8 ECO criteria 419 bool supported_in_blank; // Changing to configurations where this is false requires Z8 to be disabled during the transition 420 } z8_stutter; 421 422 struct dml2_dchub_global_register_set global_regs; 423 424 struct dml2_per_plane_programming plane_programming[DML2_MAX_PLANES]; 425 struct dml2_per_stream_programming stream_programming[DML2_MAX_PLANES]; 426 427 // Don't access this structure directly, access it through plane_programming.pipe_regs 428 struct dml2_dchub_per_pipe_register_set pipe_regs[DML2_MAX_PLANES]; 429 430 struct { 431 struct { 432 double urgent_us; 433 double writeback_urgent_us; 434 double writeback_pstate_us; 435 double writeback_fclk_pstate_us; 436 double cstate_exit_us; 437 double cstate_enter_plus_exit_us; 438 double z8_cstate_exit_us; 439 double z8_cstate_enter_plus_exit_us; 440 double pstate_change_us; 441 double fclk_pstate_change_us; 442 double usr_retraining_us; 443 double temp_read_or_ppt_watermark_us; 444 } watermarks; 445 446 struct { 447 unsigned int swath_width_plane0; 448 unsigned int swath_height_plane0; 449 unsigned int swath_height_plane1; 450 unsigned int dpte_row_height_plane0; 451 unsigned int dpte_row_height_plane1; 452 unsigned int meta_row_height_plane0; 453 unsigned int meta_row_height_plane1; 454 } plane_info[DML2_MAX_PLANES]; 455 456 struct { 457 unsigned int total_num_dpps_required; 458 } dpp; 459 460 struct { 461 unsigned long long total_surface_size_in_mall_bytes; 462 unsigned int subviewport_lines_needed_in_mall[DML2_MAX_PLANES]; 463 } mall; 464 465 struct { 466 double urgent_latency_us; // urgent ramp latency 467 double max_non_urgent_latency_us; 468 double max_urgent_latency_us; 469 double avg_non_urgent_latency_us; 470 double avg_urgent_latency_us; 471 double wm_memory_trip_us; 472 double meta_trip_memory_us; 473 double fraction_of_urgent_bandwidth; // nom 474 double fraction_of_urgent_bandwidth_immediate_flip; 475 double fraction_of_urgent_bandwidth_mall; 476 double max_active_fclk_change_latency_supported; 477 unsigned int min_return_latency_in_dcfclk; 478 479 struct { 480 struct { 481 double sdp_bw_mbps; 482 double dram_bw_mbps; 483 double dram_vm_only_bw_mbps; 484 } svp_prefetch; 485 486 struct { 487 double sdp_bw_mbps; 488 double dram_bw_mbps; 489 double dram_vm_only_bw_mbps; 490 } sys_active; 491 } urg_bw_available; 492 493 struct { 494 struct { 495 double sdp_bw_mbps; 496 double dram_bw_mbps; 497 } svp_prefetch; 498 499 struct { 500 double sdp_bw_mbps; 501 double dram_bw_mbps; 502 } sys_active; 503 } avg_bw_available; 504 505 struct { 506 struct { 507 double sdp_bw_mbps; 508 double dram_bw_mbps; 509 } svp_prefetch; 510 511 struct { 512 double sdp_bw_mbps; 513 double dram_bw_mbps; 514 } sys_active; 515 } non_urg_bw_required; 516 517 struct { 518 struct { 519 double sdp_bw_mbps; 520 double dram_bw_mbps; 521 } svp_prefetch; 522 523 struct { 524 double sdp_bw_mbps; 525 double dram_bw_mbps; 526 } sys_active; 527 } non_urg_bw_required_with_flip; 528 529 struct { 530 struct { 531 double sdp_bw_mbps; 532 double dram_bw_mbps; 533 } svp_prefetch; 534 535 struct { 536 double sdp_bw_mbps; 537 double dram_bw_mbps; 538 } sys_active; 539 540 } urg_bw_required; 541 542 struct { 543 struct { 544 double sdp_bw_mbps; 545 double dram_bw_mbps; 546 } svp_prefetch; 547 548 struct { 549 double sdp_bw_mbps; 550 double dram_bw_mbps; 551 } sys_active; 552 } urg_bw_required_with_flip; 553 554 struct { 555 struct { 556 double sdp_bw_mbps; 557 double dram_bw_mbps; 558 } svp_prefetch; 559 560 struct { 561 double sdp_bw_mbps; 562 double dram_bw_mbps; 563 } sys_active; 564 } avg_bw_required; 565 } qos; 566 567 struct { 568 unsigned long long det_size_in_kbytes[DML2_MAX_PLANES]; 569 unsigned long long DETBufferSizeY[DML2_MAX_PLANES]; 570 unsigned long long comp_buffer_size_kbytes; 571 bool UnboundedRequestEnabled; 572 unsigned int compbuf_reserved_space_64b; 573 } crb; 574 575 struct { 576 unsigned int max_uncompressed_block_plane0; 577 unsigned int max_compressed_block_plane0; 578 unsigned int independent_block_plane0; 579 unsigned int max_uncompressed_block_plane1; 580 unsigned int max_compressed_block_plane1; 581 unsigned int independent_block_plane1; 582 } dcc_control[DML2_MAX_PLANES]; 583 584 struct { 585 double stutter_efficiency; 586 double stutter_efficiency_with_vblank; 587 double stutter_num_bursts; 588 589 struct { 590 double stutter_efficiency; 591 double stutter_efficiency_with_vblank; 592 double stutter_num_bursts; 593 double stutter_period; 594 595 struct { 596 double stutter_efficiency; 597 double stutter_num_bursts; 598 double stutter_period; 599 } bestcase; 600 } z8; 601 } power_management; 602 603 struct { 604 double min_ttu_vblank_us[DML2_MAX_PLANES]; 605 bool vready_at_or_after_vsync[DML2_MAX_PLANES]; 606 double min_dst_y_next_start[DML2_MAX_PLANES]; 607 bool cstate_max_cap_mode; 608 bool hw_debug5; 609 unsigned int dcfclk_deep_sleep_hysteresis; 610 unsigned int dst_x_after_scaler[DML2_MAX_PLANES]; 611 unsigned int dst_y_after_scaler[DML2_MAX_PLANES]; 612 unsigned int prefetch_source_lines_plane0[DML2_MAX_PLANES]; 613 unsigned int prefetch_source_lines_plane1[DML2_MAX_PLANES]; 614 bool ImmediateFlipSupportedForPipe[DML2_MAX_PLANES]; 615 bool UsesMALLForStaticScreen[DML2_MAX_PLANES]; 616 unsigned int CursorDstXOffset[DML2_MAX_PLANES]; 617 unsigned int CursorDstYOffset[DML2_MAX_PLANES]; 618 unsigned int CursorChunkHDLAdjust[DML2_MAX_PLANES]; 619 unsigned int dpte_group_bytes[DML2_MAX_PLANES]; 620 unsigned int vm_group_bytes[DML2_MAX_PLANES]; 621 double DisplayPipeRequestDeliveryTimeLuma[DML2_MAX_PLANES]; 622 double DisplayPipeRequestDeliveryTimeChroma[DML2_MAX_PLANES]; 623 double DisplayPipeRequestDeliveryTimeLumaPrefetch[DML2_MAX_PLANES]; 624 double DisplayPipeRequestDeliveryTimeChromaPrefetch[DML2_MAX_PLANES]; 625 double TimePerVMGroupVBlank[DML2_MAX_PLANES]; 626 double TimePerVMGroupFlip[DML2_MAX_PLANES]; 627 double TimePerVMRequestVBlank[DML2_MAX_PLANES]; 628 double TimePerVMRequestFlip[DML2_MAX_PLANES]; 629 double Tdmdl_vm[DML2_MAX_PLANES]; 630 double Tdmdl[DML2_MAX_PLANES]; 631 unsigned int VStartup[DML2_MAX_PLANES]; 632 unsigned int VUpdateOffsetPix[DML2_MAX_PLANES]; 633 unsigned int VUpdateWidthPix[DML2_MAX_PLANES]; 634 unsigned int VReadyOffsetPix[DML2_MAX_PLANES]; 635 636 double DST_Y_PER_PTE_ROW_NOM_L[DML2_MAX_PLANES]; 637 double DST_Y_PER_PTE_ROW_NOM_C[DML2_MAX_PLANES]; 638 double time_per_pte_group_nom_luma[DML2_MAX_PLANES]; 639 double time_per_pte_group_nom_chroma[DML2_MAX_PLANES]; 640 double time_per_pte_group_vblank_luma[DML2_MAX_PLANES]; 641 double time_per_pte_group_vblank_chroma[DML2_MAX_PLANES]; 642 double time_per_pte_group_flip_luma[DML2_MAX_PLANES]; 643 double time_per_pte_group_flip_chroma[DML2_MAX_PLANES]; 644 double VRatioPrefetchY[DML2_MAX_PLANES]; 645 double VRatioPrefetchC[DML2_MAX_PLANES]; 646 double DestinationLinesForPrefetch[DML2_MAX_PLANES]; 647 double DestinationLinesToRequestVMInVBlank[DML2_MAX_PLANES]; 648 double DestinationLinesToRequestRowInVBlank[DML2_MAX_PLANES]; 649 double DestinationLinesToRequestVMInImmediateFlip[DML2_MAX_PLANES]; 650 double DestinationLinesToRequestRowInImmediateFlip[DML2_MAX_PLANES]; 651 double DisplayPipeLineDeliveryTimeLuma[DML2_MAX_PLANES]; 652 double DisplayPipeLineDeliveryTimeChroma[DML2_MAX_PLANES]; 653 double DisplayPipeLineDeliveryTimeLumaPrefetch[DML2_MAX_PLANES]; 654 double DisplayPipeLineDeliveryTimeChromaPrefetch[DML2_MAX_PLANES]; 655 656 double WritebackRequiredBandwidth; 657 double WritebackAllowDRAMClockChangeEndPosition[DML2_MAX_PLANES]; 658 double WritebackAllowFCLKChangeEndPosition[DML2_MAX_PLANES]; 659 double DSCCLK_calculated[DML2_MAX_PLANES]; 660 unsigned int BIGK_FRAGMENT_SIZE[DML2_MAX_PLANES]; 661 bool PTE_BUFFER_MODE[DML2_MAX_PLANES]; 662 double DSCDelay[DML2_MAX_PLANES]; 663 double MaxActiveDRAMClockChangeLatencySupported[DML2_MAX_PLANES]; 664 unsigned int PrefetchMode[DML2_MAX_PLANES]; // LEGACY_ONLY 665 bool ROBUrgencyAvoidance; 666 double LowestPrefetchMargin; 667 } misc; 668 669 struct dml2_mode_support_info mode_support_info; 670 unsigned int voltage_level; // LEGACY_ONLY 671 672 // For DV only 673 // This is what dml core calculated, only on the full_vp width and assume we have 674 // unlimited # of mcache 675 struct dml2_mcache_surface_allocation non_optimized_mcache_allocation[DML2_MAX_PLANES]; 676 677 bool failed_mcache_validation; 678 bool failed_dpmm; 679 bool failed_mode_programming; 680 bool failed_map_watermarks; 681 } informative; 682 }; 683 684 struct dml2_build_mode_programming_in_out { 685 /* 686 * Inputs 687 */ 688 struct dml2_instance *dml2_instance; 689 const struct dml2_display_cfg *display_config; 690 691 /* 692 * Outputs 693 */ 694 struct dml2_display_cfg_programming *programming; 695 }; 696 697 struct dml2_build_mcache_programming_in_out { 698 /* 699 * Inputs 700 */ 701 struct dml2_instance *dml2_instance; 702 703 struct dml2_plane_mcache_configuration_descriptor mcache_configurations[DML2_MAX_PLANES]; 704 char num_configurations; 705 706 /* 707 * Outputs 708 */ 709 // per_plane_pipe_mcache_regs[i][j] refers to the proper programming for the j-th pipe of the 710 // i-th plane (from mcache_configurations) 711 struct dml2_hubp_pipe_mcache_regs *per_plane_pipe_mcache_regs[DML2_MAX_PLANES][DML2_MAX_DCN_PIPES]; 712 713 // It's not a good idea to reference this directly, better to use the pointer structure above instead 714 struct dml2_hubp_pipe_mcache_regs mcache_regs_set[DML2_MAX_DCN_PIPES]; 715 }; 716 717 struct dml2_unit_test_in_out { 718 /* 719 * Inputs 720 */ 721 struct dml2_instance *dml2_instance; 722 }; 723 724 725 #endif 726