1 /* SPDX-License-Identifier: GPL-2.0-only */ 2 /* 3 * Copyright (c) 2010-2011,2013-2015,2020 The Linux Foundation. All rights reserved. 4 * 5 * lpass.h - Definitions for the QTi LPASS 6 */ 7 8 #ifndef __LPASS_H__ 9 #define __LPASS_H__ 10 11 #include <linux/clk.h> 12 #include <linux/compiler.h> 13 #include <linux/platform_device.h> 14 #include <linux/regmap.h> 15 #include <dt-bindings/sound/qcom,lpass.h> 16 #include <dt-bindings/sound/qcom,q6afe.h> 17 #include "common.h" 18 #include "lpass-hdmi.h" 19 20 #define LPASS_AHBIX_CLOCK_FREQUENCY 131072000 21 #define LPASS_MAX_PORTS (LPASS_MAX_PORT) 22 #define LPASS_MAX_MI2S_PORTS (8) 23 #define LPASS_MAX_DMA_CHANNELS (8) 24 #define LPASS_MAX_HDMI_DMA_CHANNELS (4) 25 #define LPASS_MAX_CDC_DMA_CHANNELS (8) 26 #define LPASS_MAX_VA_CDC_DMA_CHANNELS (8) 27 #define LPASS_CDC_DMA_INTF_ONE_CHANNEL (0x01) 28 #define LPASS_CDC_DMA_INTF_TWO_CHANNEL (0x03) 29 #define LPASS_CDC_DMA_INTF_FOUR_CHANNEL (0x0F) 30 #define LPASS_CDC_DMA_INTF_SIX_CHANNEL (0x3F) 31 #define LPASS_CDC_DMA_INTF_EIGHT_CHANNEL (0xFF) 32 33 #define LPASS_ACTIVE_PDS (4) 34 #define LPASS_PROXY_PDS (8) 35 36 #define QCOM_REGMAP_FIELD_ALLOC(d, m, f, mf) \ 37 do { \ 38 mf = devm_regmap_field_alloc(d, m, f); \ 39 if (IS_ERR(mf)) \ 40 return -EINVAL; \ 41 } while (0) 42 43 static inline bool is_cdc_dma_port(int dai_id) 44 { 45 switch (dai_id) { 46 case LPASS_CDC_DMA_RX0 ... LPASS_CDC_DMA_RX9: 47 case LPASS_CDC_DMA_TX0 ... LPASS_CDC_DMA_TX8: 48 case LPASS_CDC_DMA_VA_TX0 ... LPASS_CDC_DMA_VA_TX8: 49 return true; 50 } 51 return false; 52 } 53 54 static inline bool is_rxtx_cdc_dma_port(int dai_id) 55 { 56 switch (dai_id) { 57 case LPASS_CDC_DMA_RX0 ... LPASS_CDC_DMA_RX9: 58 case LPASS_CDC_DMA_TX0 ... LPASS_CDC_DMA_TX8: 59 return true; 60 } 61 return false; 62 } 63 64 struct lpaif_i2sctl { 65 struct regmap_field *loopback; 66 struct regmap_field *spken; 67 struct regmap_field *spkmode; 68 struct regmap_field *spkmono; 69 struct regmap_field *micen; 70 struct regmap_field *micmode; 71 struct regmap_field *micmono; 72 struct regmap_field *wssrc; 73 struct regmap_field *bitwidth; 74 }; 75 76 77 struct lpaif_dmactl { 78 struct regmap_field *intf; 79 struct regmap_field *bursten; 80 struct regmap_field *wpscnt; 81 struct regmap_field *fifowm; 82 struct regmap_field *enable; 83 struct regmap_field *dyncclk; 84 struct regmap_field *burst8; 85 struct regmap_field *burst16; 86 struct regmap_field *dynburst; 87 struct regmap_field *codec_enable; 88 struct regmap_field *codec_pack; 89 struct regmap_field *codec_intf; 90 struct regmap_field *codec_fs_sel; 91 struct regmap_field *codec_channel; 92 struct regmap_field *codec_fs_delay; 93 }; 94 95 /* Both the CPU DAI and platform drivers will access this data */ 96 struct lpass_data { 97 98 /* AHB-I/X bus clocks inside the low-power audio subsystem (LPASS) */ 99 struct clk *ahbix_clk; 100 101 /* MI2S system clock */ 102 struct clk *mi2s_osr_clk[LPASS_MAX_MI2S_PORTS]; 103 104 /* MI2S bit clock (derived from system clock by a divider */ 105 struct clk *mi2s_bit_clk[LPASS_MAX_MI2S_PORTS]; 106 107 struct clk *codec_mem0; 108 struct clk *codec_mem1; 109 struct clk *codec_mem2; 110 struct clk *va_mem0; 111 112 /* MI2S SD lines to use for playback/capture */ 113 unsigned int mi2s_playback_sd_mode[LPASS_MAX_MI2S_PORTS]; 114 unsigned int mi2s_capture_sd_mode[LPASS_MAX_MI2S_PORTS]; 115 116 /* The state of MI2S prepare dai_ops was called */ 117 bool mi2s_was_prepared[LPASS_MAX_MI2S_PORTS]; 118 119 int hdmi_port_enable; 120 int codec_dma_enable; 121 122 /* low-power audio interface (LPAIF) registers */ 123 void __iomem *lpaif; 124 void __iomem *hdmiif; 125 void __iomem *rxtx_lpaif; 126 void __iomem *va_lpaif; 127 128 u32 rxtx_cdc_dma_lpm_buf; 129 u32 va_cdc_dma_lpm_buf; 130 131 /* regmap backed by the low-power audio interface (LPAIF) registers */ 132 struct regmap *lpaif_map; 133 struct regmap *hdmiif_map; 134 struct regmap *rxtx_lpaif_map; 135 struct regmap *va_lpaif_map; 136 137 /* interrupts from the low-power audio interface (LPAIF) */ 138 int lpaif_irq; 139 int hdmiif_irq; 140 int rxtxif_irq; 141 int vaif_irq; 142 143 /* SOC specific variations in the LPASS IP integration */ 144 const struct lpass_variant *variant; 145 146 /* bit map to keep track of static channel allocations */ 147 unsigned long dma_ch_bit_map; 148 unsigned long hdmi_dma_ch_bit_map; 149 unsigned long rxtx_dma_ch_bit_map; 150 unsigned long va_dma_ch_bit_map; 151 152 /* used it for handling interrupt per dma channel */ 153 struct snd_pcm_substream *substream[LPASS_MAX_DMA_CHANNELS]; 154 struct snd_pcm_substream *hdmi_substream[LPASS_MAX_HDMI_DMA_CHANNELS]; 155 struct snd_pcm_substream *rxtx_substream[LPASS_MAX_CDC_DMA_CHANNELS]; 156 struct snd_pcm_substream *va_substream[LPASS_MAX_CDC_DMA_CHANNELS]; 157 158 /* SOC specific clock list */ 159 struct clk_bulk_data *clks; 160 int num_clks; 161 162 /* Regmap fields of I2SCTL & DMACTL registers bitfields */ 163 struct lpaif_i2sctl *i2sctl; 164 struct lpaif_dmactl *rd_dmactl; 165 struct lpaif_dmactl *wr_dmactl; 166 struct lpaif_dmactl *hdmi_rd_dmactl; 167 168 /* Regmap fields of CODEC DMA CTRL registers */ 169 struct lpaif_dmactl *rxtx_rd_dmactl; 170 struct lpaif_dmactl *rxtx_wr_dmactl; 171 struct lpaif_dmactl *va_wr_dmactl; 172 173 /* Regmap fields of HDMI_CTRL registers*/ 174 struct regmap_field *hdmitx_legacy_en; 175 struct regmap_field *hdmitx_parity_calc_en; 176 struct regmap_field *hdmitx_ch_msb[LPASS_MAX_HDMI_DMA_CHANNELS]; 177 struct regmap_field *hdmitx_ch_lsb[LPASS_MAX_HDMI_DMA_CHANNELS]; 178 struct lpass_hdmi_tx_ctl *tx_ctl; 179 struct lpass_vbit_ctrl *vbit_ctl; 180 struct lpass_hdmitx_dmactl *hdmi_tx_dmactl[LPASS_MAX_HDMI_DMA_CHANNELS]; 181 struct lpass_dp_metadata_ctl *meta_ctl; 182 struct lpass_sstream_ctl *sstream_ctl; 183 }; 184 185 /* Vairant data per each SOC */ 186 struct lpass_variant { 187 u32 irq_reg_base; 188 u32 irq_reg_stride; 189 u32 irq_ports; 190 u32 rdma_reg_base; 191 u32 rdma_reg_stride; 192 u32 rdma_channels; 193 u32 hdmi_rdma_reg_base; 194 u32 hdmi_rdma_reg_stride; 195 u32 hdmi_rdma_channels; 196 u32 wrdma_reg_base; 197 u32 wrdma_reg_stride; 198 u32 wrdma_channels; 199 u32 rxtx_irq_reg_base; 200 u32 rxtx_irq_reg_stride; 201 u32 rxtx_irq_ports; 202 u32 rxtx_rdma_reg_base; 203 u32 rxtx_rdma_reg_stride; 204 u32 rxtx_rdma_channels; 205 u32 rxtx_wrdma_reg_base; 206 u32 rxtx_wrdma_reg_stride; 207 u32 rxtx_wrdma_channels; 208 u32 va_irq_reg_base; 209 u32 va_irq_reg_stride; 210 u32 va_irq_ports; 211 u32 va_rdma_reg_base; 212 u32 va_rdma_reg_stride; 213 u32 va_rdma_channels; 214 u32 va_wrdma_reg_base; 215 u32 va_wrdma_reg_stride; 216 u32 va_wrdma_channels; 217 u32 i2sctrl_reg_base; 218 u32 i2sctrl_reg_stride; 219 u32 i2s_ports; 220 221 /* I2SCTL Register fields */ 222 struct reg_field loopback; 223 struct reg_field spken; 224 struct reg_field spkmode; 225 struct reg_field spkmono; 226 struct reg_field micen; 227 struct reg_field micmode; 228 struct reg_field micmono; 229 struct reg_field wssrc; 230 struct reg_field bitwidth; 231 232 u32 hdmi_irq_reg_base; 233 u32 hdmi_irq_reg_stride; 234 u32 hdmi_irq_ports; 235 236 /* HDMI specific controls */ 237 u32 hdmi_tx_ctl_addr; 238 u32 hdmi_legacy_addr; 239 u32 hdmi_vbit_addr; 240 u32 hdmi_ch_lsb_addr; 241 u32 hdmi_ch_msb_addr; 242 u32 ch_stride; 243 u32 hdmi_parity_addr; 244 u32 hdmi_dmactl_addr; 245 u32 hdmi_dma_stride; 246 u32 hdmi_DP_addr; 247 u32 hdmi_sstream_addr; 248 249 /* HDMI SSTREAM CTRL fields */ 250 struct reg_field sstream_en; 251 struct reg_field dma_sel; 252 struct reg_field auto_bbit_en; 253 struct reg_field layout; 254 struct reg_field layout_sp; 255 struct reg_field set_sp_on_en; 256 struct reg_field dp_audio; 257 struct reg_field dp_staffing_en; 258 struct reg_field dp_sp_b_hw_en; 259 260 /* HDMI DP METADATA CTL fields */ 261 struct reg_field mute; 262 struct reg_field as_sdp_cc; 263 struct reg_field as_sdp_ct; 264 struct reg_field aif_db4; 265 struct reg_field frequency; 266 struct reg_field mst_index; 267 struct reg_field dptx_index; 268 269 /* HDMI TX CTRL fields */ 270 struct reg_field soft_reset; 271 struct reg_field force_reset; 272 273 /* HDMI TX DMA CTRL */ 274 struct reg_field use_hw_chs; 275 struct reg_field use_hw_usr; 276 struct reg_field hw_chs_sel; 277 struct reg_field hw_usr_sel; 278 279 /* HDMI VBIT CTRL */ 280 struct reg_field replace_vbit; 281 struct reg_field vbit_stream; 282 283 /* HDMI TX LEGACY */ 284 struct reg_field legacy_en; 285 286 /* HDMI TX PARITY */ 287 struct reg_field calc_en; 288 289 /* HDMI CH LSB */ 290 struct reg_field lsb_bits; 291 292 /* HDMI CH MSB */ 293 struct reg_field msb_bits; 294 295 struct reg_field hdmi_rdma_bursten; 296 struct reg_field hdmi_rdma_wpscnt; 297 struct reg_field hdmi_rdma_fifowm; 298 struct reg_field hdmi_rdma_enable; 299 struct reg_field hdmi_rdma_dyncclk; 300 struct reg_field hdmi_rdma_burst8; 301 struct reg_field hdmi_rdma_burst16; 302 struct reg_field hdmi_rdma_dynburst; 303 304 /* RD_DMA Register fields */ 305 struct reg_field rdma_intf; 306 struct reg_field rdma_bursten; 307 struct reg_field rdma_wpscnt; 308 struct reg_field rdma_fifowm; 309 struct reg_field rdma_enable; 310 struct reg_field rdma_dyncclk; 311 312 /* WR_DMA Register fields */ 313 struct reg_field wrdma_intf; 314 struct reg_field wrdma_bursten; 315 struct reg_field wrdma_wpscnt; 316 struct reg_field wrdma_fifowm; 317 struct reg_field wrdma_enable; 318 struct reg_field wrdma_dyncclk; 319 320 /* CDC RXTX RD_DMA */ 321 struct reg_field rxtx_rdma_intf; 322 struct reg_field rxtx_rdma_bursten; 323 struct reg_field rxtx_rdma_wpscnt; 324 struct reg_field rxtx_rdma_fifowm; 325 struct reg_field rxtx_rdma_enable; 326 struct reg_field rxtx_rdma_dyncclk; 327 struct reg_field rxtx_rdma_burst8; 328 struct reg_field rxtx_rdma_burst16; 329 struct reg_field rxtx_rdma_dynburst; 330 struct reg_field rxtx_rdma_codec_enable; 331 struct reg_field rxtx_rdma_codec_pack; 332 struct reg_field rxtx_rdma_codec_intf; 333 struct reg_field rxtx_rdma_codec_fs_sel; 334 struct reg_field rxtx_rdma_codec_ch; 335 struct reg_field rxtx_rdma_codec_fs_delay; 336 337 /* CDC RXTX WR_DMA */ 338 struct reg_field rxtx_wrdma_intf; 339 struct reg_field rxtx_wrdma_bursten; 340 struct reg_field rxtx_wrdma_wpscnt; 341 struct reg_field rxtx_wrdma_fifowm; 342 struct reg_field rxtx_wrdma_enable; 343 struct reg_field rxtx_wrdma_dyncclk; 344 struct reg_field rxtx_wrdma_burst8; 345 struct reg_field rxtx_wrdma_burst16; 346 struct reg_field rxtx_wrdma_dynburst; 347 struct reg_field rxtx_wrdma_codec_enable; 348 struct reg_field rxtx_wrdma_codec_pack; 349 struct reg_field rxtx_wrdma_codec_intf; 350 struct reg_field rxtx_wrdma_codec_fs_sel; 351 struct reg_field rxtx_wrdma_codec_ch; 352 struct reg_field rxtx_wrdma_codec_fs_delay; 353 354 /* CDC VA WR_DMA */ 355 struct reg_field va_wrdma_intf; 356 struct reg_field va_wrdma_bursten; 357 struct reg_field va_wrdma_wpscnt; 358 struct reg_field va_wrdma_fifowm; 359 struct reg_field va_wrdma_enable; 360 struct reg_field va_wrdma_dyncclk; 361 struct reg_field va_wrdma_burst8; 362 struct reg_field va_wrdma_burst16; 363 struct reg_field va_wrdma_dynburst; 364 struct reg_field va_wrdma_codec_enable; 365 struct reg_field va_wrdma_codec_pack; 366 struct reg_field va_wrdma_codec_intf; 367 struct reg_field va_wrdma_codec_fs_sel; 368 struct reg_field va_wrdma_codec_ch; 369 struct reg_field va_wrdma_codec_fs_delay; 370 371 /** 372 * on SOCs like APQ8016 the channel control bits start 373 * at different offset to ipq806x 374 **/ 375 u32 dmactl_audif_start; 376 u32 wrdma_channel_start; 377 u32 rxtx_wrdma_channel_start; 378 u32 va_wrdma_channel_start; 379 380 /* SOC specific initialization like clocks */ 381 int (*init)(struct platform_device *pdev); 382 int (*exit)(struct platform_device *pdev); 383 int (*alloc_dma_channel)(struct lpass_data *data, int direction, unsigned int dai_id); 384 int (*free_dma_channel)(struct lpass_data *data, int ch, unsigned int dai_id); 385 386 /* SOC specific dais */ 387 struct snd_soc_dai_driver *dai_driver; 388 int num_dai; 389 const char * const *dai_osr_clk_names; 390 const char * const *dai_bit_clk_names; 391 392 /* SOC specific clocks configuration */ 393 const char **clk_name; 394 int num_clks; 395 }; 396 397 struct lpass_pcm_data { 398 int dma_ch; 399 int i2s_port; 400 }; 401 402 /* register the platform driver from the CPU DAI driver */ 403 int asoc_qcom_lpass_platform_register(struct platform_device *pdev); 404 void asoc_qcom_lpass_cpu_platform_remove(struct platform_device *pdev); 405 void asoc_qcom_lpass_cpu_platform_shutdown(struct platform_device *pdev); 406 int asoc_qcom_lpass_cpu_platform_probe(struct platform_device *pdev); 407 extern const struct snd_soc_dai_ops asoc_qcom_lpass_cpu_dai_ops; 408 extern const struct snd_soc_dai_ops asoc_qcom_lpass_cpu_dai_ops2; 409 extern const struct snd_soc_dai_ops asoc_qcom_lpass_cdc_dma_dai_ops; 410 411 #endif /* __LPASS_H__ */ 412