1 /* 2 * Copyright 2015 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 * Authors: AMD 23 * 24 */ 25 26 #ifndef _CORE_TYPES_H_ 27 #define _CORE_TYPES_H_ 28 29 #include "dc.h" 30 #include "dce_calcs.h" 31 #include "dcn_calcs.h" 32 #include "ddc_service_types.h" 33 #include "dc_bios_types.h" 34 #include "mem_input.h" 35 #include "hubp.h" 36 #include "mpc.h" 37 #include "dwb.h" 38 #include "mcif_wb.h" 39 #include "panel_cntl.h" 40 #include "dmub/inc/dmub_cmd.h" 41 #include "pg_cntl.h" 42 #include "sspl/dc_spl.h" 43 44 #define MAX_CLOCK_SOURCES 7 45 #define MAX_SVP_PHANTOM_STREAMS 2 46 #define MAX_SVP_PHANTOM_PLANES 2 47 48 #include "grph_object_id.h" 49 #include "link_encoder.h" 50 #include "stream_encoder.h" 51 #include "clock_source.h" 52 #include "audio.h" 53 #include "dm_pp_smu.h" 54 #include "dm_cp_psp.h" 55 #include "link_hwss.h" 56 57 /********** DAL Core*********************/ 58 #include "transform.h" 59 #include "dpp.h" 60 61 #include "dml2/dml21/inc/dml_top_dchub_registers.h" 62 #include "dml2/dml21/inc/dml_top_types.h" 63 64 struct resource_pool; 65 struct dc_state; 66 struct resource_context; 67 struct clk_bw_params; 68 struct dc_mcache_params; 69 70 #define MAX_RMCM_INST 2 71 72 struct resource_funcs { 73 enum engine_id (*get_preferred_eng_id_dpia)(unsigned int dpia_index); 74 void (*destroy)(struct resource_pool **pool); 75 void (*link_init)(struct dc_link *link); 76 struct panel_cntl*(*panel_cntl_create)( 77 const struct panel_cntl_init_data *panel_cntl_init_data); 78 struct link_encoder *(*link_enc_create)( 79 struct dc_context *ctx, 80 const struct encoder_init_data *init); 81 /* Create a minimal link encoder object with no dc_link object 82 * associated with it. */ 83 struct link_encoder *(*link_enc_create_minimal)(struct dc_context *ctx, enum engine_id eng_id); 84 enum dc_status (*validate_bandwidth)( 85 struct dc *dc, 86 struct dc_state *context, 87 enum dc_validate_mode validate_mode); 88 void (*calculate_wm_and_dlg)( 89 struct dc *dc, struct dc_state *context, 90 display_e2e_pipe_params_st *pipes, 91 int pipe_cnt, 92 int vlevel); 93 void (*update_soc_for_wm_a)( 94 struct dc *dc, struct dc_state *context); 95 96 unsigned int (*calculate_mall_ways_from_bytes)( 97 const struct dc *dc, 98 unsigned int total_size_in_mall_bytes); 99 void (*prepare_mcache_programming)( 100 struct dc *dc, 101 struct dc_state *context); 102 /** 103 * @populate_dml_pipes - Populate pipe data struct 104 * 105 * Returns: 106 * Total of pipes available in the specific ASIC. 107 */ 108 int (*populate_dml_pipes)( 109 struct dc *dc, 110 struct dc_state *context, 111 display_e2e_pipe_params_st *pipes, 112 enum dc_validate_mode validate_mode); 113 114 /* 115 * Algorithm for assigning available link encoders to links. 116 * 117 * Update link_enc_assignments table and link_enc_avail list accordingly in 118 * struct resource_context. 119 */ 120 void (*link_encs_assign)( 121 struct dc *dc, 122 struct dc_state *state, 123 struct dc_stream_state *streams[], 124 uint8_t stream_count); 125 /* 126 * Unassign a link encoder from a stream. 127 * 128 * Update link_enc_assignments table and link_enc_avail list accordingly in 129 * struct resource_context. 130 */ 131 void (*link_enc_unassign)( 132 struct dc_state *state, 133 struct dc_stream_state *stream); 134 135 enum dc_status (*validate_global)( 136 struct dc *dc, 137 struct dc_state *context); 138 139 struct pipe_ctx *(*acquire_free_pipe_as_secondary_dpp_pipe)( 140 const struct dc_state *cur_ctx, 141 struct dc_state *new_ctx, 142 const struct resource_pool *pool, 143 const struct pipe_ctx *opp_head_pipe); 144 145 struct pipe_ctx *(*acquire_free_pipe_as_secondary_opp_head)( 146 const struct dc_state *cur_ctx, 147 struct dc_state *new_ctx, 148 const struct resource_pool *pool, 149 const struct pipe_ctx *otg_master); 150 151 void (*release_pipe)(struct dc_state *context, 152 struct pipe_ctx *pipe, 153 const struct resource_pool *pool); 154 155 enum dc_status (*validate_plane)( 156 const struct dc_plane_state *plane_state, 157 struct dc_caps *caps); 158 159 enum dc_status (*add_stream_to_ctx)( 160 struct dc *dc, 161 struct dc_state *new_ctx, 162 struct dc_stream_state *dc_stream); 163 164 enum dc_status (*remove_stream_from_ctx)( 165 struct dc *dc, 166 struct dc_state *new_ctx, 167 struct dc_stream_state *stream); 168 169 enum dc_status (*patch_unknown_plane_state)( 170 struct dc_plane_state *plane_state); 171 172 struct stream_encoder *(*find_first_free_match_stream_enc_for_link)( 173 struct resource_context *res_ctx, 174 const struct resource_pool *pool, 175 struct dc_stream_state *stream); 176 177 void (*populate_dml_writeback_from_context)( 178 struct dc *dc, 179 struct resource_context *res_ctx, 180 display_e2e_pipe_params_st *pipes); 181 182 void (*set_mcif_arb_params)( 183 struct dc *dc, 184 struct dc_state *context, 185 display_e2e_pipe_params_st *pipes, 186 int pipe_cnt); 187 188 void (*update_bw_bounding_box)( 189 struct dc *dc, 190 struct clk_bw_params *bw_params); 191 bool (*acquire_post_bldn_3dlut)( 192 struct resource_context *res_ctx, 193 const struct resource_pool *pool, 194 int mpcc_id, 195 struct dc_3dlut **lut, 196 struct dc_transfer_func **shaper); 197 198 bool (*release_post_bldn_3dlut)( 199 struct resource_context *res_ctx, 200 const struct resource_pool *pool, 201 struct dc_3dlut **lut, 202 struct dc_transfer_func **shaper); 203 204 enum dc_status (*add_dsc_to_stream_resource)( 205 struct dc *dc, struct dc_state *state, 206 struct dc_stream_state *stream); 207 208 void (*add_phantom_pipes)( 209 struct dc *dc, 210 struct dc_state *context, 211 display_e2e_pipe_params_st *pipes, 212 unsigned int pipe_cnt, 213 unsigned int index); 214 215 void (*get_panel_config_defaults)(struct dc_panel_config *panel_config); 216 void (*build_pipe_pix_clk_params)(struct pipe_ctx *pipe_ctx); 217 /* 218 * Get indicator of power from a context that went through full validation 219 */ 220 int (*get_power_profile)(const struct dc_state *context); 221 unsigned int (*get_det_buffer_size)(const struct dc_state *context); 222 unsigned int (*get_vstartup_for_pipe)(struct pipe_ctx *pipe_ctx); 223 unsigned int (*get_max_hw_cursor_size)(const struct dc *dc, 224 struct dc_state *state, 225 const struct dc_stream_state *stream); 226 bool (*program_mcache_pipe_config)(struct dc_state *context, 227 const struct dc_mcache_params *mcache_params); 228 enum dc_status (*update_dc_state_for_encoder_switch)(struct dc_link *link, 229 struct dc_link_settings *link_setting, 230 uint8_t pipe_count, 231 struct pipe_ctx *pipes, 232 struct audio_output *audio_output); 233 }; 234 235 struct audio_support{ 236 bool dp_audio; 237 bool hdmi_audio_on_dongle; 238 bool hdmi_audio_native; 239 }; 240 241 #define NO_UNDERLAY_PIPE -1 242 243 struct resource_pool { 244 struct mem_input *mis[MAX_PIPES]; 245 struct hubp *hubps[MAX_PIPES]; 246 struct input_pixel_processor *ipps[MAX_PIPES]; 247 struct transform *transforms[MAX_PIPES]; 248 struct dpp *dpps[MAX_PIPES]; 249 struct output_pixel_processor *opps[MAX_PIPES]; 250 struct timing_generator *timing_generators[MAX_PIPES]; 251 struct stream_encoder *stream_enc[MAX_PIPES * 2]; 252 struct hubbub *hubbub; 253 struct mpc *mpc; 254 struct pp_smu_funcs *pp_smu; 255 struct dce_aux *engines[MAX_PIPES]; 256 struct dce_i2c_hw *hw_i2cs[MAX_PIPES]; 257 struct dce_i2c_sw *sw_i2cs[MAX_PIPES]; 258 bool i2c_hw_buffer_in_use; 259 260 struct dwbc *dwbc[MAX_DWB_PIPES]; 261 struct mcif_wb *mcif_wb[MAX_DWB_PIPES]; 262 struct { 263 unsigned int gsl_0:1; 264 unsigned int gsl_1:1; 265 unsigned int gsl_2:1; 266 } gsl_groups; 267 268 struct display_stream_compressor *dscs[MAX_PIPES]; 269 270 unsigned int pipe_count; 271 unsigned int underlay_pipe_index; 272 unsigned int stream_enc_count; 273 274 /* An array for accessing the link encoder objects that have been created. 275 * Index in array corresponds to engine ID - viz. 0: ENGINE_ID_DIGA 276 */ 277 struct link_encoder *link_encoders[MAX_DIG_LINK_ENCODERS]; 278 /* Number of DIG link encoder objects created - i.e. number of valid 279 * entries in link_encoders array. 280 */ 281 unsigned int dig_link_enc_count; 282 /* Number of USB4 DPIA (DisplayPort Input Adapter) link objects created.*/ 283 unsigned int usb4_dpia_count; 284 285 unsigned int hpo_dp_stream_enc_count; 286 struct hpo_dp_stream_encoder *hpo_dp_stream_enc[MAX_HPO_DP2_ENCODERS]; 287 unsigned int hpo_dp_link_enc_count; 288 struct hpo_dp_link_encoder *hpo_dp_link_enc[MAX_HPO_DP2_LINK_ENCODERS]; 289 struct dc_3dlut *mpc_lut[MAX_PIPES]; 290 struct dc_transfer_func *mpc_shaper[MAX_PIPES]; 291 struct dc_rmcm_3dlut rmcm_3dlut[MAX_RMCM_INST]; 292 293 struct { 294 unsigned int xtalin_clock_inKhz; 295 unsigned int dccg_ref_clock_inKhz; 296 unsigned int dchub_ref_clock_inKhz; 297 } ref_clocks; 298 unsigned int timing_generator_count; 299 unsigned int mpcc_count; 300 301 unsigned int writeback_pipe_count; 302 /* 303 * reserved clock source for DP 304 */ 305 struct clock_source *dp_clock_source; 306 307 struct clock_source *clock_sources[MAX_CLOCK_SOURCES]; 308 unsigned int clk_src_count; 309 310 struct audio *audios[MAX_AUDIOS]; 311 unsigned int audio_count; 312 struct audio_support audio_support; 313 314 struct dccg *dccg; 315 struct pg_cntl *pg_cntl; 316 struct irq_service *irqs; 317 318 struct abm *abm; 319 struct dmcu *dmcu; 320 struct dmub_psr *psr; 321 struct dmub_replay *replay; 322 323 struct abm *multiple_abms[MAX_PIPES]; 324 325 const struct resource_funcs *funcs; 326 const struct resource_caps *res_cap; 327 328 struct ddc_service *oem_device; 329 }; 330 331 struct dcn_fe_bandwidth { 332 int dppclk_khz; 333 334 }; 335 336 /* Parameters needed to call set_disp_pattern_generator */ 337 struct test_pattern_params { 338 enum controller_dp_test_pattern test_pattern; 339 enum controller_dp_color_space color_space; 340 enum dc_color_depth color_depth; 341 int width; 342 int height; 343 int offset; 344 }; 345 346 struct stream_resource { 347 struct output_pixel_processor *opp; 348 struct display_stream_compressor *dsc; 349 struct timing_generator *tg; 350 struct stream_encoder *stream_enc; 351 struct hpo_dp_stream_encoder *hpo_dp_stream_enc; 352 struct audio *audio; 353 354 struct pixel_clk_params pix_clk_params; 355 struct encoder_info_frame encoder_info_frame; 356 357 struct abm *abm; 358 /* There are only (num_pipes+1)/2 groups. 0 means unassigned, 359 * otherwise it's using group number 'gsl_group-1' 360 */ 361 uint8_t gsl_group; 362 363 struct test_pattern_params test_pattern_params; 364 }; 365 366 struct plane_resource { 367 /* scl_data is scratch space required to program a plane */ 368 struct scaler_data scl_data; 369 /* Below pointers to hw objects are required to enable the plane */ 370 /* spl_in and spl_out are the input and output structures for SPL 371 * which are required when using Scaler Programming Library 372 * these are scratch spaces needed when programming a plane 373 */ 374 struct spl_in spl_in; 375 struct spl_out spl_out; 376 /* Below pointers to hw objects are required to enable the plane */ 377 struct hubp *hubp; 378 struct mem_input *mi; 379 struct input_pixel_processor *ipp; 380 struct transform *xfm; 381 struct dpp *dpp; 382 uint8_t mpcc_inst; 383 384 struct dcn_fe_bandwidth bw; 385 }; 386 387 #define LINK_RES_HPO_DP_REC_MAP__MASK 0xFFFF 388 #define LINK_RES_HPO_DP_REC_MAP__SHIFT 0 389 390 /* all mappable hardware resources used to enable a link */ 391 struct link_resource { 392 struct link_encoder *dio_link_enc; 393 struct hpo_dp_link_encoder *hpo_dp_link_enc; 394 }; 395 396 struct link_config { 397 struct dc_link_settings dp_link_settings; 398 struct dc_tunnel_settings dp_tunnel_settings; 399 }; 400 401 union pipe_update_flags { 402 struct { 403 uint32_t enable : 1; 404 uint32_t disable : 1; 405 uint32_t odm : 1; 406 uint32_t global_sync : 1; 407 uint32_t opp_changed : 1; 408 uint32_t tg_changed : 1; 409 uint32_t mpcc : 1; 410 uint32_t dppclk : 1; 411 uint32_t hubp_interdependent : 1; 412 uint32_t hubp_rq_dlg_ttu : 1; 413 uint32_t gamut_remap : 1; 414 uint32_t scaler : 1; 415 uint32_t viewport : 1; 416 uint32_t plane_changed : 1; 417 uint32_t det_size : 1; 418 uint32_t unbounded_req : 1; 419 uint32_t test_pattern_changed : 1; 420 } bits; 421 uint32_t raw; 422 }; 423 424 struct pixel_rate_divider { 425 uint32_t div_factor1; 426 uint32_t div_factor2; 427 }; 428 429 enum p_state_switch_method { 430 P_STATE_UNKNOWN = 0, 431 P_STATE_V_BLANK = 1, 432 P_STATE_FPO, 433 P_STATE_V_ACTIVE, 434 P_STATE_SUB_VP, 435 P_STATE_DRR_SUB_VP, 436 P_STATE_V_BLANK_SUB_VP 437 }; 438 439 struct pipe_ctx { 440 struct dc_plane_state *plane_state; 441 struct dc_stream_state *stream; 442 443 struct plane_resource plane_res; 444 445 /** 446 * @stream_res: Reference to DCN resource components such OPP and DSC. 447 */ 448 struct stream_resource stream_res; 449 struct link_resource link_res; 450 451 struct clock_source *clock_source; 452 453 struct pll_settings pll_settings; 454 455 /** 456 * @link_config: 457 * 458 * link config records software decision for what link config should be 459 * enabled given current link capability and stream during hw resource 460 * mapping. This is to decouple the dependency on link capability during 461 * dc commit or update. 462 */ 463 struct link_config link_config; 464 465 uint8_t pipe_idx; 466 uint8_t pipe_idx_syncd; 467 468 struct pipe_ctx *top_pipe; 469 struct pipe_ctx *bottom_pipe; 470 struct pipe_ctx *next_odm_pipe; 471 struct pipe_ctx *prev_odm_pipe; 472 473 struct _vcs_dpi_display_dlg_regs_st dlg_regs; 474 struct _vcs_dpi_display_ttu_regs_st ttu_regs; 475 struct _vcs_dpi_display_rq_regs_st rq_regs; 476 struct _vcs_dpi_display_pipe_dest_params_st pipe_dlg_param; 477 struct _vcs_dpi_display_rq_params_st dml_rq_param; 478 struct _vcs_dpi_display_dlg_sys_params_st dml_dlg_sys_param; 479 struct _vcs_dpi_display_e2e_pipe_params_st dml_input; 480 int det_buffer_size_kb; 481 bool unbounded_req; 482 unsigned int surface_size_in_mall_bytes; 483 struct dml2_dchub_per_pipe_register_set hubp_regs; 484 struct dml2_hubp_pipe_mcache_regs mcache_regs; 485 union dml2_global_sync_programming global_sync; 486 487 struct dwbc *dwbc; 488 struct mcif_wb *mcif_wb; 489 union pipe_update_flags update_flags; 490 enum p_state_switch_method p_state_type; 491 struct tg_color visual_confirm_color; 492 bool has_vactive_margin; 493 /* subvp_index: only valid if the pipe is a SUBVP_MAIN*/ 494 uint8_t subvp_index; 495 struct pixel_rate_divider pixel_rate_divider; 496 /* pixels borrowed from hblank to hactive */ 497 uint8_t hblank_borrow; 498 /* next vupdate */ 499 uint32_t next_vupdate; 500 uint32_t wait_frame_count; 501 bool wait_is_required; 502 }; 503 504 /* Data used for dynamic link encoder assignment. 505 * Tracks current and future assignments; available link encoders; 506 * and mode of operation (whether to use current or future assignments). 507 */ 508 struct link_enc_cfg_context { 509 enum link_enc_cfg_mode mode; 510 struct link_enc_assignment link_enc_assignments[MAX_PIPES]; 511 enum engine_id link_enc_avail[MAX_DIG_LINK_ENCODERS]; 512 struct link_enc_assignment transient_assignments[MAX_PIPES]; 513 }; 514 515 struct resource_context { 516 struct pipe_ctx pipe_ctx[MAX_PIPES]; 517 bool is_stream_enc_acquired[MAX_PIPES * 2]; 518 bool is_audio_acquired[MAX_PIPES]; 519 uint8_t clock_source_ref_count[MAX_CLOCK_SOURCES]; 520 uint8_t dp_clock_source_ref_count; 521 bool is_dsc_acquired[MAX_PIPES]; 522 struct link_enc_cfg_context link_enc_cfg_ctx; 523 unsigned int dio_link_enc_to_link_idx[MAX_DIG_LINK_ENCODERS]; 524 int dio_link_enc_ref_cnts[MAX_DIG_LINK_ENCODERS]; 525 bool is_hpo_dp_stream_enc_acquired[MAX_HPO_DP2_ENCODERS]; 526 unsigned int hpo_dp_link_enc_to_link_idx[MAX_HPO_DP2_LINK_ENCODERS]; 527 int hpo_dp_link_enc_ref_cnts[MAX_HPO_DP2_LINK_ENCODERS]; 528 bool is_mpc_3dlut_acquired[MAX_PIPES]; 529 /* used to build scalar data in dml2 and for edp backlight programming */ 530 struct pipe_ctx temp_pipe; 531 }; 532 533 struct dce_bw_output { 534 bool cpuc_state_change_enable; 535 bool cpup_state_change_enable; 536 bool stutter_mode_enable; 537 bool nbp_state_change_enable; 538 bool all_displays_in_sync; 539 struct dce_watermarks urgent_wm_ns[MAX_PIPES]; 540 struct dce_watermarks stutter_exit_wm_ns[MAX_PIPES]; 541 struct dce_watermarks stutter_entry_wm_ns[MAX_PIPES]; 542 struct dce_watermarks nbp_state_change_wm_ns[MAX_PIPES]; 543 int sclk_khz; 544 int sclk_deep_sleep_khz; 545 int yclk_khz; 546 int dispclk_khz; 547 int blackout_recovery_time_us; 548 }; 549 550 struct dcn_bw_writeback { 551 struct mcif_arb_params mcif_wb_arb[MAX_DWB_PIPES]; 552 }; 553 554 struct dcn_bw_output { 555 struct dc_clocks clk; 556 union dcn_watermark_set watermarks; 557 struct dcn_bw_writeback bw_writeback; 558 int compbuf_size_kb; 559 unsigned int mall_ss_size_bytes; 560 unsigned int mall_ss_psr_active_size_bytes; 561 unsigned int mall_subvp_size_bytes; 562 unsigned int legacy_svp_drr_stream_index; 563 bool legacy_svp_drr_stream_index_valid; 564 struct dml2_mcache_surface_allocation mcache_allocations[DML2_MAX_PLANES]; 565 struct dmub_cmd_fams2_global_config fams2_global_config; 566 union dmub_cmd_fams2_config fams2_stream_base_params[DML2_MAX_PLANES]; 567 union { 568 union dmub_cmd_fams2_config fams2_stream_sub_params[DML2_MAX_PLANES]; 569 union dmub_fams2_stream_static_sub_state_v2 fams2_stream_sub_params_v2[DML2_MAX_PLANES]; 570 }; 571 struct dml2_display_arb_regs arb_regs; 572 }; 573 574 union bw_output { 575 struct dcn_bw_output dcn; 576 struct dce_bw_output dce; 577 }; 578 579 struct bw_context { 580 union bw_output bw; 581 struct display_mode_lib dml; 582 struct dml2_context *dml2; 583 struct dml2_context *dml2_dc_power_source; 584 }; 585 586 struct dc_dmub_cmd { 587 union dmub_rb_cmd dmub_cmd; 588 enum dm_dmub_wait_type wait_type; 589 }; 590 591 /** 592 * struct dc_state - The full description of a state requested by users 593 */ 594 struct dc_state { 595 /** 596 * @streams: Stream state properties 597 */ 598 struct dc_stream_state *streams[MAX_PIPES]; 599 600 /** 601 * @stream_status: Planes status on a given stream 602 */ 603 struct dc_stream_status stream_status[MAX_PIPES]; 604 /** 605 * @phantom_streams: Stream state properties for phantoms 606 */ 607 struct dc_stream_state *phantom_streams[MAX_PHANTOM_PIPES]; 608 /** 609 * @phantom_planes: Planes state properties for phantoms 610 */ 611 struct dc_plane_state *phantom_planes[MAX_PHANTOM_PIPES]; 612 613 /** 614 * @stream_count: Total of streams in use 615 */ 616 uint8_t stream_count; 617 uint8_t stream_mask; 618 619 /** 620 * @stream_count: Total phantom streams in use 621 */ 622 uint8_t phantom_stream_count; 623 /** 624 * @stream_count: Total phantom planes in use 625 */ 626 uint8_t phantom_plane_count; 627 /** 628 * @res_ctx: Persistent state of resources 629 */ 630 struct resource_context res_ctx; 631 632 /** 633 * @pp_display_cfg: PowerPlay clocks and settings 634 * Note: this is a big struct, do *not* put on stack! 635 */ 636 struct dm_pp_display_configuration pp_display_cfg; 637 638 /** 639 * @dcn_bw_vars: non-stack memory to support bandwidth calculations 640 * Note: this is a big struct, do *not* put on stack! 641 */ 642 struct dcn_bw_internal_vars dcn_bw_vars; 643 644 struct clk_mgr *clk_mgr; 645 646 /** 647 * @bw_ctx: The output from bandwidth and watermark calculations and the DML 648 * 649 * Each context must have its own instance of VBA, and in order to 650 * initialize and obtain IP and SOC, the base DML instance from DC is 651 * initially copied into every context. 652 */ 653 struct bw_context bw_ctx; 654 655 struct block_sequence block_sequence[MAX_HWSS_BLOCK_SEQUENCE_SIZE]; 656 unsigned int block_sequence_steps; 657 struct dc_dmub_cmd dc_dmub_cmd[10]; 658 unsigned int dmub_cmd_count; 659 660 /** 661 * @refcount: refcount reference 662 * 663 * Notice that dc_state is used around the code to capture the current 664 * context, so we need to pass it everywhere. That's why we want to use 665 * kref in this struct. 666 */ 667 struct kref refcount; 668 669 struct { 670 unsigned int stutter_period_us; 671 } perf_params; 672 673 enum dc_power_source_type power_source; 674 }; 675 676 struct replay_context { 677 /* ddc line */ 678 enum channel_id aux_inst; 679 /* Transmitter id */ 680 enum transmitter digbe_inst; 681 /* Engine Id is used for Dig Be source select */ 682 enum engine_id digfe_inst; 683 /* Controller Id used for Dig Fe source select */ 684 enum controller_id controllerId; 685 unsigned int line_time_in_ns; 686 }; 687 688 enum dc_replay_enable { 689 DC_REPLAY_DISABLE = 0, 690 DC_REPLAY_ENABLE = 1, 691 }; 692 693 struct dc_bounding_box_max_clk { 694 int max_dcfclk_mhz; 695 int max_dispclk_mhz; 696 int max_dppclk_mhz; 697 int max_phyclk_mhz; 698 }; 699 700 #endif /* _CORE_TYPES_H_ */ 701