1 /* SPDX-License-Identifier: GPL-2.0-or-later */
2
3 #ifndef BLOCK_UFS_H
4 #define BLOCK_UFS_H
5
6 #include "hw/registerfields.h"
7
8 typedef struct QEMU_PACKED UfsReg {
9 uint32_t cap;
10 uint32_t mcqcap;
11 uint32_t ver;
12 uint32_t rsvd1;
13 uint32_t hcpid;
14 uint32_t hcmid;
15 uint32_t ahit;
16 uint32_t rsvd2;
17 uint32_t is;
18 uint32_t ie;
19 uint32_t rsvd3[2];
20 uint32_t hcs;
21 uint32_t hce;
22 uint32_t uecpa;
23 uint32_t uecdl;
24 uint32_t uecn;
25 uint32_t uect;
26 uint32_t uecdme;
27 uint32_t utriacr;
28 uint32_t utrlba;
29 uint32_t utrlbau;
30 uint32_t utrldbr;
31 uint32_t utrlclr;
32 uint32_t utrlrsr;
33 uint32_t utrlcnr;
34 uint32_t rsvd4[2];
35 uint32_t utmrlba;
36 uint32_t utmrlbau;
37 uint32_t utmrldbr;
38 uint32_t utmrlclr;
39 uint32_t utmrlrsr;
40 uint32_t rsvd5[3];
41 uint32_t uiccmd;
42 uint32_t ucmdarg1;
43 uint32_t ucmdarg2;
44 uint32_t ucmdarg3;
45 uint32_t rsvd6[4];
46 uint32_t rsvd7[4];
47 uint32_t rsvd8[16];
48 uint32_t ccap;
49 uint32_t rsvd9[127];
50 uint32_t config;
51 uint32_t rsvd10[3];
52 uint32_t rsvd11[28];
53 uint32_t mcqconfig;
54 uint32_t esilba;
55 uint32_t esiuba;
56 } UfsReg;
57
58 REG32(CAP, offsetof(UfsReg, cap))
59 FIELD(CAP, NUTRS, 0, 5)
60 FIELD(CAP, RTT, 8, 8)
61 FIELD(CAP, NUTMRS, 16, 3)
62 FIELD(CAP, AUTOH8, 23, 1)
63 FIELD(CAP, 64AS, 24, 1)
64 FIELD(CAP, OODDS, 25, 1)
65 FIELD(CAP, UICDMETMS, 26, 1)
66 FIELD(CAP, CS, 28, 1)
67 FIELD(CAP, LSDBS, 29, 1)
68 FIELD(CAP, MCQS, 30, 1)
69 REG32(MCQCAP, offsetof(UfsReg, mcqcap))
70 FIELD(MCQCAP, MAXQ, 0, 8)
71 FIELD(MCQCAP, SP, 8, 1)
72 FIELD(MCQCAP, RRP, 9, 1)
73 FIELD(MCQCAP, EIS, 10, 1)
74 FIELD(MCQCAP, QCFGPTR, 16, 8)
75 FIELD(MCQCAP, MIAG, 24, 8)
76 REG32(VER, offsetof(UfsReg, ver))
77 REG32(HCPID, offsetof(UfsReg, hcpid))
78 REG32(HCMID, offsetof(UfsReg, hcmid))
79 REG32(AHIT, offsetof(UfsReg, ahit))
80 REG32(IS, offsetof(UfsReg, is))
81 FIELD(IS, UTRCS, 0, 1)
82 FIELD(IS, UDEPRI, 1, 1)
83 FIELD(IS, UE, 2, 1)
84 FIELD(IS, UTMS, 3, 1)
85 FIELD(IS, UPMS, 4, 1)
86 FIELD(IS, UHXS, 5, 1)
87 FIELD(IS, UHES, 6, 1)
88 FIELD(IS, ULLS, 7, 1)
89 FIELD(IS, ULSS, 8, 1)
90 FIELD(IS, UTMRCS, 9, 1)
91 FIELD(IS, UCCS, 10, 1)
92 FIELD(IS, DFES, 11, 1)
93 FIELD(IS, UTPES, 12, 1)
94 FIELD(IS, HCFES, 16, 1)
95 FIELD(IS, SBFES, 17, 1)
96 FIELD(IS, CEFES, 18, 1)
97 FIELD(IS, CQES, 20, 1)
98 REG32(IE, offsetof(UfsReg, ie))
99 FIELD(IE, UTRCE, 0, 1)
100 FIELD(IE, UDEPRIE, 1, 1)
101 FIELD(IE, UEE, 2, 1)
102 FIELD(IE, UTMSE, 3, 1)
103 FIELD(IE, UPMSE, 4, 1)
104 FIELD(IE, UHXSE, 5, 1)
105 FIELD(IE, UHESE, 6, 1)
106 FIELD(IE, ULLSE, 7, 1)
107 FIELD(IE, ULSSE, 8, 1)
108 FIELD(IE, UTMRCE, 9, 1)
109 FIELD(IE, UCCE, 10, 1)
110 FIELD(IE, DFEE, 11, 1)
111 FIELD(IE, UTPEE, 12, 1)
112 FIELD(IE, HCFEE, 16, 1)
113 FIELD(IE, SBFEE, 17, 1)
114 FIELD(IE, CEFEE, 18, 1)
115 FIELD(IE, CQEE, 20, 1)
116 REG32(HCS, offsetof(UfsReg, hcs))
117 FIELD(HCS, DP, 0, 1)
118 FIELD(HCS, UTRLRDY, 1, 1)
119 FIELD(HCS, UTMRLRDY, 2, 1)
120 FIELD(HCS, UCRDY, 3, 1)
121 FIELD(HCS, UPMCRS, 8, 3)
122 REG32(HCE, offsetof(UfsReg, hce))
123 FIELD(HCE, HCE, 0, 1)
124 FIELD(HCE, CGE, 1, 1)
125 REG32(UECPA, offsetof(UfsReg, uecpa))
126 REG32(UECDL, offsetof(UfsReg, uecdl))
127 REG32(UECN, offsetof(UfsReg, uecn))
128 REG32(UECT, offsetof(UfsReg, uect))
129 REG32(UECDME, offsetof(UfsReg, uecdme))
130 REG32(UTRIACR, offsetof(UfsReg, utriacr))
131 REG32(UTRLBA, offsetof(UfsReg, utrlba))
132 FIELD(UTRLBA, UTRLBA, 10, 22)
133 REG32(UTRLBAU, offsetof(UfsReg, utrlbau))
134 REG32(UTRLDBR, offsetof(UfsReg, utrldbr))
135 REG32(UTRLCLR, offsetof(UfsReg, utrlclr))
136 REG32(UTRLRSR, offsetof(UfsReg, utrlrsr))
137 REG32(UTRLCNR, offsetof(UfsReg, utrlcnr))
138 REG32(UTMRLBA, offsetof(UfsReg, utmrlba))
139 FIELD(UTMRLBA, UTMRLBA, 10, 22)
140 REG32(UTMRLBAU, offsetof(UfsReg, utmrlbau))
141 REG32(UTMRLDBR, offsetof(UfsReg, utmrldbr))
142 REG32(UTMRLCLR, offsetof(UfsReg, utmrlclr))
143 REG32(UTMRLRSR, offsetof(UfsReg, utmrlrsr))
144 REG32(UICCMD, offsetof(UfsReg, uiccmd))
145 REG32(UCMDARG1, offsetof(UfsReg, ucmdarg1))
146 REG32(UCMDARG2, offsetof(UfsReg, ucmdarg2))
147 REG32(UCMDARG3, offsetof(UfsReg, ucmdarg3))
148 REG32(CCAP, offsetof(UfsReg, ccap))
149 REG32(CONFIG, offsetof(UfsReg, config))
150 FIELD(CONFIG, QT, 0, 1)
151 REG32(MCQCONFIG, offsetof(UfsReg, mcqconfig))
152 FIELD(MCQCONFIG, MAC, 8, 8)
153
154 #define UFS_INTR_MASK \
155 ((1 << R_IS_CQES_SHIFT) | \
156 (1 << R_IS_CEFES_SHIFT) | (1 << R_IS_SBFES_SHIFT) | \
157 (1 << R_IS_HCFES_SHIFT) | (1 << R_IS_UTPES_SHIFT) | \
158 (1 << R_IS_DFES_SHIFT) | (1 << R_IS_UCCS_SHIFT) | \
159 (1 << R_IS_UTMRCS_SHIFT) | (1 << R_IS_ULSS_SHIFT) | \
160 (1 << R_IS_ULLS_SHIFT) | (1 << R_IS_UHES_SHIFT) | \
161 (1 << R_IS_UHXS_SHIFT) | (1 << R_IS_UPMS_SHIFT) | \
162 (1 << R_IS_UTMS_SHIFT) | (1 << R_IS_UE_SHIFT) | \
163 (1 << R_IS_UDEPRI_SHIFT) | (1 << R_IS_UTRCS_SHIFT))
164
165 #define UFS_UPIU_HEADER_TRANSACTION_TYPE_SHIFT 24
166 #define UFS_UPIU_HEADER_TRANSACTION_TYPE_MASK 0xff
167 #define UFS_UPIU_HEADER_TRANSACTION_TYPE(dword0) \
168 ((be32_to_cpu(dword0) >> UFS_UPIU_HEADER_TRANSACTION_TYPE_SHIFT) & \
169 UFS_UPIU_HEADER_TRANSACTION_TYPE_MASK)
170
171 #define UFS_UPIU_HEADER_QUERY_FUNC_SHIFT 16
172 #define UFS_UPIU_HEADER_QUERY_FUNC_MASK 0xff
173 #define UFS_UPIU_HEADER_QUERY_FUNC(dword1) \
174 ((be32_to_cpu(dword1) >> UFS_UPIU_HEADER_QUERY_FUNC_SHIFT) & \
175 UFS_UPIU_HEADER_QUERY_FUNC_MASK)
176
177 #define UFS_UPIU_HEADER_DATA_SEGMENT_LENGTH_SHIFT 0
178 #define UFS_UPIU_HEADER_DATA_SEGMENT_LENGTH_MASK 0xffff
179 #define UFS_UPIU_HEADER_DATA_SEGMENT_LENGTH(dword2) \
180 ((be32_to_cpu(dword2) >> UFS_UPIU_HEADER_DATA_SEGMENT_LENGTH_SHIFT) & \
181 UFS_UPIU_HEADER_DATA_SEGMENT_LENGTH_MASK)
182
183 typedef struct QEMU_PACKED UfsMcqReg {
184 uint32_t sqattr;
185 uint32_t sqlba;
186 uint32_t squba;
187 uint32_t sqdao;
188 uint32_t sqisao;
189 uint32_t sqcfg;
190 uint32_t rsvd0[2];
191 uint32_t cqattr;
192 uint32_t cqlba;
193 uint32_t cquba;
194 uint32_t cqdao;
195 uint32_t cqisao;
196 uint32_t cqcfg;
197 uint32_t rsvd1[2];
198 } UfsMcqReg;
199
200 REG32(SQATTR, offsetof(UfsMcqReg, sqattr))
201 FIELD(SQATTR, SIZE, 0, 16)
202 FIELD(SQATTR, CQID, 16, 8)
203 FIELD(SQATTR, SQPL, 28, 3)
204 FIELD(SQATTR, SQEN, 31, 1)
205 REG32(SQLBA, offsetof(UfsMcqReg, sqlba))
206 REG32(SQUBA, offsetof(UfsMcqReg, squba))
207 REG32(SQDAO, offsetof(UfsMcqReg, sqdao))
208 REG32(SQISAO, offsetof(UfsMcqReg, sqisao))
209 REG32(SQCFG, offsetof(UfsMcqReg, sqcfg))
210 REG32(CQATTR, offsetof(UfsMcqReg, cqattr))
211 FIELD(CQATTR, SIZE, 0, 16)
212 FIELD(CQATTR, CQEN, 31, 1)
213 REG32(CQLBA, offsetof(UfsMcqReg, cqlba))
214 REG32(CQUBA, offsetof(UfsMcqReg, cquba))
215 REG32(CQDAO, offsetof(UfsMcqReg, cqdao))
216 REG32(CQISAO, offsetof(UfsMcqReg, cqisao))
217 REG32(CQCFG, offsetof(UfsMcqReg, cqcfg))
218
219 typedef struct QEMU_PACKED UfsMcqSqReg {
220 uint32_t hp;
221 uint32_t tp;
222 uint32_t rtc;
223 uint32_t cti;
224 uint32_t rts;
225 } UfsMcqSqReg;
226
227 typedef struct QEMU_PACKED UfsMcqCqReg {
228 uint32_t hp;
229 uint32_t tp;
230 } UfsMcqCqReg;
231
232 typedef struct QEMU_PACKED UfsMcqSqIntReg {
233 uint32_t is;
234 uint32_t ie;
235 } UfsMcqSqIntReg;
236
237 typedef struct QEMU_PACKED UfsMcqCqIntReg {
238 uint32_t is;
239 uint32_t ie;
240 uint32_t iacr;
241 } UfsMcqCqIntReg;
242
243 REG32(CQIS, offsetof(UfsMcqCqIntReg, is))
244 FIELD(CQIS, TEPS, 0, 1)
245
246 /*
247 * Provide MCQ Operation & Runtime Registers as a contiguous addressed
248 * registers for the simplicity.
249 * DAO(Doorbell Address Offset) and ISAO(Interrupt Status Register Address
250 * Offset) registers should be properly configured with the following
251 * structure.
252 */
253 #define UFS_MCQ_OPR_START 0x1000
254 typedef struct QEMU_PACKED UfsMcqOpReg {
255 UfsMcqSqReg sq;
256 UfsMcqSqIntReg sq_int;
257 UfsMcqCqReg cq;
258 UfsMcqCqIntReg cq_int;
259 } UfsMcqOpReg;
260
261 typedef struct QEMU_PACKED DeviceDescriptor {
262 uint8_t length;
263 uint8_t descriptor_idn;
264 uint8_t device;
265 uint8_t device_class;
266 uint8_t device_sub_class;
267 uint8_t protocol;
268 uint8_t number_lu;
269 uint8_t number_wlu;
270 uint8_t boot_enable;
271 uint8_t descr_access_en;
272 uint8_t init_power_mode;
273 uint8_t high_priority_lun;
274 uint8_t secure_removal_type;
275 uint8_t security_lu;
276 uint8_t background_ops_term_lat;
277 uint8_t init_active_icc_level;
278 uint16_t spec_version;
279 uint16_t manufacture_date;
280 uint8_t manufacturer_name;
281 uint8_t product_name;
282 uint8_t serial_number;
283 uint8_t oem_id;
284 uint16_t manufacturer_id;
285 uint8_t ud_0_base_offset;
286 uint8_t ud_config_p_length;
287 uint8_t device_rtt_cap;
288 uint16_t periodic_rtc_update;
289 uint8_t ufs_features_support;
290 uint8_t ffu_timeout;
291 uint8_t queue_depth;
292 uint16_t device_version;
293 uint8_t num_secure_wp_area;
294 uint32_t psa_max_data_size;
295 uint8_t psa_state_timeout;
296 uint8_t product_revision_level;
297 uint8_t reserved[36];
298 uint32_t extended_ufs_features_support;
299 uint8_t write_booster_buffer_preserve_user_space_en;
300 uint8_t write_booster_buffer_type;
301 uint32_t num_shared_write_booster_buffer_alloc_units;
302 } DeviceDescriptor;
303
304 typedef struct QEMU_PACKED GeometryDescriptor {
305 uint8_t length;
306 uint8_t descriptor_idn;
307 uint8_t media_technology;
308 uint8_t reserved;
309 uint64_t total_raw_device_capacity;
310 uint8_t max_number_lu;
311 uint32_t segment_size;
312 uint8_t allocation_unit_size;
313 uint8_t min_addr_block_size;
314 uint8_t optimal_read_block_size;
315 uint8_t optimal_write_block_size;
316 uint8_t max_in_buffer_size;
317 uint8_t max_out_buffer_size;
318 uint8_t rpmb_read_write_size;
319 uint8_t dynamic_capacity_resource_policy;
320 uint8_t data_ordering;
321 uint8_t max_context_id_number;
322 uint8_t sys_data_tag_unit_size;
323 uint8_t sys_data_tag_res_size;
324 uint8_t supported_sec_r_types;
325 uint16_t supported_memory_types;
326 uint32_t system_code_max_n_alloc_u;
327 uint16_t system_code_cap_adj_fac;
328 uint32_t non_persist_max_n_alloc_u;
329 uint16_t non_persist_cap_adj_fac;
330 uint32_t enhanced_1_max_n_alloc_u;
331 uint16_t enhanced_1_cap_adj_fac;
332 uint32_t enhanced_2_max_n_alloc_u;
333 uint16_t enhanced_2_cap_adj_fac;
334 uint32_t enhanced_3_max_n_alloc_u;
335 uint16_t enhanced_3_cap_adj_fac;
336 uint32_t enhanced_4_max_n_alloc_u;
337 uint16_t enhanced_4_cap_adj_fac;
338 uint32_t optimal_logical_block_size;
339 uint8_t reserved2[7];
340 uint32_t write_booster_buffer_max_n_alloc_units;
341 uint8_t device_max_write_booster_l_us;
342 uint8_t write_booster_buffer_cap_adj_fac;
343 uint8_t supported_write_booster_buffer_user_space_reduction_types;
344 uint8_t supported_write_booster_buffer_types;
345 } GeometryDescriptor;
346
347 #define UFS_GEOMETRY_CAPACITY_SHIFT 9
348
349 typedef struct QEMU_PACKED UnitDescriptor {
350 uint8_t length;
351 uint8_t descriptor_idn;
352 uint8_t unit_index;
353 uint8_t lu_enable;
354 uint8_t boot_lun_id;
355 uint8_t lu_write_protect;
356 uint8_t lu_queue_depth;
357 uint8_t psa_sensitive;
358 uint8_t memory_type;
359 uint8_t data_reliability;
360 uint8_t logical_block_size;
361 uint64_t logical_block_count;
362 uint32_t erase_block_size;
363 uint8_t provisioning_type;
364 uint64_t phy_mem_resource_count;
365 uint16_t context_capabilities;
366 uint8_t large_unit_granularity_m1;
367 uint8_t reserved[6];
368 uint32_t lu_num_write_booster_buffer_alloc_units;
369 } UnitDescriptor;
370
371 typedef struct QEMU_PACKED RpmbUnitDescriptor {
372 uint8_t length;
373 uint8_t descriptor_idn;
374 uint8_t unit_index;
375 uint8_t lu_enable;
376 uint8_t boot_lun_id;
377 uint8_t lu_write_protect;
378 uint8_t lu_queue_depth;
379 uint8_t psa_sensitive;
380 uint8_t memory_type;
381 uint8_t reserved;
382 uint8_t logical_block_size;
383 uint64_t logical_block_count;
384 uint32_t erase_block_size;
385 uint8_t provisioning_type;
386 uint64_t phy_mem_resource_count;
387 uint8_t reserved2[3];
388 } RpmbUnitDescriptor;
389
390 typedef struct QEMU_PACKED PowerParametersDescriptor {
391 uint8_t length;
392 uint8_t descriptor_idn;
393 uint16_t active_icc_levels_vcc[16];
394 uint16_t active_icc_levels_vccq[16];
395 uint16_t active_icc_levels_vccq_2[16];
396 } PowerParametersDescriptor;
397
398 typedef struct QEMU_PACKED InterconnectDescriptor {
399 uint8_t length;
400 uint8_t descriptor_idn;
401 uint16_t bcd_unipro_version;
402 uint16_t bcd_mphy_version;
403 } InterconnectDescriptor;
404
405 typedef struct QEMU_PACKED StringDescriptor {
406 uint8_t length;
407 uint8_t descriptor_idn;
408 uint16_t UC[126];
409 } StringDescriptor;
410
411 typedef struct QEMU_PACKED DeviceHealthDescriptor {
412 uint8_t length;
413 uint8_t descriptor_idn;
414 uint8_t pre_eol_info;
415 uint8_t device_life_time_est_a;
416 uint8_t device_life_time_est_b;
417 uint8_t vendor_prop_info[32];
418 uint32_t refresh_total_count;
419 uint32_t refresh_progress;
420 } DeviceHealthDescriptor;
421
422 typedef struct QEMU_PACKED Flags {
423 uint8_t reserved;
424 uint8_t device_init;
425 uint8_t permanent_wp_en;
426 uint8_t power_on_wp_en;
427 uint8_t background_ops_en;
428 uint8_t device_life_span_mode_en;
429 uint8_t purge_enable;
430 uint8_t refresh_enable;
431 uint8_t phy_resource_removal;
432 uint8_t busy_rtc;
433 uint8_t reserved2;
434 uint8_t permanently_disable_fw_update;
435 uint8_t reserved3[2];
436 uint8_t wb_en;
437 uint8_t wb_buffer_flush_en;
438 uint8_t wb_buffer_flush_during_hibernate;
439 uint8_t reserved4[2];
440 } Flags;
441
442 typedef struct Attributes {
443 uint8_t boot_lun_en;
444 uint8_t reserved;
445 uint8_t current_power_mode;
446 uint8_t active_icc_level;
447 uint8_t out_of_order_data_en;
448 uint8_t background_op_status;
449 uint8_t purge_status;
450 uint8_t max_data_in_size;
451 uint8_t max_data_out_size;
452 uint32_t dyn_cap_needed;
453 uint8_t ref_clk_freq;
454 uint8_t config_descr_lock;
455 uint8_t max_num_of_rtt;
456 uint16_t exception_event_control;
457 uint16_t exception_event_status;
458 uint32_t seconds_passed;
459 uint16_t context_conf;
460 uint8_t device_ffu_status;
461 uint8_t psa_state;
462 uint32_t psa_data_size;
463 uint8_t ref_clk_gating_wait_time;
464 uint8_t device_case_rough_temperature;
465 uint8_t device_too_high_temp_boundary;
466 uint8_t device_too_low_temp_boundary;
467 uint8_t throttling_status;
468 uint8_t wb_buffer_flush_status;
469 uint8_t available_wb_buffer_size;
470 uint8_t wb_buffer_life_time_est;
471 uint32_t current_wb_buffer_size;
472 uint8_t refresh_status;
473 uint8_t refresh_freq;
474 uint8_t refresh_unit;
475 uint8_t refresh_method;
476 } Attributes;
477
478 #define UFS_TRANSACTION_SPECIFIC_FIELD_SIZE 20
479 #define UFS_MAX_QUERY_DATA_SIZE 256
480
481 /* Command response result code */
482 typedef enum CommandRespCode {
483 UFS_COMMAND_RESULT_SUCCESS = 0x00,
484 UFS_COMMAND_RESULT_FAIL = 0x01,
485 } CommandRespCode;
486
487 enum {
488 UFS_UPIU_FLAG_UNDERFLOW = 0x20,
489 UFS_UPIU_FLAG_OVERFLOW = 0x40,
490 };
491
492 typedef struct QEMU_PACKED UtpUpiuHeader {
493 uint8_t trans_type;
494 uint8_t flags;
495 uint8_t lun;
496 uint8_t task_tag;
497 uint8_t iid_cmd_set_type;
498 uint8_t query_func;
499 uint8_t response;
500 uint8_t scsi_status;
501 uint8_t ehs_len;
502 uint8_t device_inf;
503 uint16_t data_segment_length;
504 } UtpUpiuHeader;
505
506 /*
507 * The code below is copied from the linux kernel
508 * ("include/uapi/scsi/scsi_bsg_ufs.h") and modified to fit the qemu style.
509 */
510
511 typedef struct QEMU_PACKED UtpUpiuQuery {
512 uint8_t opcode;
513 uint8_t idn;
514 uint8_t index;
515 uint8_t selector;
516 uint16_t reserved_osf;
517 uint16_t length;
518 uint32_t value;
519 uint32_t reserved[2];
520 /* EHS length should be 0. We don't have to worry about EHS area. */
521 uint8_t data[UFS_MAX_QUERY_DATA_SIZE];
522 } UtpUpiuQuery;
523
524 #define UFS_CDB_SIZE 16
525
526 /*
527 * struct UtpUpiuCmd - Command UPIU structure
528 * @data_transfer_len: Data Transfer Length DW-3
529 * @cdb: Command Descriptor Block CDB DW-4 to DW-7
530 */
531 typedef struct QEMU_PACKED UtpUpiuCmd {
532 uint32_t exp_data_transfer_len;
533 uint8_t cdb[UFS_CDB_SIZE];
534 } UtpUpiuCmd;
535
536 /*
537 * struct UtpUpiuReq - general upiu request structure
538 * @header:UPIU header structure DW-0 to DW-2
539 * @sc: fields structure for scsi command DW-3 to DW-7
540 * @qr: fields structure for query request DW-3 to DW-7
541 * @uc: use utp_upiu_query to host the 4 dwords of uic command
542 */
543 typedef struct QEMU_PACKED UtpUpiuReq {
544 UtpUpiuHeader header;
545 union {
546 UtpUpiuCmd sc;
547 UtpUpiuQuery qr;
548 };
549 } UtpUpiuReq;
550
551 /*
552 * The code below is copied from the linux kernel ("include/ufs/ufshci.h") and
553 * modified to fit the qemu style.
554 */
555
556 enum {
557 UFS_PWR_OK = 0x0,
558 UFS_PWR_LOCAL = 0x01,
559 UFS_PWR_REMOTE = 0x02,
560 UFS_PWR_BUSY = 0x03,
561 UFS_PWR_ERROR_CAP = 0x04,
562 UFS_PWR_FATAL_ERROR = 0x05,
563 };
564
565 /* UIC Commands */
566 enum uic_cmd_dme {
567 UFS_UIC_CMD_DME_GET = 0x01,
568 UFS_UIC_CMD_DME_SET = 0x02,
569 UFS_UIC_CMD_DME_PEER_GET = 0x03,
570 UFS_UIC_CMD_DME_PEER_SET = 0x04,
571 UFS_UIC_CMD_DME_POWERON = 0x10,
572 UFS_UIC_CMD_DME_POWEROFF = 0x11,
573 UFS_UIC_CMD_DME_ENABLE = 0x12,
574 UFS_UIC_CMD_DME_RESET = 0x14,
575 UFS_UIC_CMD_DME_END_PT_RST = 0x15,
576 UFS_UIC_CMD_DME_LINK_STARTUP = 0x16,
577 UFS_UIC_CMD_DME_HIBER_ENTER = 0x17,
578 UFS_UIC_CMD_DME_HIBER_EXIT = 0x18,
579 UFS_UIC_CMD_DME_TEST_MODE = 0x1A,
580 };
581
582 /* UIC Config result code / Generic error code */
583 enum {
584 UFS_UIC_CMD_RESULT_SUCCESS = 0x00,
585 UFS_UIC_CMD_RESULT_INVALID_ATTR = 0x01,
586 UFS_UIC_CMD_RESULT_FAILURE = 0x01,
587 UFS_UIC_CMD_RESULT_INVALID_ATTR_VALUE = 0x02,
588 UFS_UIC_CMD_RESULT_READ_ONLY_ATTR = 0x03,
589 UFS_UIC_CMD_RESULT_WRITE_ONLY_ATTR = 0x04,
590 UFS_UIC_CMD_RESULT_BAD_INDEX = 0x05,
591 UFS_UIC_CMD_RESULT_LOCKED_ATTR = 0x06,
592 UFS_UIC_CMD_RESULT_BAD_TEST_FEATURE_INDEX = 0x07,
593 UFS_UIC_CMD_RESULT_PEER_COMM_FAILURE = 0x08,
594 UFS_UIC_CMD_RESULT_BUSY = 0x09,
595 UFS_UIC_CMD_RESULT_DME_FAILURE = 0x0A,
596 };
597
598 #define UFS_MASK_UIC_COMMAND_RESULT 0xFF
599
600 /*
601 * Request Descriptor Definitions
602 */
603
604 /* Transfer request command type */
605 enum {
606 UFS_UTP_CMD_TYPE_SCSI = 0x0,
607 UFS_UTP_CMD_TYPE_UFS = 0x1,
608 UFS_UTP_CMD_TYPE_DEV_MANAGE = 0x2,
609 };
610
611 /* To accommodate UFS2.0 required Command type */
612 enum {
613 UFS_UTP_CMD_TYPE_UFS_STORAGE = 0x1,
614 };
615
616 enum {
617 UFS_UTP_SCSI_COMMAND = 0x00000000,
618 UFS_UTP_NATIVE_UFS_COMMAND = 0x10000000,
619 UFS_UTP_DEVICE_MANAGEMENT_FUNCTION = 0x20000000,
620 UFS_UTP_REQ_DESC_INT_CMD = 0x01000000,
621 UFS_UTP_REQ_DESC_CRYPTO_ENABLE_CMD = 0x00800000,
622 };
623
624 /* UTP Transfer Request Data Direction (DD) */
625 enum {
626 UFS_UTP_NO_DATA_TRANSFER = 0x00000000,
627 UFS_UTP_HOST_TO_DEVICE = 0x02000000,
628 UFS_UTP_DEVICE_TO_HOST = 0x04000000,
629 };
630
631 /* Overall command status values */
632 enum UtpOcsCodes {
633 UFS_OCS_SUCCESS = 0x0,
634 UFS_OCS_INVALID_CMD_TABLE_ATTR = 0x1,
635 UFS_OCS_INVALID_PRDT_ATTR = 0x2,
636 UFS_OCS_MISMATCH_DATA_BUF_SIZE = 0x3,
637 UFS_OCS_MISMATCH_RESP_UPIU_SIZE = 0x4,
638 UFS_OCS_PEER_COMM_FAILURE = 0x5,
639 UFS_OCS_ABORTED = 0x6,
640 UFS_OCS_FATAL_ERROR = 0x7,
641 UFS_OCS_DEVICE_FATAL_ERROR = 0x8,
642 UFS_OCS_INVALID_CRYPTO_CONFIG = 0x9,
643 UFS_OCS_GENERAL_CRYPTO_ERROR = 0xa,
644 UFS_OCS_INVALID_COMMAND_STATUS = 0xf,
645 };
646
647 enum {
648 UFS_MASK_OCS = 0x0F,
649 };
650
651 /*
652 * struct UfshcdSgEntry - UFSHCI PRD Entry
653 * @addr: Physical address; DW-0 and DW-1.
654 * @reserved: Reserved for future use DW-2
655 * @size: size of physical segment DW-3
656 */
657 typedef struct QEMU_PACKED UfshcdSgEntry {
658 uint64_t addr;
659 uint32_t reserved;
660 uint32_t size;
661 /*
662 * followed by variant-specific fields if
663 * CONFIG_SCSI_UFS_VARIABLE_SG_ENTRY_SIZE has been defined.
664 */
665 } UfshcdSgEntry;
666
667 /*
668 * struct RequestDescHeader - Descriptor Header common to both UTRD and UTMRD
669 * @dword0: Descriptor Header DW0
670 * @dword1: Descriptor Header DW1
671 * @dword2: Descriptor Header DW2
672 * @dword3: Descriptor Header DW3
673 */
674 typedef struct QEMU_PACKED RequestDescHeader {
675 uint32_t dword_0;
676 uint32_t dword_1;
677 uint32_t dword_2;
678 uint32_t dword_3;
679 } RequestDescHeader;
680
681 /*
682 * struct UtpTransferReqDesc - UTP Transfer Request Descriptor (UTRD)
683 * @header: UTRD header DW-0 to DW-3
684 * @command_desc_base_addr_lo: UCD base address low DW-4
685 * @command_desc_base_addr_hi: UCD base address high DW-5
686 * @response_upiu_length: response UPIU length DW-6
687 * @response_upiu_offset: response UPIU offset DW-6
688 * @prd_table_length: Physical region descriptor length DW-7
689 * @prd_table_offset: Physical region descriptor offset DW-7
690 */
691 typedef struct QEMU_PACKED UtpTransferReqDesc {
692 /* DW 0-3 */
693 RequestDescHeader header;
694
695 /* DW 4-5*/
696 uint32_t command_desc_base_addr_lo;
697 uint32_t command_desc_base_addr_hi;
698
699 /* DW 6 */
700 uint16_t response_upiu_length;
701 uint16_t response_upiu_offset;
702
703 /* DW 7 */
704 uint16_t prd_table_length;
705 uint16_t prd_table_offset;
706 } UtpTransferReqDesc;
707
708 /*
709 * UTMRD structure.
710 */
711 typedef struct QEMU_PACKED UtpTaskReqDesc {
712 /* DW 0-3 */
713 RequestDescHeader header;
714
715 /* DW 4-11 - Task request UPIU structure */
716 struct {
717 UtpUpiuHeader req_header;
718 uint32_t input_param1;
719 uint32_t input_param2;
720 uint32_t input_param3;
721 uint32_t reserved1[2];
722 } upiu_req;
723
724 /* DW 12-19 - Task Management Response UPIU structure */
725 struct {
726 UtpUpiuHeader rsp_header;
727 uint32_t output_param1;
728 uint32_t output_param2;
729 uint32_t reserved2[3];
730 } upiu_rsp;
731 } UtpTaskReqDesc;
732
733 /*
734 * The code below is copied from the linux kernel ("include/ufs/ufs.h") and
735 * modified to fit the qemu style.
736 */
737
738 #define UFS_GENERAL_UPIU_REQUEST_SIZE (sizeof(UtpUpiuReq))
739 #define UFS_QUERY_DESC_MAX_SIZE 255
740 #define UFS_QUERY_DESC_MIN_SIZE 2
741 #define UFS_QUERY_DESC_HDR_SIZE 2
742 #define UFS_QUERY_OSF_SIZE (GENERAL_UPIU_REQUEST_SIZE - (sizeof(UtpUpiuHeader)))
743 #define UFS_SENSE_SIZE 18
744
745 /*
746 * UFS device may have standard LUs and LUN id could be from 0x00 to
747 * 0x7F. Standard LUs use "Peripheral Device Addressing Format".
748 * UFS device may also have the Well Known LUs (also referred as W-LU)
749 * which again could be from 0x00 to 0x7F. For W-LUs, device only use
750 * the "Extended Addressing Format" which means the W-LUNs would be
751 * from 0xc100 (SCSI_W_LUN_BASE) onwards.
752 * This means max. LUN number reported from UFS device could be 0xC17F.
753 */
754 #define UFS_UPIU_MAX_UNIT_NUM_ID 0x7F
755 #define UFS_UPIU_WLUN_ID (1 << 7)
756
757 /* WriteBooster buffer is available only for the logical unit from 0 to 7 */
758 #define UFS_UPIU_MAX_WB_LUN_ID 8
759
760 /*
761 * WriteBooster buffer lifetime has a limit set by vendor.
762 * If it is over the limit, WriteBooster feature will be disabled.
763 */
764 #define UFS_WB_EXCEED_LIFETIME 0x0B
765
766 /*
767 * The range of valid value of Active ICC attritbute
768 * is from 0x00 to 0x0F.
769 */
770 #define UFS_QUERY_ATTR_ACTIVE_ICC_MAXVALUE 0x0F
771
772 /*
773 * In UFS Spec, the Extra Header Segment (EHS) starts from byte 32 in UPIU
774 * request/response packet
775 */
776 #define UFS_EHS_OFFSET_IN_RESPONSE 32
777
778 /* Well known logical unit id in LUN field of UPIU */
779 enum {
780 UFS_UPIU_REPORT_LUNS_WLUN = 0x81,
781 UFS_UPIU_UFS_DEVICE_WLUN = 0xD0,
782 UFS_UPIU_BOOT_WLUN = 0xB0,
783 UFS_UPIU_RPMB_WLUN = 0xC4,
784 };
785
786 /*
787 * UFS Protocol Information Unit related definitions
788 */
789
790 /* Task management functions */
791 enum {
792 UFS_ABORT_TASK = 0x01,
793 UFS_ABORT_TASK_SET = 0x02,
794 UFS_CLEAR_TASK_SET = 0x04,
795 UFS_LOGICAL_RESET = 0x08,
796 UFS_QUERY_TASK = 0x80,
797 UFS_QUERY_TASK_SET = 0x81,
798 };
799
800 /* UTP UPIU Transaction Codes Initiator to Target */
801 enum {
802 UFS_UPIU_TRANSACTION_NOP_OUT = 0x00,
803 UFS_UPIU_TRANSACTION_COMMAND = 0x01,
804 UFS_UPIU_TRANSACTION_DATA_OUT = 0x02,
805 UFS_UPIU_TRANSACTION_TASK_REQ = 0x04,
806 UFS_UPIU_TRANSACTION_QUERY_REQ = 0x16,
807 };
808
809 /* UTP UPIU Transaction Codes Target to Initiator */
810 enum {
811 UFS_UPIU_TRANSACTION_NOP_IN = 0x20,
812 UFS_UPIU_TRANSACTION_RESPONSE = 0x21,
813 UFS_UPIU_TRANSACTION_DATA_IN = 0x22,
814 UFS_UPIU_TRANSACTION_TASK_RSP = 0x24,
815 UFS_UPIU_TRANSACTION_READY_XFER = 0x31,
816 UFS_UPIU_TRANSACTION_QUERY_RSP = 0x36,
817 UFS_UPIU_TRANSACTION_REJECT_UPIU = 0x3F,
818 };
819
820 /* UPIU Read/Write flags */
821 enum {
822 UFS_UPIU_CMD_FLAGS_NONE = 0x00,
823 UFS_UPIU_CMD_FLAGS_WRITE = 0x20,
824 UFS_UPIU_CMD_FLAGS_READ = 0x40,
825 };
826
827 /* UPIU Task Attributes */
828 enum {
829 UFS_UPIU_TASK_ATTR_SIMPLE = 0x00,
830 UFS_UPIU_TASK_ATTR_ORDERED = 0x01,
831 UFS_UPIU_TASK_ATTR_HEADQ = 0x02,
832 UFS_UPIU_TASK_ATTR_ACA = 0x03,
833 };
834
835 /* UPIU Query request function */
836 enum {
837 UFS_UPIU_QUERY_FUNC_STANDARD_READ_REQUEST = 0x01,
838 UFS_UPIU_QUERY_FUNC_STANDARD_WRITE_REQUEST = 0x81,
839 };
840
841 /* Flag idn for Query Requests*/
842 enum flag_idn {
843 UFS_QUERY_FLAG_IDN_FDEVICEINIT = 0x01,
844 UFS_QUERY_FLAG_IDN_PERMANENT_WPE = 0x02,
845 UFS_QUERY_FLAG_IDN_PWR_ON_WPE = 0x03,
846 UFS_QUERY_FLAG_IDN_BKOPS_EN = 0x04,
847 UFS_QUERY_FLAG_IDN_LIFE_SPAN_MODE_ENABLE = 0x05,
848 UFS_QUERY_FLAG_IDN_PURGE_ENABLE = 0x06,
849 UFS_QUERY_FLAG_IDN_REFRESH_ENABLE = 0x07,
850 UFS_QUERY_FLAG_IDN_FPHYRESOURCEREMOVAL = 0x08,
851 UFS_QUERY_FLAG_IDN_BUSY_RTC = 0x09,
852 UFS_QUERY_FLAG_IDN_RESERVED3 = 0x0A,
853 UFS_QUERY_FLAG_IDN_PERMANENTLY_DISABLE_FW_UPDATE = 0x0B,
854 UFS_QUERY_FLAG_IDN_WB_EN = 0x0E,
855 UFS_QUERY_FLAG_IDN_WB_BUFF_FLUSH_EN = 0x0F,
856 UFS_QUERY_FLAG_IDN_WB_BUFF_FLUSH_DURING_HIBERN8 = 0x10,
857 UFS_QUERY_FLAG_IDN_HPB_RESET = 0x11,
858 UFS_QUERY_FLAG_IDN_HPB_EN = 0x12,
859 UFS_QUERY_FLAG_IDN_COUNT,
860 };
861
862 /* Attribute idn for Query requests */
863 enum attr_idn {
864 UFS_QUERY_ATTR_IDN_BOOT_LU_EN = 0x00,
865 UFS_QUERY_ATTR_IDN_MAX_HPB_SINGLE_CMD = 0x01,
866 UFS_QUERY_ATTR_IDN_POWER_MODE = 0x02,
867 UFS_QUERY_ATTR_IDN_ACTIVE_ICC_LVL = 0x03,
868 UFS_QUERY_ATTR_IDN_OOO_DATA_EN = 0x04,
869 UFS_QUERY_ATTR_IDN_BKOPS_STATUS = 0x05,
870 UFS_QUERY_ATTR_IDN_PURGE_STATUS = 0x06,
871 UFS_QUERY_ATTR_IDN_MAX_DATA_IN = 0x07,
872 UFS_QUERY_ATTR_IDN_MAX_DATA_OUT = 0x08,
873 UFS_QUERY_ATTR_IDN_DYN_CAP_NEEDED = 0x09,
874 UFS_QUERY_ATTR_IDN_REF_CLK_FREQ = 0x0A,
875 UFS_QUERY_ATTR_IDN_CONF_DESC_LOCK = 0x0B,
876 UFS_QUERY_ATTR_IDN_MAX_NUM_OF_RTT = 0x0C,
877 UFS_QUERY_ATTR_IDN_EE_CONTROL = 0x0D,
878 UFS_QUERY_ATTR_IDN_EE_STATUS = 0x0E,
879 UFS_QUERY_ATTR_IDN_SECONDS_PASSED = 0x0F,
880 UFS_QUERY_ATTR_IDN_CNTX_CONF = 0x10,
881 UFS_QUERY_ATTR_IDN_CORR_PRG_BLK_NUM = 0x11,
882 UFS_QUERY_ATTR_IDN_RESERVED2 = 0x12,
883 UFS_QUERY_ATTR_IDN_RESERVED3 = 0x13,
884 UFS_QUERY_ATTR_IDN_FFU_STATUS = 0x14,
885 UFS_QUERY_ATTR_IDN_PSA_STATE = 0x15,
886 UFS_QUERY_ATTR_IDN_PSA_DATA_SIZE = 0x16,
887 UFS_QUERY_ATTR_IDN_REF_CLK_GATING_WAIT_TIME = 0x17,
888 UFS_QUERY_ATTR_IDN_CASE_ROUGH_TEMP = 0x18,
889 UFS_QUERY_ATTR_IDN_HIGH_TEMP_BOUND = 0x19,
890 UFS_QUERY_ATTR_IDN_LOW_TEMP_BOUND = 0x1A,
891 UFS_QUERY_ATTR_IDN_THROTTLING_STATUS = 0x1B,
892 UFS_QUERY_ATTR_IDN_WB_FLUSH_STATUS = 0x1C,
893 UFS_QUERY_ATTR_IDN_AVAIL_WB_BUFF_SIZE = 0x1D,
894 UFS_QUERY_ATTR_IDN_WB_BUFF_LIFE_TIME_EST = 0x1E,
895 UFS_QUERY_ATTR_IDN_CURR_WB_BUFF_SIZE = 0x1F,
896 UFS_QUERY_ATTR_IDN_REFRESH_STATUS = 0x2C,
897 UFS_QUERY_ATTR_IDN_REFRESH_FREQ = 0x2D,
898 UFS_QUERY_ATTR_IDN_REFRESH_UNIT = 0x2E,
899 UFS_QUERY_ATTR_IDN_COUNT,
900 };
901
902 /* Descriptor idn for Query requests */
903 enum desc_idn {
904 UFS_QUERY_DESC_IDN_DEVICE = 0x0,
905 UFS_QUERY_DESC_IDN_CONFIGURATION = 0x1,
906 UFS_QUERY_DESC_IDN_UNIT = 0x2,
907 UFS_QUERY_DESC_IDN_RFU_0 = 0x3,
908 UFS_QUERY_DESC_IDN_INTERCONNECT = 0x4,
909 UFS_QUERY_DESC_IDN_STRING = 0x5,
910 UFS_QUERY_DESC_IDN_RFU_1 = 0x6,
911 UFS_QUERY_DESC_IDN_GEOMETRY = 0x7,
912 UFS_QUERY_DESC_IDN_POWER = 0x8,
913 UFS_QUERY_DESC_IDN_HEALTH = 0x9,
914 UFS_QUERY_DESC_IDN_MAX,
915 };
916
917 enum desc_header_offset {
918 UFS_QUERY_DESC_LENGTH_OFFSET = 0x00,
919 UFS_QUERY_DESC_DESC_TYPE_OFFSET = 0x01,
920 };
921
922 /* Unit descriptor parameters offsets in bytes*/
923 enum unit_desc_param {
924 UFS_UNIT_DESC_PARAM_LEN = 0x0,
925 UFS_UNIT_DESC_PARAM_TYPE = 0x1,
926 UFS_UNIT_DESC_PARAM_UNIT_INDEX = 0x2,
927 UFS_UNIT_DESC_PARAM_LU_ENABLE = 0x3,
928 UFS_UNIT_DESC_PARAM_BOOT_LUN_ID = 0x4,
929 UFS_UNIT_DESC_PARAM_LU_WR_PROTECT = 0x5,
930 UFS_UNIT_DESC_PARAM_LU_Q_DEPTH = 0x6,
931 UFS_UNIT_DESC_PARAM_PSA_SENSITIVE = 0x7,
932 UFS_UNIT_DESC_PARAM_MEM_TYPE = 0x8,
933 UFS_UNIT_DESC_PARAM_DATA_RELIABILITY = 0x9,
934 UFS_UNIT_DESC_PARAM_LOGICAL_BLK_SIZE = 0xA,
935 UFS_UNIT_DESC_PARAM_LOGICAL_BLK_COUNT = 0xB,
936 UFS_UNIT_DESC_PARAM_ERASE_BLK_SIZE = 0x13,
937 UFS_UNIT_DESC_PARAM_PROVISIONING_TYPE = 0x17,
938 UFS_UNIT_DESC_PARAM_PHY_MEM_RSRC_CNT = 0x18,
939 UFS_UNIT_DESC_PARAM_CTX_CAPABILITIES = 0x20,
940 UFS_UNIT_DESC_PARAM_LARGE_UNIT_SIZE_M1 = 0x22,
941 UFS_UNIT_DESC_PARAM_HPB_LU_MAX_ACTIVE_RGNS = 0x23,
942 UFS_UNIT_DESC_PARAM_HPB_PIN_RGN_START_OFF = 0x25,
943 UFS_UNIT_DESC_PARAM_HPB_NUM_PIN_RGNS = 0x27,
944 UFS_UNIT_DESC_PARAM_WB_BUF_ALLOC_UNITS = 0x29,
945 };
946
947 /* RPMB Unit descriptor parameters offsets in bytes*/
948 enum rpmb_unit_desc_param {
949 UFS_RPMB_UNIT_DESC_PARAM_LEN = 0x0,
950 UFS_RPMB_UNIT_DESC_PARAM_TYPE = 0x1,
951 UFS_RPMB_UNIT_DESC_PARAM_UNIT_INDEX = 0x2,
952 UFS_RPMB_UNIT_DESC_PARAM_LU_ENABLE = 0x3,
953 UFS_RPMB_UNIT_DESC_PARAM_BOOT_LUN_ID = 0x4,
954 UFS_RPMB_UNIT_DESC_PARAM_LU_WR_PROTECT = 0x5,
955 UFS_RPMB_UNIT_DESC_PARAM_LU_Q_DEPTH = 0x6,
956 UFS_RPMB_UNIT_DESC_PARAM_PSA_SENSITIVE = 0x7,
957 UFS_RPMB_UNIT_DESC_PARAM_MEM_TYPE = 0x8,
958 UFS_RPMB_UNIT_DESC_PARAM_REGION_EN = 0x9,
959 UFS_RPMB_UNIT_DESC_PARAM_LOGICAL_BLK_SIZE = 0xA,
960 UFS_RPMB_UNIT_DESC_PARAM_LOGICAL_BLK_COUNT = 0xB,
961 UFS_RPMB_UNIT_DESC_PARAM_REGION0_SIZE = 0x13,
962 UFS_RPMB_UNIT_DESC_PARAM_REGION1_SIZE = 0x14,
963 UFS_RPMB_UNIT_DESC_PARAM_REGION2_SIZE = 0x15,
964 UFS_RPMB_UNIT_DESC_PARAM_REGION3_SIZE = 0x16,
965 UFS_RPMB_UNIT_DESC_PARAM_PROVISIONING_TYPE = 0x17,
966 UFS_RPMB_UNIT_DESC_PARAM_PHY_MEM_RSRC_CNT = 0x18,
967 };
968
969 /* Device descriptor parameters offsets in bytes*/
970 enum device_desc_param {
971 UFS_DEVICE_DESC_PARAM_LEN = 0x0,
972 UFS_DEVICE_DESC_PARAM_TYPE = 0x1,
973 UFS_DEVICE_DESC_PARAM_DEVICE_TYPE = 0x2,
974 UFS_DEVICE_DESC_PARAM_DEVICE_CLASS = 0x3,
975 UFS_DEVICE_DESC_PARAM_DEVICE_SUB_CLASS = 0x4,
976 UFS_DEVICE_DESC_PARAM_PRTCL = 0x5,
977 UFS_DEVICE_DESC_PARAM_NUM_LU = 0x6,
978 UFS_DEVICE_DESC_PARAM_NUM_WLU = 0x7,
979 UFS_DEVICE_DESC_PARAM_BOOT_ENBL = 0x8,
980 UFS_DEVICE_DESC_PARAM_DESC_ACCSS_ENBL = 0x9,
981 UFS_DEVICE_DESC_PARAM_INIT_PWR_MODE = 0xA,
982 UFS_DEVICE_DESC_PARAM_HIGH_PR_LUN = 0xB,
983 UFS_DEVICE_DESC_PARAM_SEC_RMV_TYPE = 0xC,
984 UFS_DEVICE_DESC_PARAM_SEC_LU = 0xD,
985 UFS_DEVICE_DESC_PARAM_BKOP_TERM_LT = 0xE,
986 UFS_DEVICE_DESC_PARAM_ACTVE_ICC_LVL = 0xF,
987 UFS_DEVICE_DESC_PARAM_SPEC_VER = 0x10,
988 UFS_DEVICE_DESC_PARAM_MANF_DATE = 0x12,
989 UFS_DEVICE_DESC_PARAM_MANF_NAME = 0x14,
990 UFS_DEVICE_DESC_PARAM_PRDCT_NAME = 0x15,
991 UFS_DEVICE_DESC_PARAM_SN = 0x16,
992 UFS_DEVICE_DESC_PARAM_OEM_ID = 0x17,
993 UFS_DEVICE_DESC_PARAM_MANF_ID = 0x18,
994 UFS_DEVICE_DESC_PARAM_UD_OFFSET = 0x1A,
995 UFS_DEVICE_DESC_PARAM_UD_LEN = 0x1B,
996 UFS_DEVICE_DESC_PARAM_RTT_CAP = 0x1C,
997 UFS_DEVICE_DESC_PARAM_FRQ_RTC = 0x1D,
998 UFS_DEVICE_DESC_PARAM_UFS_FEAT = 0x1F,
999 UFS_DEVICE_DESC_PARAM_FFU_TMT = 0x20,
1000 UFS_DEVICE_DESC_PARAM_Q_DPTH = 0x21,
1001 UFS_DEVICE_DESC_PARAM_DEV_VER = 0x22,
1002 UFS_DEVICE_DESC_PARAM_NUM_SEC_WPA = 0x24,
1003 UFS_DEVICE_DESC_PARAM_PSA_MAX_DATA = 0x25,
1004 UFS_DEVICE_DESC_PARAM_PSA_TMT = 0x29,
1005 UFS_DEVICE_DESC_PARAM_PRDCT_REV = 0x2A,
1006 UFS_DEVICE_DESC_PARAM_HPB_VER = 0x40,
1007 UFS_DEVICE_DESC_PARAM_HPB_CONTROL = 0x42,
1008 UFS_DEVICE_DESC_PARAM_EXT_UFS_FEATURE_SUP = 0x4F,
1009 UFS_DEVICE_DESC_PARAM_WB_PRESRV_USRSPC_EN = 0x53,
1010 UFS_DEVICE_DESC_PARAM_WB_TYPE = 0x54,
1011 UFS_DEVICE_DESC_PARAM_WB_SHARED_ALLOC_UNITS = 0x55,
1012 };
1013
1014 /* Interconnect descriptor parameters offsets in bytes*/
1015 enum interconnect_desc_param {
1016 UFS_INTERCONNECT_DESC_PARAM_LEN = 0x0,
1017 UFS_INTERCONNECT_DESC_PARAM_TYPE = 0x1,
1018 UFS_INTERCONNECT_DESC_PARAM_UNIPRO_VER = 0x2,
1019 UFS_INTERCONNECT_DESC_PARAM_MPHY_VER = 0x4,
1020 };
1021
1022 /* Geometry descriptor parameters offsets in bytes*/
1023 enum geometry_desc_param {
1024 UFS_GEOMETRY_DESC_PARAM_LEN = 0x0,
1025 UFS_GEOMETRY_DESC_PARAM_TYPE = 0x1,
1026 UFS_GEOMETRY_DESC_PARAM_DEV_CAP = 0x4,
1027 UFS_GEOMETRY_DESC_PARAM_MAX_NUM_LUN = 0xC,
1028 UFS_GEOMETRY_DESC_PARAM_SEG_SIZE = 0xD,
1029 UFS_GEOMETRY_DESC_PARAM_ALLOC_UNIT_SIZE = 0x11,
1030 UFS_GEOMETRY_DESC_PARAM_MIN_BLK_SIZE = 0x12,
1031 UFS_GEOMETRY_DESC_PARAM_OPT_RD_BLK_SIZE = 0x13,
1032 UFS_GEOMETRY_DESC_PARAM_OPT_WR_BLK_SIZE = 0x14,
1033 UFS_GEOMETRY_DESC_PARAM_MAX_IN_BUF_SIZE = 0x15,
1034 UFS_GEOMETRY_DESC_PARAM_MAX_OUT_BUF_SIZE = 0x16,
1035 UFS_GEOMETRY_DESC_PARAM_RPMB_RW_SIZE = 0x17,
1036 UFS_GEOMETRY_DESC_PARAM_DYN_CAP_RSRC_PLC = 0x18,
1037 UFS_GEOMETRY_DESC_PARAM_DATA_ORDER = 0x19,
1038 UFS_GEOMETRY_DESC_PARAM_MAX_NUM_CTX = 0x1A,
1039 UFS_GEOMETRY_DESC_PARAM_TAG_UNIT_SIZE = 0x1B,
1040 UFS_GEOMETRY_DESC_PARAM_TAG_RSRC_SIZE = 0x1C,
1041 UFS_GEOMETRY_DESC_PARAM_SEC_RM_TYPES = 0x1D,
1042 UFS_GEOMETRY_DESC_PARAM_MEM_TYPES = 0x1E,
1043 UFS_GEOMETRY_DESC_PARAM_SCM_MAX_NUM_UNITS = 0x20,
1044 UFS_GEOMETRY_DESC_PARAM_SCM_CAP_ADJ_FCTR = 0x24,
1045 UFS_GEOMETRY_DESC_PARAM_NPM_MAX_NUM_UNITS = 0x26,
1046 UFS_GEOMETRY_DESC_PARAM_NPM_CAP_ADJ_FCTR = 0x2A,
1047 UFS_GEOMETRY_DESC_PARAM_ENM1_MAX_NUM_UNITS = 0x2C,
1048 UFS_GEOMETRY_DESC_PARAM_ENM1_CAP_ADJ_FCTR = 0x30,
1049 UFS_GEOMETRY_DESC_PARAM_ENM2_MAX_NUM_UNITS = 0x32,
1050 UFS_GEOMETRY_DESC_PARAM_ENM2_CAP_ADJ_FCTR = 0x36,
1051 UFS_GEOMETRY_DESC_PARAM_ENM3_MAX_NUM_UNITS = 0x38,
1052 UFS_GEOMETRY_DESC_PARAM_ENM3_CAP_ADJ_FCTR = 0x3C,
1053 UFS_GEOMETRY_DESC_PARAM_ENM4_MAX_NUM_UNITS = 0x3E,
1054 UFS_GEOMETRY_DESC_PARAM_ENM4_CAP_ADJ_FCTR = 0x42,
1055 UFS_GEOMETRY_DESC_PARAM_OPT_LOG_BLK_SIZE = 0x44,
1056 UFS_GEOMETRY_DESC_PARAM_HPB_REGION_SIZE = 0x48,
1057 UFS_GEOMETRY_DESC_PARAM_HPB_NUMBER_LU = 0x49,
1058 UFS_GEOMETRY_DESC_PARAM_HPB_SUBREGION_SIZE = 0x4A,
1059 UFS_GEOMETRY_DESC_PARAM_HPB_MAX_ACTIVE_REGS = 0x4B,
1060 UFS_GEOMETRY_DESC_PARAM_WB_MAX_ALLOC_UNITS = 0x4F,
1061 UFS_GEOMETRY_DESC_PARAM_WB_MAX_WB_LUNS = 0x53,
1062 UFS_GEOMETRY_DESC_PARAM_WB_BUFF_CAP_ADJ = 0x54,
1063 UFS_GEOMETRY_DESC_PARAM_WB_SUP_RED_TYPE = 0x55,
1064 UFS_GEOMETRY_DESC_PARAM_WB_SUP_WB_TYPE = 0x56,
1065 };
1066
1067 /* Health descriptor parameters offsets in bytes*/
1068 enum health_desc_param {
1069 UFS_HEALTH_DESC_PARAM_LEN = 0x0,
1070 UFS_HEALTH_DESC_PARAM_TYPE = 0x1,
1071 UFS_HEALTH_DESC_PARAM_EOL_INFO = 0x2,
1072 UFS_HEALTH_DESC_PARAM_LIFE_TIME_EST_A = 0x3,
1073 UFS_HEALTH_DESC_PARAM_LIFE_TIME_EST_B = 0x4,
1074 };
1075
1076 enum {
1077 UFS_DEV_HIGH_TEMP_NOTIF = BIT(4),
1078 UFS_DEV_LOW_TEMP_NOTIF = BIT(5),
1079 };
1080
1081 /* WriteBooster buffer mode */
1082 enum {
1083 UFS_WB_BUF_MODE_LU_DEDICATED = 0x0,
1084 UFS_WB_BUF_MODE_SHARED = 0x1,
1085 };
1086
1087 /*
1088 * Logical Unit Write Protect
1089 * 00h: LU not write protected
1090 * 01h: LU write protected when fPowerOnWPEn =1
1091 * 02h: LU permanently write protected when fPermanentWPEn =1
1092 */
1093 enum ufs_lu_wp_type {
1094 UFS_LU_NO_WP = 0x00,
1095 UFS_LU_POWER_ON_WP = 0x01,
1096 UFS_LU_PERM_WP = 0x02,
1097 };
1098
1099 /* Exception event mask values */
1100 enum {
1101 MASK_EE_TOO_HIGH_TEMP = BIT(3),
1102 MASK_EE_TOO_LOW_TEMP = BIT(4),
1103 };
1104
1105 /* UTP QUERY Transaction Specific Fields OpCode */
1106 enum query_opcode {
1107 UFS_UPIU_QUERY_OPCODE_NOP = 0x0,
1108 UFS_UPIU_QUERY_OPCODE_READ_DESC = 0x1,
1109 UFS_UPIU_QUERY_OPCODE_WRITE_DESC = 0x2,
1110 UFS_UPIU_QUERY_OPCODE_READ_ATTR = 0x3,
1111 UFS_UPIU_QUERY_OPCODE_WRITE_ATTR = 0x4,
1112 UFS_UPIU_QUERY_OPCODE_READ_FLAG = 0x5,
1113 UFS_UPIU_QUERY_OPCODE_SET_FLAG = 0x6,
1114 UFS_UPIU_QUERY_OPCODE_CLEAR_FLAG = 0x7,
1115 UFS_UPIU_QUERY_OPCODE_TOGGLE_FLAG = 0x8,
1116 };
1117
1118 /* Query response result code */
1119 typedef enum QueryRespCode {
1120 UFS_QUERY_RESULT_SUCCESS = 0x00,
1121 UFS_QUERY_RESULT_NOT_READABLE = 0xF6,
1122 UFS_QUERY_RESULT_NOT_WRITEABLE = 0xF7,
1123 UFS_QUERY_RESULT_ALREADY_WRITTEN = 0xF8,
1124 UFS_QUERY_RESULT_INVALID_LENGTH = 0xF9,
1125 UFS_QUERY_RESULT_INVALID_VALUE = 0xFA,
1126 UFS_QUERY_RESULT_INVALID_SELECTOR = 0xFB,
1127 UFS_QUERY_RESULT_INVALID_INDEX = 0xFC,
1128 UFS_QUERY_RESULT_INVALID_IDN = 0xFD,
1129 UFS_QUERY_RESULT_INVALID_OPCODE = 0xFE,
1130 UFS_QUERY_RESULT_GENERAL_FAILURE = 0xFF,
1131 } QueryRespCode;
1132
1133 /* UTP Transfer Request Command Type (CT) */
1134 enum {
1135 UFS_UPIU_COMMAND_SET_TYPE_SCSI = 0x0,
1136 UFS_UPIU_COMMAND_SET_TYPE_UFS = 0x1,
1137 UFS_UPIU_COMMAND_SET_TYPE_QUERY = 0x2,
1138 };
1139
1140 /* Task management service response */
1141 enum {
1142 UFS_UPIU_TASK_MANAGEMENT_FUNC_COMPL = 0x00,
1143 UFS_UPIU_TASK_MANAGEMENT_FUNC_NOT_SUPPORTED = 0x04,
1144 UFS_UPIU_TASK_MANAGEMENT_FUNC_SUCCEEDED = 0x08,
1145 UFS_UPIU_TASK_MANAGEMENT_FUNC_FAILED = 0x05,
1146 UFS_UPIU_INCORRECT_LOGICAL_UNIT_NO = 0x09,
1147 };
1148
1149 /* UFS device power modes */
1150 enum ufs_dev_pwr_mode {
1151 UFS_ACTIVE_PWR_MODE = 1,
1152 UFS_SLEEP_PWR_MODE = 2,
1153 UFS_POWERDOWN_PWR_MODE = 3,
1154 UFS_DEEPSLEEP_PWR_MODE = 4,
1155 };
1156
1157 /*
1158 * struct UtpCmdRsp - Response UPIU structure
1159 * @residual_transfer_count: Residual transfer count DW-3
1160 * @reserved: Reserved double words DW-4 to DW-7
1161 * @sense_data_len: Sense data length DW-8 U16
1162 * @sense_data: Sense data field DW-8 to DW-12
1163 */
1164 typedef struct QEMU_PACKED UtpCmdRsp {
1165 uint32_t residual_transfer_count;
1166 uint32_t reserved[4];
1167 uint16_t sense_data_len;
1168 uint8_t sense_data[UFS_SENSE_SIZE];
1169 } UtpCmdRsp;
1170
1171 /*
1172 * struct UtpUpiuRsp - general upiu response structure
1173 * @header: UPIU header structure DW-0 to DW-2
1174 * @sr: fields structure for scsi command DW-3 to DW-12
1175 * @qr: fields structure for query request DW-3 to DW-7
1176 */
1177 typedef struct QEMU_PACKED UtpUpiuRsp {
1178 UtpUpiuHeader header;
1179 union {
1180 UtpCmdRsp sr;
1181 UtpUpiuQuery qr;
1182 };
1183 } UtpUpiuRsp;
1184
1185 /*
1186 * MCQ Completion Queue Entry
1187 */
1188 typedef UtpTransferReqDesc UfsSqEntry;
1189 typedef struct QEMU_PACKED UfsCqEntry {
1190 uint64_t utp_addr;
1191 uint16_t resp_len;
1192 uint16_t resp_off;
1193 uint16_t prdt_len;
1194 uint16_t prdt_off;
1195 uint8_t status;
1196 uint8_t error;
1197 uint16_t rsvd1;
1198 uint32_t rsvd2[3];
1199 } UfsCqEntry;
1200
_ufs_check_size(void)1201 static inline void _ufs_check_size(void)
1202 {
1203 QEMU_BUILD_BUG_ON(sizeof(UfsReg) != 0x38C);
1204 QEMU_BUILD_BUG_ON(sizeof(UfsMcqReg) != 64);
1205 QEMU_BUILD_BUG_ON(sizeof(UfsMcqSqReg) != 20);
1206 QEMU_BUILD_BUG_ON(sizeof(UfsMcqCqReg) != 8);
1207 QEMU_BUILD_BUG_ON(sizeof(UfsMcqSqIntReg) != 8);
1208 QEMU_BUILD_BUG_ON(sizeof(UfsMcqCqIntReg) != 12);
1209 QEMU_BUILD_BUG_ON(sizeof(UfsMcqOpReg) != 48);
1210 QEMU_BUILD_BUG_ON(sizeof(DeviceDescriptor) != 89);
1211 QEMU_BUILD_BUG_ON(sizeof(GeometryDescriptor) != 87);
1212 QEMU_BUILD_BUG_ON(sizeof(UnitDescriptor) != 45);
1213 QEMU_BUILD_BUG_ON(sizeof(RpmbUnitDescriptor) != 35);
1214 QEMU_BUILD_BUG_ON(sizeof(PowerParametersDescriptor) != 98);
1215 QEMU_BUILD_BUG_ON(sizeof(InterconnectDescriptor) != 6);
1216 QEMU_BUILD_BUG_ON(sizeof(StringDescriptor) != 254);
1217 QEMU_BUILD_BUG_ON(sizeof(DeviceHealthDescriptor) != 45);
1218 QEMU_BUILD_BUG_ON(sizeof(Flags) != 0x13);
1219 QEMU_BUILD_BUG_ON(sizeof(UtpUpiuHeader) != 12);
1220 QEMU_BUILD_BUG_ON(sizeof(UtpUpiuQuery) != 276);
1221 QEMU_BUILD_BUG_ON(sizeof(UtpUpiuCmd) != 20);
1222 QEMU_BUILD_BUG_ON(sizeof(UtpUpiuReq) != 288);
1223 QEMU_BUILD_BUG_ON(sizeof(UfshcdSgEntry) != 16);
1224 QEMU_BUILD_BUG_ON(sizeof(RequestDescHeader) != 16);
1225 QEMU_BUILD_BUG_ON(sizeof(UtpTransferReqDesc) != 32);
1226 QEMU_BUILD_BUG_ON(sizeof(UtpTaskReqDesc) != 80);
1227 QEMU_BUILD_BUG_ON(sizeof(UtpCmdRsp) != 40);
1228 QEMU_BUILD_BUG_ON(sizeof(UtpUpiuRsp) != 288);
1229 QEMU_BUILD_BUG_ON(sizeof(UfsSqEntry) != 32);
1230 QEMU_BUILD_BUG_ON(sizeof(UfsCqEntry) != 32);
1231 }
1232 #endif
1233