1 // SPDX-License-Identifier: (GPL-2.0-or-later OR BSD-3-Clause)
2 /*
3 * Copyright (c) 2014-2025, Advanced Micro Devices, Inc.
4 * Copyright (c) 2014, Synopsys, Inc.
5 * All rights reserved
6 */
7
8 #ifndef __XGBE_H__
9 #define __XGBE_H__
10
11 #include <linux/dma-mapping.h>
12 #include <linux/netdevice.h>
13 #include <linux/workqueue.h>
14 #include <linux/phy.h>
15 #include <linux/if_vlan.h>
16 #include <linux/bitops.h>
17 #include <linux/ptp_clock_kernel.h>
18 #include <linux/timecounter.h>
19 #include <linux/net_tstamp.h>
20 #include <net/dcbnl.h>
21 #include <linux/completion.h>
22 #include <linux/cpumask.h>
23 #include <linux/interrupt.h>
24 #include <linux/dcache.h>
25 #include <linux/ethtool.h>
26 #include <linux/list.h>
27
28 #define XGBE_DRV_NAME "amd-xgbe"
29 #define XGBE_DRV_DESC "AMD 10 Gigabit Ethernet Driver"
30
31 /* Descriptor related defines */
32 #define XGBE_TX_DESC_CNT 512
33 #define XGBE_TX_DESC_MIN_FREE (XGBE_TX_DESC_CNT >> 3)
34 #define XGBE_TX_DESC_MAX_PROC (XGBE_TX_DESC_CNT >> 1)
35 #define XGBE_RX_DESC_CNT 512
36
37 #define XGBE_TX_DESC_CNT_MIN 64
38 #define XGBE_TX_DESC_CNT_MAX 4096
39 #define XGBE_RX_DESC_CNT_MIN 64
40 #define XGBE_RX_DESC_CNT_MAX 4096
41
42 #define XGBE_TX_MAX_BUF_SIZE (0x3fff & ~(64 - 1))
43
44 /* Descriptors required for maximum contiguous TSO/GSO packet */
45 #define XGBE_TX_MAX_SPLIT \
46 ((GSO_LEGACY_MAX_SIZE / XGBE_TX_MAX_BUF_SIZE) + 1)
47
48 /* Maximum possible descriptors needed for an SKB:
49 * - Maximum number of SKB frags
50 * - Maximum descriptors for contiguous TSO/GSO packet
51 * - Possible context descriptor
52 * - Possible TSO header descriptor
53 */
54 #define XGBE_TX_MAX_DESCS (MAX_SKB_FRAGS + XGBE_TX_MAX_SPLIT + 2)
55
56 #define XGBE_RX_MIN_BUF_SIZE (ETH_FRAME_LEN + ETH_FCS_LEN + VLAN_HLEN)
57 #define XGBE_RX_BUF_ALIGN 64
58 #define XGBE_SKB_ALLOC_SIZE 256
59 #define XGBE_SPH_HDSMS_SIZE 2 /* Keep in sync with SKB_ALLOC_SIZE */
60
61 #define XGBE_MAX_DMA_CHANNELS 16
62 #define XGBE_MAX_QUEUES 16
63 #define XGBE_PRIORITY_QUEUES 8
64 #define XGBE_DMA_STOP_TIMEOUT 1
65
66 /* DMA cache settings - Outer sharable, write-back, write-allocate */
67 #define XGBE_DMA_OS_ARCR 0x002b2b2b
68 #define XGBE_DMA_OS_AWCR 0x2f2f2f2f
69
70 /* DMA cache settings - System, no caches used */
71 #define XGBE_DMA_SYS_ARCR 0x00303030
72 #define XGBE_DMA_SYS_AWCR 0x30303030
73
74 /* DMA cache settings - PCI device */
75 #define XGBE_DMA_PCI_ARCR 0x000f0f0f
76 #define XGBE_DMA_PCI_AWCR 0x0f0f0f0f
77 #define XGBE_DMA_PCI_AWARCR 0x00000f0f
78
79 /* DMA channel interrupt modes */
80 #define XGBE_IRQ_MODE_EDGE 0
81 #define XGBE_IRQ_MODE_LEVEL 1
82
83 #define XGBE_ETH_FRAME_HDR (ETH_HLEN + ETH_FCS_LEN + VLAN_HLEN)
84 #define XGMAC_MIN_PACKET 60
85 #define XGMAC_STD_PACKET_MTU 1500
86 #define XGMAC_MAX_STD_PACKET 1518
87 #define XGMAC_JUMBO_PACKET_MTU 9000
88 #define XGMAC_MAX_JUMBO_PACKET 9018
89 #define XGMAC_GIANT_PACKET_MTU 16368
90 #define XGMAC_ETH_PREAMBLE (12 + 8) /* Inter-frame gap + preamble */
91
92 #define XGMAC_PFC_DATA_LEN 46
93 #define XGMAC_PFC_DELAYS 14000
94
95 #define XGMAC_PRIO_QUEUES(_cnt) \
96 min_t(unsigned int, IEEE_8021QAZ_MAX_TCS, (_cnt))
97
98 /* Common property names */
99 #define XGBE_PHY_MODE_PROPERTY "phy-mode"
100 #define XGBE_DMA_IRQS_PROPERTY "amd,per-channel-interrupt"
101 #define XGBE_SPEEDSET_PROPERTY "amd,speed-set"
102
103 /* Device-tree clock names */
104 #define XGBE_DMA_CLOCK "dma_clk"
105 #define XGBE_PTP_CLOCK "ptp_clk"
106
107 /* ACPI property names */
108 #define XGBE_ACPI_DMA_FREQ "amd,dma-freq"
109 #define XGBE_ACPI_PTP_FREQ "amd,ptp-freq"
110
111 /* PCI BAR mapping */
112 #define XGBE_XGMAC_BAR 0
113 #define XGBE_XPCS_BAR 1
114 #define XGBE_MAC_PROP_OFFSET 0x1d000
115 #define XGBE_I2C_CTRL_OFFSET 0x1e000
116
117 /* PCI MSI/MSIx support */
118 #define XGBE_MSI_BASE_COUNT 4
119 #define XGBE_MSI_MIN_COUNT (XGBE_MSI_BASE_COUNT + 1)
120
121 /* Initial PTP register values based on Link Speed. */
122 #define MAC_TICNR_1G_INITVAL 0x10
123 #define MAC_TECNR_1G_INITVAL 0x28
124
125 #define MAC_TICSNR_10G_INITVAL 0x33
126 #define MAC_TECNR_10G_INITVAL 0x14
127 #define MAC_TECSNR_10G_INITVAL 0xCC
128
129 /* PCI clock frequencies */
130 #define XGBE_V2_DMA_CLOCK_FREQ 500000000 /* 500 MHz */
131 #define XGBE_V2_PTP_CLOCK_FREQ 125000000 /* 125 MHz */
132
133 /* Timestamp support - values based on 50MHz PTP clock
134 * 50MHz => 20 nsec
135 */
136 #define XGBE_TSTAMP_SSINC 20
137 #define XGBE_TSTAMP_SNSINC 0
138 #define XGBE_PTP_ACT_CLK_FREQ 500000000
139
140 #define XGBE_V2_TSTAMP_SSINC 0xA
141 #define XGBE_V2_TSTAMP_SNSINC 0
142 #define XGBE_V2_PTP_ACT_CLK_FREQ 1000000000
143
144 /* Define maximum supported values */
145 #define XGBE_MAX_PPS_OUT 4
146 #define XGBE_MAX_AUX_SNAP 4
147
148 #define XGMAC_FIFO_MIN_ALLOC 2048
149 #define XGMAC_FIFO_UNIT 256
150 #define XGMAC_FIFO_ALIGN(_x) \
151 (((_x) + XGMAC_FIFO_UNIT - 1) & ~(XGMAC_FIFO_UNIT - 1))
152 #define XGMAC_FIFO_FC_OFF 2048
153 #define XGMAC_FIFO_FC_MIN 4096
154
155 #define XGBE_TC_MIN_QUANTUM 10
156
157 /* Helper macro for descriptor handling
158 * Always use XGBE_GET_DESC_DATA to access the descriptor data
159 * since the index is free-running and needs to be and-ed
160 * with the descriptor count value of the ring to index to
161 * the proper descriptor data.
162 */
163 #define XGBE_GET_DESC_DATA(_ring, _idx) \
164 ((_ring)->rdata + \
165 ((_idx) & ((_ring)->rdesc_count - 1)))
166
167 /* Default coalescing parameters */
168 #define XGMAC_INIT_DMA_TX_USECS 1000
169 #define XGMAC_INIT_DMA_TX_FRAMES 25
170 #define XGMAC_MAX_COAL_TX_TICK 100000
171
172 #define XGMAC_MAX_DMA_RIWT 0xff
173 #define XGMAC_INIT_DMA_RX_USECS 30
174 #define XGMAC_INIT_DMA_RX_FRAMES 25
175
176 /* Flow control queue count */
177 #define XGMAC_MAX_FLOW_CONTROL_QUEUES 8
178
179 /* Flow control threshold units */
180 #define XGMAC_FLOW_CONTROL_UNIT 512
181 #define XGMAC_FLOW_CONTROL_ALIGN(_x) \
182 (((_x) + XGMAC_FLOW_CONTROL_UNIT - 1) & ~(XGMAC_FLOW_CONTROL_UNIT - 1))
183 #define XGMAC_FLOW_CONTROL_VALUE(_x) \
184 (((_x) < 1024) ? 0 : ((_x) / XGMAC_FLOW_CONTROL_UNIT) - 2)
185 #define XGMAC_FLOW_CONTROL_MAX 33280
186
187 /* Maximum MAC address hash table size (256 bits = 8 bytes) */
188 #define XGBE_MAC_HASH_TABLE_SIZE 8
189
190 /* Receive Side Scaling */
191 #define XGBE_RSS_HASH_KEY_SIZE 40
192 #define XGBE_RSS_MAX_TABLE_SIZE 256
193 #define XGBE_RSS_LOOKUP_TABLE_TYPE 0
194 #define XGBE_RSS_HASH_KEY_TYPE 1
195
196 /* Auto-negotiation */
197 #define XGBE_AN_MS_TIMEOUT 500
198 #define XGBE_LINK_TIMEOUT 5
199 #define XGBE_KR_TRAINING_WAIT_ITER 50
200
201 #define XGBE_SGMII_AN_LINK_DUPLEX BIT(1)
202 #define XGBE_SGMII_AN_LINK_SPEED (BIT(2) | BIT(3))
203 #define XGBE_SGMII_AN_LINK_SPEED_10 0x00
204 #define XGBE_SGMII_AN_LINK_SPEED_100 0x04
205 #define XGBE_SGMII_AN_LINK_SPEED_1000 0x08
206 #define XGBE_SGMII_AN_LINK_STATUS BIT(4)
207
208 /* ECC correctable error notification window (seconds) */
209 #define XGBE_ECC_LIMIT 60
210
211 /* MDIO port types */
212 #define XGMAC_MAX_C22_PORT 3
213
214 /* Link mode bit operations */
215 #define XGBE_ZERO_SUP(_ls) \
216 ethtool_link_ksettings_zero_link_mode((_ls), supported)
217
218 #define XGBE_SET_SUP(_ls, _mode) \
219 ethtool_link_ksettings_add_link_mode((_ls), supported, _mode)
220
221 #define XGBE_CLR_SUP(_ls, _mode) \
222 ethtool_link_ksettings_del_link_mode((_ls), supported, _mode)
223
224 #define XGBE_IS_SUP(_ls, _mode) \
225 ethtool_link_ksettings_test_link_mode((_ls), supported, _mode)
226
227 #define XGBE_ZERO_ADV(_ls) \
228 ethtool_link_ksettings_zero_link_mode((_ls), advertising)
229
230 #define XGBE_SET_ADV(_ls, _mode) \
231 ethtool_link_ksettings_add_link_mode((_ls), advertising, _mode)
232
233 #define XGBE_CLR_ADV(_ls, _mode) \
234 ethtool_link_ksettings_del_link_mode((_ls), advertising, _mode)
235
236 #define XGBE_ADV(_ls, _mode) \
237 ethtool_link_ksettings_test_link_mode((_ls), advertising, _mode)
238
239 #define XGBE_ZERO_LP_ADV(_ls) \
240 ethtool_link_ksettings_zero_link_mode((_ls), lp_advertising)
241
242 #define XGBE_SET_LP_ADV(_ls, _mode) \
243 ethtool_link_ksettings_add_link_mode((_ls), lp_advertising, _mode)
244
245 #define XGBE_CLR_LP_ADV(_ls, _mode) \
246 ethtool_link_ksettings_del_link_mode((_ls), lp_advertising, _mode)
247
248 #define XGBE_LP_ADV(_ls, _mode) \
249 ethtool_link_ksettings_test_link_mode((_ls), lp_advertising, _mode)
250
251 #define XGBE_LM_COPY(_dst, _dname, _src, _sname) \
252 bitmap_copy((_dst)->link_modes._dname, \
253 (_src)->link_modes._sname, \
254 __ETHTOOL_LINK_MODE_MASK_NBITS)
255
256 /* XGBE PCI device id */
257 #define XGBE_RV_PCI_DEVICE_ID 0x15d0
258 #define XGBE_YC_PCI_DEVICE_ID 0x14b5
259 #define XGBE_RN_PCI_DEVICE_ID 0x1630
260 #define XGBE_P100a_PCI_DEVICE_ID 0x1122
261
262 /* Generic low and high masks */
263 #define XGBE_GEN_HI_MASK GENMASK(31, 16)
264 #define XGBE_GEN_LO_MASK GENMASK(15, 0)
265
266 /* MAC hardware version numbers (SNPSVER field in MAC_VR register) */
267 #define XGBE_MAC_VER_30 0x30 /* Baseline Rx adaptation support */
268 #define XGBE_MAC_VER_33 0x33 /* P100a platform */
269
270 /* MAC Speed Select (SS) values for MAC_TCR register
271 * These values are written to the SS field to configure link speed.
272 * Note: P100a uses XGMII mode (0x06) for 2.5G instead of GMII (0x02)
273 */
274 /* Note: 100M and 2.5G GMII share the same value (0x02) but are
275 * differentiated by the mode/interface type at the PHY level
276 */
277
278 #define XGBE_MAC_SS_10G 0x00 /* 10Gbps - XGMII mode */
279 #define XGBE_MAC_SS_2_5G_GMII 0x02 /* 2.5Gbps - GMII mode (YC) */
280 #define XGBE_MAC_SS_2_5G_XGMII 0x06 /* 2.5Gbps - XGMII mode (P100a) */
281 #define XGBE_MAC_SS_1G 0x03 /* 1Gbps */
282 #define XGBE_MAC_SS_100M 0x02 /* 100Mbps */
283 #define XGBE_MAC_SS_10M 0x07 /* 10Mbps */
284
285 struct xgbe_prv_data;
286
287 struct xgbe_packet_data {
288 struct sk_buff *skb;
289
290 unsigned int attributes;
291
292 unsigned int errors;
293
294 unsigned int rdesc_count;
295 unsigned int length;
296
297 unsigned int header_len;
298 unsigned int tcp_header_len;
299 unsigned int tcp_payload_len;
300 unsigned short mss;
301
302 unsigned short vlan_ctag;
303
304 u64 rx_tstamp;
305
306 u32 rss_hash;
307 enum pkt_hash_types rss_hash_type;
308
309 unsigned int tx_packets;
310 unsigned int tx_bytes;
311 };
312
313 /* Common Rx and Tx descriptor mapping */
314 struct xgbe_ring_desc {
315 __le32 desc0;
316 __le32 desc1;
317 __le32 desc2;
318 __le32 desc3;
319 };
320
321 /* Page allocation related values */
322 struct xgbe_page_alloc {
323 struct page *pages;
324 unsigned int pages_len;
325 unsigned int pages_offset;
326
327 dma_addr_t pages_dma;
328 };
329
330 /* Ring entry buffer data */
331 struct xgbe_buffer_data {
332 struct xgbe_page_alloc pa;
333 struct xgbe_page_alloc pa_unmap;
334
335 dma_addr_t dma_base;
336 unsigned long dma_off;
337 unsigned int dma_len;
338 };
339
340 /* Tx-related ring data */
341 struct xgbe_tx_ring_data {
342 unsigned int packets; /* BQL packet count */
343 unsigned int bytes; /* BQL byte count */
344 };
345
346 /* Rx-related ring data */
347 struct xgbe_rx_ring_data {
348 struct xgbe_buffer_data hdr; /* Header locations */
349 struct xgbe_buffer_data buf; /* Payload locations */
350
351 unsigned short hdr_len; /* Length of received header */
352 unsigned short len; /* Length of received packet */
353 };
354
355 /* Structure used to hold information related to the descriptor
356 * and the packet associated with the descriptor (always use
357 * the XGBE_GET_DESC_DATA macro to access this data from the ring)
358 */
359 struct xgbe_ring_data {
360 struct xgbe_ring_desc *rdesc; /* Virtual address of descriptor */
361 dma_addr_t rdesc_dma; /* DMA address of descriptor */
362
363 struct sk_buff *skb; /* Virtual address of SKB */
364 dma_addr_t skb_dma; /* DMA address of SKB data */
365 unsigned int skb_dma_len; /* Length of SKB DMA area */
366
367 struct xgbe_tx_ring_data tx; /* Tx-related data */
368 struct xgbe_rx_ring_data rx; /* Rx-related data */
369
370 unsigned int mapped_as_page;
371
372 /* Incomplete receive save location. If the budget is exhausted
373 * or the last descriptor (last normal descriptor or a following
374 * context descriptor) has not been DMA'd yet the current state
375 * of the receive processing needs to be saved.
376 */
377 unsigned int state_saved;
378 struct {
379 struct sk_buff *skb;
380 unsigned int len;
381 unsigned int error;
382 } state;
383 };
384
385 struct xgbe_ring {
386 /* Ring lock - used just for TX rings at the moment */
387 spinlock_t lock;
388
389 /* Per packet related information */
390 struct xgbe_packet_data packet_data;
391
392 /* Virtual/DMA addresses and count of allocated descriptor memory */
393 struct xgbe_ring_desc *rdesc;
394 dma_addr_t rdesc_dma;
395 unsigned int rdesc_count;
396
397 /* Array of descriptor data corresponding the descriptor memory
398 * (always use the XGBE_GET_DESC_DATA macro to access this data)
399 */
400 struct xgbe_ring_data *rdata;
401
402 /* Page allocation for RX buffers */
403 struct xgbe_page_alloc rx_hdr_pa;
404 struct xgbe_page_alloc rx_buf_pa;
405 int node;
406
407 /* Ring index values
408 * cur - Tx: index of descriptor to be used for current transfer
409 * Rx: index of descriptor to check for packet availability
410 * dirty - Tx: index of descriptor to check for transfer complete
411 * Rx: index of descriptor to check for buffer reallocation
412 */
413 unsigned int cur;
414 unsigned int dirty;
415
416 /* Coalesce frame count used for interrupt bit setting */
417 unsigned int coalesce_count;
418
419 union {
420 struct {
421 unsigned int queue_stopped;
422 unsigned int xmit_more;
423 unsigned short cur_mss;
424 unsigned short cur_vlan_ctag;
425 } tx;
426 };
427 } ____cacheline_aligned;
428
429 /* Structure used to describe the descriptor rings associated with
430 * a DMA channel.
431 */
432 struct xgbe_channel {
433 char name[20];
434
435 /* Address of private data area for device */
436 struct xgbe_prv_data *pdata;
437
438 /* Queue index and base address of queue's DMA registers */
439 unsigned int queue_index;
440 void __iomem *dma_regs;
441
442 /* Per channel interrupt irq number */
443 int dma_irq;
444 char dma_irq_name[IFNAMSIZ + 32];
445
446 /* Netdev related settings */
447 struct napi_struct napi;
448
449 /* Per channel interrupt enablement tracker */
450 unsigned int curr_ier;
451 unsigned int saved_ier;
452
453 unsigned int tx_timer_active;
454 struct timer_list tx_timer;
455
456 struct xgbe_ring *tx_ring;
457 struct xgbe_ring *rx_ring;
458
459 int node;
460 cpumask_t affinity_mask;
461 } ____cacheline_aligned;
462
463 enum xgbe_state {
464 XGBE_DOWN,
465 XGBE_LINK_INIT,
466 XGBE_LINK_ERR,
467 XGBE_STOPPED,
468 };
469
470 enum xgbe_int {
471 XGMAC_INT_DMA_CH_SR_TI,
472 XGMAC_INT_DMA_CH_SR_TPS,
473 XGMAC_INT_DMA_CH_SR_TBU,
474 XGMAC_INT_DMA_CH_SR_RI,
475 XGMAC_INT_DMA_CH_SR_RBU,
476 XGMAC_INT_DMA_CH_SR_RPS,
477 XGMAC_INT_DMA_CH_SR_TI_RI,
478 XGMAC_INT_DMA_CH_SR_FBE,
479 XGMAC_INT_DMA_ALL,
480 };
481
482 enum xgbe_int_state {
483 XGMAC_INT_STATE_SAVE,
484 XGMAC_INT_STATE_RESTORE,
485 };
486
487 enum xgbe_ecc_sec {
488 XGBE_ECC_SEC_TX,
489 XGBE_ECC_SEC_RX,
490 XGBE_ECC_SEC_DESC,
491 };
492
493 enum xgbe_speed {
494 XGBE_SPEED_1000 = 0,
495 XGBE_SPEED_2500,
496 XGBE_SPEED_10000,
497 XGBE_SPEEDS,
498 };
499
500 enum xgbe_xpcs_access {
501 XGBE_XPCS_ACCESS_V1 = 0,
502 XGBE_XPCS_ACCESS_V2,
503 XGBE_XPCS_ACCESS_V3,
504 };
505
506 enum xgbe_an_mode {
507 XGBE_AN_MODE_CL73 = 0,
508 XGBE_AN_MODE_CL73_REDRV,
509 XGBE_AN_MODE_CL37,
510 XGBE_AN_MODE_CL37_SGMII,
511 XGBE_AN_MODE_NONE,
512 };
513
514 enum xgbe_an {
515 XGBE_AN_READY = 0,
516 XGBE_AN_PAGE_RECEIVED,
517 XGBE_AN_INCOMPAT_LINK,
518 XGBE_AN_COMPLETE,
519 XGBE_AN_NO_LINK,
520 XGBE_AN_ERROR,
521 };
522
523 enum xgbe_rx {
524 XGBE_RX_BPA = 0,
525 XGBE_RX_XNP,
526 XGBE_RX_COMPLETE,
527 XGBE_RX_ERROR,
528 };
529
530 enum xgbe_mode {
531 XGBE_MODE_KX_1000 = 0,
532 XGBE_MODE_KX_2500,
533 XGBE_MODE_KR,
534 XGBE_MODE_X,
535 XGBE_MODE_SGMII_10,
536 XGBE_MODE_SGMII_100,
537 XGBE_MODE_SGMII_1000,
538 XGBE_MODE_SFI,
539 XGBE_MODE_UNKNOWN,
540 };
541
542 enum xgbe_speedset {
543 XGBE_SPEEDSET_1000_10000 = 0,
544 XGBE_SPEEDSET_2500_10000,
545 };
546
547 enum xgbe_mdio_mode {
548 XGBE_MDIO_MODE_NONE = 0,
549 XGBE_MDIO_MODE_CL22,
550 XGBE_MDIO_MODE_CL45,
551 };
552
553 enum xgbe_mb_cmd {
554 XGBE_MB_CMD_POWER_OFF = 0,
555 XGBE_MB_CMD_SET_1G,
556 XGBE_MB_CMD_SET_2_5G,
557 XGBE_MB_CMD_SET_10G_SFI,
558 XGBE_MB_CMD_SET_10G_KR,
559 XGBE_MB_CMD_RRC
560 };
561
562 enum xgbe_mb_subcmd {
563 XGBE_MB_SUBCMD_NONE = 0,
564 XGBE_MB_SUBCMD_RX_ADAP,
565
566 /* 10GbE SFP subcommands */
567 XGBE_MB_SUBCMD_ACTIVE = 0,
568 XGBE_MB_SUBCMD_PASSIVE_1M,
569 XGBE_MB_SUBCMD_PASSIVE_3M,
570 XGBE_MB_SUBCMD_PASSIVE_OTHER,
571
572 /* 1GbE Mode subcommands */
573 XGBE_MB_SUBCMD_10MBITS = 0,
574 XGBE_MB_SUBCMD_100MBITS,
575 XGBE_MB_SUBCMD_1G_SGMII,
576 XGBE_MB_SUBCMD_1G_KX,
577
578 /* 2.5GbE Mode subcommands */
579 XGBE_MB_SUBCMD_2_5G_KX = 1
580 };
581
582 struct xgbe_phy {
583 struct ethtool_link_ksettings lks;
584
585 int address;
586
587 int autoneg;
588 int speed;
589 int duplex;
590
591 int link;
592
593 int pause_autoneg;
594 int tx_pause;
595 int rx_pause;
596 };
597
598 enum xgbe_i2c_cmd {
599 XGBE_I2C_CMD_READ = 0,
600 XGBE_I2C_CMD_WRITE,
601 };
602
603 struct xgbe_i2c_op {
604 enum xgbe_i2c_cmd cmd;
605
606 unsigned int target;
607
608 void *buf;
609 unsigned int len;
610 };
611
612 struct xgbe_i2c_op_state {
613 struct xgbe_i2c_op *op;
614
615 unsigned int tx_len;
616 unsigned char *tx_buf;
617
618 unsigned int rx_len;
619 unsigned char *rx_buf;
620
621 unsigned int tx_abort_source;
622
623 int ret;
624 };
625
626 struct xgbe_i2c {
627 unsigned int started;
628 unsigned int max_speed_mode;
629 unsigned int rx_fifo_size;
630 unsigned int tx_fifo_size;
631
632 struct xgbe_i2c_op_state op_state;
633 };
634
635 struct xgbe_mmc_stats {
636 /* Tx Stats */
637 u64 txoctetcount_gb;
638 u64 txframecount_gb;
639 u64 txbroadcastframes_g;
640 u64 txmulticastframes_g;
641 u64 tx64octets_gb;
642 u64 tx65to127octets_gb;
643 u64 tx128to255octets_gb;
644 u64 tx256to511octets_gb;
645 u64 tx512to1023octets_gb;
646 u64 tx1024tomaxoctets_gb;
647 u64 txunicastframes_gb;
648 u64 txmulticastframes_gb;
649 u64 txbroadcastframes_gb;
650 u64 txunderflowerror;
651 u64 txoctetcount_g;
652 u64 txframecount_g;
653 u64 txpauseframes;
654 u64 txvlanframes_g;
655
656 /* Rx Stats */
657 u64 rxframecount_gb;
658 u64 rxoctetcount_gb;
659 u64 rxoctetcount_g;
660 u64 rxbroadcastframes_g;
661 u64 rxmulticastframes_g;
662 u64 rxcrcerror;
663 u64 rxrunterror;
664 u64 rxjabbererror;
665 u64 rxundersize_g;
666 u64 rxoversize_g;
667 u64 rx64octets_gb;
668 u64 rx65to127octets_gb;
669 u64 rx128to255octets_gb;
670 u64 rx256to511octets_gb;
671 u64 rx512to1023octets_gb;
672 u64 rx1024tomaxoctets_gb;
673 u64 rxunicastframes_g;
674 u64 rxlengtherror;
675 u64 rxoutofrangetype;
676 u64 rxpauseframes;
677 u64 rxfifooverflow;
678 u64 rxvlanframes_gb;
679 u64 rxwatchdogerror;
680 u64 rxalignmenterror;
681 };
682
683 struct xgbe_ext_stats {
684 u64 tx_tso_packets;
685 u64 rx_split_header_packets;
686 u64 rx_buffer_unavailable;
687
688 u64 txq_packets[XGBE_MAX_DMA_CHANNELS];
689 u64 txq_bytes[XGBE_MAX_DMA_CHANNELS];
690 u64 rxq_packets[XGBE_MAX_DMA_CHANNELS];
691 u64 rxq_bytes[XGBE_MAX_DMA_CHANNELS];
692
693 u64 tx_vxlan_packets;
694 u64 rx_vxlan_packets;
695 u64 rx_csum_errors;
696 u64 rx_vxlan_csum_errors;
697 };
698
699 struct xgbe_pps_config {
700 struct timespec64 start;
701 struct timespec64 period;
702 };
703
704 struct xgbe_hw_if {
705 int (*tx_complete)(struct xgbe_ring_desc *);
706
707 int (*set_mac_address)(struct xgbe_prv_data *, const u8 *addr);
708 int (*config_rx_mode)(struct xgbe_prv_data *);
709
710 int (*enable_rx_csum)(struct xgbe_prv_data *);
711 int (*disable_rx_csum)(struct xgbe_prv_data *);
712
713 int (*enable_rx_vlan_stripping)(struct xgbe_prv_data *);
714 int (*disable_rx_vlan_stripping)(struct xgbe_prv_data *);
715 int (*enable_rx_vlan_filtering)(struct xgbe_prv_data *);
716 int (*disable_rx_vlan_filtering)(struct xgbe_prv_data *);
717 int (*update_vlan_hash_table)(struct xgbe_prv_data *);
718
719 int (*read_mmd_regs)(struct xgbe_prv_data *, int, int);
720 void (*write_mmd_regs)(struct xgbe_prv_data *, int, int, int);
721 int (*set_speed)(struct xgbe_prv_data *, int);
722
723 int (*set_ext_mii_mode)(struct xgbe_prv_data *, unsigned int,
724 enum xgbe_mdio_mode);
725 int (*read_ext_mii_regs_c22)(struct xgbe_prv_data *, int, int);
726 int (*write_ext_mii_regs_c22)(struct xgbe_prv_data *, int, int, u16);
727 int (*read_ext_mii_regs_c45)(struct xgbe_prv_data *, int, int, int);
728 int (*write_ext_mii_regs_c45)(struct xgbe_prv_data *, int, int, int,
729 u16);
730
731 int (*set_gpio)(struct xgbe_prv_data *, unsigned int);
732 int (*clr_gpio)(struct xgbe_prv_data *, unsigned int);
733
734 void (*enable_tx)(struct xgbe_prv_data *);
735 void (*disable_tx)(struct xgbe_prv_data *);
736 void (*enable_rx)(struct xgbe_prv_data *);
737 void (*disable_rx)(struct xgbe_prv_data *);
738
739 void (*powerup_tx)(struct xgbe_prv_data *);
740 void (*powerdown_tx)(struct xgbe_prv_data *);
741 void (*powerup_rx)(struct xgbe_prv_data *);
742 void (*powerdown_rx)(struct xgbe_prv_data *);
743
744 int (*init)(struct xgbe_prv_data *);
745 int (*exit)(struct xgbe_prv_data *);
746
747 int (*enable_int)(struct xgbe_channel *, enum xgbe_int);
748 int (*disable_int)(struct xgbe_channel *, enum xgbe_int);
749 void (*dev_xmit)(struct xgbe_channel *);
750 int (*dev_read)(struct xgbe_channel *);
751 void (*tx_desc_init)(struct xgbe_channel *);
752 void (*rx_desc_init)(struct xgbe_channel *);
753 void (*tx_desc_reset)(struct xgbe_ring_data *);
754 void (*rx_desc_reset)(struct xgbe_prv_data *, struct xgbe_ring_data *,
755 unsigned int);
756 int (*is_last_desc)(struct xgbe_ring_desc *);
757 int (*is_context_desc)(struct xgbe_ring_desc *);
758 void (*tx_start_xmit)(struct xgbe_channel *, struct xgbe_ring *);
759
760 /* For FLOW ctrl */
761 int (*config_tx_flow_control)(struct xgbe_prv_data *);
762 int (*config_rx_flow_control)(struct xgbe_prv_data *);
763
764 /* For RX coalescing */
765 int (*config_rx_coalesce)(struct xgbe_prv_data *);
766 int (*config_tx_coalesce)(struct xgbe_prv_data *);
767 unsigned int (*usec_to_riwt)(struct xgbe_prv_data *, unsigned int);
768 unsigned int (*riwt_to_usec)(struct xgbe_prv_data *, unsigned int);
769
770 /* For RX and TX threshold config */
771 int (*config_rx_threshold)(struct xgbe_prv_data *, unsigned int);
772 int (*config_tx_threshold)(struct xgbe_prv_data *, unsigned int);
773
774 /* For RX and TX Store and Forward Mode config */
775 int (*config_rsf_mode)(struct xgbe_prv_data *, unsigned int);
776 int (*config_tsf_mode)(struct xgbe_prv_data *, unsigned int);
777
778 /* For TX DMA Operate on Second Frame config */
779 int (*config_osp_mode)(struct xgbe_prv_data *);
780
781 /* For MMC statistics */
782 void (*rx_mmc_int)(struct xgbe_prv_data *);
783 void (*tx_mmc_int)(struct xgbe_prv_data *);
784 void (*read_mmc_stats)(struct xgbe_prv_data *);
785
786 /* For Data Center Bridging config */
787 void (*config_tc)(struct xgbe_prv_data *);
788 void (*config_dcb_tc)(struct xgbe_prv_data *);
789 void (*config_dcb_pfc)(struct xgbe_prv_data *);
790
791 /* For Receive Side Scaling */
792 int (*enable_rss)(struct xgbe_prv_data *);
793 int (*disable_rss)(struct xgbe_prv_data *);
794 int (*set_rss_hash_key)(struct xgbe_prv_data *, const u8 *);
795 int (*set_rss_lookup_table)(struct xgbe_prv_data *, const u32 *);
796
797 /* For ECC */
798 void (*disable_ecc_ded)(struct xgbe_prv_data *);
799 void (*disable_ecc_sec)(struct xgbe_prv_data *, enum xgbe_ecc_sec);
800
801 /* For VXLAN */
802 void (*enable_vxlan)(struct xgbe_prv_data *);
803 void (*disable_vxlan)(struct xgbe_prv_data *);
804 void (*set_vxlan_id)(struct xgbe_prv_data *);
805
806 /* For Split Header */
807 void (*enable_sph)(struct xgbe_prv_data *pdata);
808 void (*disable_sph)(struct xgbe_prv_data *pdata);
809 };
810
811 /* This structure represents implementation specific routines for an
812 * implementation of a PHY. All routines are required unless noted below.
813 * Optional routines:
814 * an_pre, an_post
815 * kr_training_pre, kr_training_post
816 * module_info, module_eeprom
817 */
818 struct xgbe_phy_impl_if {
819 /* Perform Setup/teardown actions */
820 int (*init)(struct xgbe_prv_data *);
821 void (*exit)(struct xgbe_prv_data *);
822
823 /* Perform start/stop specific actions */
824 int (*reset)(struct xgbe_prv_data *);
825 int (*start)(struct xgbe_prv_data *);
826 void (*stop)(struct xgbe_prv_data *);
827
828 /* Return the link status */
829 int (*link_status)(struct xgbe_prv_data *, int *);
830
831 /* Indicate if a particular speed is valid */
832 bool (*valid_speed)(struct xgbe_prv_data *, int);
833
834 /* Check if the specified mode can/should be used */
835 bool (*use_mode)(struct xgbe_prv_data *, enum xgbe_mode);
836 /* Switch the PHY into various modes */
837 void (*set_mode)(struct xgbe_prv_data *, enum xgbe_mode);
838 /* Retrieve mode needed for a specific speed */
839 enum xgbe_mode (*get_mode)(struct xgbe_prv_data *, int);
840 /* Retrieve new/next mode when trying to auto-negotiate */
841 enum xgbe_mode (*switch_mode)(struct xgbe_prv_data *);
842 /* Retrieve current mode */
843 enum xgbe_mode (*cur_mode)(struct xgbe_prv_data *);
844
845 /* Retrieve current auto-negotiation mode */
846 enum xgbe_an_mode (*an_mode)(struct xgbe_prv_data *);
847
848 /* Configure auto-negotiation settings */
849 int (*an_config)(struct xgbe_prv_data *);
850
851 /* Set/override auto-negotiation advertisement settings */
852 void (*an_advertising)(struct xgbe_prv_data *,
853 struct ethtool_link_ksettings *);
854
855 /* Process results of auto-negotiation */
856 enum xgbe_mode (*an_outcome)(struct xgbe_prv_data *);
857
858 /* Pre/Post auto-negotiation support */
859 void (*an_pre)(struct xgbe_prv_data *);
860 void (*an_post)(struct xgbe_prv_data *);
861
862 /* Pre/Post KR training enablement support */
863 void (*kr_training_pre)(struct xgbe_prv_data *);
864 void (*kr_training_post)(struct xgbe_prv_data *);
865
866 /* SFP module related info */
867 int (*module_info)(struct xgbe_prv_data *pdata,
868 struct ethtool_modinfo *modinfo);
869 int (*module_eeprom)(struct xgbe_prv_data *pdata,
870 struct ethtool_eeprom *eeprom, u8 *data);
871 };
872
873 struct xgbe_phy_if {
874 /* For PHY setup/teardown */
875 int (*phy_init)(struct xgbe_prv_data *);
876 void (*phy_exit)(struct xgbe_prv_data *);
877
878 /* For PHY support when setting device up/down */
879 int (*phy_reset)(struct xgbe_prv_data *);
880 int (*phy_start)(struct xgbe_prv_data *);
881 void (*phy_stop)(struct xgbe_prv_data *);
882
883 /* For PHY support while device is up */
884 void (*phy_status)(struct xgbe_prv_data *);
885 int (*phy_config_aneg)(struct xgbe_prv_data *);
886
887 /* For PHY settings validation */
888 bool (*phy_valid_speed)(struct xgbe_prv_data *, int);
889
890 /* For single interrupt support */
891 irqreturn_t (*an_isr)(struct xgbe_prv_data *);
892
893 /* For ethtool PHY support */
894 int (*module_info)(struct xgbe_prv_data *pdata,
895 struct ethtool_modinfo *modinfo);
896 int (*module_eeprom)(struct xgbe_prv_data *pdata,
897 struct ethtool_eeprom *eeprom, u8 *data);
898
899 /* PHY implementation specific services */
900 struct xgbe_phy_impl_if phy_impl;
901 };
902
903 struct xgbe_i2c_if {
904 /* For initial I2C setup */
905 int (*i2c_init)(struct xgbe_prv_data *);
906
907 /* For I2C support when setting device up/down */
908 int (*i2c_start)(struct xgbe_prv_data *);
909 void (*i2c_stop)(struct xgbe_prv_data *);
910
911 /* For performing I2C operations */
912 int (*i2c_xfer)(struct xgbe_prv_data *, struct xgbe_i2c_op *);
913
914 /* For single interrupt support */
915 irqreturn_t (*i2c_isr)(struct xgbe_prv_data *);
916 };
917
918 struct xgbe_desc_if {
919 int (*alloc_ring_resources)(struct xgbe_prv_data *);
920 void (*free_ring_resources)(struct xgbe_prv_data *);
921 int (*map_tx_skb)(struct xgbe_channel *, struct sk_buff *);
922 int (*map_rx_buffer)(struct xgbe_prv_data *, struct xgbe_ring *,
923 struct xgbe_ring_data *);
924 void (*unmap_rdata)(struct xgbe_prv_data *, struct xgbe_ring_data *);
925 void (*wrapper_tx_desc_init)(struct xgbe_prv_data *);
926 void (*wrapper_rx_desc_init)(struct xgbe_prv_data *);
927 };
928
929 /* This structure contains flags that indicate what hardware features
930 * or configurations are present in the device.
931 */
932 struct xgbe_hw_features {
933 /* HW Version */
934 unsigned int version;
935
936 /* HW Feature Register0 */
937 unsigned int gmii; /* 1000 Mbps support */
938 unsigned int vlhash; /* VLAN Hash Filter */
939 unsigned int sma; /* SMA(MDIO) Interface */
940 unsigned int rwk; /* PMT remote wake-up packet */
941 unsigned int mgk; /* PMT magic packet */
942 unsigned int mmc; /* RMON module */
943 unsigned int aoe; /* ARP Offload */
944 unsigned int ts; /* IEEE 1588-2008 Advanced Timestamp */
945 unsigned int eee; /* Energy Efficient Ethernet */
946 unsigned int tx_coe; /* Tx Checksum Offload */
947 unsigned int rx_coe; /* Rx Checksum Offload */
948 unsigned int addn_mac; /* Additional MAC Addresses */
949 unsigned int ts_src; /* Timestamp Source */
950 unsigned int sa_vlan_ins; /* Source Address or VLAN Insertion */
951 unsigned int vxn; /* VXLAN/NVGRE */
952
953 /* HW Feature Register1 */
954 unsigned int rx_fifo_size; /* MTL Receive FIFO Size */
955 unsigned int tx_fifo_size; /* MTL Transmit FIFO Size */
956 unsigned int adv_ts_hi; /* Advance Timestamping High Word */
957 unsigned int dma_width; /* DMA width */
958 unsigned int dcb; /* DCB Feature */
959 unsigned int sph; /* Split Header Feature */
960 unsigned int tso; /* TCP Segmentation Offload */
961 unsigned int dma_debug; /* DMA Debug Registers */
962 unsigned int rss; /* Receive Side Scaling */
963 unsigned int tc_cnt; /* Number of Traffic Classes */
964 unsigned int hash_table_size; /* Hash Table Size */
965 unsigned int l3l4_filter_num; /* Number of L3-L4 Filters */
966
967 /* HW Feature Register2 */
968 unsigned int rx_q_cnt; /* Number of MTL Receive Queues */
969 unsigned int tx_q_cnt; /* Number of MTL Transmit Queues */
970 unsigned int rx_ch_cnt; /* Number of DMA Receive Channels */
971 unsigned int tx_ch_cnt; /* Number of DMA Transmit Channels */
972 unsigned int pps_out_num; /* Number of PPS outputs */
973 unsigned int aux_snap_num; /* Number of Aux snapshot inputs */
974 };
975
976 struct xgbe_version_data {
977 void (*init_function_ptrs_phy_impl)(struct xgbe_phy_if *);
978 enum xgbe_xpcs_access xpcs_access;
979 unsigned int mmc_64bit;
980 unsigned int tx_max_fifo_size;
981 unsigned int rx_max_fifo_size;
982 unsigned int tx_tstamp_workaround;
983 unsigned int tstamp_ptp_clock_freq;
984 unsigned int ecc_support;
985 unsigned int i2c_support;
986 unsigned int irq_reissue_support;
987 unsigned int tx_desc_prefetch;
988 unsigned int rx_desc_prefetch;
989 unsigned int an_cdr_workaround;
990 unsigned int enable_rrc;
991 };
992
993 struct xgbe_prv_data {
994 struct net_device *netdev;
995 struct pci_dev *pcidev;
996 struct platform_device *platdev;
997 struct acpi_device *adev;
998 struct device *dev;
999 struct platform_device *phy_platdev;
1000 struct device *phy_dev;
1001 unsigned int smn_base;
1002
1003 /* Version related data */
1004 struct xgbe_version_data *vdata;
1005
1006 /* ACPI or DT flag */
1007 unsigned int use_acpi;
1008
1009 /* XGMAC/XPCS related mmio registers */
1010 void __iomem *xgmac_regs; /* XGMAC CSRs */
1011 void __iomem *xpcs_regs; /* XPCS MMD registers */
1012 void __iomem *rxtx_regs; /* SerDes Rx/Tx CSRs */
1013 void __iomem *sir0_regs; /* SerDes integration registers (1/2) */
1014 void __iomem *sir1_regs; /* SerDes integration registers (2/2) */
1015 void __iomem *xprop_regs; /* XGBE property registers */
1016 void __iomem *xi2c_regs; /* XGBE I2C CSRs */
1017
1018 /* Port property registers */
1019 unsigned int pp0;
1020 unsigned int pp1;
1021 unsigned int pp2;
1022 unsigned int pp3;
1023 unsigned int pp4;
1024
1025 /* XPCS indirect addressing lock */
1026 spinlock_t xpcs_lock;
1027 unsigned int xpcs_window_def_reg;
1028 unsigned int xpcs_window_sel_reg;
1029 unsigned int xpcs_window;
1030 unsigned int xpcs_window_size;
1031 unsigned int xpcs_window_mask;
1032
1033 /* RSS addressing mutex */
1034 struct mutex rss_mutex;
1035
1036 /* Flags representing xgbe_state */
1037 unsigned long dev_state;
1038
1039 /* ECC support */
1040 unsigned long tx_sec_period;
1041 unsigned long tx_ded_period;
1042 unsigned long rx_sec_period;
1043 unsigned long rx_ded_period;
1044 unsigned long desc_sec_period;
1045 unsigned long desc_ded_period;
1046
1047 unsigned int tx_sec_count;
1048 unsigned int tx_ded_count;
1049 unsigned int rx_sec_count;
1050 unsigned int rx_ded_count;
1051 unsigned int desc_ded_count;
1052 unsigned int desc_sec_count;
1053
1054 int dev_irq;
1055 int ecc_irq;
1056 int i2c_irq;
1057 int channel_irq[XGBE_MAX_DMA_CHANNELS];
1058
1059 unsigned int per_channel_irq;
1060 unsigned int irq_count;
1061 unsigned int channel_irq_count;
1062 unsigned int channel_irq_mode;
1063
1064 char ecc_name[IFNAMSIZ + 32];
1065
1066 struct xgbe_hw_if hw_if;
1067 struct xgbe_phy_if phy_if;
1068 struct xgbe_desc_if desc_if;
1069 struct xgbe_i2c_if i2c_if;
1070
1071 /* AXI DMA settings */
1072 unsigned int coherent;
1073 unsigned int arcr;
1074 unsigned int awcr;
1075 unsigned int awarcr;
1076
1077 /* Service routine support */
1078 struct workqueue_struct *dev_workqueue;
1079 struct work_struct service_work;
1080 struct timer_list service_timer;
1081
1082 /* Rings for Tx/Rx on a DMA channel */
1083 struct xgbe_channel *channel[XGBE_MAX_DMA_CHANNELS];
1084 unsigned int tx_max_channel_count;
1085 unsigned int rx_max_channel_count;
1086 unsigned int channel_count;
1087 unsigned int tx_ring_count;
1088 unsigned int tx_desc_count;
1089 unsigned int rx_ring_count;
1090 unsigned int rx_desc_count;
1091
1092 unsigned int new_tx_ring_count;
1093 unsigned int new_rx_ring_count;
1094
1095 unsigned int tx_max_q_count;
1096 unsigned int rx_max_q_count;
1097 unsigned int tx_q_count;
1098 unsigned int rx_q_count;
1099
1100 /* Tx/Rx common settings */
1101 unsigned int blen;
1102 unsigned int pbl;
1103 unsigned int aal;
1104 unsigned int rd_osr_limit;
1105 unsigned int wr_osr_limit;
1106
1107 /* Tx settings */
1108 unsigned int tx_sf_mode;
1109 unsigned int tx_threshold;
1110 unsigned int tx_osp_mode;
1111 unsigned int tx_max_fifo_size;
1112
1113 /* Rx settings */
1114 unsigned int rx_sf_mode;
1115 unsigned int rx_threshold;
1116 unsigned int rx_max_fifo_size;
1117
1118 /* Tx coalescing settings */
1119 unsigned int tx_usecs;
1120 unsigned int tx_frames;
1121
1122 /* Rx coalescing settings */
1123 unsigned int rx_riwt;
1124 unsigned int rx_usecs;
1125 unsigned int rx_frames;
1126
1127 /* Current Rx buffer size */
1128 unsigned int rx_buf_size;
1129
1130 /* Flow control settings */
1131 unsigned int pause_autoneg;
1132 unsigned int tx_pause;
1133 unsigned int rx_pause;
1134 unsigned int rx_rfa[XGBE_MAX_QUEUES];
1135 unsigned int rx_rfd[XGBE_MAX_QUEUES];
1136
1137 /* Receive Side Scaling settings */
1138 u8 rss_key[XGBE_RSS_HASH_KEY_SIZE];
1139 u32 rss_table[XGBE_RSS_MAX_TABLE_SIZE];
1140 u32 rss_options;
1141
1142 /* VXLAN settings */
1143 u16 vxlan_port;
1144
1145 /* Netdev related settings */
1146 unsigned char mac_addr[ETH_ALEN];
1147 netdev_features_t netdev_features;
1148 struct napi_struct napi;
1149 struct xgbe_mmc_stats mmc_stats;
1150 struct xgbe_ext_stats ext_stats;
1151
1152 /* Filtering support */
1153 unsigned long active_vlans[BITS_TO_LONGS(VLAN_N_VID)];
1154
1155 /* Device clocks */
1156 struct clk *sysclk;
1157 unsigned long sysclk_rate;
1158 struct clk *ptpclk;
1159 unsigned long ptpclk_rate;
1160
1161 /* Timestamp support */
1162 spinlock_t tstamp_lock;
1163 struct ptp_clock_info ptp_clock_info;
1164 struct ptp_clock *ptp_clock;
1165 struct kernel_hwtstamp_config tstamp_config;
1166 unsigned int tstamp_addend;
1167 struct work_struct tx_tstamp_work;
1168 struct sk_buff *tx_tstamp_skb;
1169 u64 tx_tstamp;
1170
1171 /* Pulse Per Second output */
1172 struct xgbe_pps_config pps[XGBE_MAX_PPS_OUT];
1173
1174 /* DCB support */
1175 struct ieee_ets *ets;
1176 struct ieee_pfc *pfc;
1177 unsigned int q2tc_map[XGBE_MAX_QUEUES];
1178 unsigned int prio2q_map[IEEE_8021QAZ_MAX_TCS];
1179 unsigned int pfcq[XGBE_MAX_QUEUES];
1180 unsigned int pfc_rfa;
1181 u8 num_tcs;
1182
1183 /* Hardware features of the device */
1184 struct xgbe_hw_features hw_feat;
1185
1186 /* Device work structures */
1187 struct work_struct restart_work;
1188 struct work_struct stopdev_work;
1189
1190 /* Keeps track of power mode */
1191 unsigned int power_down;
1192
1193 /* Network interface message level setting */
1194 u32 msg_enable;
1195
1196 /* Current PHY settings */
1197 phy_interface_t phy_mode;
1198 int phy_link;
1199 int phy_speed;
1200
1201 /* MDIO/PHY related settings */
1202 unsigned int phy_started;
1203 void *phy_data;
1204 struct xgbe_phy phy;
1205 int mdio_mmd;
1206 unsigned long link_check;
1207 struct completion mdio_complete;
1208
1209 unsigned int kr_redrv;
1210
1211 char an_name[IFNAMSIZ + 32];
1212 struct workqueue_struct *an_workqueue;
1213
1214 int an_irq;
1215 struct work_struct an_irq_work;
1216
1217 /* Auto-negotiation state machine support */
1218 unsigned int an_int;
1219 unsigned int an_status;
1220 struct mutex an_mutex;
1221 enum xgbe_an an_result;
1222 enum xgbe_an an_state;
1223 enum xgbe_rx kr_state;
1224 enum xgbe_rx kx_state;
1225 struct work_struct an_work;
1226 unsigned int an_again;
1227 unsigned int an_supported;
1228 unsigned int parallel_detect;
1229 unsigned int fec_ability;
1230 unsigned long an_start;
1231 unsigned long kr_start_time;
1232 enum xgbe_an_mode an_mode;
1233
1234 /* I2C support */
1235 struct xgbe_i2c i2c;
1236 struct mutex i2c_mutex;
1237 struct completion i2c_complete;
1238 char i2c_name[IFNAMSIZ + 32];
1239
1240 unsigned int lpm_ctrl; /* CTRL1 for resume */
1241
1242 unsigned int isr_as_bh_work;
1243 struct work_struct dev_bh_work;
1244 struct work_struct ecc_bh_work;
1245 struct work_struct i2c_bh_work;
1246 struct work_struct an_bh_work;
1247
1248 struct dentry *xgbe_debugfs;
1249
1250 unsigned int debugfs_xgmac_reg;
1251
1252 unsigned int debugfs_xpcs_mmd;
1253 unsigned int debugfs_xpcs_reg;
1254
1255 unsigned int debugfs_xprop_reg;
1256
1257 unsigned int debugfs_xi2c_reg;
1258
1259 bool debugfs_an_cdr_workaround;
1260 bool debugfs_an_cdr_track_early;
1261 bool en_rx_adap;
1262 int rx_adapt_retries;
1263 bool rx_adapt_done;
1264 /* Flag to track if data path (TX/RX) was stopped for RX adaptation.
1265 * This prevents packet corruption during the adaptation window.
1266 */
1267 bool data_path_stopped;
1268 bool mode_set;
1269 bool sph;
1270 };
1271
1272 /* Function prototypes*/
1273 struct xgbe_prv_data *xgbe_alloc_pdata(struct device *);
1274 void xgbe_free_pdata(struct xgbe_prv_data *);
1275 void xgbe_set_counts(struct xgbe_prv_data *);
1276 int xgbe_config_netdev(struct xgbe_prv_data *);
1277 void xgbe_deconfig_netdev(struct xgbe_prv_data *);
1278
1279 int xgbe_platform_init(void);
1280 void xgbe_platform_exit(void);
1281 #ifdef CONFIG_PCI
1282 int xgbe_pci_init(void);
1283 void xgbe_pci_exit(void);
1284 #else
xgbe_pci_init(void)1285 static inline int xgbe_pci_init(void) { return 0; }
xgbe_pci_exit(void)1286 static inline void xgbe_pci_exit(void) { }
1287 #endif
1288
1289 void xgbe_init_function_ptrs_dev(struct xgbe_hw_if *);
1290 void xgbe_init_function_ptrs_phy(struct xgbe_phy_if *);
1291 void xgbe_init_function_ptrs_phy_v1(struct xgbe_phy_if *);
1292 void xgbe_init_function_ptrs_phy_v2(struct xgbe_phy_if *);
1293 void xgbe_init_function_ptrs_desc(struct xgbe_desc_if *);
1294 void xgbe_init_function_ptrs_i2c(struct xgbe_i2c_if *);
1295 const struct net_device_ops *xgbe_get_netdev_ops(void);
1296 const struct ethtool_ops *xgbe_get_ethtool_ops(void);
1297 const struct udp_tunnel_nic_info *xgbe_get_udp_tunnel_info(void);
1298
1299 #ifdef CONFIG_AMD_XGBE_DCB
1300 const struct dcbnl_rtnl_ops *xgbe_get_dcbnl_ops(void);
1301 #endif
1302
1303 void xgbe_ptp_register(struct xgbe_prv_data *);
1304 void xgbe_ptp_unregister(struct xgbe_prv_data *);
1305 void xgbe_dump_tx_desc(struct xgbe_prv_data *, struct xgbe_ring *,
1306 unsigned int, unsigned int, unsigned int);
1307 void xgbe_dump_rx_desc(struct xgbe_prv_data *, struct xgbe_ring *,
1308 unsigned int);
1309 void xgbe_print_pkt(struct net_device *, struct sk_buff *, bool);
1310 void xgbe_get_all_hw_features(struct xgbe_prv_data *);
1311 int xgbe_powerup(struct net_device *netdev);
1312 int xgbe_powerdown(struct net_device *netdev);
1313 void xgbe_init_rx_coalesce(struct xgbe_prv_data *);
1314 void xgbe_init_tx_coalesce(struct xgbe_prv_data *);
1315 void xgbe_restart_dev(struct xgbe_prv_data *pdata);
1316 void xgbe_full_restart_dev(struct xgbe_prv_data *pdata);
1317
1318 /* For Timestamp config */
1319 void xgbe_config_tstamp(struct xgbe_prv_data *pdata, unsigned int mac_tscr);
1320 u64 xgbe_get_tstamp_time(struct xgbe_prv_data *pdata);
1321 u64 xgbe_get_tx_tstamp(struct xgbe_prv_data *pdata);
1322 void xgbe_get_rx_tstamp(struct xgbe_packet_data *packet,
1323 struct xgbe_ring_desc *rdesc);
1324 void xgbe_get_rx_tstamp(struct xgbe_packet_data *packet,
1325 struct xgbe_ring_desc *rdesc);
1326 void xgbe_update_tstamp_addend(struct xgbe_prv_data *pdata,
1327 unsigned int addend);
1328 void xgbe_set_tstamp_time(struct xgbe_prv_data *pdata, unsigned int sec,
1329 unsigned int nsec);
1330 void xgbe_tx_tstamp(struct work_struct *work);
1331 int xgbe_get_hwtstamp_settings(struct net_device *netdev,
1332 struct kernel_hwtstamp_config *config);
1333 int xgbe_set_hwtstamp_settings(struct net_device *netdev,
1334 struct kernel_hwtstamp_config *config,
1335 struct netlink_ext_ack *extack);
1336 void xgbe_prep_tx_tstamp(struct xgbe_prv_data *pdata,
1337 struct sk_buff *skb,
1338 struct xgbe_packet_data *packet);
1339 int xgbe_init_ptp(struct xgbe_prv_data *pdata);
1340 void xgbe_update_tstamp_time(struct xgbe_prv_data *pdata, unsigned int sec,
1341 unsigned int nsec);
1342
1343 int xgbe_pps_config(struct xgbe_prv_data *pdata, struct xgbe_pps_config *cfg,
1344 int index, bool on);
1345
1346 /* Selftest functions */
1347 void xgbe_selftest_run(struct net_device *dev,
1348 struct ethtool_test *etest, u64 *buf);
1349 void xgbe_selftest_get_strings(struct xgbe_prv_data *pdata, u8 *data);
1350 int xgbe_selftest_get_count(struct xgbe_prv_data *pdata);
1351
1352 /* Loopback control */
1353 int xgbe_enable_mac_loopback(struct xgbe_prv_data *pdata);
1354 void xgbe_disable_mac_loopback(struct xgbe_prv_data *pdata);
1355
1356 #ifdef CONFIG_DEBUG_FS
1357 void xgbe_debugfs_init(struct xgbe_prv_data *);
1358 void xgbe_debugfs_exit(struct xgbe_prv_data *);
1359 void xgbe_debugfs_rename(struct xgbe_prv_data *pdata);
1360 #else
xgbe_debugfs_init(struct xgbe_prv_data * pdata)1361 static inline void xgbe_debugfs_init(struct xgbe_prv_data *pdata) {}
xgbe_debugfs_exit(struct xgbe_prv_data * pdata)1362 static inline void xgbe_debugfs_exit(struct xgbe_prv_data *pdata) {}
xgbe_debugfs_rename(struct xgbe_prv_data * pdata)1363 static inline void xgbe_debugfs_rename(struct xgbe_prv_data *pdata) {}
1364 #endif /* CONFIG_DEBUG_FS */
1365
1366 /* NOTE: Uncomment for function trace log messages in KERNEL LOG */
1367 #if 0
1368 #define YDEBUG
1369 #define YDEBUG_MDIO
1370 #endif
1371
1372 /* For debug prints */
1373 #ifdef YDEBUG
1374 #define DBGPR(x...) pr_alert(x)
1375 #else
1376 #define DBGPR(x...) do { } while (0)
1377 #endif
1378
1379 #ifdef YDEBUG_MDIO
1380 #define DBGPR_MDIO(x...) pr_alert(x)
1381 #else
1382 #define DBGPR_MDIO(x...) do { } while (0)
1383 #endif
1384
1385 #endif
1386