1 /* 2 * Copyright 2012-15 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 * Authors: AMD 23 * 24 */ 25 26 #ifndef __DC_TIMING_GENERATOR_DCN10_H__ 27 #define __DC_TIMING_GENERATOR_DCN10_H__ 28 29 #include "optc.h" 30 31 #define DCN10TG_FROM_TG(tg)\ 32 container_of(tg, struct optc, base) 33 34 #define TG_COMMON_REG_LIST_DCN(inst) \ 35 SRI(OTG_VSTARTUP_PARAM, OTG, inst),\ 36 SRI(OTG_VUPDATE_PARAM, OTG, inst),\ 37 SRI(OTG_VREADY_PARAM, OTG, inst),\ 38 SRI(OTG_BLANK_CONTROL, OTG, inst),\ 39 SRI(OTG_MASTER_UPDATE_LOCK, OTG, inst),\ 40 SRI(OTG_GLOBAL_CONTROL0, OTG, inst),\ 41 SRI(OTG_DOUBLE_BUFFER_CONTROL, OTG, inst),\ 42 SRI(OTG_H_TOTAL, OTG, inst),\ 43 SRI(OTG_H_BLANK_START_END, OTG, inst),\ 44 SRI(OTG_H_SYNC_A, OTG, inst),\ 45 SRI(OTG_H_SYNC_A_CNTL, OTG, inst),\ 46 SRI(OTG_H_TIMING_CNTL, OTG, inst),\ 47 SRI(OTG_V_TOTAL, OTG, inst),\ 48 SRI(OTG_V_BLANK_START_END, OTG, inst),\ 49 SRI(OTG_V_SYNC_A, OTG, inst),\ 50 SRI(OTG_V_SYNC_A_CNTL, OTG, inst),\ 51 SRI(OTG_INTERLACE_CONTROL, OTG, inst),\ 52 SRI(OTG_CONTROL, OTG, inst),\ 53 SRI(OTG_STEREO_CONTROL, OTG, inst),\ 54 SRI(OTG_3D_STRUCTURE_CONTROL, OTG, inst),\ 55 SRI(OTG_STEREO_STATUS, OTG, inst),\ 56 SRI(OTG_V_TOTAL_MAX, OTG, inst),\ 57 SRI(OTG_V_TOTAL_MID, OTG, inst),\ 58 SRI(OTG_V_TOTAL_MIN, OTG, inst),\ 59 SRI(OTG_V_TOTAL_CONTROL, OTG, inst),\ 60 SRI(OTG_TRIGA_CNTL, OTG, inst),\ 61 SRI(OTG_FORCE_COUNT_NOW_CNTL, OTG, inst),\ 62 SRI(OTG_STATIC_SCREEN_CONTROL, OTG, inst),\ 63 SRI(OTG_STATUS_FRAME_COUNT, OTG, inst),\ 64 SRI(OTG_STATUS, OTG, inst),\ 65 SRI(OTG_STATUS_POSITION, OTG, inst),\ 66 SRI(OTG_NOM_VERT_POSITION, OTG, inst),\ 67 SRI(OTG_BLACK_COLOR, OTG, inst),\ 68 SRI(OTG_CLOCK_CONTROL, OTG, inst),\ 69 SRI(OTG_VERTICAL_INTERRUPT0_CONTROL, OTG, inst),\ 70 SRI(OTG_VERTICAL_INTERRUPT0_POSITION, OTG, inst),\ 71 SRI(OTG_VERTICAL_INTERRUPT1_CONTROL, OTG, inst),\ 72 SRI(OTG_VERTICAL_INTERRUPT1_POSITION, OTG, inst),\ 73 SRI(OTG_VERTICAL_INTERRUPT2_CONTROL, OTG, inst),\ 74 SRI(OTG_VERTICAL_INTERRUPT2_POSITION, OTG, inst),\ 75 SRI(OPTC_INPUT_CLOCK_CONTROL, ODM, inst),\ 76 SRI(OPTC_DATA_SOURCE_SELECT, ODM, inst),\ 77 SRI(OPTC_INPUT_GLOBAL_CONTROL, ODM, inst),\ 78 SRI(CONTROL, VTG, inst),\ 79 SRI(OTG_VERT_SYNC_CONTROL, OTG, inst),\ 80 SRI(OTG_MASTER_UPDATE_MODE, OTG, inst),\ 81 SRI(OTG_GSL_CONTROL, OTG, inst),\ 82 SRI(OTG_CRC_CNTL, OTG, inst),\ 83 SRI(OTG_CRC0_DATA_RG, OTG, inst),\ 84 SRI(OTG_CRC0_DATA_B, OTG, inst),\ 85 SRI(OTG_CRC0_WINDOWA_X_CONTROL, OTG, inst),\ 86 SRI(OTG_CRC0_WINDOWA_Y_CONTROL, OTG, inst),\ 87 SRI(OTG_CRC0_WINDOWB_X_CONTROL, OTG, inst),\ 88 SRI(OTG_CRC0_WINDOWB_Y_CONTROL, OTG, inst),\ 89 SRI(OTG_CRC1_DATA_RG, OTG, inst),\ 90 SRI(OTG_CRC1_DATA_B, OTG, inst),\ 91 SRI(OTG_CRC1_WINDOWA_X_CONTROL, OTG, inst),\ 92 SRI(OTG_CRC1_WINDOWA_Y_CONTROL, OTG, inst),\ 93 SRI(OTG_CRC1_WINDOWB_X_CONTROL, OTG, inst),\ 94 SRI(OTG_CRC1_WINDOWB_Y_CONTROL, OTG, inst),\ 95 SR(GSL_SOURCE_SELECT),\ 96 SRI(OTG_GLOBAL_CONTROL2, OTG, inst),\ 97 SRI(OTG_TRIGA_MANUAL_TRIG, OTG, inst) 98 99 #define TG_COMMON_REG_LIST_DCN1_0(inst) \ 100 TG_COMMON_REG_LIST_DCN(inst),\ 101 SRI(OTG_TEST_PATTERN_PARAMETERS, OTG, inst),\ 102 SRI(OTG_TEST_PATTERN_CONTROL, OTG, inst),\ 103 SRI(OTG_TEST_PATTERN_COLOR, OTG, inst),\ 104 SRI(OTG_MANUAL_FLOW_CONTROL, OTG, inst) 105 106 107 #define OPTC_REG_VARIABLE_LIST_DCN \ 108 uint32_t OTG_GLOBAL_CONTROL1; \ 109 uint32_t OTG_GLOBAL_CONTROL2; \ 110 uint32_t OTG_VERT_SYNC_CONTROL; \ 111 uint32_t OTG_MASTER_UPDATE_MODE; \ 112 uint32_t OTG_GSL_CONTROL; \ 113 uint32_t OTG_VSTARTUP_PARAM; \ 114 uint32_t OTG_VUPDATE_PARAM; \ 115 uint32_t OTG_VREADY_PARAM; \ 116 uint32_t OTG_BLANK_CONTROL; \ 117 uint32_t OTG_MASTER_UPDATE_LOCK; \ 118 uint32_t OTG_GLOBAL_CONTROL0; \ 119 uint32_t OTG_DOUBLE_BUFFER_CONTROL; \ 120 uint32_t OTG_H_TOTAL; \ 121 uint32_t OTG_H_BLANK_START_END; \ 122 uint32_t OTG_H_SYNC_A; \ 123 uint32_t OTG_H_SYNC_A_CNTL; \ 124 uint32_t OTG_H_TIMING_CNTL; \ 125 uint32_t OTG_V_TOTAL; \ 126 uint32_t OTG_V_BLANK_START_END; \ 127 uint32_t OTG_V_SYNC_A; \ 128 uint32_t OTG_V_SYNC_A_CNTL; \ 129 uint32_t OTG_INTERLACE_CONTROL; \ 130 uint32_t OTG_CONTROL; \ 131 uint32_t OTG_STEREO_CONTROL; \ 132 uint32_t OTG_3D_STRUCTURE_CONTROL; \ 133 uint32_t OTG_STEREO_STATUS; \ 134 uint32_t OTG_V_TOTAL_MAX; \ 135 uint32_t OTG_V_TOTAL_MID; \ 136 uint32_t OTG_V_TOTAL_MIN; \ 137 uint32_t OTG_V_TOTAL_CONTROL; \ 138 uint32_t OTG_V_COUNT_STOP_CONTROL; \ 139 uint32_t OTG_V_COUNT_STOP_CONTROL2; \ 140 uint32_t OTG_TRIGA_CNTL; \ 141 uint32_t OTG_TRIGA_MANUAL_TRIG; \ 142 uint32_t OTG_MANUAL_FLOW_CONTROL; \ 143 uint32_t OTG_FORCE_COUNT_NOW_CNTL; \ 144 uint32_t OTG_STATIC_SCREEN_CONTROL; \ 145 uint32_t OTG_STATUS_FRAME_COUNT; \ 146 uint32_t OTG_STATUS; \ 147 uint32_t OTG_STATUS_POSITION; \ 148 uint32_t OTG_NOM_VERT_POSITION; \ 149 uint32_t OTG_BLACK_COLOR; \ 150 uint32_t OTG_TEST_PATTERN_PARAMETERS; \ 151 uint32_t OTG_TEST_PATTERN_CONTROL; \ 152 uint32_t OTG_TEST_PATTERN_COLOR; \ 153 uint32_t OTG_CLOCK_CONTROL; \ 154 uint32_t OTG_VERTICAL_INTERRUPT0_CONTROL; \ 155 uint32_t OTG_VERTICAL_INTERRUPT0_POSITION; \ 156 uint32_t OTG_VERTICAL_INTERRUPT1_CONTROL; \ 157 uint32_t OTG_VERTICAL_INTERRUPT1_POSITION; \ 158 uint32_t OTG_VERTICAL_INTERRUPT2_CONTROL; \ 159 uint32_t OTG_VERTICAL_INTERRUPT2_POSITION; \ 160 uint32_t OPTC_INPUT_CLOCK_CONTROL; \ 161 uint32_t OPTC_DATA_SOURCE_SELECT; \ 162 uint32_t OPTC_MEMORY_CONFIG; \ 163 uint32_t OPTC_INPUT_GLOBAL_CONTROL; \ 164 uint32_t CONTROL; \ 165 uint32_t OTG_GSL_WINDOW_X; \ 166 uint32_t OTG_GSL_WINDOW_Y; \ 167 uint32_t OTG_VUPDATE_KEEPOUT; \ 168 uint32_t OTG_CRC_CNTL; \ 169 uint32_t OTG_CRC_CNTL2; \ 170 uint32_t OTG_CRC0_DATA_RG; \ 171 uint32_t OTG_CRC0_DATA_B; \ 172 uint32_t OTG_CRC1_DATA_B; \ 173 uint32_t OTG_CRC2_DATA_B; \ 174 uint32_t OTG_CRC3_DATA_B; \ 175 uint32_t OTG_CRC1_DATA_RG; \ 176 uint32_t OTG_CRC2_DATA_RG; \ 177 uint32_t OTG_CRC3_DATA_RG; \ 178 uint32_t OTG_CRC0_WINDOWA_X_CONTROL; \ 179 uint32_t OTG_CRC0_WINDOWA_Y_CONTROL; \ 180 uint32_t OTG_CRC0_WINDOWB_X_CONTROL; \ 181 uint32_t OTG_CRC0_WINDOWB_Y_CONTROL; \ 182 uint32_t OTG_CRC1_WINDOWA_X_CONTROL; \ 183 uint32_t OTG_CRC1_WINDOWA_Y_CONTROL; \ 184 uint32_t OTG_CRC1_WINDOWB_X_CONTROL; \ 185 uint32_t OTG_CRC1_WINDOWB_Y_CONTROL; \ 186 uint32_t GSL_SOURCE_SELECT; \ 187 uint32_t DWB_SOURCE_SELECT; \ 188 uint32_t OTG_DSC_START_POSITION; \ 189 uint32_t OPTC_DATA_FORMAT_CONTROL; \ 190 uint32_t OPTC_BYTES_PER_PIXEL; \ 191 uint32_t OPTC_WIDTH_CONTROL; \ 192 uint32_t OTG_DRR_CONTROL; \ 193 uint32_t OTG_BLANK_DATA_COLOR; \ 194 uint32_t OTG_BLANK_DATA_COLOR_EXT; \ 195 uint32_t OTG_DRR_TRIGGER_WINDOW; \ 196 uint32_t OTG_M_CONST_DTO0; \ 197 uint32_t OTG_M_CONST_DTO1; \ 198 uint32_t OTG_DRR_V_TOTAL_CHANGE; \ 199 uint32_t OTG_GLOBAL_CONTROL4; \ 200 uint32_t OTG_CRC0_WINDOWA_X_CONTROL_READBACK; \ 201 uint32_t OTG_CRC0_WINDOWA_Y_CONTROL_READBACK; \ 202 uint32_t OTG_CRC0_WINDOWB_X_CONTROL_READBACK; \ 203 uint32_t OTG_CRC0_WINDOWB_Y_CONTROL_READBACK; \ 204 uint32_t OTG_CRC1_WINDOWA_X_CONTROL_READBACK; \ 205 uint32_t OTG_CRC1_WINDOWA_Y_CONTROL_READBACK; \ 206 uint32_t OTG_CRC1_WINDOWB_X_CONTROL_READBACK; \ 207 uint32_t OTG_CRC1_WINDOWB_Y_CONTROL_READBACK; \ 208 uint32_t OPTC_CLOCK_CONTROL; \ 209 uint32_t OPTC_WIDTH_CONTROL2; \ 210 uint32_t OTG_PSTATE_REGISTER; \ 211 uint32_t OTG_PIPE_UPDATE_STATUS; \ 212 uint32_t INTERRUPT_DEST; \ 213 uint32_t OPTC_INPUT_SPARE_REGISTER; \ 214 uint32_t OPTC_RSMU_UNDERFLOW; \ 215 uint32_t OPTC_UNDERFLOW_THRESHOLD; \ 216 uint32_t OTG_COUNT_CONTROL; \ 217 uint32_t OTG_COUNT_RESET; \ 218 uint32_t OTG_CRC_SIG_BLUE_CONTROL_MASK; \ 219 uint32_t OTG_CRC_SIG_RED_GREEN_MASK; \ 220 uint32_t OTG_DLPC_CONTROL; \ 221 uint32_t OTG_DRR_CONTROL2; \ 222 uint32_t OTG_DRR_TIMING_INT_STATUS; \ 223 uint32_t OTG_GLOBAL_CONTROL3; \ 224 uint32_t OTG_GLOBAL_SYNC_STATUS; \ 225 uint32_t OTG_GSL_VSYNC_GAP; \ 226 uint32_t OTG_INTERLACE_STATUS; \ 227 uint32_t OTG_INTERRUPT_CONTROL; \ 228 uint32_t OTG_LONG_VBLANK_STATUS; \ 229 uint32_t OTG_MANUAL_FORCE_VSYNC_NEXT_LINE; \ 230 uint32_t OTG_MASTER_EN; \ 231 uint32_t OTG_PIXEL_DATA_READBACK0; \ 232 uint32_t OTG_PIXEL_DATA_READBACK1; \ 233 uint32_t OTG_REQUEST_CONTROL; \ 234 uint32_t OTG_SNAPSHOT_CONTROL; \ 235 uint32_t OTG_SNAPSHOT_FRAME; \ 236 uint32_t OTG_SNAPSHOT_POSITION; \ 237 uint32_t OTG_SNAPSHOT_STATUS; \ 238 uint32_t OTG_SPARE_REGISTER; \ 239 uint32_t OTG_STATUS_HV_COUNT; \ 240 uint32_t OTG_STATUS_VF_COUNT; \ 241 uint32_t OTG_STEREO_FORCE_NEXT_EYE; \ 242 uint32_t OTG_TRIG_MANUAL_CONTROL; \ 243 uint32_t OTG_TRIGB_CNTL; \ 244 uint32_t OTG_TRIGB_MANUAL_TRIG; \ 245 uint32_t OTG_UPDATE_LOCK; \ 246 uint32_t OTG_V_TOTAL_INT_STATUS; \ 247 uint32_t OTG_VSYNC_NOM_INT_STATUS; \ 248 uint32_t OTG_CRC0_DATA_R32; \ 249 uint32_t OTG_CRC0_DATA_G32; \ 250 uint32_t OTG_CRC0_DATA_B32; \ 251 uint32_t OTG_CRC1_DATA_R32; \ 252 uint32_t OTG_CRC1_DATA_G32; \ 253 uint32_t OTG_CRC1_DATA_B32 254 255 256 struct dcn_optc_registers { 257 OPTC_REG_VARIABLE_LIST_DCN; 258 }; 259 260 #define TG_COMMON_MASK_SH_LIST_DCN(mask_sh)\ 261 SF(OTG0_OTG_VSTARTUP_PARAM, VSTARTUP_START, mask_sh),\ 262 SF(OTG0_OTG_VUPDATE_PARAM, VUPDATE_OFFSET, mask_sh),\ 263 SF(OTG0_OTG_VUPDATE_PARAM, VUPDATE_WIDTH, mask_sh),\ 264 SF(OTG0_OTG_VREADY_PARAM, VREADY_OFFSET, mask_sh),\ 265 SF(OTG0_OTG_BLANK_CONTROL, OTG_BLANK_DATA_EN, mask_sh),\ 266 SF(OTG0_OTG_BLANK_CONTROL, OTG_BLANK_DE_MODE, mask_sh),\ 267 SF(OTG0_OTG_BLANK_CONTROL, OTG_CURRENT_BLANK_STATE, mask_sh),\ 268 SF(OTG0_OTG_MASTER_UPDATE_LOCK, OTG_MASTER_UPDATE_LOCK, mask_sh),\ 269 SF(OTG0_OTG_MASTER_UPDATE_LOCK, UPDATE_LOCK_STATUS, mask_sh),\ 270 SF(OTG0_OTG_GLOBAL_CONTROL0, OTG_MASTER_UPDATE_LOCK_SEL, mask_sh),\ 271 SF(OTG0_OTG_DOUBLE_BUFFER_CONTROL, OTG_UPDATE_PENDING, mask_sh),\ 272 SF(OTG0_OTG_DOUBLE_BUFFER_CONTROL, OTG_BLANK_DATA_DOUBLE_BUFFER_EN, mask_sh),\ 273 SF(OTG0_OTG_DOUBLE_BUFFER_CONTROL, OTG_RANGE_TIMING_DBUF_UPDATE_MODE, mask_sh),\ 274 SF(OTG0_OTG_VUPDATE_KEEPOUT, OTG_MASTER_UPDATE_LOCK_VUPDATE_KEEPOUT_EN, mask_sh), \ 275 SF(OTG0_OTG_VUPDATE_KEEPOUT, MASTER_UPDATE_LOCK_VUPDATE_KEEPOUT_START_OFFSET, mask_sh), \ 276 SF(OTG0_OTG_VUPDATE_KEEPOUT, MASTER_UPDATE_LOCK_VUPDATE_KEEPOUT_END_OFFSET, mask_sh), \ 277 SF(OTG0_OTG_H_TOTAL, OTG_H_TOTAL, mask_sh),\ 278 SF(OTG0_OTG_H_BLANK_START_END, OTG_H_BLANK_START, mask_sh),\ 279 SF(OTG0_OTG_H_BLANK_START_END, OTG_H_BLANK_END, mask_sh),\ 280 SF(OTG0_OTG_H_SYNC_A, OTG_H_SYNC_A_START, mask_sh),\ 281 SF(OTG0_OTG_H_SYNC_A, OTG_H_SYNC_A_END, mask_sh),\ 282 SF(OTG0_OTG_H_SYNC_A_CNTL, OTG_H_SYNC_A_POL, mask_sh),\ 283 SF(OTG0_OTG_H_TIMING_CNTL, OTG_H_TIMING_DIV_BY2, mask_sh),\ 284 SF(OTG0_OTG_V_TOTAL, OTG_V_TOTAL, mask_sh),\ 285 SF(OTG0_OTG_V_BLANK_START_END, OTG_V_BLANK_START, mask_sh),\ 286 SF(OTG0_OTG_V_BLANK_START_END, OTG_V_BLANK_END, mask_sh),\ 287 SF(OTG0_OTG_V_SYNC_A, OTG_V_SYNC_A_START, mask_sh),\ 288 SF(OTG0_OTG_V_SYNC_A, OTG_V_SYNC_A_END, mask_sh),\ 289 SF(OTG0_OTG_V_SYNC_A_CNTL, OTG_V_SYNC_A_POL, mask_sh),\ 290 SF(OTG0_OTG_INTERLACE_CONTROL, OTG_INTERLACE_ENABLE, mask_sh),\ 291 SF(OTG0_OTG_CONTROL, OTG_MASTER_EN, mask_sh),\ 292 SF(OTG0_OTG_CONTROL, OTG_START_POINT_CNTL, mask_sh),\ 293 SF(OTG0_OTG_CONTROL, OTG_DISABLE_POINT_CNTL, mask_sh),\ 294 SF(OTG0_OTG_CONTROL, OTG_FIELD_NUMBER_CNTL, mask_sh),\ 295 SF(OTG0_OTG_CONTROL, OTG_CURRENT_MASTER_EN_STATE, mask_sh),\ 296 SF(OTG0_OTG_STEREO_CONTROL, OTG_STEREO_EN, mask_sh),\ 297 SF(OTG0_OTG_STEREO_CONTROL, OTG_STEREO_SYNC_OUTPUT_LINE_NUM, mask_sh),\ 298 SF(OTG0_OTG_STEREO_CONTROL, OTG_STEREO_SYNC_OUTPUT_POLARITY, mask_sh),\ 299 SF(OTG0_OTG_STEREO_CONTROL, OTG_STEREO_EYE_FLAG_POLARITY, mask_sh),\ 300 SF(OTG0_OTG_STEREO_CONTROL, OTG_DISABLE_STEREOSYNC_OUTPUT_FOR_DP, mask_sh),\ 301 SF(OTG0_OTG_STEREO_CONTROL, OTG_DISABLE_STEREOSYNC_OUTPUT_FOR_DP, mask_sh),\ 302 SF(OTG0_OTG_STEREO_STATUS, OTG_STEREO_CURRENT_EYE, mask_sh),\ 303 SF(OTG0_OTG_3D_STRUCTURE_CONTROL, OTG_3D_STRUCTURE_EN, mask_sh),\ 304 SF(OTG0_OTG_3D_STRUCTURE_CONTROL, OTG_3D_STRUCTURE_V_UPDATE_MODE, mask_sh),\ 305 SF(OTG0_OTG_3D_STRUCTURE_CONTROL, OTG_3D_STRUCTURE_STEREO_SEL_OVR, mask_sh),\ 306 SF(OTG0_OTG_V_TOTAL_MAX, OTG_V_TOTAL_MAX, mask_sh),\ 307 SF(OTG0_OTG_V_TOTAL_MID, OTG_V_TOTAL_MID, mask_sh),\ 308 SF(OTG0_OTG_V_TOTAL_MIN, OTG_V_TOTAL_MIN, mask_sh),\ 309 SF(OTG0_OTG_V_TOTAL_CONTROL, OTG_V_TOTAL_MIN_SEL, mask_sh),\ 310 SF(OTG0_OTG_V_TOTAL_CONTROL, OTG_V_TOTAL_MAX_SEL, mask_sh),\ 311 SF(OTG0_OTG_V_TOTAL_CONTROL, OTG_FORCE_LOCK_ON_EVENT, mask_sh),\ 312 SF(OTG0_OTG_V_TOTAL_CONTROL, OTG_SET_V_TOTAL_MIN_MASK_EN, mask_sh),\ 313 SF(OTG0_OTG_V_TOTAL_CONTROL, OTG_SET_V_TOTAL_MIN_MASK, mask_sh),\ 314 SF(OTG0_OTG_V_TOTAL_CONTROL, OTG_VTOTAL_MID_REPLACING_MAX_EN, mask_sh),\ 315 SF(OTG0_OTG_V_TOTAL_CONTROL, OTG_VTOTAL_MID_FRAME_NUM, mask_sh),\ 316 SF(OTG0_OTG_FORCE_COUNT_NOW_CNTL, OTG_FORCE_COUNT_NOW_CLEAR, mask_sh),\ 317 SF(OTG0_OTG_FORCE_COUNT_NOW_CNTL, OTG_FORCE_COUNT_NOW_MODE, mask_sh),\ 318 SF(OTG0_OTG_FORCE_COUNT_NOW_CNTL, OTG_FORCE_COUNT_NOW_OCCURRED, mask_sh),\ 319 SF(OTG0_OTG_TRIGA_CNTL, OTG_TRIGA_SOURCE_SELECT, mask_sh),\ 320 SF(OTG0_OTG_TRIGA_CNTL, OTG_TRIGA_SOURCE_PIPE_SELECT, mask_sh),\ 321 SF(OTG0_OTG_TRIGA_CNTL, OTG_TRIGA_RISING_EDGE_DETECT_CNTL, mask_sh),\ 322 SF(OTG0_OTG_TRIGA_CNTL, OTG_TRIGA_FALLING_EDGE_DETECT_CNTL, mask_sh),\ 323 SF(OTG0_OTG_TRIGA_CNTL, OTG_TRIGA_POLARITY_SELECT, mask_sh),\ 324 SF(OTG0_OTG_TRIGA_CNTL, OTG_TRIGA_FREQUENCY_SELECT, mask_sh),\ 325 SF(OTG0_OTG_TRIGA_CNTL, OTG_TRIGA_DELAY, mask_sh),\ 326 SF(OTG0_OTG_TRIGA_CNTL, OTG_TRIGA_CLEAR, mask_sh),\ 327 SF(OTG0_OTG_TRIGA_MANUAL_TRIG, OTG_TRIGA_MANUAL_TRIG, mask_sh),\ 328 SF(OTG0_OTG_STATIC_SCREEN_CONTROL, OTG_STATIC_SCREEN_EVENT_MASK, mask_sh),\ 329 SF(OTG0_OTG_STATIC_SCREEN_CONTROL, OTG_STATIC_SCREEN_FRAME_COUNT, mask_sh),\ 330 SF(OTG0_OTG_STATUS_FRAME_COUNT, OTG_FRAME_COUNT, mask_sh),\ 331 SF(OTG0_OTG_STATUS, OTG_V_BLANK, mask_sh),\ 332 SF(OTG0_OTG_STATUS, OTG_V_ACTIVE_DISP, mask_sh),\ 333 SF(OTG0_OTG_STATUS_POSITION, OTG_HORZ_COUNT, mask_sh),\ 334 SF(OTG0_OTG_STATUS_POSITION, OTG_VERT_COUNT, mask_sh),\ 335 SF(OTG0_OTG_NOM_VERT_POSITION, OTG_VERT_COUNT_NOM, mask_sh),\ 336 SF(OTG0_OTG_BLACK_COLOR, OTG_BLACK_COLOR_B_CB, mask_sh),\ 337 SF(OTG0_OTG_BLACK_COLOR, OTG_BLACK_COLOR_G_Y, mask_sh),\ 338 SF(OTG0_OTG_BLACK_COLOR, OTG_BLACK_COLOR_R_CR, mask_sh),\ 339 SF(OTG0_OTG_CLOCK_CONTROL, OTG_BUSY, mask_sh),\ 340 SF(OTG0_OTG_CLOCK_CONTROL, OTG_CLOCK_EN, mask_sh),\ 341 SF(OTG0_OTG_CLOCK_CONTROL, OTG_CLOCK_ON, mask_sh),\ 342 SF(OTG0_OTG_CLOCK_CONTROL, OTG_CLOCK_GATE_DIS, mask_sh),\ 343 SF(OTG0_OTG_VERTICAL_INTERRUPT0_CONTROL, OTG_VERTICAL_INTERRUPT0_INT_ENABLE, mask_sh),\ 344 SF(OTG0_OTG_VERTICAL_INTERRUPT0_POSITION, OTG_VERTICAL_INTERRUPT0_LINE_START, mask_sh),\ 345 SF(OTG0_OTG_VERTICAL_INTERRUPT0_POSITION, OTG_VERTICAL_INTERRUPT0_LINE_END, mask_sh),\ 346 SF(OTG0_OTG_VERTICAL_INTERRUPT1_CONTROL, OTG_VERTICAL_INTERRUPT1_INT_ENABLE, mask_sh),\ 347 SF(OTG0_OTG_VERTICAL_INTERRUPT1_POSITION, OTG_VERTICAL_INTERRUPT1_LINE_START, mask_sh),\ 348 SF(OTG0_OTG_VERTICAL_INTERRUPT2_CONTROL, OTG_VERTICAL_INTERRUPT2_INT_ENABLE, mask_sh),\ 349 SF(OTG0_OTG_VERTICAL_INTERRUPT2_POSITION, OTG_VERTICAL_INTERRUPT2_LINE_START, mask_sh),\ 350 SF(ODM0_OPTC_INPUT_CLOCK_CONTROL, OPTC_INPUT_CLK_EN, mask_sh),\ 351 SF(ODM0_OPTC_INPUT_CLOCK_CONTROL, OPTC_INPUT_CLK_ON, mask_sh),\ 352 SF(ODM0_OPTC_INPUT_CLOCK_CONTROL, OPTC_INPUT_CLK_GATE_DIS, mask_sh),\ 353 SF(ODM0_OPTC_INPUT_GLOBAL_CONTROL, OPTC_UNDERFLOW_OCCURRED_STATUS, mask_sh),\ 354 SF(ODM0_OPTC_INPUT_GLOBAL_CONTROL, OPTC_UNDERFLOW_CLEAR, mask_sh),\ 355 SF(VTG0_CONTROL, VTG0_ENABLE, mask_sh),\ 356 SF(VTG0_CONTROL, VTG0_FP2, mask_sh),\ 357 SF(VTG0_CONTROL, VTG0_VCOUNT_INIT, mask_sh),\ 358 SF(OTG0_OTG_VERT_SYNC_CONTROL, OTG_FORCE_VSYNC_NEXT_LINE_OCCURRED, mask_sh),\ 359 SF(OTG0_OTG_VERT_SYNC_CONTROL, OTG_FORCE_VSYNC_NEXT_LINE_CLEAR, mask_sh),\ 360 SF(OTG0_OTG_VERT_SYNC_CONTROL, OTG_AUTO_FORCE_VSYNC_MODE, mask_sh),\ 361 SF(OTG0_OTG_MASTER_UPDATE_MODE, MASTER_UPDATE_INTERLACED_MODE, mask_sh),\ 362 SF(OTG0_OTG_GSL_CONTROL, OTG_GSL0_EN, mask_sh),\ 363 SF(OTG0_OTG_GSL_CONTROL, OTG_GSL1_EN, mask_sh),\ 364 SF(OTG0_OTG_GSL_CONTROL, OTG_GSL2_EN, mask_sh),\ 365 SF(OTG0_OTG_GSL_CONTROL, OTG_GSL_MASTER_EN, mask_sh),\ 366 SF(OTG0_OTG_GSL_CONTROL, OTG_GSL_FORCE_DELAY, mask_sh),\ 367 SF(OTG0_OTG_GSL_CONTROL, OTG_GSL_CHECK_ALL_FIELDS, mask_sh),\ 368 SF(OTG0_OTG_CRC_CNTL, OTG_CRC_CONT_EN, mask_sh),\ 369 SF(OTG0_OTG_CRC_CNTL, OTG_CRC0_SELECT, mask_sh),\ 370 SF(OTG0_OTG_CRC_CNTL, OTG_CRC1_SELECT, mask_sh),\ 371 SF(OTG0_OTG_CRC_CNTL, OTG_CRC_EN, mask_sh),\ 372 SF(OTG0_OTG_CRC0_DATA_RG, CRC0_R_CR, mask_sh),\ 373 SF(OTG0_OTG_CRC0_DATA_RG, CRC0_G_Y, mask_sh),\ 374 SF(OTG0_OTG_CRC0_DATA_B, CRC0_B_CB, mask_sh),\ 375 SF(OTG0_OTG_CRC0_WINDOWA_X_CONTROL, OTG_CRC0_WINDOWA_X_START, mask_sh),\ 376 SF(OTG0_OTG_CRC0_WINDOWA_X_CONTROL, OTG_CRC0_WINDOWA_X_END, mask_sh),\ 377 SF(OTG0_OTG_CRC0_WINDOWA_Y_CONTROL, OTG_CRC0_WINDOWA_Y_START, mask_sh),\ 378 SF(OTG0_OTG_CRC0_WINDOWA_Y_CONTROL, OTG_CRC0_WINDOWA_Y_END, mask_sh),\ 379 SF(OTG0_OTG_CRC0_WINDOWB_X_CONTROL, OTG_CRC0_WINDOWB_X_START, mask_sh),\ 380 SF(OTG0_OTG_CRC0_WINDOWB_X_CONTROL, OTG_CRC0_WINDOWB_X_END, mask_sh),\ 381 SF(OTG0_OTG_CRC0_WINDOWB_Y_CONTROL, OTG_CRC0_WINDOWB_Y_START, mask_sh),\ 382 SF(OTG0_OTG_CRC0_WINDOWB_Y_CONTROL, OTG_CRC0_WINDOWB_Y_END, mask_sh),\ 383 SF(OTG0_OTG_CRC1_DATA_RG, CRC1_R_CR, mask_sh),\ 384 SF(OTG0_OTG_CRC1_DATA_RG, CRC1_G_Y, mask_sh),\ 385 SF(OTG0_OTG_CRC1_DATA_B, CRC1_B_CB, mask_sh),\ 386 SF(OTG0_OTG_CRC1_WINDOWA_X_CONTROL, OTG_CRC1_WINDOWA_X_START, mask_sh),\ 387 SF(OTG0_OTG_CRC1_WINDOWA_X_CONTROL, OTG_CRC1_WINDOWA_X_END, mask_sh),\ 388 SF(OTG0_OTG_CRC1_WINDOWA_Y_CONTROL, OTG_CRC1_WINDOWA_Y_START, mask_sh),\ 389 SF(OTG0_OTG_CRC1_WINDOWA_Y_CONTROL, OTG_CRC1_WINDOWA_Y_END, mask_sh),\ 390 SF(OTG0_OTG_CRC1_WINDOWB_X_CONTROL, OTG_CRC1_WINDOWB_X_START, mask_sh),\ 391 SF(OTG0_OTG_CRC1_WINDOWB_X_CONTROL, OTG_CRC1_WINDOWB_X_END, mask_sh),\ 392 SF(OTG0_OTG_CRC1_WINDOWB_Y_CONTROL, OTG_CRC1_WINDOWB_Y_START, mask_sh),\ 393 SF(OTG0_OTG_CRC1_WINDOWB_Y_CONTROL, OTG_CRC1_WINDOWB_Y_END, mask_sh),\ 394 SF(GSL_SOURCE_SELECT, GSL0_READY_SOURCE_SEL, mask_sh),\ 395 SF(GSL_SOURCE_SELECT, GSL1_READY_SOURCE_SEL, mask_sh),\ 396 SF(GSL_SOURCE_SELECT, GSL2_READY_SOURCE_SEL, mask_sh),\ 397 SF(OTG0_OTG_GLOBAL_CONTROL2, MANUAL_FLOW_CONTROL_SEL, mask_sh) 398 399 #define TG_COMMON_MASK_SH_LIST_DCN1_0(mask_sh)\ 400 TG_COMMON_MASK_SH_LIST_DCN(mask_sh),\ 401 SF(OTG0_OTG_TEST_PATTERN_PARAMETERS, OTG_TEST_PATTERN_INC0, mask_sh),\ 402 SF(OTG0_OTG_TEST_PATTERN_PARAMETERS, OTG_TEST_PATTERN_INC1, mask_sh),\ 403 SF(OTG0_OTG_TEST_PATTERN_PARAMETERS, OTG_TEST_PATTERN_VRES, mask_sh),\ 404 SF(OTG0_OTG_TEST_PATTERN_PARAMETERS, OTG_TEST_PATTERN_HRES, mask_sh),\ 405 SF(OTG0_OTG_TEST_PATTERN_PARAMETERS, OTG_TEST_PATTERN_RAMP0_OFFSET, mask_sh),\ 406 SF(OTG0_OTG_TEST_PATTERN_CONTROL, OTG_TEST_PATTERN_EN, mask_sh),\ 407 SF(OTG0_OTG_TEST_PATTERN_CONTROL, OTG_TEST_PATTERN_MODE, mask_sh),\ 408 SF(OTG0_OTG_TEST_PATTERN_CONTROL, OTG_TEST_PATTERN_DYNAMIC_RANGE, mask_sh),\ 409 SF(OTG0_OTG_TEST_PATTERN_CONTROL, OTG_TEST_PATTERN_COLOR_FORMAT, mask_sh),\ 410 SF(OTG0_OTG_TEST_PATTERN_COLOR, OTG_TEST_PATTERN_MASK, mask_sh),\ 411 SF(OTG0_OTG_TEST_PATTERN_COLOR, OTG_TEST_PATTERN_DATA, mask_sh),\ 412 SF(ODM0_OPTC_DATA_SOURCE_SELECT, OPTC_SRC_SEL, mask_sh),\ 413 SF(OTG0_OTG_MANUAL_FLOW_CONTROL, MANUAL_FLOW_CONTROL, mask_sh),\ 414 415 #define TG_REG_FIELD_LIST_DCN1_0(type) \ 416 type VSTARTUP_START;\ 417 type VUPDATE_OFFSET;\ 418 type VUPDATE_WIDTH;\ 419 type VREADY_OFFSET;\ 420 type OTG_BLANK_DATA_EN;\ 421 type OTG_BLANK_DE_MODE;\ 422 type OTG_CURRENT_BLANK_STATE;\ 423 type OTG_MASTER_UPDATE_LOCK;\ 424 type UPDATE_LOCK_STATUS;\ 425 type OTG_UPDATE_PENDING;\ 426 type OTG_MASTER_UPDATE_LOCK_SEL;\ 427 type OTG_BLANK_DATA_DOUBLE_BUFFER_EN;\ 428 type OTG_H_TOTAL;\ 429 type OTG_H_BLANK_START;\ 430 type OTG_H_BLANK_END;\ 431 type OTG_H_SYNC_A_START;\ 432 type OTG_H_SYNC_A_END;\ 433 type OTG_H_SYNC_A_POL;\ 434 type OTG_H_TIMING_DIV_BY2;\ 435 type OTG_V_TOTAL;\ 436 type OTG_V_BLANK_START;\ 437 type OTG_V_BLANK_END;\ 438 type OTG_V_SYNC_A_START;\ 439 type OTG_V_SYNC_A_END;\ 440 type OTG_V_SYNC_A_POL;\ 441 type OTG_INTERLACE_ENABLE;\ 442 type OTG_MASTER_EN;\ 443 type OTG_START_POINT_CNTL;\ 444 type OTG_DISABLE_POINT_CNTL;\ 445 type OTG_FIELD_NUMBER_CNTL;\ 446 type OTG_CURRENT_MASTER_EN_STATE;\ 447 type OTG_STEREO_EN;\ 448 type OTG_STEREO_SYNC_OUTPUT_LINE_NUM;\ 449 type OTG_STEREO_SYNC_OUTPUT_POLARITY;\ 450 type OTG_STEREO_EYE_FLAG_POLARITY;\ 451 type OTG_STEREO_CURRENT_EYE;\ 452 type OTG_DISABLE_STEREOSYNC_OUTPUT_FOR_DP;\ 453 type OTG_3D_STRUCTURE_EN;\ 454 type OTG_3D_STRUCTURE_V_UPDATE_MODE;\ 455 type OTG_3D_STRUCTURE_STEREO_SEL_OVR;\ 456 type OTG_V_TOTAL_MAX;\ 457 type OTG_V_TOTAL_MID;\ 458 type OTG_V_TOTAL_MIN;\ 459 type OTG_V_TOTAL_MIN_SEL;\ 460 type OTG_V_TOTAL_MAX_SEL;\ 461 type OTG_VTOTAL_MID_REPLACING_MAX_EN;\ 462 type OTG_VTOTAL_MID_FRAME_NUM;\ 463 type OTG_FORCE_LOCK_ON_EVENT;\ 464 type OTG_SET_V_TOTAL_MIN_MASK_EN;\ 465 type OTG_SET_V_TOTAL_MIN_MASK;\ 466 type OTG_FORCE_COUNT_NOW_CLEAR;\ 467 type OTG_FORCE_COUNT_NOW_MODE;\ 468 type OTG_FORCE_COUNT_NOW_OCCURRED;\ 469 type OTG_TRIGA_SOURCE_SELECT;\ 470 type OTG_TRIGA_SOURCE_PIPE_SELECT;\ 471 type OTG_TRIGA_RISING_EDGE_DETECT_CNTL;\ 472 type OTG_TRIGA_FALLING_EDGE_DETECT_CNTL;\ 473 type OTG_TRIGA_POLARITY_SELECT;\ 474 type OTG_TRIGA_FREQUENCY_SELECT;\ 475 type OTG_TRIGA_DELAY;\ 476 type OTG_TRIGA_CLEAR;\ 477 type OTG_TRIGA_MANUAL_TRIG;\ 478 type OTG_STATIC_SCREEN_EVENT_MASK;\ 479 type OTG_STATIC_SCREEN_FRAME_COUNT;\ 480 type OTG_FRAME_COUNT;\ 481 type OTG_V_BLANK;\ 482 type OTG_V_ACTIVE_DISP;\ 483 type OTG_HORZ_COUNT;\ 484 type OTG_VERT_COUNT;\ 485 type OTG_VERT_COUNT_NOM;\ 486 type OTG_BLACK_COLOR_B_CB;\ 487 type OTG_BLACK_COLOR_G_Y;\ 488 type OTG_BLACK_COLOR_R_CR;\ 489 type OTG_BLANK_DATA_COLOR_BLUE_CB;\ 490 type OTG_BLANK_DATA_COLOR_GREEN_Y;\ 491 type OTG_BLANK_DATA_COLOR_RED_CR;\ 492 type OTG_BLANK_DATA_COLOR_BLUE_CB_EXT;\ 493 type OTG_BLANK_DATA_COLOR_GREEN_Y_EXT;\ 494 type OTG_BLANK_DATA_COLOR_RED_CR_EXT;\ 495 type OTG_VTOTAL_MID_REPLACING_MIN_EN;\ 496 type OTG_TEST_PATTERN_INC0;\ 497 type OTG_TEST_PATTERN_INC1;\ 498 type OTG_TEST_PATTERN_VRES;\ 499 type OTG_TEST_PATTERN_HRES;\ 500 type OTG_TEST_PATTERN_RAMP0_OFFSET;\ 501 type OTG_TEST_PATTERN_EN;\ 502 type OTG_TEST_PATTERN_MODE;\ 503 type OTG_TEST_PATTERN_DYNAMIC_RANGE;\ 504 type OTG_TEST_PATTERN_COLOR_FORMAT;\ 505 type OTG_TEST_PATTERN_MASK;\ 506 type OTG_TEST_PATTERN_DATA;\ 507 type OTG_BUSY;\ 508 type OTG_CLOCK_EN;\ 509 type OTG_CLOCK_ON;\ 510 type OTG_CLOCK_GATE_DIS;\ 511 type OTG_VERTICAL_INTERRUPT0_INT_ENABLE;\ 512 type OTG_VERTICAL_INTERRUPT0_LINE_START;\ 513 type OTG_VERTICAL_INTERRUPT0_LINE_END;\ 514 type OTG_VERTICAL_INTERRUPT1_INT_ENABLE;\ 515 type OTG_VERTICAL_INTERRUPT1_LINE_START;\ 516 type OTG_VERTICAL_INTERRUPT2_INT_ENABLE;\ 517 type OTG_VERTICAL_INTERRUPT2_LINE_START;\ 518 type OPTC_INPUT_CLK_EN;\ 519 type OPTC_INPUT_CLK_ON;\ 520 type OPTC_INPUT_CLK_GATE_DIS;\ 521 type OPTC_UNDERFLOW_OCCURRED_STATUS;\ 522 type OPTC_UNDERFLOW_CLEAR;\ 523 type OPTC_SRC_SEL;\ 524 type VTG0_ENABLE;\ 525 type VTG0_FP2;\ 526 type VTG0_VCOUNT_INIT;\ 527 type OTG_FORCE_VSYNC_NEXT_LINE_OCCURRED;\ 528 type OTG_FORCE_VSYNC_NEXT_LINE_CLEAR;\ 529 type OTG_AUTO_FORCE_VSYNC_MODE;\ 530 type MASTER_UPDATE_INTERLACED_MODE;\ 531 type OTG_GSL0_EN;\ 532 type OTG_GSL1_EN;\ 533 type OTG_GSL2_EN;\ 534 type OTG_GSL_MASTER_EN;\ 535 type OTG_GSL_FORCE_DELAY;\ 536 type OTG_GSL_CHECK_ALL_FIELDS;\ 537 type OTG_GSL_WINDOW_START_X;\ 538 type OTG_GSL_WINDOW_END_X;\ 539 type OTG_GSL_WINDOW_START_Y;\ 540 type OTG_GSL_WINDOW_END_Y;\ 541 type OTG_RANGE_TIMING_DBUF_UPDATE_MODE;\ 542 type OTG_GSL_MASTER_MODE;\ 543 type OTG_MASTER_UPDATE_LOCK_GSL_EN;\ 544 type MASTER_UPDATE_LOCK_VUPDATE_KEEPOUT_START_OFFSET;\ 545 type MASTER_UPDATE_LOCK_VUPDATE_KEEPOUT_END_OFFSET;\ 546 type OTG_MASTER_UPDATE_LOCK_VUPDATE_KEEPOUT_EN;\ 547 type OTG_CRC_CONT_EN;\ 548 type OTG_CRC0_SELECT;\ 549 type OTG_CRC1_SELECT;\ 550 type OTG_CRC_EN;\ 551 type CRC0_R_CR;\ 552 type CRC0_G_Y;\ 553 type CRC0_B_CB;\ 554 type CRC1_R_CR;\ 555 type CRC1_G_Y;\ 556 type CRC1_B_CB;\ 557 type CRC2_R_CR;\ 558 type CRC2_G_Y;\ 559 type CRC2_B_CB;\ 560 type CRC3_R_CR;\ 561 type CRC3_G_Y;\ 562 type CRC3_B_CB;\ 563 type OTG_CRC0_WINDOWA_X_START;\ 564 type OTG_CRC0_WINDOWA_X_END;\ 565 type OTG_CRC0_WINDOWA_Y_START;\ 566 type OTG_CRC0_WINDOWA_Y_END;\ 567 type OTG_CRC0_WINDOWB_X_START;\ 568 type OTG_CRC0_WINDOWB_X_END;\ 569 type OTG_CRC0_WINDOWB_Y_START;\ 570 type OTG_CRC0_WINDOWB_Y_END;\ 571 type OTG_CRC_WINDOW_DB_EN;\ 572 type OTG_CRC1_WINDOWA_X_START;\ 573 type OTG_CRC1_WINDOWA_X_END;\ 574 type OTG_CRC1_WINDOWA_Y_START;\ 575 type OTG_CRC1_WINDOWA_Y_END;\ 576 type OTG_CRC1_WINDOWB_X_START;\ 577 type OTG_CRC1_WINDOWB_X_END;\ 578 type OTG_CRC1_WINDOWB_Y_START;\ 579 type OTG_CRC1_WINDOWB_Y_END;\ 580 type GSL0_READY_SOURCE_SEL;\ 581 type GSL1_READY_SOURCE_SEL;\ 582 type GSL2_READY_SOURCE_SEL;\ 583 type MANUAL_FLOW_CONTROL;\ 584 type MANUAL_FLOW_CONTROL_SEL; 585 586 #define V_TOTAL_REGS(type) 587 588 #define TG_REG_FIELD_LIST(type) \ 589 TG_REG_FIELD_LIST_DCN1_0(type)\ 590 type OTG_V_SYNC_MODE;\ 591 type OTG_DRR_TRIGGER_WINDOW_START_X;\ 592 type OTG_DRR_TRIGGER_WINDOW_END_X;\ 593 type OTG_DRR_V_TOTAL_CHANGE_LIMIT;\ 594 V_TOTAL_REGS(type)\ 595 type OTG_OUT_MUX;\ 596 type OTG_M_CONST_DTO_PHASE;\ 597 type OTG_M_CONST_DTO_MODULO;\ 598 type MASTER_UPDATE_LOCK_DB_X;\ 599 type MASTER_UPDATE_LOCK_DB_Y;\ 600 type MASTER_UPDATE_LOCK_DB_EN;\ 601 type GLOBAL_UPDATE_LOCK_EN;\ 602 type DIG_UPDATE_LOCATION;\ 603 type OTG_DSC_START_POSITION_X;\ 604 type OTG_DSC_START_POSITION_LINE_NUM;\ 605 type OPTC_NUM_OF_INPUT_SEGMENT;\ 606 type OPTC_SEG0_SRC_SEL;\ 607 type OPTC_SEG1_SRC_SEL;\ 608 type OPTC_SEG2_SRC_SEL;\ 609 type OPTC_SEG3_SRC_SEL;\ 610 type OPTC_MEM_SEL;\ 611 type OPTC_DATA_FORMAT;\ 612 type OPTC_DSC_MODE;\ 613 type OPTC_DSC_BYTES_PER_PIXEL;\ 614 type OPTC_DSC_SLICE_WIDTH;\ 615 type OPTC_SEGMENT_WIDTH;\ 616 type OPTC_DWB0_SOURCE_SELECT;\ 617 type OPTC_DWB1_SOURCE_SELECT;\ 618 type MASTER_UPDATE_LOCK_DB_START_X;\ 619 type MASTER_UPDATE_LOCK_DB_END_X;\ 620 type MASTER_UPDATE_LOCK_DB_START_Y;\ 621 type MASTER_UPDATE_LOCK_DB_END_Y;\ 622 type DIG_UPDATE_POSITION_X;\ 623 type DIG_UPDATE_POSITION_Y;\ 624 type OTG_H_TIMING_DIV_MODE;\ 625 type OTG_DRR_TIMING_DBUF_UPDATE_MODE;\ 626 type OTG_CRC_DSC_MODE;\ 627 type OTG_CRC_DATA_STREAM_COMBINE_MODE;\ 628 type OTG_CRC_DATA_STREAM_SPLIT_MODE;\ 629 type OTG_CRC_DATA_FORMAT;\ 630 type OTG_V_TOTAL_LAST_USED_BY_DRR;\ 631 type OTG_DRR_TIMING_DBUF_UPDATE_PENDING;\ 632 type OTG_H_TIMING_DIV_MODE_DB_UPDATE_PENDING;\ 633 type OPTC_DOUBLE_BUFFER_PENDING;\ 634 635 #define TG_REG_FIELD_LIST_DCN2_0(type) \ 636 type OTG_FLIP_PENDING;\ 637 type OTG_DC_REG_UPDATE_PENDING;\ 638 type OTG_CURSOR_UPDATE_PENDING;\ 639 type OTG_VUPDATE_KEEPOUT_STATUS;\ 640 type OTG0_IHC_OTG_VERTICAL_INTERRUPT2_DEST; 641 642 #define TG_REG_FIELD_LIST_DCN3_2(type) \ 643 type OTG_H_TIMING_DIV_MODE_MANUAL; 644 645 #define TG_REG_FIELD_LIST_DCN3_5(type) \ 646 type OTG_CRC0_WINDOWA_X_START_READBACK;\ 647 type OTG_CRC0_WINDOWA_X_END_READBACK;\ 648 type OTG_CRC0_WINDOWA_Y_START_READBACK;\ 649 type OTG_CRC0_WINDOWA_Y_END_READBACK;\ 650 type OTG_CRC0_WINDOWB_X_START_READBACK;\ 651 type OTG_CRC0_WINDOWB_X_END_READBACK;\ 652 type OTG_CRC0_WINDOWB_Y_START_READBACK;\ 653 type OTG_CRC0_WINDOWB_Y_END_READBACK; \ 654 type OTG_CRC1_WINDOWA_X_START_READBACK;\ 655 type OTG_CRC1_WINDOWA_X_END_READBACK;\ 656 type OTG_CRC1_WINDOWA_Y_START_READBACK;\ 657 type OTG_CRC1_WINDOWA_Y_END_READBACK;\ 658 type OTG_CRC1_WINDOWB_X_START_READBACK;\ 659 type OTG_CRC1_WINDOWB_X_END_READBACK;\ 660 type OTG_CRC1_WINDOWB_Y_START_READBACK;\ 661 type OTG_CRC1_WINDOWB_Y_END_READBACK;\ 662 type OPTC_FGCG_REP_DIS;\ 663 type OTG_V_COUNT_STOP;\ 664 type OTG_V_COUNT_STOP_TIMER; 665 666 #define TG_REG_FIELD_LIST_DCN3_6(type) \ 667 type OTG_CRC_POLY_SEL; \ 668 type CRC0_R_CR32; \ 669 type CRC0_G_Y32; \ 670 type CRC0_B_CB32; \ 671 type CRC1_R_CR32; \ 672 type CRC1_G_Y32; \ 673 type CRC1_B_CB32; 674 675 #define TG_REG_FIELD_LIST_DCN401(type) \ 676 type OPTC_SEGMENT_WIDTH_LAST;\ 677 type OTG_PSTATE_KEEPOUT_START;\ 678 type OTG_PSTATE_EXTEND;\ 679 type OTG_UNBLANK;\ 680 type OTG_PSTATE_ALLOW_WIDTH_MIN; 681 682 683 struct dcn_optc_shift { 684 TG_REG_FIELD_LIST(uint8_t) 685 TG_REG_FIELD_LIST_DCN2_0(uint8_t) 686 TG_REG_FIELD_LIST_DCN3_2(uint8_t) 687 TG_REG_FIELD_LIST_DCN3_5(uint8_t) 688 TG_REG_FIELD_LIST_DCN3_6(uint8_t) 689 TG_REG_FIELD_LIST_DCN401(uint8_t) 690 }; 691 692 struct dcn_optc_mask { 693 TG_REG_FIELD_LIST(uint32_t) 694 TG_REG_FIELD_LIST_DCN2_0(uint32_t) 695 TG_REG_FIELD_LIST_DCN3_2(uint32_t) 696 TG_REG_FIELD_LIST_DCN3_5(uint32_t) 697 TG_REG_FIELD_LIST_DCN3_6(uint32_t) 698 TG_REG_FIELD_LIST_DCN401(uint32_t) 699 }; 700 701 void dcn10_timing_generator_init(struct optc *optc); 702 703 #endif /* __DC_TIMING_GENERATOR_DCN10_H__ */ 704