1 /* SPDX-License-Identifier: MIT */
2 /* Copyright 2025 Advanced Micro Devices, Inc. */
3
4 #include "dm_services.h"
5 #include "dc.h"
6
7 #include "dcn31/dcn31_init.h"
8 #include "dcn35/dcn35_init.h"
9 #include "dcn36/dcn36_resource.h"
10
11 #include "resource.h"
12 #include "include/irq_service_interface.h"
13 #include "dcn36_resource.h"
14 #include "dml2_0/dml2_wrapper.h"
15
16 #include "dcn20/dcn20_resource.h"
17 #include "dcn30/dcn30_resource.h"
18 #include "dcn31/dcn31_resource.h"
19 #include "dcn32/dcn32_resource.h"
20 #include "dcn35/dcn35_resource.h"
21
22 #include "dcn10/dcn10_ipp.h"
23 #include "dcn30/dcn30_hubbub.h"
24 #include "dcn31/dcn31_hubbub.h"
25 #include "dcn35/dcn35_hubbub.h"
26 #include "dcn32/dcn32_mpc.h"
27 #include "dcn35/dcn35_hubp.h"
28 #include "irq/dcn36/irq_service_dcn36.h"
29 #include "dcn35/dcn35_dpp.h"
30 #include "dcn35/dcn35_optc.h"
31 #include "dcn20/dcn20_hwseq.h"
32 #include "dcn30/dcn30_hwseq.h"
33 #include "dce110/dce110_hwseq.h"
34 #include "dcn35/dcn35_opp.h"
35 #include "dcn35/dcn35_dsc.h"
36 #include "dcn30/dcn30_vpg.h"
37 #include "dcn30/dcn30_afmt.h"
38 #include "dcn31/dcn31_dio_link_encoder.h"
39 #include "dcn35/dcn35_dio_stream_encoder.h"
40 #include "dcn31/dcn31_hpo_dp_stream_encoder.h"
41 #include "dcn31/dcn31_hpo_dp_link_encoder.h"
42 #include "dcn32/dcn32_hpo_dp_link_encoder.h"
43 #include "link_service.h"
44 #include "dcn31/dcn31_apg.h"
45 #include "dcn32/dcn32_dio_link_encoder.h"
46 #include "dcn31/dcn31_vpg.h"
47 #include "dcn31/dcn31_afmt.h"
48 #include "dce/dce_clock_source.h"
49 #include "dce/dce_audio.h"
50 #include "dce/dce_hwseq.h"
51 #include "clk_mgr.h"
52 #include "dio/virtual/virtual_stream_encoder.h"
53 #include "dio/dcn10/dcn10_dio.h"
54 #include "dce110/dce110_resource.h"
55 #include "dml/display_mode_vba.h"
56 #include "dcn35/dcn35_dccg.h"
57 #include "dcn35/dcn35_pg_cntl.h"
58 #include "dcn10/dcn10_resource.h"
59 #include "dcn31/dcn31_panel_cntl.h"
60 #include "dcn35/dcn35_hwseq.h"
61 #include "dcn35/dcn35_dio_link_encoder.h"
62 #include "dml/dcn31/dcn31_fpu.h" /*todo*/
63 #include "dml/dcn35/dcn35_fpu.h"
64 #include "dcn35/dcn35_dwb.h"
65 #include "dcn35/dcn35_mmhubbub.h"
66
67 #include "dcn/dcn_3_6_0_offset.h"
68 #include "dcn/dcn_3_6_0_sh_mask.h"
69
70 #define regBIF_BX2_BIOS_SCRATCH_2 0x2ffc004e
71 #define regBIF_BX2_BIOS_SCRATCH_2_BASE_IDX 5
72
73 #define regBIF_BX2_BIOS_SCRATCH_3 0x2ffc004f
74 #define regBIF_BX2_BIOS_SCRATCH_3_BASE_IDX 5
75
76 #define regBIF_BX2_BIOS_SCRATCH_6 0x2ffc0052
77 #define regBIF_BX2_BIOS_SCRATCH_6_BASE_IDX 5
78
79 #define DSCC0_DSCC_CONFIG0__ICH_RESET_AT_END_OF_LINE__SHIFT 0x0
80 #define DSCC0_DSCC_CONFIG0__ICH_RESET_AT_END_OF_LINE_MASK 0x0000000FL
81
82 #include "reg_helper.h"
83 #include "dce/dmub_abm.h"
84 #include "dce/dmub_psr.h"
85 #include "dce/dmub_replay.h"
86 #include "dce/dce_aux.h"
87 #include "dce/dce_i2c.h"
88 #include "dml/dcn31/display_mode_vba_31.h" /*temp*/
89 #include "vm_helper.h"
90 #include "dcn20/dcn20_vmid.h"
91
92 #include "dc_state_priv.h"
93
94 #include "link_enc_cfg.h"
95 #define DC_LOGGER_INIT(logger)
96
97 enum dcn36_clk_src_array_id {
98 DCN36_CLK_SRC_PLL0,
99 DCN36_CLK_SRC_PLL1,
100 DCN36_CLK_SRC_PLL2,
101 DCN36_CLK_SRC_PLL3,
102 DCN36_CLK_SRC_PLL4,
103 DCN36_CLK_SRC_TOTAL
104 };
105
106 /* begin *********************
107 * macros to expend register list macro defined in HW object header file
108 */
109
110 /* DCN */
111 /* TODO awful hack. fixup dcn20_dwb.h */
112 #undef BASE_INNER
113 #define BASE_INNER(seg) ctx->dcn_reg_offsets[seg]
114
115 #define BASE(seg) BASE_INNER(seg)
116
117 #define SR(reg_name)\
118 REG_STRUCT.reg_name = BASE(reg ## reg_name ## _BASE_IDX) + \
119 reg ## reg_name
120
121 #define SR_ARR(reg_name, id) \
122 REG_STRUCT[id].reg_name = BASE(reg##reg_name##_BASE_IDX) + reg##reg_name
123
124 #define SR_ARR_INIT(reg_name, id, value) \
125 REG_STRUCT[id].reg_name = value
126
127 #define SRI(reg_name, block, id)\
128 REG_STRUCT.reg_name = BASE(reg ## block ## id ## _ ## reg_name ## _BASE_IDX) + \
129 reg ## block ## id ## _ ## reg_name
130
131 #define SRI_ARR(reg_name, block, id)\
132 REG_STRUCT[id].reg_name = BASE(reg ## block ## id ## _ ## reg_name ## _BASE_IDX) + \
133 reg ## block ## id ## _ ## reg_name
134
135 #define SR_ARR_I2C(reg_name, id) \
136 REG_STRUCT[id-1].reg_name = BASE(reg##reg_name##_BASE_IDX) + reg##reg_name
137
138 #define SRI_ARR_I2C(reg_name, block, id)\
139 REG_STRUCT[id-1].reg_name = BASE(reg ## block ## id ## _ ## reg_name ## _BASE_IDX) + \
140 reg ## block ## id ## _ ## reg_name
141
142 #define SRI_ARR_ALPHABET(reg_name, block, index, id)\
143 REG_STRUCT[index].reg_name = BASE(reg ## block ## id ## _ ## reg_name ## _BASE_IDX) + \
144 reg ## block ## id ## _ ## reg_name
145
146 #define SRI2(reg_name, block, id)\
147 .reg_name = BASE(reg ## reg_name ## _BASE_IDX) + \
148 reg ## reg_name
149
150 #define SRI2_ARR(reg_name, block, id)\
151 REG_STRUCT[id].reg_name = BASE(reg ## reg_name ## _BASE_IDX) + \
152 reg ## reg_name
153
154 #define SRIR(var_name, reg_name, block, id)\
155 .var_name = BASE(reg ## block ## id ## _ ## reg_name ## _BASE_IDX) + \
156 reg ## block ## id ## _ ## reg_name
157
158 #define SRII(reg_name, block, id)\
159 REG_STRUCT.reg_name[id] = BASE(reg ## block ## id ## _ ## reg_name ## _BASE_IDX) + \
160 reg ## block ## id ## _ ## reg_name
161
162 #define SRII_ARR_2(reg_name, block, id, inst)\
163 REG_STRUCT[inst].reg_name[id] = BASE(reg ## block ## id ## _ ## reg_name ## _BASE_IDX) + \
164 reg ## block ## id ## _ ## reg_name
165
166 #define SRII_MPC_RMU(reg_name, block, id)\
167 .RMU##_##reg_name[id] = BASE(reg ## block ## id ## _ ## reg_name ## _BASE_IDX) + \
168 reg ## block ## id ## _ ## reg_name
169
170 #define SRII_DWB(reg_name, temp_name, block, id)\
171 REG_STRUCT.reg_name[id] = BASE(reg ## block ## id ## _ ## temp_name ## _BASE_IDX) + \
172 reg ## block ## id ## _ ## temp_name
173
174 #define SF_DWB2(reg_name, block, id, field_name, post_fix) \
175 .field_name = reg_name ## __ ## field_name ## post_fix
176
177 #define DCCG_SRII(reg_name, block, id)\
178 REG_STRUCT.block ## _ ## reg_name[id] = BASE(reg ## block ## id ## _ ## reg_name ## _BASE_IDX) + \
179 reg ## block ## id ## _ ## reg_name
180
181 #define VUPDATE_SRII(reg_name, block, id)\
182 REG_STRUCT.reg_name[id] = BASE(reg ## reg_name ## _ ## block ## id ## _BASE_IDX) + \
183 reg ## reg_name ## _ ## block ## id
184
185 /* NBIO */
186 #define NBIO_BASE_INNER(seg) ctx->nbio_reg_offsets[seg]
187
188 #define NBIO_BASE(seg) \
189 NBIO_BASE_INNER(seg)
190
191 #define NBIO_SR(reg_name)\
192 REG_STRUCT.reg_name = NBIO_BASE(regBIF_BX2_ ## reg_name ## _BASE_IDX) + \
193 regBIF_BX2_ ## reg_name
194
195 #define NBIO_SR_ARR(reg_name, id)\
196 REG_STRUCT[id].reg_name = NBIO_BASE(regBIF_BX2_ ## reg_name ## _BASE_IDX) + \
197 regBIF_BX2_ ## reg_name
198
199 #define bios_regs_init() \
200 ( \
201 NBIO_SR(BIOS_SCRATCH_3),\
202 NBIO_SR(BIOS_SCRATCH_6)\
203 )
204
205 static struct bios_registers bios_regs;
206
207 #define clk_src_regs_init(index, pllid)\
208 CS_COMMON_REG_LIST_DCN3_0_RI(index, pllid)
209
210 static struct dce110_clk_src_regs clk_src_regs[5];
211
212 static const struct dce110_clk_src_shift cs_shift = {
213 CS_COMMON_MASK_SH_LIST_DCN3_1_4(__SHIFT)
214 };
215
216 static const struct dce110_clk_src_mask cs_mask = {
217 CS_COMMON_MASK_SH_LIST_DCN3_1_4(_MASK)
218 };
219
220 #define abm_regs_init(id)\
221 ABM_DCN32_REG_LIST_RI(id)
222
223 static struct dce_abm_registers abm_regs[4];
224
225 static const struct dce_abm_shift abm_shift = {
226 ABM_MASK_SH_LIST_DCN35(__SHIFT)
227 };
228
229 static const struct dce_abm_mask abm_mask = {
230 ABM_MASK_SH_LIST_DCN35(_MASK)
231 };
232
233 #define audio_regs_init(id)\
234 AUD_COMMON_REG_LIST_RI(id)
235
236 static struct dce_audio_registers audio_regs[7];
237
238
239 #define DCE120_AUD_COMMON_MASK_SH_LIST(mask_sh)\
240 SF(AZF0ENDPOINT0_AZALIA_F0_CODEC_ENDPOINT_INDEX, AZALIA_ENDPOINT_REG_INDEX, mask_sh),\
241 SF(AZF0ENDPOINT0_AZALIA_F0_CODEC_ENDPOINT_DATA, AZALIA_ENDPOINT_REG_DATA, mask_sh),\
242 AUD_COMMON_MASK_SH_LIST_BASE(mask_sh)
243
244 static const struct dce_audio_shift audio_shift = {
245 DCE120_AUD_COMMON_MASK_SH_LIST(__SHIFT)
246 };
247
248 static const struct dce_audio_mask audio_mask = {
249 DCE120_AUD_COMMON_MASK_SH_LIST(_MASK)
250 };
251
252 #define vpg_regs_init(id)\
253 VPG_DCN31_REG_LIST_RI(id)
254
255 static struct dcn31_vpg_registers vpg_regs[10];
256
257 static const struct dcn31_vpg_shift vpg_shift = {
258 DCN31_VPG_MASK_SH_LIST(__SHIFT)
259 };
260
261 static const struct dcn31_vpg_mask vpg_mask = {
262 DCN31_VPG_MASK_SH_LIST(_MASK)
263 };
264
265 #define afmt_regs_init(id)\
266 AFMT_DCN31_REG_LIST_RI(id)
267
268 static struct dcn31_afmt_registers afmt_regs[6];
269
270 static const struct dcn31_afmt_shift afmt_shift = {
271 DCN31_AFMT_MASK_SH_LIST(__SHIFT)
272 };
273
274 static const struct dcn31_afmt_mask afmt_mask = {
275 DCN31_AFMT_MASK_SH_LIST(_MASK)
276 };
277
278 #define apg_regs_init(id)\
279 APG_DCN31_REG_LIST_RI(id)
280
281 static struct dcn31_apg_registers apg_regs[4];
282
283 static const struct dcn31_apg_shift apg_shift = {
284 DCN31_APG_MASK_SH_LIST(__SHIFT)
285 };
286
287 static const struct dcn31_apg_mask apg_mask = {
288 DCN31_APG_MASK_SH_LIST(_MASK)
289 };
290
291 #define stream_enc_regs_init(id)\
292 SE_DCN35_REG_LIST_RI(id)
293
294 static struct dcn10_stream_enc_registers stream_enc_regs[5];
295
296 static const struct dcn10_stream_encoder_shift se_shift = {
297 SE_COMMON_MASK_SH_LIST_DCN35(__SHIFT)
298 };
299
300 static const struct dcn10_stream_encoder_mask se_mask = {
301 SE_COMMON_MASK_SH_LIST_DCN35(_MASK)
302 };
303
304 #define aux_regs_init(id)\
305 DCN2_AUX_REG_LIST_RI(id)
306
307 static struct dcn10_link_enc_aux_registers link_enc_aux_regs[5];
308
309 #define hpd_regs_init(id)\
310 HPD_REG_LIST_RI(id)
311
312 static struct dcn10_link_enc_hpd_registers link_enc_hpd_regs[5];
313
314
315 static const struct dce110_aux_registers_shift aux_shift = {
316 DCN_AUX_MASK_SH_LIST(__SHIFT)
317 };
318
319 static const struct dce110_aux_registers_mask aux_mask = {
320 DCN_AUX_MASK_SH_LIST(_MASK)
321 };
322
323 #define link_regs_init(id, phyid)\
324 ( \
325 LE_DCN35_REG_LIST_RI(id), \
326 UNIPHY_DCN2_REG_LIST_RI(id, phyid)\
327 )
328
329 static struct dcn10_link_enc_registers link_enc_regs[5];
330
331 static const struct dcn10_link_enc_shift le_shift = {
332 LINK_ENCODER_MASK_SH_LIST_DCN35(__SHIFT), \
333 //DPCS_DCN31_MASK_SH_LIST(__SHIFT)
334 };
335
336 static const struct dcn10_link_enc_mask le_mask = {
337 LINK_ENCODER_MASK_SH_LIST_DCN35(_MASK), \
338 //DPCS_DCN31_MASK_SH_LIST(_MASK)
339 };
340
341 #define hpo_dp_stream_encoder_reg_init(id)\
342 DCN3_1_HPO_DP_STREAM_ENC_REG_LIST_RI(id)
343
344 static struct dcn31_hpo_dp_stream_encoder_registers hpo_dp_stream_enc_regs[4];
345
346 static const struct dcn31_hpo_dp_stream_encoder_shift hpo_dp_se_shift = {
347 DCN3_1_HPO_DP_STREAM_ENC_MASK_SH_LIST(__SHIFT)
348 };
349
350 static const struct dcn31_hpo_dp_stream_encoder_mask hpo_dp_se_mask = {
351 DCN3_1_HPO_DP_STREAM_ENC_MASK_SH_LIST(_MASK)
352 };
353
354 #define hpo_dp_link_encoder_reg_init(id)\
355 DCN3_1_HPO_DP_LINK_ENC_REG_LIST_RI(id)
356
357 static struct dcn31_hpo_dp_link_encoder_registers hpo_dp_link_enc_regs[2];
358
359 static const struct dcn31_hpo_dp_link_encoder_shift hpo_dp_le_shift = {
360 DCN3_1_HPO_DP_LINK_ENC_COMMON_MASK_SH_LIST(__SHIFT)
361 };
362
363 static const struct dcn31_hpo_dp_link_encoder_mask hpo_dp_le_mask = {
364 DCN3_1_HPO_DP_LINK_ENC_COMMON_MASK_SH_LIST(_MASK)
365 };
366
367 #define dpp_regs_init(id)\
368 DPP_REG_LIST_DCN35_RI(id)
369
370 static struct dcn3_dpp_registers dpp_regs[4];
371
372 static const struct dcn35_dpp_shift tf_shift = {
373 DPP_REG_LIST_SH_MASK_DCN35(__SHIFT)
374 };
375
376 static const struct dcn35_dpp_mask tf_mask = {
377 DPP_REG_LIST_SH_MASK_DCN35(_MASK)
378 };
379
380 #define opp_regs_init(id)\
381 OPP_REG_LIST_DCN35_RI(id)
382
383 static struct dcn35_opp_registers opp_regs[4];
384
385 static const struct dcn35_opp_shift opp_shift = {
386 OPP_MASK_SH_LIST_DCN35(__SHIFT)
387 };
388
389 static const struct dcn35_opp_mask opp_mask = {
390 OPP_MASK_SH_LIST_DCN35(_MASK)
391 };
392
393 #define aux_engine_regs_init(id)\
394 ( \
395 AUX_COMMON_REG_LIST0_RI(id), \
396 SR_ARR_INIT(AUXN_IMPCAL, id, 0), \
397 SR_ARR_INIT(AUXP_IMPCAL, id, 0), \
398 SR_ARR_INIT(AUX_RESET_MASK, id, DP_AUX0_AUX_CONTROL__AUX_RESET_MASK) \
399 )
400
401 static struct dce110_aux_registers aux_engine_regs[5];
402
403 #define dwbc_regs_dcn3_init(id)\
404 DWBC_COMMON_REG_LIST_DCN30_RI(id)
405
406 static struct dcn30_dwbc_registers dwbc35_regs[1];
407
408 static const struct dcn35_dwbc_shift dwbc35_shift = {
409 DWBC_COMMON_MASK_SH_LIST_DCN35(__SHIFT)
410 };
411
412 static const struct dcn35_dwbc_mask dwbc35_mask = {
413 DWBC_COMMON_MASK_SH_LIST_DCN35(_MASK)
414 };
415
416 #define mcif_wb_regs_dcn3_init(id)\
417 MCIF_WB_COMMON_REG_LIST_DCN3_5_RI(id)
418
419 static struct dcn35_mmhubbub_registers mcif_wb35_regs[1];
420
421 static const struct dcn35_mmhubbub_shift mcif_wb35_shift = {
422 MCIF_WB_COMMON_MASK_SH_LIST_DCN3_5(__SHIFT)
423 };
424
425 static const struct dcn35_mmhubbub_mask mcif_wb35_mask = {
426 MCIF_WB_COMMON_MASK_SH_LIST_DCN3_5(_MASK)
427 };
428
429 #define dsc_regsDCN35_init(id)\
430 DSC_REG_LIST_DCN20_RI(id)
431
432 static struct dcn20_dsc_registers dsc_regs[4];
433
434 static const struct dcn35_dsc_shift dsc_shift = {
435 DSC_REG_LIST_SH_MASK_DCN35(__SHIFT)
436 };
437
438 static const struct dcn35_dsc_mask dsc_mask = {
439 DSC_REG_LIST_SH_MASK_DCN35(_MASK)
440 };
441
442 static struct dcn30_mpc_registers mpc_regs;
443
444 #define dcn_mpc_regs_init() \
445 MPC_REG_LIST_DCN3_2_RI(0),\
446 MPC_REG_LIST_DCN3_2_RI(1),\
447 MPC_REG_LIST_DCN3_2_RI(2),\
448 MPC_REG_LIST_DCN3_2_RI(3),\
449 MPC_OUT_MUX_REG_LIST_DCN3_0_RI(0),\
450 MPC_OUT_MUX_REG_LIST_DCN3_0_RI(1),\
451 MPC_OUT_MUX_REG_LIST_DCN3_0_RI(2),\
452 MPC_OUT_MUX_REG_LIST_DCN3_0_RI(3),\
453 MPC_DWB_MUX_REG_LIST_DCN3_0_RI(0)
454
455 static const struct dcn30_mpc_shift mpc_shift = {
456 MPC_COMMON_MASK_SH_LIST_DCN32(__SHIFT)
457 };
458
459 static const struct dcn30_mpc_mask mpc_mask = {
460 MPC_COMMON_MASK_SH_LIST_DCN32(_MASK)
461 };
462
463 #define optc_regs_init(id)\
464 OPTC_COMMON_REG_LIST_DCN3_5_RI(id),\
465 SRI_ARR(OTG_CRC0_DATA_R32, OTG_CRC32, id),\
466 SRI_ARR(OTG_CRC0_DATA_G32, OTG_CRC32, id),\
467 SRI_ARR(OTG_CRC0_DATA_B32, OTG_CRC32, id),\
468 SRI_ARR(OTG_CRC1_DATA_R32, OTG_CRC32, id),\
469 SRI_ARR(OTG_CRC1_DATA_G32, OTG_CRC32, id),\
470 SRI_ARR(OTG_CRC1_DATA_B32, OTG_CRC32, id)
471
472 static struct dcn_optc_registers optc_regs[4];
473
474 static const struct dcn_optc_shift optc_shift = {
475 OPTC_COMMON_MASK_SH_LIST_DCN3_6(__SHIFT)
476 };
477
478 static const struct dcn_optc_mask optc_mask = {
479 OPTC_COMMON_MASK_SH_LIST_DCN3_6(_MASK)
480 };
481
482 #define hubp_regs_init(id)\
483 HUBP_REG_LIST_DCN30_RI(id)
484
485 static struct dcn_hubp2_registers hubp_regs[4];
486
487
488 static const struct dcn35_hubp2_shift hubp_shift = {
489 HUBP_MASK_SH_LIST_DCN35(__SHIFT)
490 };
491
492 static const struct dcn35_hubp2_mask hubp_mask = {
493 HUBP_MASK_SH_LIST_DCN35(_MASK)
494 };
495
496 static struct dcn_hubbub_registers hubbub_reg;
497
498 #define hubbub_reg_init()\
499 HUBBUB_REG_LIST_DCN35(0)
500
501 static const struct dcn_hubbub_shift hubbub_shift = {
502 HUBBUB_MASK_SH_LIST_DCN35(__SHIFT)
503 };
504
505 static const struct dcn_hubbub_mask hubbub_mask = {
506 HUBBUB_MASK_SH_LIST_DCN35(_MASK)
507 };
508
509 static struct dccg_registers dccg_regs;
510
511 #define dccg_regs_init()\
512 DCCG_REG_LIST_DCN35()
513
514 static const struct dccg_shift dccg_shift = {
515 DCCG_MASK_SH_LIST_DCN35(__SHIFT)
516 };
517
518 static const struct dccg_mask dccg_mask = {
519 DCCG_MASK_SH_LIST_DCN35(_MASK)
520 };
521
522 static struct pg_cntl_registers pg_cntl_regs;
523
524 #define pg_cntl_dcn35_regs_init() \
525 PG_CNTL_REG_LIST_DCN35()
526
527 static const struct pg_cntl_shift pg_cntl_shift = {
528 PG_CNTL_MASK_SH_LIST_DCN35(__SHIFT)
529 };
530
531 static const struct pg_cntl_mask pg_cntl_mask = {
532 PG_CNTL_MASK_SH_LIST_DCN35(_MASK)
533 };
534
535 #define SRII2(reg_name_pre, reg_name_post, id)\
536 .reg_name_pre ## _ ## reg_name_post[id] = BASE(reg ## reg_name_pre \
537 ## id ## _ ## reg_name_post ## _BASE_IDX) + \
538 reg ## reg_name_pre ## id ## _ ## reg_name_post
539
540 static struct dce_hwseq_registers hwseq_reg;
541
542 #define hwseq_reg_init()\
543 HWSEQ_DCN36_REG_LIST()
544
545 #define HWSEQ_DCN36_MASK_SH_LIST(mask_sh)\
546 HWSEQ_DCN_MASK_SH_LIST(mask_sh), \
547 HWS_SF(, DCHUBBUB_GLOBAL_TIMER_CNTL, DCHUBBUB_GLOBAL_TIMER_REFDIV, mask_sh), \
548 HWS_SF(, DCHUBBUB_ARB_HOSTVM_CNTL, DISABLE_HOSTVM_FORCE_ALLOW_PSTATE, mask_sh), \
549 HWS_SF(, DOMAIN0_PG_CONFIG, DOMAIN_POWER_FORCEON, mask_sh), \
550 HWS_SF(, DOMAIN0_PG_CONFIG, DOMAIN_POWER_GATE, mask_sh), \
551 HWS_SF(, DOMAIN1_PG_CONFIG, DOMAIN_POWER_FORCEON, mask_sh), \
552 HWS_SF(, DOMAIN1_PG_CONFIG, DOMAIN_POWER_GATE, mask_sh), \
553 HWS_SF(, DOMAIN2_PG_CONFIG, DOMAIN_POWER_FORCEON, mask_sh), \
554 HWS_SF(, DOMAIN2_PG_CONFIG, DOMAIN_POWER_GATE, mask_sh), \
555 HWS_SF(, DOMAIN3_PG_CONFIG, DOMAIN_POWER_FORCEON, mask_sh), \
556 HWS_SF(, DOMAIN3_PG_CONFIG, DOMAIN_POWER_GATE, mask_sh), \
557 HWS_SF(, DOMAIN16_PG_CONFIG, DOMAIN_POWER_FORCEON, mask_sh), \
558 HWS_SF(, DOMAIN16_PG_CONFIG, DOMAIN_POWER_GATE, mask_sh), \
559 HWS_SF(, DOMAIN17_PG_CONFIG, DOMAIN_POWER_FORCEON, mask_sh), \
560 HWS_SF(, DOMAIN17_PG_CONFIG, DOMAIN_POWER_GATE, mask_sh), \
561 HWS_SF(, DOMAIN18_PG_CONFIG, DOMAIN_POWER_FORCEON, mask_sh), \
562 HWS_SF(, DOMAIN18_PG_CONFIG, DOMAIN_POWER_GATE, mask_sh), \
563 HWS_SF(, DOMAIN19_PG_CONFIG, DOMAIN_POWER_FORCEON, mask_sh), \
564 HWS_SF(, DOMAIN19_PG_CONFIG, DOMAIN_POWER_GATE, mask_sh), \
565 HWS_SF(, DOMAIN22_PG_CONFIG, DOMAIN_POWER_FORCEON, mask_sh), \
566 HWS_SF(, DOMAIN22_PG_CONFIG, DOMAIN_POWER_GATE, mask_sh), \
567 HWS_SF(, DOMAIN23_PG_CONFIG, DOMAIN_POWER_FORCEON, mask_sh), \
568 HWS_SF(, DOMAIN23_PG_CONFIG, DOMAIN_POWER_GATE, mask_sh), \
569 HWS_SF(, DOMAIN24_PG_CONFIG, DOMAIN_POWER_FORCEON, mask_sh), \
570 HWS_SF(, DOMAIN24_PG_CONFIG, DOMAIN_POWER_GATE, mask_sh), \
571 HWS_SF(, DOMAIN25_PG_CONFIG, DOMAIN_POWER_FORCEON, mask_sh), \
572 HWS_SF(, DOMAIN25_PG_CONFIG, DOMAIN_POWER_GATE, mask_sh), \
573 HWS_SF(, DOMAIN0_PG_STATUS, DOMAIN_PGFSM_PWR_STATUS, mask_sh), \
574 HWS_SF(, DOMAIN1_PG_STATUS, DOMAIN_PGFSM_PWR_STATUS, mask_sh), \
575 HWS_SF(, DOMAIN2_PG_STATUS, DOMAIN_PGFSM_PWR_STATUS, mask_sh), \
576 HWS_SF(, DOMAIN3_PG_STATUS, DOMAIN_PGFSM_PWR_STATUS, mask_sh), \
577 HWS_SF(, DOMAIN16_PG_STATUS, DOMAIN_PGFSM_PWR_STATUS, mask_sh), \
578 HWS_SF(, DOMAIN17_PG_STATUS, DOMAIN_PGFSM_PWR_STATUS, mask_sh), \
579 HWS_SF(, DOMAIN18_PG_STATUS, DOMAIN_PGFSM_PWR_STATUS, mask_sh), \
580 HWS_SF(, DOMAIN19_PG_STATUS, DOMAIN_PGFSM_PWR_STATUS, mask_sh), \
581 HWS_SF(, DOMAIN22_PG_STATUS, DOMAIN_PGFSM_PWR_STATUS, mask_sh), \
582 HWS_SF(, DOMAIN23_PG_STATUS, DOMAIN_PGFSM_PWR_STATUS, mask_sh), \
583 HWS_SF(, DOMAIN24_PG_STATUS, DOMAIN_PGFSM_PWR_STATUS, mask_sh), \
584 HWS_SF(, DOMAIN25_PG_STATUS, DOMAIN_PGFSM_PWR_STATUS, mask_sh), \
585 HWS_SF(, DC_IP_REQUEST_CNTL, IP_REQUEST_EN, mask_sh), \
586 HWS_SF(, AZALIA_AUDIO_DTO, AZALIA_AUDIO_DTO_MODULE, mask_sh), \
587 HWS_SF(, HPO_TOP_CLOCK_CONTROL, HPO_HDMISTREAMCLK_G_GATE_DIS, mask_sh), \
588 HWS_SF(, ODM_MEM_PWR_CTRL3, ODM_MEM_UNASSIGNED_PWR_MODE, mask_sh), \
589 HWS_SF(, ODM_MEM_PWR_CTRL3, ODM_MEM_VBLANK_PWR_MODE, mask_sh), \
590 HWS_SF(, DIO_MEM_PWR_CTRL, I2C_LIGHT_SLEEP_FORCE, mask_sh), \
591 HWS_SF(, HPO_TOP_HW_CONTROL, HPO_IO_EN, mask_sh),\
592 HWS_SF(, DMU_CLK_CNTL, DISPCLK_R_DMU_GATE_DIS, mask_sh),\
593 HWS_SF(, DMU_CLK_CNTL, DISPCLK_G_RBBMIF_GATE_DIS, mask_sh),\
594 HWS_SF(, DMU_CLK_CNTL, RBBMIF_FGCG_REP_DIS, mask_sh),\
595 HWS_SF(, DMU_CLK_CNTL, DPREFCLK_ALLOW_DS_CLKSTOP, mask_sh),\
596 HWS_SF(, DMU_CLK_CNTL, DISPCLK_ALLOW_DS_CLKSTOP, mask_sh),\
597 HWS_SF(, DMU_CLK_CNTL, DPPCLK_ALLOW_DS_CLKSTOP, mask_sh),\
598 HWS_SF(, DMU_CLK_CNTL, DTBCLK_ALLOW_DS_CLKSTOP, mask_sh),\
599 HWS_SF(, DMU_CLK_CNTL, DCFCLK_ALLOW_DS_CLKSTOP, mask_sh),\
600 HWS_SF(, DMU_CLK_CNTL, DPIACLK_ALLOW_DS_CLKSTOP, mask_sh),\
601 HWS_SF(, DMU_CLK_CNTL, LONO_FGCG_REP_DIS, mask_sh),\
602 HWS_SF(, DMU_CLK_CNTL, LONO_DISPCLK_GATE_DISABLE, mask_sh),\
603 HWS_SF(, DMU_CLK_CNTL, LONO_SOCCLK_GATE_DISABLE, mask_sh),\
604 HWS_SF(, DMU_CLK_CNTL, LONO_DMCUBCLK_GATE_DISABLE, mask_sh),\
605 HWS_SF(, DCCG_GATE_DISABLE_CNTL2, SYMCLKA_FE_GATE_DISABLE, mask_sh), \
606 HWS_SF(, DCCG_GATE_DISABLE_CNTL2, SYMCLKB_FE_GATE_DISABLE, mask_sh), \
607 HWS_SF(, DCCG_GATE_DISABLE_CNTL2, SYMCLKC_FE_GATE_DISABLE, mask_sh), \
608 HWS_SF(, DCCG_GATE_DISABLE_CNTL2, SYMCLKD_FE_GATE_DISABLE, mask_sh), \
609 HWS_SF(, DCCG_GATE_DISABLE_CNTL2, SYMCLKE_FE_GATE_DISABLE, mask_sh), \
610 HWS_SF(, DCCG_GATE_DISABLE_CNTL2, HDMICHARCLK0_GATE_DISABLE, mask_sh), \
611 HWS_SF(, DCCG_GATE_DISABLE_CNTL2, SYMCLKA_GATE_DISABLE, mask_sh), \
612 HWS_SF(, DCCG_GATE_DISABLE_CNTL2, SYMCLKB_GATE_DISABLE, mask_sh), \
613 HWS_SF(, DCCG_GATE_DISABLE_CNTL2, SYMCLKC_GATE_DISABLE, mask_sh), \
614 HWS_SF(, DCCG_GATE_DISABLE_CNTL2, SYMCLKD_GATE_DISABLE, mask_sh), \
615 HWS_SF(, DCCG_GATE_DISABLE_CNTL2, SYMCLKE_GATE_DISABLE, mask_sh), \
616 HWS_SF(, DCCG_GATE_DISABLE_CNTL2, PHYASYMCLK_ROOT_GATE_DISABLE, mask_sh), \
617 HWS_SF(, DCCG_GATE_DISABLE_CNTL2, PHYBSYMCLK_ROOT_GATE_DISABLE, mask_sh), \
618 HWS_SF(, DCCG_GATE_DISABLE_CNTL2, PHYCSYMCLK_ROOT_GATE_DISABLE, mask_sh), \
619 HWS_SF(, DCCG_GATE_DISABLE_CNTL2, PHYDSYMCLK_ROOT_GATE_DISABLE, mask_sh), \
620 HWS_SF(, DCCG_GATE_DISABLE_CNTL2, PHYESYMCLK_ROOT_GATE_DISABLE, mask_sh),\
621 HWS_SF(, DCCG_GATE_DISABLE_CNTL5, DTBCLK_P0_GATE_DISABLE, mask_sh),\
622 HWS_SF(, DCCG_GATE_DISABLE_CNTL5, DTBCLK_P1_GATE_DISABLE, mask_sh),\
623 HWS_SF(, DCCG_GATE_DISABLE_CNTL5, DTBCLK_P2_GATE_DISABLE, mask_sh),\
624 HWS_SF(, DCCG_GATE_DISABLE_CNTL5, DTBCLK_P3_GATE_DISABLE, mask_sh),\
625 HWS_SF(, DCCG_GATE_DISABLE_CNTL5, DPSTREAMCLK0_GATE_DISABLE, mask_sh),\
626 HWS_SF(, DCCG_GATE_DISABLE_CNTL5, DPSTREAMCLK1_GATE_DISABLE, mask_sh),\
627 HWS_SF(, DCCG_GATE_DISABLE_CNTL5, DPSTREAMCLK2_GATE_DISABLE, mask_sh),\
628 HWS_SF(, DCCG_GATE_DISABLE_CNTL5, DPSTREAMCLK3_GATE_DISABLE, mask_sh),\
629 HWS_SF(, DCCG_GATE_DISABLE_CNTL4, DPIASYMCLK0_GATE_DISABLE, mask_sh),\
630 HWS_SF(, DCCG_GATE_DISABLE_CNTL4, DPIASYMCLK1_GATE_DISABLE, mask_sh),\
631 HWS_SF(, DCCG_GATE_DISABLE_CNTL4, DPIASYMCLK2_GATE_DISABLE, mask_sh),\
632 HWS_SF(, DCCG_GATE_DISABLE_CNTL4, DPIASYMCLK3_GATE_DISABLE, mask_sh)
633
634 static const struct dce_hwseq_shift hwseq_shift = {
635 HWSEQ_DCN36_MASK_SH_LIST(__SHIFT)
636 };
637
638 static const struct dce_hwseq_mask hwseq_mask = {
639 HWSEQ_DCN36_MASK_SH_LIST(_MASK)
640 };
641
642 #define vmid_regs_init(id)\
643 DCN20_VMID_REG_LIST_RI(id)
644
645 static struct dcn_vmid_registers vmid_regs[16];
646
647 static const struct dcn20_vmid_shift vmid_shifts = {
648 DCN20_VMID_MASK_SH_LIST(__SHIFT)
649 };
650
651 static const struct dcn20_vmid_mask vmid_masks = {
652 DCN20_VMID_MASK_SH_LIST(_MASK)
653 };
654
655 static struct dcn_dio_registers dio_regs;
656
657 #define DIO_MASK_SH_LIST(mask_sh)\
658 HWS_SF(, DIO_MEM_PWR_CTRL, I2C_LIGHT_SLEEP_FORCE, mask_sh)
659
660 static const struct dcn_dio_shift dio_shift = {
661 DIO_MASK_SH_LIST(__SHIFT)
662 };
663
664 static const struct dcn_dio_mask dio_mask = {
665 DIO_MASK_SH_LIST(_MASK)
666 };
667
668 static const struct resource_caps res_cap_dcn36 = {
669 .num_timing_generator = 4,
670 .num_opp = 4,
671 .num_video_plane = 4,
672 .num_audio = 5,
673 .num_stream_encoder = 5,
674 .num_dig_link_enc = 5,
675 .num_hpo_dp_stream_encoder = 4,
676 .num_hpo_dp_link_encoder = 2,
677 .num_pll = 4,/*1 c10 edp, 3xc20 combo PHY*/
678 .num_dwb = 1,
679 .num_ddc = 5,
680 .num_vmid = 16,
681 .num_mpc_3dlut = 2,
682 .num_dsc = 4,
683 };
684
685 static const struct dc_plane_cap plane_cap = {
686 .type = DC_PLANE_TYPE_DCN_UNIVERSAL,
687 .per_pixel_alpha = true,
688
689 .pixel_format_support = {
690 .argb8888 = true,
691 .nv12 = true,
692 .fp16 = true,
693 .p010 = true,
694 .ayuv = false,
695 },
696
697 .max_upscale_factor = {
698 .argb8888 = 16000,
699 .nv12 = 16000,
700 .fp16 = 16000
701 },
702
703 // 6:1 downscaling ratio: 1000/6 = 166.666
704 .max_downscale_factor = {
705 .argb8888 = 250,
706 .nv12 = 167,
707 .fp16 = 167
708 },
709 64,
710 64
711 };
712
713 static const struct dc_debug_options debug_defaults_drv = {
714 .disable_dmcu = true,
715 .force_abm_enable = false,
716 .clock_trace = true,
717 .disable_pplib_clock_request = false,
718 .pipe_split_policy = MPC_SPLIT_AVOID,
719 .force_single_disp_pipe_split = false,
720 .disable_dcc = DCC_ENABLE,
721 .disable_dpp_power_gate = true,
722 .disable_hubp_power_gate = true,
723 .disable_optc_power_gate = true, /*should the same as above two*/
724 .disable_hpo_power_gate = true, /*dmubfw force domain25 on*/
725 .disable_clock_gate = false,
726 .disable_dsc_power_gate = true,
727 .vsr_support = true,
728 .performance_trace = false,
729 .max_downscale_src_width = 4096,/*upto true 4k*/
730 .disable_pplib_wm_range = false,
731 .scl_reset_length10 = true,
732 .sanity_checks = false,
733 .underflow_assert_delay_us = 0xFFFFFFFF,
734 .dwb_fi_phase = -1, // -1 = disable,
735 .dmub_command_table = true,
736 .pstate_enabled = true,
737 .use_max_lb = true,
738 .enable_mem_low_power = {
739 .bits = {
740 .vga = false,
741 .i2c = true,
742 .dmcu = false, // This is previously known to cause hang on S3 cycles if enabled
743 .dscl = true,
744 .cm = true,
745 .mpc = true,
746 .optc = true,
747 .vpg = true,
748 .afmt = true,
749 }
750 },
751 .root_clock_optimization = {
752 .bits = {
753 .dpp = true,
754 .dsc = true,/*dscclk and dsc pg*/
755 .hdmistream = true,
756 .hdmichar = true,
757 .dpstream = true,
758 .symclk32_se = true,
759 .symclk32_le = true,
760 .symclk_fe = true,
761 .physymclk = false,
762 .dpiasymclk = true,
763 }
764 },
765 .seamless_boot_odm_combine = DML_FAIL_SOURCE_PIXEL_FORMAT,
766 .enable_z9_disable_interface = true, /* Allow support for the PMFW interface for disable Z9*/
767 .minimum_z8_residency_time = 1, /* Always allow when other conditions are met */
768 .using_dml2 = true,
769 .support_eDP1_5 = true,
770 .enable_hpo_pg_support = false,
771 .enable_single_display_2to1_odm_policy = true,
772 .disable_idle_power_optimizations = false,
773 .dmcub_emulation = false,
774 .disable_boot_optimizations = false,
775 .disable_unbounded_requesting = false,
776 .disable_mem_low_power = false,
777 //must match enable_single_display_2to1_odm_policy to support dynamic ODM transitions
778 .enable_double_buffered_dsc_pg_support = true,
779 .enable_dp_dig_pixel_rate_div_policy = 1,
780 .disable_z10 = false,
781 .ignore_pg = true,
782 .psp_disabled_wa = true,
783 .ips2_eval_delay_us = 2000,
784 .ips2_entry_delay_us = 800,
785 .disable_dmub_reallow_idle = false,
786 .static_screen_wait_frames = 2,
787 .disable_timeout = true,
788 .min_disp_clk_khz = 50000,
789 };
790
791 static const struct dc_check_config config_defaults = {
792 .enable_legacy_fast_update = false,
793 };
794
795 static const struct dc_panel_config panel_config_defaults = {
796 .psr = {
797 .disable_psr = false,
798 .disallow_psrsu = false,
799 .disallow_replay = false,
800 },
801 .ilr = {
802 .optimize_edp_link_rate = true,
803 },
804 };
805
dcn35_dpp_destroy(struct dpp ** dpp)806 static void dcn35_dpp_destroy(struct dpp **dpp)
807 {
808 kfree(TO_DCN20_DPP(*dpp));
809 *dpp = NULL;
810 }
811
dcn35_dpp_create(struct dc_context * ctx,uint32_t inst)812 static struct dpp *dcn35_dpp_create(struct dc_context *ctx, uint32_t inst)
813 {
814 struct dcn3_dpp *dpp = kzalloc_obj(struct dcn3_dpp);
815 bool success = (dpp != NULL);
816
817 if (!success)
818 return NULL;
819
820 #undef REG_STRUCT
821 #define REG_STRUCT dpp_regs
822 dpp_regs_init(0),
823 dpp_regs_init(1),
824 dpp_regs_init(2),
825 dpp_regs_init(3);
826
827 success = dpp35_construct(dpp, ctx, inst, &dpp_regs[inst], &tf_shift,
828 &tf_mask);
829 if (success) {
830 dpp35_set_fgcg(
831 dpp,
832 ctx->dc->debug.enable_fine_grain_clock_gating.bits.dpp);
833 return &dpp->base;
834 }
835
836 BREAK_TO_DEBUGGER();
837 kfree(dpp);
838 return NULL;
839 }
840
dcn35_opp_create(struct dc_context * ctx,uint32_t inst)841 static struct output_pixel_processor *dcn35_opp_create(
842 struct dc_context *ctx, uint32_t inst)
843 {
844 struct dcn20_opp *opp =
845 kzalloc_obj(struct dcn20_opp);
846
847 if (!opp) {
848 BREAK_TO_DEBUGGER();
849 return NULL;
850 }
851
852 #undef REG_STRUCT
853 #define REG_STRUCT opp_regs
854 opp_regs_init(0),
855 opp_regs_init(1),
856 opp_regs_init(2),
857 opp_regs_init(3);
858
859 dcn35_opp_construct(opp, ctx, inst,
860 &opp_regs[inst], &opp_shift, &opp_mask);
861
862 dcn35_opp_set_fgcg(opp, ctx->dc->debug.enable_fine_grain_clock_gating.bits.opp);
863
864 return &opp->base;
865 }
866
dcn31_aux_engine_create(struct dc_context * ctx,uint32_t inst)867 static struct dce_aux *dcn31_aux_engine_create(
868 struct dc_context *ctx,
869 uint32_t inst)
870 {
871 struct aux_engine_dce110 *aux_engine =
872 kzalloc_obj(struct aux_engine_dce110);
873
874 if (!aux_engine)
875 return NULL;
876
877 #undef REG_STRUCT
878 #define REG_STRUCT aux_engine_regs
879 aux_engine_regs_init(0),
880 aux_engine_regs_init(1),
881 aux_engine_regs_init(2),
882 aux_engine_regs_init(3),
883 aux_engine_regs_init(4);
884
885 dce110_aux_engine_construct(aux_engine, ctx, inst,
886 SW_AUX_TIMEOUT_PERIOD_MULTIPLIER * AUX_TIMEOUT_PERIOD,
887 &aux_engine_regs[inst],
888 &aux_mask,
889 &aux_shift,
890 ctx->dc->caps.extended_aux_timeout_support);
891
892 return &aux_engine->base;
893 }
894
895 #define i2c_inst_regs_init(id)\
896 I2C_HW_ENGINE_COMMON_REG_LIST_DCN30_RI(id)
897
898 static struct dce_i2c_registers i2c_hw_regs[5];
899
900 static const struct dce_i2c_shift i2c_shifts = {
901 I2C_COMMON_MASK_SH_LIST_DCN35(__SHIFT)
902 };
903
904 static const struct dce_i2c_mask i2c_masks = {
905 I2C_COMMON_MASK_SH_LIST_DCN35(_MASK)
906 };
907
908 /* ========================================================== */
909
910 /*
911 * DPIA index | Preferred Encoder | Host Router
912 * 0 | C | 0
913 * 1 | First Available | 0
914 * 2 | D | 1
915 * 3 | First Available | 1
916 */
917 /* ========================================================== */
918 static const enum engine_id dpia_to_preferred_enc_id_table[] = {
919 ENGINE_ID_DIGC,
920 ENGINE_ID_DIGC,
921 ENGINE_ID_DIGD,
922 ENGINE_ID_DIGD
923 };
924
dcn36_get_preferred_eng_id_dpia(unsigned int dpia_index)925 static enum engine_id dcn36_get_preferred_eng_id_dpia(unsigned int dpia_index)
926 {
927 return dpia_to_preferred_enc_id_table[dpia_index];
928 }
929
dcn31_i2c_hw_create(struct dc_context * ctx,uint32_t inst)930 static struct dce_i2c_hw *dcn31_i2c_hw_create(
931 struct dc_context *ctx,
932 uint32_t inst)
933 {
934 struct dce_i2c_hw *dce_i2c_hw =
935 kzalloc_obj(struct dce_i2c_hw);
936
937 if (!dce_i2c_hw)
938 return NULL;
939
940 #undef REG_STRUCT
941 #define REG_STRUCT i2c_hw_regs
942 i2c_inst_regs_init(1),
943 i2c_inst_regs_init(2),
944 i2c_inst_regs_init(3),
945 i2c_inst_regs_init(4),
946 i2c_inst_regs_init(5);
947
948 dcn2_i2c_hw_construct(dce_i2c_hw, ctx, inst,
949 &i2c_hw_regs[inst], &i2c_shifts, &i2c_masks);
950
951 return dce_i2c_hw;
952 }
dcn35_mpc_create(struct dc_context * ctx,int num_mpcc,int num_rmu)953 static struct mpc *dcn35_mpc_create(
954 struct dc_context *ctx,
955 int num_mpcc,
956 int num_rmu)
957 {
958 struct dcn30_mpc *mpc30 = kzalloc_obj(struct dcn30_mpc);
959
960 if (!mpc30)
961 return NULL;
962
963 #undef REG_STRUCT
964 #define REG_STRUCT mpc_regs
965 dcn_mpc_regs_init();
966
967 dcn32_mpc_construct(mpc30, ctx,
968 &mpc_regs,
969 &mpc_shift,
970 &mpc_mask,
971 num_mpcc,
972 num_rmu);
973
974 return &mpc30->base;
975 }
976
dcn36_dio_create(struct dc_context * ctx)977 static struct dio *dcn36_dio_create(struct dc_context *ctx)
978 {
979 struct dcn10_dio *dio10 = kzalloc_obj(struct dcn10_dio);
980
981 if (!dio10)
982 return NULL;
983
984 #undef REG_STRUCT
985 #define REG_STRUCT dio_regs
986 DIO_REG_LIST_DCN10();
987
988 dcn10_dio_construct(dio10, ctx, &dio_regs, &dio_shift, &dio_mask);
989
990 return &dio10->base;
991 }
992
dcn35_hubbub_create(struct dc_context * ctx)993 static struct hubbub *dcn35_hubbub_create(struct dc_context *ctx)
994 {
995 int i;
996
997 struct dcn20_hubbub *hubbub3 = kzalloc_obj(struct dcn20_hubbub);
998
999 if (!hubbub3)
1000 return NULL;
1001
1002 #undef REG_STRUCT
1003 #define REG_STRUCT hubbub_reg
1004 hubbub_reg_init();
1005
1006 #undef REG_STRUCT
1007 #define REG_STRUCT vmid_regs
1008 vmid_regs_init(0),
1009 vmid_regs_init(1),
1010 vmid_regs_init(2),
1011 vmid_regs_init(3),
1012 vmid_regs_init(4),
1013 vmid_regs_init(5),
1014 vmid_regs_init(6),
1015 vmid_regs_init(7),
1016 vmid_regs_init(8),
1017 vmid_regs_init(9),
1018 vmid_regs_init(10),
1019 vmid_regs_init(11),
1020 vmid_regs_init(12),
1021 vmid_regs_init(13),
1022 vmid_regs_init(14),
1023 vmid_regs_init(15);
1024
1025 hubbub35_construct(hubbub3, ctx,
1026 &hubbub_reg,
1027 &hubbub_shift,
1028 &hubbub_mask,
1029 384,/*ctx->dc->dml.ip.det_buffer_size_kbytes,*/
1030 8, /*ctx->dc->dml.ip.pixel_chunk_size_kbytes,*/
1031 1792 /*ctx->dc->dml.ip.config_return_buffer_size_in_kbytes*/);
1032
1033
1034 for (i = 0; i < res_cap_dcn36.num_vmid; i++) {
1035 struct dcn20_vmid *vmid = &hubbub3->vmid[i];
1036
1037 vmid->ctx = ctx;
1038
1039 vmid->regs = &vmid_regs[i];
1040 vmid->shifts = &vmid_shifts;
1041 vmid->masks = &vmid_masks;
1042 }
1043
1044 return &hubbub3->base;
1045 }
1046
dcn35_timing_generator_create(struct dc_context * ctx,uint32_t instance)1047 static struct timing_generator *dcn35_timing_generator_create(
1048 struct dc_context *ctx,
1049 uint32_t instance)
1050 {
1051 struct optc *tgn10 =
1052 kzalloc_obj(struct optc);
1053
1054 if (!tgn10)
1055 return NULL;
1056
1057 #undef REG_STRUCT
1058 #define REG_STRUCT optc_regs
1059 optc_regs_init(0),
1060 optc_regs_init(1),
1061 optc_regs_init(2),
1062 optc_regs_init(3);
1063
1064 tgn10->base.inst = instance;
1065 tgn10->base.ctx = ctx;
1066
1067 tgn10->tg_regs = &optc_regs[instance];
1068 tgn10->tg_shift = &optc_shift;
1069 tgn10->tg_mask = &optc_mask;
1070
1071 dcn35_timing_generator_init(tgn10);
1072
1073 return &tgn10->base;
1074 }
1075
1076 static const struct encoder_feature_support link_enc_feature = {
1077 .max_hdmi_deep_color = COLOR_DEPTH_121212,
1078 .max_hdmi_pixel_clock = 600000,
1079 .hdmi_ycbcr420_supported = true,
1080 .dp_ycbcr420_supported = true,
1081 .fec_supported = true,
1082 .flags.bits.IS_HBR2_CAPABLE = true,
1083 .flags.bits.IS_HBR3_CAPABLE = true,
1084 .flags.bits.IS_TPS3_CAPABLE = true,
1085 .flags.bits.IS_TPS4_CAPABLE = true
1086 };
1087
dcn35_link_encoder_create(struct dc_context * ctx,const struct encoder_init_data * enc_init_data)1088 static struct link_encoder *dcn35_link_encoder_create(
1089 struct dc_context *ctx,
1090 const struct encoder_init_data *enc_init_data)
1091 {
1092 struct dcn20_link_encoder *enc20 =
1093 kzalloc_obj(struct dcn20_link_encoder);
1094
1095 if (!enc20 || enc_init_data->hpd_source >= ARRAY_SIZE(link_enc_hpd_regs))
1096 return NULL;
1097
1098 #undef REG_STRUCT
1099 #define REG_STRUCT link_enc_aux_regs
1100 aux_regs_init(0),
1101 aux_regs_init(1),
1102 aux_regs_init(2),
1103 aux_regs_init(3),
1104 aux_regs_init(4);
1105
1106 #undef REG_STRUCT
1107 #define REG_STRUCT link_enc_hpd_regs
1108 hpd_regs_init(0),
1109 hpd_regs_init(1),
1110 hpd_regs_init(2),
1111 hpd_regs_init(3),
1112 hpd_regs_init(4);
1113
1114 #undef REG_STRUCT
1115 #define REG_STRUCT link_enc_regs
1116 link_regs_init(0, A),
1117 link_regs_init(1, B),
1118 link_regs_init(2, C),
1119 link_regs_init(3, D),
1120 link_regs_init(4, E);
1121
1122 dcn35_link_encoder_construct(enc20,
1123 enc_init_data,
1124 &link_enc_feature,
1125 &link_enc_regs[enc_init_data->transmitter],
1126 &link_enc_aux_regs[enc_init_data->channel - 1],
1127 &link_enc_hpd_regs[enc_init_data->hpd_source],
1128 &le_shift,
1129 &le_mask);
1130
1131 return &enc20->enc10.base;
1132 }
1133
1134 /* Create a minimal link encoder object not associated with a particular
1135 * physical connector.
1136 * resource_funcs.link_enc_create_minimal
1137 */
dcn31_link_enc_create_minimal(struct dc_context * ctx,enum engine_id eng_id)1138 static struct link_encoder *dcn31_link_enc_create_minimal(
1139 struct dc_context *ctx, enum engine_id eng_id)
1140 {
1141 struct dcn20_link_encoder *enc20;
1142
1143 if ((eng_id - ENGINE_ID_DIGA) > ctx->dc->res_pool->res_cap->num_dig_link_enc)
1144 return NULL;
1145
1146 enc20 = kzalloc_obj(struct dcn20_link_encoder);
1147 if (!enc20)
1148 return NULL;
1149
1150 dcn31_link_encoder_construct_minimal(
1151 enc20,
1152 ctx,
1153 &link_enc_feature,
1154 &link_enc_regs[eng_id - ENGINE_ID_DIGA],
1155 eng_id);
1156
1157 return &enc20->enc10.base;
1158 }
1159
dcn31_panel_cntl_create(const struct panel_cntl_init_data * init_data)1160 static struct panel_cntl *dcn31_panel_cntl_create(const struct panel_cntl_init_data *init_data)
1161 {
1162 struct dcn31_panel_cntl *panel_cntl =
1163 kzalloc_obj(struct dcn31_panel_cntl);
1164
1165 if (!panel_cntl)
1166 return NULL;
1167
1168 dcn31_panel_cntl_construct(panel_cntl, init_data);
1169
1170 return &panel_cntl->base;
1171 }
1172
read_dce_straps(struct dc_context * ctx,struct resource_straps * straps)1173 static void read_dce_straps(
1174 struct dc_context *ctx,
1175 struct resource_straps *straps)
1176 {
1177 generic_reg_get(ctx, regDC_PINSTRAPS + BASE(regDC_PINSTRAPS_BASE_IDX),
1178 FN(DC_PINSTRAPS, DC_PINSTRAPS_AUDIO), &straps->dc_pinstraps_audio);
1179
1180 }
1181
dcn31_create_audio(struct dc_context * ctx,unsigned int inst)1182 static struct audio *dcn31_create_audio(
1183 struct dc_context *ctx, unsigned int inst)
1184 {
1185
1186 #undef REG_STRUCT
1187 #define REG_STRUCT audio_regs
1188 audio_regs_init(0),
1189 audio_regs_init(1),
1190 audio_regs_init(2),
1191 audio_regs_init(3),
1192 audio_regs_init(4);
1193 audio_regs_init(5);
1194 audio_regs_init(6);
1195
1196 return dce_audio_create(ctx, inst,
1197 &audio_regs[inst], &audio_shift, &audio_mask);
1198 }
1199
dcn31_vpg_create(struct dc_context * ctx,uint32_t inst)1200 static struct vpg *dcn31_vpg_create(
1201 struct dc_context *ctx,
1202 uint32_t inst)
1203 {
1204 struct dcn31_vpg *vpg31 = kzalloc_obj(struct dcn31_vpg);
1205
1206 if (!vpg31)
1207 return NULL;
1208
1209 #undef REG_STRUCT
1210 #define REG_STRUCT vpg_regs
1211 vpg_regs_init(0),
1212 vpg_regs_init(1),
1213 vpg_regs_init(2),
1214 vpg_regs_init(3),
1215 vpg_regs_init(4),
1216 vpg_regs_init(5),
1217 vpg_regs_init(6),
1218 vpg_regs_init(7),
1219 vpg_regs_init(8),
1220 vpg_regs_init(9);
1221
1222 vpg31_construct(vpg31, ctx, inst,
1223 &vpg_regs[inst],
1224 &vpg_shift,
1225 &vpg_mask);
1226
1227 return &vpg31->base;
1228 }
1229
dcn31_afmt_create(struct dc_context * ctx,uint32_t inst)1230 static struct afmt *dcn31_afmt_create(
1231 struct dc_context *ctx,
1232 uint32_t inst)
1233 {
1234 struct dcn31_afmt *afmt31 = kzalloc_obj(struct dcn31_afmt);
1235
1236 if (!afmt31)
1237 return NULL;
1238
1239 #undef REG_STRUCT
1240 #define REG_STRUCT afmt_regs
1241 afmt_regs_init(0),
1242 afmt_regs_init(1),
1243 afmt_regs_init(2),
1244 afmt_regs_init(3),
1245 afmt_regs_init(4),
1246 afmt_regs_init(5);
1247
1248 afmt31_construct(afmt31, ctx, inst,
1249 &afmt_regs[inst],
1250 &afmt_shift,
1251 &afmt_mask);
1252
1253 // Light sleep by default, no need to power down here
1254
1255 return &afmt31->base;
1256 }
1257
dcn31_apg_create(struct dc_context * ctx,uint32_t inst)1258 static struct apg *dcn31_apg_create(
1259 struct dc_context *ctx,
1260 uint32_t inst)
1261 {
1262 struct dcn31_apg *apg31 = kzalloc_obj(struct dcn31_apg);
1263
1264 if (!apg31)
1265 return NULL;
1266
1267 #undef REG_STRUCT
1268 #define REG_STRUCT apg_regs
1269 apg_regs_init(0),
1270 apg_regs_init(1),
1271 apg_regs_init(2),
1272 apg_regs_init(3);
1273
1274 apg31_construct(apg31, ctx, inst,
1275 &apg_regs[inst],
1276 &apg_shift,
1277 &apg_mask);
1278
1279 return &apg31->base;
1280 }
1281
dcn35_stream_encoder_create(enum engine_id eng_id,struct dc_context * ctx)1282 static struct stream_encoder *dcn35_stream_encoder_create(
1283 enum engine_id eng_id,
1284 struct dc_context *ctx)
1285 {
1286 struct dcn10_stream_encoder *enc1;
1287 struct vpg *vpg;
1288 struct afmt *afmt;
1289 int vpg_inst;
1290 int afmt_inst;
1291
1292 /* Mapping of VPG, AFMT, DME register blocks to DIO block instance */
1293 if (eng_id <= ENGINE_ID_DIGF) {
1294 vpg_inst = eng_id;
1295 afmt_inst = eng_id;
1296 } else
1297 return NULL;
1298
1299 enc1 = kzalloc_obj(struct dcn10_stream_encoder);
1300 vpg = dcn31_vpg_create(ctx, vpg_inst);
1301 afmt = dcn31_afmt_create(ctx, afmt_inst);
1302
1303 if (!enc1 || !vpg || !afmt) {
1304 kfree(enc1);
1305 kfree(vpg);
1306 kfree(afmt);
1307 return NULL;
1308 }
1309
1310 #undef REG_STRUCT
1311 #define REG_STRUCT stream_enc_regs
1312 stream_enc_regs_init(0),
1313 stream_enc_regs_init(1),
1314 stream_enc_regs_init(2),
1315 stream_enc_regs_init(3),
1316 stream_enc_regs_init(4);
1317
1318 dcn35_dio_stream_encoder_construct(enc1, ctx, ctx->dc_bios,
1319 eng_id, vpg, afmt,
1320 &stream_enc_regs[eng_id],
1321 &se_shift, &se_mask);
1322
1323 return &enc1->base;
1324 }
1325
dcn31_hpo_dp_stream_encoder_create(enum engine_id eng_id,struct dc_context * ctx)1326 static struct hpo_dp_stream_encoder *dcn31_hpo_dp_stream_encoder_create(
1327 enum engine_id eng_id,
1328 struct dc_context *ctx)
1329 {
1330 struct dcn31_hpo_dp_stream_encoder *hpo_dp_enc31;
1331 struct vpg *vpg;
1332 struct apg *apg;
1333 uint32_t hpo_dp_inst;
1334 uint32_t vpg_inst;
1335 uint32_t apg_inst;
1336
1337 ASSERT((eng_id >= ENGINE_ID_HPO_DP_0) && (eng_id <= ENGINE_ID_HPO_DP_3));
1338 hpo_dp_inst = eng_id - ENGINE_ID_HPO_DP_0;
1339
1340 /* Mapping of VPG register blocks to HPO DP block instance:
1341 * VPG[6] -> HPO_DP[0]
1342 * VPG[7] -> HPO_DP[1]
1343 * VPG[8] -> HPO_DP[2]
1344 * VPG[9] -> HPO_DP[3]
1345 */
1346 vpg_inst = hpo_dp_inst + 6;
1347
1348 /* Mapping of APG register blocks to HPO DP block instance:
1349 * APG[0] -> HPO_DP[0]
1350 * APG[1] -> HPO_DP[1]
1351 * APG[2] -> HPO_DP[2]
1352 * APG[3] -> HPO_DP[3]
1353 */
1354 apg_inst = hpo_dp_inst;
1355
1356 /* allocate HPO stream encoder and create VPG sub-block */
1357 hpo_dp_enc31 = kzalloc_obj(struct dcn31_hpo_dp_stream_encoder);
1358 vpg = dcn31_vpg_create(ctx, vpg_inst);
1359 apg = dcn31_apg_create(ctx, apg_inst);
1360
1361 if (!hpo_dp_enc31 || !vpg || !apg) {
1362 kfree(hpo_dp_enc31);
1363 kfree(vpg);
1364 kfree(apg);
1365 return NULL;
1366 }
1367
1368 #undef REG_STRUCT
1369 #define REG_STRUCT hpo_dp_stream_enc_regs
1370 hpo_dp_stream_encoder_reg_init(0),
1371 hpo_dp_stream_encoder_reg_init(1),
1372 hpo_dp_stream_encoder_reg_init(2),
1373 hpo_dp_stream_encoder_reg_init(3);
1374
1375 dcn31_hpo_dp_stream_encoder_construct(hpo_dp_enc31, ctx, ctx->dc_bios,
1376 hpo_dp_inst, eng_id, vpg, apg,
1377 &hpo_dp_stream_enc_regs[hpo_dp_inst],
1378 &hpo_dp_se_shift, &hpo_dp_se_mask);
1379
1380 return &hpo_dp_enc31->base;
1381 }
1382
dcn31_hpo_dp_link_encoder_create(uint8_t inst,struct dc_context * ctx)1383 static struct hpo_dp_link_encoder *dcn31_hpo_dp_link_encoder_create(
1384 uint8_t inst,
1385 struct dc_context *ctx)
1386 {
1387 struct dcn31_hpo_dp_link_encoder *hpo_dp_enc31;
1388
1389 /* allocate HPO link encoder */
1390 hpo_dp_enc31 = kzalloc_obj(struct dcn31_hpo_dp_link_encoder);
1391 if (!hpo_dp_enc31)
1392 return NULL; /* out of memory */
1393
1394 #undef REG_STRUCT
1395 #define REG_STRUCT hpo_dp_link_enc_regs
1396 hpo_dp_link_encoder_reg_init(0),
1397 hpo_dp_link_encoder_reg_init(1);
1398
1399 hpo_dp_link_encoder31_construct(hpo_dp_enc31, ctx, inst,
1400 &hpo_dp_link_enc_regs[inst],
1401 &hpo_dp_le_shift, &hpo_dp_le_mask);
1402
1403 return &hpo_dp_enc31->base;
1404 }
1405
dcn36_hwseq_create(struct dc_context * ctx)1406 static struct dce_hwseq *dcn36_hwseq_create(
1407 struct dc_context *ctx)
1408 {
1409 struct dce_hwseq *hws = kzalloc_obj(struct dce_hwseq);
1410
1411 #undef REG_STRUCT
1412 #define REG_STRUCT hwseq_reg
1413 hwseq_reg_init();
1414
1415 if (hws) {
1416 hws->ctx = ctx;
1417 hws->regs = &hwseq_reg;
1418 hws->shifts = &hwseq_shift;
1419 hws->masks = &hwseq_mask;
1420 }
1421 return hws;
1422 }
1423 static const struct resource_create_funcs res_create_funcs = {
1424 .read_dce_straps = read_dce_straps,
1425 .create_audio = dcn31_create_audio,
1426 .create_stream_encoder = dcn35_stream_encoder_create,
1427 .create_hpo_dp_stream_encoder = dcn31_hpo_dp_stream_encoder_create,
1428 .create_hpo_dp_link_encoder = dcn31_hpo_dp_link_encoder_create,
1429 .create_hwseq = dcn36_hwseq_create,
1430 };
1431
dcn36_resource_destruct(struct dcn36_resource_pool * pool)1432 static void dcn36_resource_destruct(struct dcn36_resource_pool *pool)
1433 {
1434 unsigned int i;
1435
1436 for (i = 0; i < pool->base.stream_enc_count; i++) {
1437 if (pool->base.stream_enc[i] != NULL) {
1438 if (pool->base.stream_enc[i]->vpg != NULL) {
1439 kfree(DCN30_VPG_FROM_VPG(pool->base.stream_enc[i]->vpg));
1440 pool->base.stream_enc[i]->vpg = NULL;
1441 }
1442 if (pool->base.stream_enc[i]->afmt != NULL) {
1443 kfree(DCN30_AFMT_FROM_AFMT(pool->base.stream_enc[i]->afmt));
1444 pool->base.stream_enc[i]->afmt = NULL;
1445 }
1446 kfree(DCN10STRENC_FROM_STRENC(pool->base.stream_enc[i]));
1447 pool->base.stream_enc[i] = NULL;
1448 }
1449 }
1450
1451 for (i = 0; i < pool->base.hpo_dp_stream_enc_count; i++) {
1452 if (pool->base.hpo_dp_stream_enc[i] != NULL) {
1453 if (pool->base.hpo_dp_stream_enc[i]->vpg != NULL) {
1454 kfree(DCN30_VPG_FROM_VPG(pool->base.hpo_dp_stream_enc[i]->vpg));
1455 pool->base.hpo_dp_stream_enc[i]->vpg = NULL;
1456 }
1457 if (pool->base.hpo_dp_stream_enc[i]->apg != NULL) {
1458 kfree(DCN31_APG_FROM_APG(pool->base.hpo_dp_stream_enc[i]->apg));
1459 pool->base.hpo_dp_stream_enc[i]->apg = NULL;
1460 }
1461 kfree(DCN3_1_HPO_DP_STREAM_ENC_FROM_HPO_STREAM_ENC(pool->base.hpo_dp_stream_enc[i]));
1462 pool->base.hpo_dp_stream_enc[i] = NULL;
1463 }
1464 }
1465
1466 for (i = 0; i < pool->base.hpo_dp_link_enc_count; i++) {
1467 if (pool->base.hpo_dp_link_enc[i] != NULL) {
1468 kfree(DCN3_1_HPO_DP_LINK_ENC_FROM_HPO_LINK_ENC(pool->base.hpo_dp_link_enc[i]));
1469 pool->base.hpo_dp_link_enc[i] = NULL;
1470 }
1471 }
1472
1473 for (i = 0; i < pool->base.res_cap->num_dsc; i++) {
1474 if (pool->base.dscs[i] != NULL)
1475 dcn20_dsc_destroy(&pool->base.dscs[i]);
1476 }
1477
1478 if (pool->base.mpc != NULL) {
1479 kfree(TO_DCN20_MPC(pool->base.mpc));
1480 pool->base.mpc = NULL;
1481 }
1482 if (pool->base.hubbub != NULL) {
1483 kfree(pool->base.hubbub);
1484 pool->base.hubbub = NULL;
1485 }
1486 for (i = 0; i < pool->base.pipe_count; i++) {
1487 if (pool->base.dpps[i] != NULL)
1488 dcn35_dpp_destroy(&pool->base.dpps[i]);
1489
1490 if (pool->base.ipps[i] != NULL)
1491 pool->base.ipps[i]->funcs->ipp_destroy(&pool->base.ipps[i]);
1492
1493 if (pool->base.hubps[i] != NULL) {
1494 kfree(TO_DCN20_HUBP(pool->base.hubps[i]));
1495 pool->base.hubps[i] = NULL;
1496 }
1497
1498 if (pool->base.irqs != NULL) {
1499 dal_irq_service_destroy(&pool->base.irqs);
1500 }
1501 }
1502
1503 for (i = 0; i < pool->base.res_cap->num_ddc; i++) {
1504 if (pool->base.engines[i] != NULL)
1505 dce110_engine_destroy(&pool->base.engines[i]);
1506 if (pool->base.hw_i2cs[i] != NULL) {
1507 kfree(pool->base.hw_i2cs[i]);
1508 pool->base.hw_i2cs[i] = NULL;
1509 }
1510 if (pool->base.sw_i2cs[i] != NULL) {
1511 kfree(pool->base.sw_i2cs[i]);
1512 pool->base.sw_i2cs[i] = NULL;
1513 }
1514 }
1515
1516 for (i = 0; i < pool->base.res_cap->num_opp; i++) {
1517 if (pool->base.opps[i] != NULL)
1518 pool->base.opps[i]->funcs->opp_destroy(&pool->base.opps[i]);
1519 }
1520
1521 for (i = 0; i < pool->base.res_cap->num_timing_generator; i++) {
1522 if (pool->base.timing_generators[i] != NULL) {
1523 kfree(DCN10TG_FROM_TG(pool->base.timing_generators[i]));
1524 pool->base.timing_generators[i] = NULL;
1525 }
1526 }
1527
1528 for (i = 0; i < pool->base.res_cap->num_dwb; i++) {
1529 if (pool->base.dwbc[i] != NULL) {
1530 kfree(TO_DCN30_DWBC(pool->base.dwbc[i]));
1531 pool->base.dwbc[i] = NULL;
1532 }
1533 if (pool->base.mcif_wb[i] != NULL) {
1534 kfree(TO_DCN30_MMHUBBUB(pool->base.mcif_wb[i]));
1535 pool->base.mcif_wb[i] = NULL;
1536 }
1537 }
1538
1539 for (i = 0; i < pool->base.audio_count; i++) {
1540 if (pool->base.audios[i])
1541 dce_aud_destroy(&pool->base.audios[i]);
1542 }
1543
1544 for (i = 0; i < pool->base.clk_src_count; i++) {
1545 if (pool->base.clock_sources[i] != NULL) {
1546 dcn20_clock_source_destroy(&pool->base.clock_sources[i]);
1547 pool->base.clock_sources[i] = NULL;
1548 }
1549 }
1550
1551 for (i = 0; i < pool->base.res_cap->num_mpc_3dlut; i++) {
1552 if (pool->base.mpc_lut[i] != NULL) {
1553 dc_3dlut_func_release(pool->base.mpc_lut[i]);
1554 pool->base.mpc_lut[i] = NULL;
1555 }
1556 if (pool->base.mpc_shaper[i] != NULL) {
1557 dc_transfer_func_release(pool->base.mpc_shaper[i]);
1558 pool->base.mpc_shaper[i] = NULL;
1559 }
1560 }
1561
1562 if (pool->base.dp_clock_source != NULL) {
1563 dcn20_clock_source_destroy(&pool->base.dp_clock_source);
1564 pool->base.dp_clock_source = NULL;
1565 }
1566
1567 for (i = 0; i < pool->base.res_cap->num_timing_generator; i++) {
1568 if (pool->base.multiple_abms[i] != NULL)
1569 dce_abm_destroy(&pool->base.multiple_abms[i]);
1570 }
1571
1572 if (pool->base.psr != NULL)
1573 dmub_psr_destroy(&pool->base.psr);
1574
1575 if (pool->base.replay != NULL)
1576 dmub_replay_destroy(&pool->base.replay);
1577
1578 if (pool->base.pg_cntl != NULL)
1579 dcn_pg_cntl_destroy(&pool->base.pg_cntl);
1580
1581 if (pool->base.dccg != NULL)
1582 dcn_dccg_destroy(&pool->base.dccg);
1583
1584 if (pool->base.dio != NULL) {
1585 kfree(TO_DCN10_DIO(pool->base.dio));
1586 pool->base.dio = NULL;
1587 }
1588 }
1589
dcn35_hubp_create(struct dc_context * ctx,uint32_t inst)1590 static struct hubp *dcn35_hubp_create(
1591 struct dc_context *ctx,
1592 uint32_t inst)
1593 {
1594 struct dcn20_hubp *hubp2 =
1595 kzalloc_obj(struct dcn20_hubp);
1596
1597 if (!hubp2)
1598 return NULL;
1599
1600 #undef REG_STRUCT
1601 #define REG_STRUCT hubp_regs
1602 hubp_regs_init(0),
1603 hubp_regs_init(1),
1604 hubp_regs_init(2),
1605 hubp_regs_init(3);
1606
1607 if (hubp35_construct(hubp2, ctx, inst,
1608 &hubp_regs[inst], &hubp_shift, &hubp_mask))
1609 return &hubp2->base;
1610
1611 BREAK_TO_DEBUGGER();
1612 kfree(hubp2);
1613 return NULL;
1614 }
1615
dcn35_dwbc_init(struct dcn30_dwbc * dwbc30,struct dc_context * ctx)1616 static void dcn35_dwbc_init(struct dcn30_dwbc *dwbc30, struct dc_context *ctx)
1617 {
1618 dcn35_dwbc_set_fgcg(
1619 dwbc30, ctx->dc->debug.enable_fine_grain_clock_gating.bits.dwb);
1620 }
1621
dcn35_dwbc_create(struct dc_context * ctx,struct resource_pool * pool)1622 static bool dcn35_dwbc_create(struct dc_context *ctx, struct resource_pool *pool)
1623 {
1624 int i;
1625 uint32_t pipe_count = pool->res_cap->num_dwb;
1626
1627 for (i = 0; i < pipe_count; i++) {
1628 struct dcn30_dwbc *dwbc30 = kzalloc_obj(struct dcn30_dwbc);
1629
1630 if (!dwbc30) {
1631 dm_error("DC: failed to create dwbc30!\n");
1632 return false;
1633 }
1634
1635 #undef REG_STRUCT
1636 #define REG_STRUCT dwbc35_regs
1637 dwbc_regs_dcn3_init(0);
1638
1639 dcn35_dwbc_construct(dwbc30, ctx,
1640 &dwbc35_regs[i],
1641 &dwbc35_shift,
1642 &dwbc35_mask,
1643 i);
1644
1645 pool->dwbc[i] = &dwbc30->base;
1646
1647 dcn35_dwbc_init(dwbc30, ctx);
1648 }
1649 return true;
1650 }
1651
dcn35_mmhubbub_init(struct dcn30_mmhubbub * mcif_wb30,struct dc_context * ctx)1652 static void dcn35_mmhubbub_init(struct dcn30_mmhubbub *mcif_wb30,
1653 struct dc_context *ctx)
1654 {
1655 dcn35_mmhubbub_set_fgcg(
1656 mcif_wb30,
1657 ctx->dc->debug.enable_fine_grain_clock_gating.bits.mmhubbub);
1658 }
1659
dcn35_mmhubbub_create(struct dc_context * ctx,struct resource_pool * pool)1660 static bool dcn35_mmhubbub_create(struct dc_context *ctx, struct resource_pool *pool)
1661 {
1662 int i;
1663 uint32_t pipe_count = pool->res_cap->num_dwb;
1664
1665 for (i = 0; i < pipe_count; i++) {
1666 struct dcn30_mmhubbub *mcif_wb30 = kzalloc_obj(struct dcn30_mmhubbub);
1667
1668 if (!mcif_wb30) {
1669 dm_error("DC: failed to create mcif_wb30!\n");
1670 return false;
1671 }
1672
1673 #undef REG_STRUCT
1674 #define REG_STRUCT mcif_wb35_regs
1675 mcif_wb_regs_dcn3_init(0);
1676
1677 dcn35_mmhubbub_construct(mcif_wb30, ctx,
1678 &mcif_wb35_regs[i],
1679 &mcif_wb35_shift,
1680 &mcif_wb35_mask,
1681 i);
1682
1683 dcn35_mmhubbub_init(mcif_wb30, ctx);
1684
1685 pool->mcif_wb[i] = &mcif_wb30->base;
1686 }
1687 return true;
1688 }
1689
dcn35_dsc_create(struct dc_context * ctx,uint32_t inst)1690 static struct display_stream_compressor *dcn35_dsc_create(
1691 struct dc_context *ctx, uint32_t inst)
1692 {
1693 struct dcn20_dsc *dsc =
1694 kzalloc_obj(struct dcn20_dsc);
1695
1696 if (!dsc) {
1697 BREAK_TO_DEBUGGER();
1698 return NULL;
1699 }
1700
1701 #undef REG_STRUCT
1702 #define REG_STRUCT dsc_regs
1703 dsc_regsDCN35_init(0),
1704 dsc_regsDCN35_init(1),
1705 dsc_regsDCN35_init(2),
1706 dsc_regsDCN35_init(3);
1707
1708 dsc35_construct(dsc, ctx, inst, &dsc_regs[inst], &dsc_shift, &dsc_mask);
1709 dsc35_set_fgcg(dsc,
1710 ctx->dc->debug.enable_fine_grain_clock_gating.bits.dsc);
1711 return &dsc->base;
1712 }
1713
dcn36_destroy_resource_pool(struct resource_pool ** pool)1714 static void dcn36_destroy_resource_pool(struct resource_pool **pool)
1715 {
1716 struct dcn36_resource_pool *dcn36_pool = TO_DCN36_RES_POOL(*pool);
1717
1718 dcn36_resource_destruct(dcn36_pool);
1719 kfree(dcn36_pool);
1720 *pool = NULL;
1721 }
1722
dcn35_clock_source_create(struct dc_context * ctx,struct dc_bios * bios,enum clock_source_id id,const struct dce110_clk_src_regs * regs,bool dp_clk_src)1723 static struct clock_source *dcn35_clock_source_create(
1724 struct dc_context *ctx,
1725 struct dc_bios *bios,
1726 enum clock_source_id id,
1727 const struct dce110_clk_src_regs *regs,
1728 bool dp_clk_src)
1729 {
1730 struct dce110_clk_src *clk_src =
1731 kzalloc_obj(struct dce110_clk_src);
1732
1733 if (!clk_src)
1734 return NULL;
1735
1736 if (dcn31_clk_src_construct(clk_src, ctx, bios, id,
1737 regs, &cs_shift, &cs_mask)) {
1738 clk_src->base.dp_clk_src = dp_clk_src;
1739 return &clk_src->base;
1740 }
1741
1742 kfree(clk_src);
1743 BREAK_TO_DEBUGGER();
1744 return NULL;
1745 }
1746
1747 static struct dc_cap_funcs cap_funcs = {
1748 .get_dcc_compression_cap = dcn20_get_dcc_compression_cap
1749 };
1750
dcn35_get_panel_config_defaults(struct dc_panel_config * panel_config)1751 static void dcn35_get_panel_config_defaults(struct dc_panel_config *panel_config)
1752 {
1753 *panel_config = panel_config_defaults;
1754 }
1755
1756
dcn35_validate_bandwidth(struct dc * dc,struct dc_state * context,enum dc_validate_mode validate_mode)1757 static enum dc_status dcn35_validate_bandwidth(struct dc *dc,
1758 struct dc_state *context,
1759 enum dc_validate_mode validate_mode)
1760 {
1761 bool out = false;
1762
1763 out = dml2_validate(dc, context,
1764 context->power_source == DC_POWER_SOURCE_DC ? context->bw_ctx.dml2_dc_power_source : context->bw_ctx.dml2,
1765 validate_mode);
1766
1767 if (validate_mode != DC_VALIDATE_MODE_AND_PROGRAMMING)
1768 return out ? DC_OK : DC_FAIL_BANDWIDTH_VALIDATE;
1769
1770 DC_FP_START();
1771 dcn35_decide_zstate_support(dc, context);
1772 DC_FP_END();
1773
1774 return out ? DC_OK : DC_FAIL_BANDWIDTH_VALIDATE;
1775 }
1776
1777
populate_dml_pipes_from_context_fpu(struct dc * dc,struct dc_state * context,display_e2e_pipe_params_st * pipes,enum dc_validate_mode validate_mode)1778 static int populate_dml_pipes_from_context_fpu(struct dc *dc,
1779 struct dc_state *context,
1780 display_e2e_pipe_params_st *pipes,
1781 enum dc_validate_mode validate_mode)
1782 {
1783 int ret;
1784
1785 DC_FP_START();
1786 ret = dcn35_populate_dml_pipes_from_context_fpu(dc, context, pipes, validate_mode);
1787 DC_FP_END();
1788
1789 return ret;
1790 }
1791
1792 static struct resource_funcs dcn36_res_pool_funcs = {
1793 .destroy = dcn36_destroy_resource_pool,
1794 .link_enc_create = dcn35_link_encoder_create,
1795 .link_enc_create_minimal = dcn31_link_enc_create_minimal,
1796 .link_encs_assign = link_enc_cfg_link_encs_assign,
1797 .link_enc_unassign = link_enc_cfg_link_enc_unassign,
1798 .panel_cntl_create = dcn31_panel_cntl_create,
1799 .validate_bandwidth = dcn35_validate_bandwidth,
1800 .calculate_wm_and_dlg = NULL,
1801 .update_soc_for_wm_a = dcn31_update_soc_for_wm_a,
1802 .populate_dml_pipes = populate_dml_pipes_from_context_fpu,
1803 .acquire_free_pipe_as_secondary_dpp_pipe = dcn20_acquire_free_pipe_for_layer,
1804 .release_pipe = dcn20_release_pipe,
1805 .add_stream_to_ctx = dcn30_add_stream_to_ctx,
1806 .add_dsc_to_stream_resource = dcn20_add_dsc_to_stream_resource,
1807 .remove_stream_from_ctx = dcn20_remove_stream_from_ctx,
1808 .populate_dml_writeback_from_context = dcn30_populate_dml_writeback_from_context,
1809 .set_mcif_arb_params = dcn30_set_mcif_arb_params,
1810 .find_first_free_match_stream_enc_for_link = dcn10_find_first_free_match_stream_enc_for_link,
1811 .acquire_post_bldn_3dlut = dcn30_acquire_post_bldn_3dlut,
1812 .release_post_bldn_3dlut = dcn30_release_post_bldn_3dlut,
1813 .update_bw_bounding_box = dcn35_update_bw_bounding_box_fpu,
1814 .patch_unknown_plane_state = dcn20_patch_unknown_plane_state,
1815 .get_panel_config_defaults = dcn35_get_panel_config_defaults,
1816 .get_preferred_eng_id_dpia = dcn36_get_preferred_eng_id_dpia,
1817 .get_vstartup_for_pipe = dcn10_get_vstartup_for_pipe,
1818 .update_dc_state_for_encoder_switch = dcn31_update_dc_state_for_encoder_switch,
1819 .build_pipe_pix_clk_params = dcn20_build_pipe_pix_clk_params
1820 };
1821
dcn36_resource_construct(uint8_t num_virtual_links,struct dc * dc,struct dcn36_resource_pool * pool)1822 static bool dcn36_resource_construct(
1823 uint8_t num_virtual_links,
1824 struct dc *dc,
1825 struct dcn36_resource_pool *pool)
1826 {
1827 int i;
1828 struct dc_context *ctx = dc->ctx;
1829 struct irq_service_init_data init_data;
1830
1831 #undef REG_STRUCT
1832 #define REG_STRUCT bios_regs
1833 bios_regs_init();
1834
1835 #undef REG_STRUCT
1836 #define REG_STRUCT clk_src_regs
1837 clk_src_regs_init(0, A),
1838 clk_src_regs_init(1, B),
1839 clk_src_regs_init(2, C),
1840 clk_src_regs_init(3, D),
1841 clk_src_regs_init(4, E);
1842
1843 #undef REG_STRUCT
1844 #define REG_STRUCT abm_regs
1845 abm_regs_init(0),
1846 abm_regs_init(1),
1847 abm_regs_init(2),
1848 abm_regs_init(3);
1849
1850 #undef REG_STRUCT
1851 #define REG_STRUCT dccg_regs
1852 dccg_regs_init();
1853
1854 ctx->dc_bios->regs = &bios_regs;
1855
1856 pool->base.res_cap = &res_cap_dcn36;
1857
1858 pool->base.funcs = &dcn36_res_pool_funcs;
1859
1860 /*************************************************
1861 * Resource + asic cap harcoding *
1862 *************************************************/
1863 pool->base.underlay_pipe_index = NO_UNDERLAY_PIPE;
1864 pool->base.pipe_count = pool->base.res_cap->num_timing_generator;
1865 pool->base.mpcc_count = pool->base.res_cap->num_timing_generator;
1866 dc->caps.max_downscale_ratio = 600;
1867 dc->caps.i2c_speed_in_khz = 100;
1868 dc->caps.i2c_speed_in_khz_hdcp = 100;
1869 dc->caps.max_cursor_size = 256;
1870 dc->caps.min_horizontal_blanking_period = 80;
1871 dc->caps.dmdata_alloc_size = 2048;
1872 dc->caps.max_slave_planes = 3;
1873 dc->caps.max_slave_yuv_planes = 3;
1874 dc->caps.max_slave_rgb_planes = 3;
1875 dc->caps.post_blend_color_processing = true;
1876 dc->caps.force_dp_tps4_for_cp2520 = true;
1877 if (dc->config.forceHBR2CP2520)
1878 dc->caps.force_dp_tps4_for_cp2520 = false;
1879 dc->caps.dp_hpo = true;
1880 dc->caps.dp_hdmi21_pcon_support = true;
1881
1882 dc->caps.edp_dsc_support = true;
1883 dc->caps.extended_aux_timeout_support = true;
1884 dc->caps.dmcub_support = true;
1885 dc->caps.is_apu = true;
1886 dc->caps.seamless_odm = true;
1887
1888 dc->caps.zstate_support = true;
1889 dc->caps.ips_support = true;
1890 dc->caps.max_v_total = (1 << 15) - 1;
1891 dc->caps.vtotal_limited_by_fp2 = true;
1892
1893 /* Color pipeline capabilities */
1894 dc->caps.color.dpp.dcn_arch = 1;
1895 dc->caps.color.dpp.input_lut_shared = 0;
1896 dc->caps.color.dpp.icsc = 1;
1897 dc->caps.color.dpp.dgam_ram = 0; // must use gamma_corr
1898 dc->caps.color.dpp.dgam_rom_caps.srgb = 1;
1899 dc->caps.color.dpp.dgam_rom_caps.bt2020 = 1;
1900 dc->caps.color.dpp.dgam_rom_caps.gamma2_2 = 1;
1901 dc->caps.color.dpp.dgam_rom_caps.pq = 1;
1902 dc->caps.color.dpp.dgam_rom_caps.hlg = 1;
1903 dc->caps.color.dpp.post_csc = 1;
1904 dc->caps.color.dpp.gamma_corr = 1;
1905 dc->caps.color.dpp.dgam_rom_for_yuv = 0;
1906
1907 dc->caps.color.dpp.hw_3d_lut = 0;
1908 dc->caps.color.dpp.ogam_ram = 0; // no OGAM in DPP since DCN1
1909 // no OGAM ROM on DCN301
1910 dc->caps.color.dpp.ogam_rom_caps.srgb = 0;
1911 dc->caps.color.dpp.ogam_rom_caps.bt2020 = 0;
1912 dc->caps.color.dpp.ogam_rom_caps.gamma2_2 = 0;
1913 dc->caps.color.dpp.ogam_rom_caps.pq = 0;
1914 dc->caps.color.dpp.ogam_rom_caps.hlg = 0;
1915 dc->caps.color.dpp.ocsc = 0;
1916
1917 dc->caps.color.mpc.gamut_remap = 1;
1918 dc->caps.color.mpc.num_3dluts = pool->base.res_cap->num_mpc_3dlut; //2
1919 dc->caps.color.mpc.ogam_ram = 1;
1920 dc->caps.color.mpc.ogam_rom_caps.srgb = 0;
1921 dc->caps.color.mpc.ogam_rom_caps.bt2020 = 0;
1922 dc->caps.color.mpc.ogam_rom_caps.gamma2_2 = 0;
1923 dc->caps.color.mpc.ogam_rom_caps.pq = 0;
1924 dc->caps.color.mpc.ogam_rom_caps.hlg = 0;
1925 dc->caps.color.mpc.ocsc = 1;
1926 dc->caps.color.mpc.preblend = true;
1927
1928 dc->caps.num_of_host_routers = 2;
1929 dc->caps.num_of_dpias_per_host_router = 2;
1930
1931 /* max_disp_clock_khz_at_vmin is slightly lower than the STA value in order
1932 * to provide some margin.
1933 * It's expected for furture ASIC to have equal or higher value, in order to
1934 * have determinstic power improvement from generate to genration.
1935 * (i.e., we should not expect new ASIC generation with lower vmin rate)
1936 */
1937 dc->caps.max_disp_clock_khz_at_vmin = 650000;
1938
1939 /* Sequential ONO is based on ASIC. */
1940 if (dc->ctx->asic_id.hw_internal_rev >= 0x40)
1941 dc->caps.sequential_ono = true;
1942
1943 /* Use pipe context based otg sync logic */
1944 dc->config.use_pipe_ctx_sync_logic = true;
1945
1946 dc->config.disable_hbr_audio_dp2 = true;
1947 /* read VBIOS LTTPR caps */
1948 {
1949 if (ctx->dc_bios->funcs->get_lttpr_caps) {
1950 enum bp_result bp_query_result;
1951 uint8_t is_vbios_lttpr_enable = 0;
1952
1953 bp_query_result = ctx->dc_bios->funcs->get_lttpr_caps(ctx->dc_bios, &is_vbios_lttpr_enable);
1954 dc->caps.vbios_lttpr_enable = (bp_query_result == BP_RESULT_OK) && !!is_vbios_lttpr_enable;
1955 }
1956
1957 /* interop bit is implicit */
1958 {
1959 dc->caps.vbios_lttpr_aware = true;
1960 }
1961 }
1962 dc->check_config = config_defaults;
1963
1964 if (dc->ctx->dce_environment == DCE_ENV_PRODUCTION_DRV)
1965 dc->debug = debug_defaults_drv;
1966
1967 /*HW default is to have all the FGCG enabled, SW no need to program them*/
1968 dc->debug.enable_fine_grain_clock_gating.u32All = 0xFFFF;
1969 // Init the vm_helper
1970 if (dc->vm_helper)
1971 vm_helper_init(dc->vm_helper, 16);
1972
1973 /*************************************************
1974 * Create resources *
1975 *************************************************/
1976
1977 /* Clock Sources for Pixel Clock*/
1978 pool->base.clock_sources[DCN36_CLK_SRC_PLL0] =
1979 dcn35_clock_source_create(ctx, ctx->dc_bios,
1980 CLOCK_SOURCE_COMBO_PHY_PLL0,
1981 &clk_src_regs[0], false);
1982 pool->base.clock_sources[DCN36_CLK_SRC_PLL1] =
1983 dcn35_clock_source_create(ctx, ctx->dc_bios,
1984 CLOCK_SOURCE_COMBO_PHY_PLL1,
1985 &clk_src_regs[1], false);
1986 pool->base.clock_sources[DCN36_CLK_SRC_PLL2] =
1987 dcn35_clock_source_create(ctx, ctx->dc_bios,
1988 CLOCK_SOURCE_COMBO_PHY_PLL2,
1989 &clk_src_regs[2], false);
1990 pool->base.clock_sources[DCN36_CLK_SRC_PLL3] =
1991 dcn35_clock_source_create(ctx, ctx->dc_bios,
1992 CLOCK_SOURCE_COMBO_PHY_PLL3,
1993 &clk_src_regs[3], false);
1994 pool->base.clock_sources[DCN36_CLK_SRC_PLL4] =
1995 dcn35_clock_source_create(ctx, ctx->dc_bios,
1996 CLOCK_SOURCE_COMBO_PHY_PLL4,
1997 &clk_src_regs[4], false);
1998
1999 pool->base.clk_src_count = DCN36_CLK_SRC_TOTAL;
2000
2001 /* todo: not reuse phy_pll registers */
2002 pool->base.dp_clock_source =
2003 dcn35_clock_source_create(ctx, ctx->dc_bios,
2004 CLOCK_SOURCE_ID_DP_DTO,
2005 &clk_src_regs[0], true);
2006
2007 for (i = 0; i < pool->base.clk_src_count; i++) {
2008 if (pool->base.clock_sources[i] == NULL) {
2009 dm_error("DC: failed to create clock sources!\n");
2010 BREAK_TO_DEBUGGER();
2011 goto create_fail;
2012 }
2013 }
2014 /*temp till dml2 fully work without dml1*/
2015 dml_init_instance(&dc->dml, &dcn3_5_soc, &dcn3_5_ip, DML_PROJECT_DCN31);
2016
2017 /* TODO: DCCG */
2018 pool->base.dccg = dccg35_create(ctx, &dccg_regs, &dccg_shift, &dccg_mask);
2019 if (pool->base.dccg == NULL) {
2020 dm_error("DC: failed to create dccg!\n");
2021 BREAK_TO_DEBUGGER();
2022 goto create_fail;
2023 }
2024
2025 #undef REG_STRUCT
2026 #define REG_STRUCT pg_cntl_regs
2027 pg_cntl_dcn35_regs_init();
2028
2029 pool->base.pg_cntl = pg_cntl35_create(ctx, &pg_cntl_regs, &pg_cntl_shift, &pg_cntl_mask);
2030 if (pool->base.pg_cntl == NULL) {
2031 dm_error("DC: failed to create power gate control!\n");
2032 BREAK_TO_DEBUGGER();
2033 goto create_fail;
2034 }
2035
2036 /* TODO: IRQ */
2037 init_data.ctx = dc->ctx;
2038 pool->base.irqs = dal_irq_service_dcn36_create(&init_data);
2039 if (!pool->base.irqs)
2040 goto create_fail;
2041
2042 /* HUBBUB */
2043 pool->base.hubbub = dcn35_hubbub_create(ctx);
2044 if (pool->base.hubbub == NULL) {
2045 BREAK_TO_DEBUGGER();
2046 dm_error("DC: failed to create hubbub!\n");
2047 goto create_fail;
2048 }
2049
2050 /* DIO */
2051 pool->base.dio = dcn36_dio_create(ctx);
2052 if (pool->base.dio == NULL) {
2053 BREAK_TO_DEBUGGER();
2054 dm_error("DC: failed to create dio!\n");
2055 goto create_fail;
2056 }
2057
2058 /* HUBPs, DPPs, OPPs and TGs */
2059 for (i = 0; i < pool->base.pipe_count; i++) {
2060 pool->base.hubps[i] = dcn35_hubp_create(ctx, i);
2061 if (pool->base.hubps[i] == NULL) {
2062 BREAK_TO_DEBUGGER();
2063 dm_error(
2064 "DC: failed to create hubps!\n");
2065 goto create_fail;
2066 }
2067
2068 pool->base.dpps[i] = dcn35_dpp_create(ctx, i);
2069 if (pool->base.dpps[i] == NULL) {
2070 BREAK_TO_DEBUGGER();
2071 dm_error(
2072 "DC: failed to create dpps!\n");
2073 goto create_fail;
2074 }
2075 }
2076
2077 for (i = 0; i < pool->base.res_cap->num_opp; i++) {
2078 pool->base.opps[i] = dcn35_opp_create(ctx, i);
2079 if (pool->base.opps[i] == NULL) {
2080 BREAK_TO_DEBUGGER();
2081 dm_error(
2082 "DC: failed to create output pixel processor!\n");
2083 goto create_fail;
2084 }
2085 }
2086
2087 for (i = 0; i < pool->base.res_cap->num_timing_generator; i++) {
2088 pool->base.timing_generators[i] = dcn35_timing_generator_create(
2089 ctx, i);
2090 if (pool->base.timing_generators[i] == NULL) {
2091 BREAK_TO_DEBUGGER();
2092 dm_error("DC: failed to create tg!\n");
2093 goto create_fail;
2094 }
2095 }
2096 pool->base.timing_generator_count = i;
2097
2098 /* PSR */
2099 pool->base.psr = dmub_psr_create(ctx);
2100 if (pool->base.psr == NULL) {
2101 dm_error("DC: failed to create psr obj!\n");
2102 BREAK_TO_DEBUGGER();
2103 goto create_fail;
2104 }
2105
2106 /* Replay */
2107 pool->base.replay = dmub_replay_create(ctx);
2108 if (pool->base.replay == NULL) {
2109 dm_error("DC: failed to create replay obj!\n");
2110 BREAK_TO_DEBUGGER();
2111 goto create_fail;
2112 }
2113
2114 /* ABM */
2115 for (i = 0; i < pool->base.res_cap->num_timing_generator; i++) {
2116 pool->base.multiple_abms[i] = dmub_abm_create(ctx,
2117 &abm_regs[i],
2118 &abm_shift,
2119 &abm_mask);
2120 if (pool->base.multiple_abms[i] == NULL) {
2121 dm_error("DC: failed to create abm for pipe %d!\n", i);
2122 BREAK_TO_DEBUGGER();
2123 goto create_fail;
2124 }
2125 }
2126
2127 /* MPC and DSC */
2128 pool->base.mpc = dcn35_mpc_create(ctx, pool->base.mpcc_count, pool->base.res_cap->num_mpc_3dlut);
2129 if (pool->base.mpc == NULL) {
2130 BREAK_TO_DEBUGGER();
2131 dm_error("DC: failed to create mpc!\n");
2132 goto create_fail;
2133 }
2134
2135 for (i = 0; i < pool->base.res_cap->num_dsc; i++) {
2136 pool->base.dscs[i] = dcn35_dsc_create(ctx, i);
2137 if (pool->base.dscs[i] == NULL) {
2138 BREAK_TO_DEBUGGER();
2139 dm_error("DC: failed to create display stream compressor %d!\n", i);
2140 goto create_fail;
2141 }
2142 }
2143
2144 /* DWB and MMHUBBUB */
2145 if (!dcn35_dwbc_create(ctx, &pool->base)) {
2146 BREAK_TO_DEBUGGER();
2147 dm_error("DC: failed to create dwbc!\n");
2148 goto create_fail;
2149 }
2150
2151 if (!dcn35_mmhubbub_create(ctx, &pool->base)) {
2152 BREAK_TO_DEBUGGER();
2153 dm_error("DC: failed to create mcif_wb!\n");
2154 goto create_fail;
2155 }
2156
2157 /* AUX and I2C */
2158 for (i = 0; i < pool->base.res_cap->num_ddc; i++) {
2159 pool->base.engines[i] = dcn31_aux_engine_create(ctx, i);
2160 if (pool->base.engines[i] == NULL) {
2161 BREAK_TO_DEBUGGER();
2162 dm_error(
2163 "DC:failed to create aux engine!!\n");
2164 goto create_fail;
2165 }
2166 pool->base.hw_i2cs[i] = dcn31_i2c_hw_create(ctx, i);
2167 if (pool->base.hw_i2cs[i] == NULL) {
2168 BREAK_TO_DEBUGGER();
2169 dm_error(
2170 "DC:failed to create hw i2c!!\n");
2171 goto create_fail;
2172 }
2173 pool->base.sw_i2cs[i] = NULL;
2174 }
2175
2176 /* DCN3.5 has 6 DPIA */
2177 pool->base.usb4_dpia_count = 4;
2178 if (dc->debug.dpia_debug.bits.disable_dpia)
2179 pool->base.usb4_dpia_count = 0;
2180
2181 /* Audio, Stream Encoders including HPO and virtual, MPC 3D LUTs */
2182 if (!resource_construct(num_virtual_links, dc, &pool->base,
2183 &res_create_funcs))
2184 goto create_fail;
2185
2186 /* HW Sequencer and Plane caps */
2187 dcn35_hw_sequencer_construct(dc);
2188
2189 dc->caps.max_planes = pool->base.pipe_count;
2190
2191 for (i = 0; i < dc->caps.max_planes; ++i)
2192 dc->caps.planes[i] = plane_cap;
2193
2194 dc->caps.max_odm_combine_factor = 4;
2195
2196 dc->cap_funcs = cap_funcs;
2197
2198 dc->dcn_ip->max_num_dpp = pool->base.pipe_count;
2199
2200 dc->dml2_options.dcn_pipe_count = pool->base.pipe_count;
2201 dc->dml2_options.use_native_soc_bb_construction = true;
2202 dc->dml2_options.minimize_dispclk_using_odm = false;
2203 if (dc->config.EnableMinDispClkODM)
2204 dc->dml2_options.minimize_dispclk_using_odm = true;
2205 dc->dml2_options.enable_windowed_mpo_odm = dc->config.enable_windowed_mpo_odm;
2206
2207 resource_init_common_dml2_callbacks(dc, &dc->dml2_options);
2208 dc->dml2_options.callbacks.can_support_mclk_switch_using_fw_based_vblank_stretch = &dcn30_can_support_mclk_switch_using_fw_based_vblank_stretch;
2209
2210 dc->dml2_options.max_segments_per_hubp = 24;
2211 dc->dml2_options.det_segment_size = DCN3_2_DET_SEG_SIZE;/*todo*/
2212 dc->dml2_options.override_det_buffer_size_kbytes = true;
2213
2214 if (dc->config.sdpif_request_limit_words_per_umc == 0)
2215 dc->config.sdpif_request_limit_words_per_umc = 16;/*todo*/
2216
2217 return true;
2218
2219 create_fail:
2220
2221 dcn36_resource_destruct(pool);
2222
2223 return false;
2224 }
2225
dcn36_create_resource_pool(const struct dc_init_data * init_data,struct dc * dc)2226 struct resource_pool *dcn36_create_resource_pool(
2227 const struct dc_init_data *init_data,
2228 struct dc *dc)
2229 {
2230 struct dcn36_resource_pool *pool =
2231 kzalloc_obj(struct dcn36_resource_pool);
2232
2233 if (!pool)
2234 return NULL;
2235
2236 if (dcn36_resource_construct(init_data->num_virtual_links, dc, pool))
2237 return &pool->base;
2238
2239 BREAK_TO_DEBUGGER();
2240 kfree(pool);
2241 return NULL;
2242 }
2243