1 /* SPDX-License-Identifier: MIT */
2 /*
3 * Copyright 2023 Advanced Micro Devices, Inc.
4 *
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the "Software"),
7 * to deal in the Software without restriction, including without limitation
8 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
9 * and/or sell copies of the Software, and to permit persons to whom the
10 * Software is furnished to do so, subject to the following conditions:
11 *
12 * The above copyright notice and this permission notice shall be included in
13 * all copies or substantial portions of the Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
19 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
20 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
21 * OTHER DEALINGS IN THE SOFTWARE.
22 *
23 * Authors: AMD
24 *
25 */
26
27 #include "dcn35_optc.h"
28
29 #include "dcn30/dcn30_optc.h"
30 #include "dcn31/dcn31_optc.h"
31 #include "dcn32/dcn32_optc.h"
32 #include "reg_helper.h"
33 #include "dc.h"
34 #include "dcn_calc_math.h"
35 #include "dc_dmub_srv.h"
36
37 #define REG(reg)\
38 optc1->tg_regs->reg
39
40 #define CTX \
41 optc1->base.ctx
42
43 #undef FN
44 #define FN(reg_name, field_name) \
45 optc1->tg_shift->field_name, optc1->tg_mask->field_name
46
47 /**
48 * optc35_set_odm_combine() - Enable CRTC - call ASIC Control Object to enable Timing generator.
49 *
50 * @optc: Output Pipe Timing Combine instance reference.
51 * @opp_id: Output Plane Processor instance ID.
52 * @opp_cnt: Output Plane Processor count.
53 * @segment_width: Width of the segment.
54 * @last_segment_width: Width of the last segment.
55 *
56 * Return: void.
57 */
optc35_set_odm_combine(struct timing_generator * optc,int * opp_id,int opp_cnt,int segment_width,int last_segment_width)58 static void optc35_set_odm_combine(struct timing_generator *optc, int *opp_id, int opp_cnt,
59 int segment_width, int last_segment_width)
60 {
61 struct optc *optc1 = DCN10TG_FROM_TG(optc);
62 uint32_t memory_mask = 0;
63 int h_active = segment_width * opp_cnt;
64 /* Each memory instance is 2048x(314x2) bits to support half line of 4096 */
65 int odm_mem_count = (h_active + 2047) / 2048;
66
67 /*
68 * display <= 4k : 2 memories + 2 pipes
69 * 4k < display <= 8k : 4 memories + 2 pipes
70 * 8k < display <= 12k : 6 memories + 4 pipes
71 */
72 if (opp_cnt == 4) {
73 if (odm_mem_count <= 2)
74 memory_mask = 0x3;
75 else if (odm_mem_count <= 4)
76 memory_mask = 0xf;
77 else
78 memory_mask = 0x3f;
79 } else {
80 if (odm_mem_count <= 2)
81 memory_mask = 0x1 << (opp_id[0] * 2) | 0x1 << (opp_id[1] * 2);
82 else if (odm_mem_count <= 4)
83 memory_mask = 0x3 << (opp_id[0] * 2) | 0x3 << (opp_id[1] * 2);
84 else
85 memory_mask = 0x77;
86 }
87
88 REG_SET(OPTC_MEMORY_CONFIG, 0,
89 OPTC_MEM_SEL, memory_mask);
90
91 if (opp_cnt == 2) {
92 REG_SET_3(OPTC_DATA_SOURCE_SELECT, 0,
93 OPTC_NUM_OF_INPUT_SEGMENT, 1,
94 OPTC_SEG0_SRC_SEL, opp_id[0],
95 OPTC_SEG1_SRC_SEL, opp_id[1]);
96 } else if (opp_cnt == 4) {
97 REG_SET_5(OPTC_DATA_SOURCE_SELECT, 0,
98 OPTC_NUM_OF_INPUT_SEGMENT, 3,
99 OPTC_SEG0_SRC_SEL, opp_id[0],
100 OPTC_SEG1_SRC_SEL, opp_id[1],
101 OPTC_SEG2_SRC_SEL, opp_id[2],
102 OPTC_SEG3_SRC_SEL, opp_id[3]);
103 }
104
105 REG_UPDATE(OPTC_WIDTH_CONTROL,
106 OPTC_SEGMENT_WIDTH, segment_width);
107
108 REG_UPDATE(OTG_H_TIMING_CNTL, OTG_H_TIMING_DIV_MODE, opp_cnt - 1);
109 optc1->opp_count = opp_cnt;
110 }
111
optc35_enable_crtc(struct timing_generator * optc)112 static bool optc35_enable_crtc(struct timing_generator *optc)
113 {
114 struct optc *optc1 = DCN10TG_FROM_TG(optc);
115
116 /* opp instance for OTG, 1 to 1 mapping and odm will adjust */
117 REG_UPDATE(OPTC_DATA_SOURCE_SELECT,
118 OPTC_SEG0_SRC_SEL, optc->inst);
119
120 /* VTG enable first is for HW workaround */
121 REG_UPDATE(CONTROL,
122 VTG0_ENABLE, 1);
123
124 REG_SEQ_START();
125
126 /* Enable CRTC */
127 REG_UPDATE_2(OTG_CONTROL,
128 OTG_DISABLE_POINT_CNTL, 2,
129 OTG_MASTER_EN, 1);
130
131 REG_SEQ_SUBMIT();
132 REG_SEQ_WAIT_DONE();
133
134 return true;
135 }
136
137 /* disable_crtc */
optc35_disable_crtc(struct timing_generator * optc)138 static bool optc35_disable_crtc(struct timing_generator *optc)
139 {
140 struct optc *optc1 = DCN10TG_FROM_TG(optc);
141
142 REG_UPDATE_5(OPTC_DATA_SOURCE_SELECT,
143 OPTC_SEG0_SRC_SEL, 0xf,
144 OPTC_SEG1_SRC_SEL, 0xf,
145 OPTC_SEG2_SRC_SEL, 0xf,
146 OPTC_SEG3_SRC_SEL, 0xf,
147 OPTC_NUM_OF_INPUT_SEGMENT, 0);
148
149 REG_UPDATE(OPTC_MEMORY_CONFIG,
150 OPTC_MEM_SEL, 0);
151
152 /* disable otg request until end of the first line
153 * in the vertical blank region
154 */
155 REG_UPDATE(OTG_CONTROL,
156 OTG_MASTER_EN, 0);
157
158 REG_UPDATE(CONTROL,
159 VTG0_ENABLE, 0);
160
161 /* CRTC disabled, so disable clock. */
162 REG_WAIT(OTG_CLOCK_CONTROL,
163 OTG_BUSY, 0,
164 1, 100000);
165 REG_WAIT(OTG_CONTROL, OTG_CURRENT_MASTER_EN_STATE, 0, 1, 100000);
166
167 optc1_clear_optc_underflow(optc);
168
169 return true;
170 }
171
optc35_phantom_crtc_post_enable(struct timing_generator * optc)172 static void optc35_phantom_crtc_post_enable(struct timing_generator *optc)
173 {
174 struct optc *optc1 = DCN10TG_FROM_TG(optc);
175
176 /* Disable immediately. */
177 REG_UPDATE_2(OTG_CONTROL, OTG_DISABLE_POINT_CNTL, 0, OTG_MASTER_EN, 0);
178
179 /* CRTC disabled, so disable clock. */
180 REG_WAIT(OTG_CLOCK_CONTROL, OTG_BUSY, 0, 1, 100000);
181 }
182
183 /**
184 * optc35_get_crc - Capture CRC result per component
185 *
186 * @optc: timing_generator instance.
187 * @idx: index of crc engine to get CRC from
188 * @r_cr: primary CRC signature for red data.
189 * @g_y: primary CRC signature for green data.
190 * @b_cb: primary CRC signature for blue data.
191 *
192 * This function reads the CRC signature from the OPTC registers. Notice that
193 * we have three registers to keep the CRC result per color component (RGB).
194 *
195 * For different DCN versions:
196 * - If CRC32 registers (OTG_CRC0_DATA_R32/G32/B32) are available, read from
197 * 32-bit CRC registers. DCN 3.6+ supports both CRC-32 and CRC-16 polynomials
198 * selectable via OTG_CRC_POLY_SEL.
199 * - Otherwise, read from legacy 16-bit CRC registers (OTG_CRC0_DATA_RG/B)
200 * which only support CRC-16 polynomial.
201 *
202 * Returns:
203 * If CRC is disabled, return false; otherwise, return true, and the CRC
204 * results in the parameters.
205 */
optc35_get_crc(struct timing_generator * optc,uint8_t idx,uint32_t * r_cr,uint32_t * g_y,uint32_t * b_cb)206 static bool optc35_get_crc(struct timing_generator *optc, uint8_t idx,
207 uint32_t *r_cr, uint32_t *g_y, uint32_t *b_cb)
208 {
209 uint32_t field = 0;
210 struct optc *optc1 = DCN10TG_FROM_TG(optc);
211
212 REG_GET(OTG_CRC_CNTL, OTG_CRC_EN, &field);
213
214 /* Early return if CRC is not enabled for this CRTC */
215 if (!field)
216 return false;
217
218 if (optc1->tg_mask->CRC0_R_CR32 != 0 && optc1->tg_mask->CRC1_R_CR32 != 0 &&
219 optc1->tg_mask->CRC0_G_Y32 != 0 && optc1->tg_mask->CRC1_G_Y32 != 0 &&
220 optc1->tg_mask->CRC0_B_CB32 != 0 && optc1->tg_mask->CRC1_B_CB32 != 0) {
221 switch (idx) {
222 case 0:
223 /* OTG_CRC0_DATA_R32/G32/B32 has the CRC32 results */
224 REG_GET(OTG_CRC0_DATA_R32,
225 CRC0_R_CR32, r_cr);
226 REG_GET(OTG_CRC0_DATA_G32,
227 CRC0_G_Y32, g_y);
228 REG_GET(OTG_CRC0_DATA_B32,
229 CRC0_B_CB32, b_cb);
230 break;
231 case 1:
232 /* OTG_CRC1_DATA_R32/G32/B32 has the CRC32 results */
233 REG_GET(OTG_CRC1_DATA_R32,
234 CRC1_R_CR32, r_cr);
235 REG_GET(OTG_CRC1_DATA_G32,
236 CRC1_G_Y32, g_y);
237 REG_GET(OTG_CRC1_DATA_B32,
238 CRC1_B_CB32, b_cb);
239 break;
240 default:
241 return false;
242 }
243 } else {
244 switch (idx) {
245 case 0:
246 /* OTG_CRC0_DATA_RG has the CRC16 results for the red and green component */
247 REG_GET_2(OTG_CRC0_DATA_RG,
248 CRC0_R_CR, r_cr,
249 CRC0_G_Y, g_y);
250
251 /* OTG_CRC0_DATA_B has the CRC16 results for the blue component */
252 REG_GET(OTG_CRC0_DATA_B,
253 CRC0_B_CB, b_cb);
254 break;
255 case 1:
256 /* OTG_CRC1_DATA_RG has the CRC16 results for the red and green component */
257 REG_GET_2(OTG_CRC1_DATA_RG,
258 CRC1_R_CR, r_cr,
259 CRC1_G_Y, g_y);
260
261 /* OTG_CRC1_DATA_B has the CRC16 results for the blue component */
262 REG_GET(OTG_CRC1_DATA_B,
263 CRC1_B_CB, b_cb);
264 break;
265 default:
266 return false;
267 }
268 }
269
270 return true;
271 }
272
optc35_configure_crc(struct timing_generator * optc,const struct crc_params * params)273 bool optc35_configure_crc(struct timing_generator *optc,
274 const struct crc_params *params)
275 {
276 struct optc *optc1 = DCN10TG_FROM_TG(optc);
277
278 /* Cannot configure crc on a CRTC that is disabled */
279 if (!optc1_is_tg_enabled(optc))
280 return false;
281
282 if (!params->enable || params->reset)
283 REG_WRITE(OTG_CRC_CNTL, 0);
284
285 if (!params->enable)
286 return true;
287
288 /* Program frame boundaries */
289 switch (params->crc_eng_inst) {
290 case 0:
291 /* Window A x axis start and end. */
292 REG_UPDATE_2(OTG_CRC0_WINDOWA_X_CONTROL,
293 OTG_CRC0_WINDOWA_X_START, params->windowa_x_start,
294 OTG_CRC0_WINDOWA_X_END, params->windowa_x_end);
295
296 /* Window A y axis start and end. */
297 REG_UPDATE_2(OTG_CRC0_WINDOWA_Y_CONTROL,
298 OTG_CRC0_WINDOWA_Y_START, params->windowa_y_start,
299 OTG_CRC0_WINDOWA_Y_END, params->windowa_y_end);
300
301 /* Window B x axis start and end. */
302 REG_UPDATE_2(OTG_CRC0_WINDOWB_X_CONTROL,
303 OTG_CRC0_WINDOWB_X_START, params->windowb_x_start,
304 OTG_CRC0_WINDOWB_X_END, params->windowb_x_end);
305
306 /* Window B y axis start and end. */
307 REG_UPDATE_2(OTG_CRC0_WINDOWB_Y_CONTROL,
308 OTG_CRC0_WINDOWB_Y_START, params->windowb_y_start,
309 OTG_CRC0_WINDOWB_Y_END, params->windowb_y_end);
310
311 if (optc1->base.ctx->dc->debug.otg_crc_db && optc1->tg_mask->OTG_CRC_WINDOW_DB_EN != 0)
312 REG_UPDATE_4(OTG_CRC_CNTL,
313 OTG_CRC_CONT_EN, params->continuous_mode ? 1 : 0,
314 OTG_CRC0_SELECT, params->selection,
315 OTG_CRC_EN, 1,
316 OTG_CRC_WINDOW_DB_EN, 1);
317 else
318 REG_UPDATE_3(OTG_CRC_CNTL,
319 OTG_CRC_CONT_EN, params->continuous_mode ? 1 : 0,
320 OTG_CRC0_SELECT, params->selection,
321 OTG_CRC_EN, 1);
322 break;
323 case 1:
324 /* Window A x axis start and end. */
325 REG_UPDATE_2(OTG_CRC1_WINDOWA_X_CONTROL,
326 OTG_CRC1_WINDOWA_X_START, params->windowa_x_start,
327 OTG_CRC1_WINDOWA_X_END, params->windowa_x_end);
328
329 /* Window A y axis start and end. */
330 REG_UPDATE_2(OTG_CRC1_WINDOWA_Y_CONTROL,
331 OTG_CRC1_WINDOWA_Y_START, params->windowa_y_start,
332 OTG_CRC1_WINDOWA_Y_END, params->windowa_y_end);
333
334 /* Window B x axis start and end. */
335 REG_UPDATE_2(OTG_CRC1_WINDOWB_X_CONTROL,
336 OTG_CRC1_WINDOWB_X_START, params->windowb_x_start,
337 OTG_CRC1_WINDOWB_X_END, params->windowb_x_end);
338
339 /* Window B y axis start and end. */
340 REG_UPDATE_2(OTG_CRC1_WINDOWB_Y_CONTROL,
341 OTG_CRC1_WINDOWB_Y_START, params->windowb_y_start,
342 OTG_CRC1_WINDOWB_Y_END, params->windowb_y_end);
343
344 if (optc1->base.ctx->dc->debug.otg_crc_db && optc1->tg_mask->OTG_CRC_WINDOW_DB_EN != 0)
345 REG_UPDATE_4(OTG_CRC_CNTL,
346 OTG_CRC_CONT_EN, params->continuous_mode ? 1 : 0,
347 OTG_CRC1_SELECT, params->selection,
348 OTG_CRC_EN, 1,
349 OTG_CRC_WINDOW_DB_EN, 1);
350 else
351 REG_UPDATE_3(OTG_CRC_CNTL,
352 OTG_CRC_CONT_EN, params->continuous_mode ? 1 : 0,
353 OTG_CRC1_SELECT, params->selection,
354 OTG_CRC_EN, 1);
355 break;
356 default:
357 return false;
358 }
359 if (optc1->tg_mask->OTG_CRC_POLY_SEL != 0) {
360 REG_UPDATE(OTG_CRC_CNTL,
361 OTG_CRC_POLY_SEL, params->crc_poly_mode);
362 }
363 return true;
364 }
365
optc35_setup_manual_trigger(struct timing_generator * optc)366 static void optc35_setup_manual_trigger(struct timing_generator *optc)
367 {
368 if (!optc || !optc->ctx)
369 return;
370
371 struct optc *optc1 = DCN10TG_FROM_TG(optc);
372 struct dc *dc = optc->ctx->dc;
373
374 if (dc->caps.dmub_caps.mclk_sw && !dc->debug.disable_fams)
375 dc_dmub_srv_set_drr_manual_trigger_cmd(dc, optc->inst);
376 else {
377 /*
378 * MIN_MASK_EN is gone and MASK is now always enabled.
379 *
380 * To get it to it work with manual trigger we need to make sure
381 * we program the correct bit.
382 */
383 REG_UPDATE_4(OTG_V_TOTAL_CONTROL,
384 OTG_V_TOTAL_MIN_SEL, 1,
385 OTG_V_TOTAL_MAX_SEL, 1,
386 OTG_FORCE_LOCK_ON_EVENT, 0,
387 OTG_SET_V_TOTAL_MIN_MASK, (1 << 1)); /* TRIGA */
388
389 // Setup manual flow control for EOF via TRIG_A
390 if (optc->funcs && optc->funcs->setup_manual_trigger)
391 optc->funcs->setup_manual_trigger(optc);
392 }
393 }
394
optc35_set_drr(struct timing_generator * optc,const struct drr_params * params)395 void optc35_set_drr(
396 struct timing_generator *optc,
397 const struct drr_params *params)
398 {
399 if (!optc || !params)
400 return;
401
402 struct optc *optc1 = DCN10TG_FROM_TG(optc);
403 uint32_t max_otg_v_total = optc1->max_v_total - 1;
404
405 if (params != NULL &&
406 params->vertical_total_max > 0 &&
407 params->vertical_total_min > 0) {
408
409 if (params->vertical_total_mid != 0) {
410
411 REG_SET(OTG_V_TOTAL_MID, 0,
412 OTG_V_TOTAL_MID, params->vertical_total_mid - 1);
413
414 REG_UPDATE_2(OTG_V_TOTAL_CONTROL,
415 OTG_VTOTAL_MID_REPLACING_MAX_EN, 1,
416 OTG_VTOTAL_MID_FRAME_NUM,
417 (uint8_t)params->vertical_total_mid_frame_num);
418
419 }
420
421 if (optc->funcs && optc->funcs->set_vtotal_min_max)
422 optc->funcs->set_vtotal_min_max(optc,
423 params->vertical_total_min - 1, params->vertical_total_max - 1);
424 optc35_setup_manual_trigger(optc);
425 } else {
426 REG_UPDATE_4(OTG_V_TOTAL_CONTROL,
427 OTG_SET_V_TOTAL_MIN_MASK, 0,
428 OTG_V_TOTAL_MIN_SEL, 0,
429 OTG_V_TOTAL_MAX_SEL, 0,
430 OTG_FORCE_LOCK_ON_EVENT, 0);
431
432 if (optc->funcs && optc->funcs->set_vtotal_min_max)
433 optc->funcs->set_vtotal_min_max(optc, 0, 0);
434 }
435
436 REG_WRITE(OTG_V_COUNT_STOP_CONTROL, max_otg_v_total);
437 REG_WRITE(OTG_V_COUNT_STOP_CONTROL2, 0);
438 }
439
optc35_set_long_vtotal(struct timing_generator * optc,const struct long_vtotal_params * params)440 void optc35_set_long_vtotal(
441 struct timing_generator *optc,
442 const struct long_vtotal_params *params)
443 {
444 if (!optc || !params)
445 return;
446
447 struct optc *optc1 = DCN10TG_FROM_TG(optc);
448 uint32_t vcount_stop_timer = 0, vcount_stop = 0;
449 uint32_t max_otg_v_total = optc1->max_v_total - 1;
450
451 if (params->vertical_total_min <= max_otg_v_total && params->vertical_total_max <= max_otg_v_total)
452 return;
453
454 if (params->vertical_total_max == 0 || params->vertical_total_min == 0) {
455 REG_UPDATE_4(OTG_V_TOTAL_CONTROL,
456 OTG_SET_V_TOTAL_MIN_MASK, 0,
457 OTG_V_TOTAL_MIN_SEL, 0,
458 OTG_V_TOTAL_MAX_SEL, 0,
459 OTG_FORCE_LOCK_ON_EVENT, 0);
460
461 if (optc->funcs && optc->funcs->set_vtotal_min_max)
462 optc->funcs->set_vtotal_min_max(optc, 0, 0);
463 } else if (params->vertical_total_max == params->vertical_total_min) {
464 vcount_stop = params->vertical_blank_start;
465 vcount_stop_timer = params->vertical_total_max - max_otg_v_total;
466
467 REG_UPDATE_4(OTG_V_TOTAL_CONTROL,
468 OTG_V_TOTAL_MIN_SEL, 1,
469 OTG_V_TOTAL_MAX_SEL, 1,
470 OTG_FORCE_LOCK_ON_EVENT, 0,
471 OTG_SET_V_TOTAL_MIN_MASK, 0);
472
473 if (optc->funcs && optc->funcs->set_vtotal_min_max)
474 optc->funcs->set_vtotal_min_max(optc, max_otg_v_total, max_otg_v_total);
475
476 REG_WRITE(OTG_V_COUNT_STOP_CONTROL, vcount_stop);
477 REG_WRITE(OTG_V_COUNT_STOP_CONTROL2, vcount_stop_timer);
478 } else {
479 // Variable rate, keep DRR trigger mask
480 if (params->vertical_total_min > max_otg_v_total) {
481 // cannot be supported
482 // If MAX_OTG_V_COUNT < DRR trigger < v_total_min < v_total_max,
483 // DRR trigger will drop the vtotal counting directly to a new frame.
484 // But it should trigger between v_total_min and v_total_max.
485 ASSERT(0);
486
487 REG_UPDATE_4(OTG_V_TOTAL_CONTROL,
488 OTG_SET_V_TOTAL_MIN_MASK, 0,
489 OTG_V_TOTAL_MIN_SEL, 0,
490 OTG_V_TOTAL_MAX_SEL, 0,
491 OTG_FORCE_LOCK_ON_EVENT, 0);
492
493 if (optc->funcs && optc->funcs->set_vtotal_min_max)
494 optc->funcs->set_vtotal_min_max(optc, 0, 0);
495
496 REG_WRITE(OTG_V_COUNT_STOP_CONTROL, max_otg_v_total);
497 REG_WRITE(OTG_V_COUNT_STOP_CONTROL2, 0);
498 } else {
499 // For total_min <= MAX_OTG_V_COUNT and total_max > MAX_OTG_V_COUNT
500 vcount_stop = params->vertical_total_min;
501 vcount_stop_timer = params->vertical_total_max - max_otg_v_total;
502
503 // Example:
504 // params->vertical_total_min 1000
505 // params->vertical_total_max 2000
506 // MAX_OTG_V_COUNT_STOP = 1500
507 //
508 // If DRR event not happened,
509 // time 0,1,2,3,4,...1000,1001,........,1500,1501,1502, ...1999
510 // vcount 0,1,2,3,4....1000...................,1001,1002,1003,...1399
511 // vcount2 0,1,2,3,4,..499,
512 // else (DRR event happened, ex : at line 1004)
513 // time 0,1,2,3,4,...1000,1001.....1004, 0
514 // vcount 0,1,2,3,4....1000,.............. 0 (new frame)
515 // vcount2 0,1,2, 3, -
516 if (optc->funcs && optc->funcs->set_vtotal_min_max)
517 optc->funcs->set_vtotal_min_max(optc,
518 params->vertical_total_min - 1, max_otg_v_total);
519 optc35_setup_manual_trigger(optc);
520
521 REG_WRITE(OTG_V_COUNT_STOP_CONTROL, vcount_stop);
522 REG_WRITE(OTG_V_COUNT_STOP_CONTROL2, vcount_stop_timer);
523 }
524 }
525 }
526
optc35_wait_otg_disable(struct timing_generator * optc)527 void optc35_wait_otg_disable(struct timing_generator *optc)
528 {
529 struct optc *optc1;
530 uint32_t is_master_en;
531
532 if (!optc || !optc->ctx)
533 return;
534
535 optc1 = DCN10TG_FROM_TG(optc);
536
537 REG_GET(OTG_CONTROL, OTG_MASTER_EN, &is_master_en);
538 if (!is_master_en)
539 REG_WAIT(OTG_CLOCK_CONTROL, OTG_CURRENT_MASTER_EN_STATE, 0, 1, 100000);
540 }
541
542 static const struct timing_generator_funcs dcn35_tg_funcs = {
543 .validate_timing = optc1_validate_timing,
544 .program_timing = optc1_program_timing,
545 .setup_vertical_interrupt0 = optc1_setup_vertical_interrupt0,
546 .setup_vertical_interrupt1 = optc1_setup_vertical_interrupt1,
547 .setup_vertical_interrupt2 = optc1_setup_vertical_interrupt2,
548 .program_global_sync = optc1_program_global_sync,
549 .enable_crtc = optc35_enable_crtc,
550 .disable_crtc = optc35_disable_crtc,
551 .immediate_disable_crtc = optc31_immediate_disable_crtc,
552 .phantom_crtc_post_enable = optc35_phantom_crtc_post_enable,
553 /* used by enable_timing_synchronization. Not need for FPGA */
554 .is_counter_moving = optc1_is_counter_moving,
555 .get_position = optc1_get_position,
556 .get_frame_count = optc1_get_vblank_counter,
557 .get_scanoutpos = optc1_get_crtc_scanoutpos,
558 .get_otg_active_size = optc1_get_otg_active_size,
559 .set_early_control = optc1_set_early_control,
560 /* used by enable_timing_synchronization. Not need for FPGA */
561 .wait_for_state = optc1_wait_for_state,
562 .set_blank_color = optc3_program_blank_color,
563 .did_triggered_reset_occur = optc1_did_triggered_reset_occur,
564 .triplebuffer_lock = optc3_triplebuffer_lock,
565 .triplebuffer_unlock = optc2_triplebuffer_unlock,
566 .enable_reset_trigger = optc1_enable_reset_trigger,
567 .enable_crtc_reset = optc1_enable_crtc_reset,
568 .disable_reset_trigger = optc1_disable_reset_trigger,
569 .lock = optc3_lock,
570 .unlock = optc1_unlock,
571 .lock_doublebuffer_enable = optc3_lock_doublebuffer_enable,
572 .lock_doublebuffer_disable = optc3_lock_doublebuffer_disable,
573 .enable_optc_clock = optc1_enable_optc_clock,
574 .set_drr = optc35_set_drr,
575 .get_last_used_drr_vtotal = optc2_get_last_used_drr_vtotal,
576 .set_vtotal_min_max = optc1_set_vtotal_min_max,
577 .set_static_screen_control = optc1_set_static_screen_control,
578 .program_stereo = optc1_program_stereo,
579 .is_stereo_left_eye = optc1_is_stereo_left_eye,
580 .tg_init = optc3_tg_init,
581 .is_tg_enabled = optc1_is_tg_enabled,
582 .is_optc_underflow_occurred = optc1_is_optc_underflow_occurred,
583 .clear_optc_underflow = optc1_clear_optc_underflow,
584 .setup_global_swap_lock = NULL,
585 .get_crc = optc35_get_crc,
586 .configure_crc = optc35_configure_crc,
587 .set_dsc_config = optc3_set_dsc_config,
588 .get_dsc_status = optc2_get_dsc_status,
589 .set_dwb_source = NULL,
590 .set_odm_bypass = optc32_set_odm_bypass,
591 .set_odm_combine = optc35_set_odm_combine,
592 .get_optc_source = optc2_get_optc_source,
593 .wait_otg_disable = optc35_wait_otg_disable,
594 .set_h_timing_div_manual_mode = optc32_set_h_timing_div_manual_mode,
595 .set_out_mux = optc3_set_out_mux,
596 .set_drr_trigger_window = optc3_set_drr_trigger_window,
597 .set_vtotal_change_limit = optc3_set_vtotal_change_limit,
598 .set_gsl = optc2_set_gsl,
599 .set_gsl_source_select = optc2_set_gsl_source_select,
600 .set_vtg_params = optc1_set_vtg_params,
601 .program_manual_trigger = optc2_program_manual_trigger,
602 .setup_manual_trigger = optc2_setup_manual_trigger,
603 .get_hw_timing = optc1_get_hw_timing,
604 .init_odm = optc3_init_odm,
605 .set_long_vtotal = optc35_set_long_vtotal,
606 .is_two_pixels_per_container = optc1_is_two_pixels_per_container,
607 .read_otg_state = optc31_read_otg_state,
608 .optc_read_reg_state = optc31_read_reg_state,
609 };
610
dcn35_timing_generator_init(struct optc * optc1)611 void dcn35_timing_generator_init(struct optc *optc1)
612 {
613 optc1->base.funcs = &dcn35_tg_funcs;
614
615 optc1->max_h_total = optc1->tg_mask->OTG_H_TOTAL + 1;
616 optc1->max_v_total = optc1->tg_mask->OTG_V_TOTAL + 1;
617
618 optc1->min_h_blank = 32;
619 optc1->min_v_blank = 3;
620 optc1->min_v_blank_interlace = 5;
621 optc1->min_h_sync_width = 4;
622 optc1->min_v_sync_width = 1;
623 optc1->max_frame_count = 0xFFFFFF;
624
625 dcn35_timing_generator_set_fgcg(
626 optc1, CTX->dc->debug.enable_fine_grain_clock_gating.bits.optc);
627 }
628
dcn35_timing_generator_set_fgcg(struct optc * optc1,bool enable)629 void dcn35_timing_generator_set_fgcg(struct optc *optc1, bool enable)
630 {
631 REG_UPDATE(OPTC_CLOCK_CONTROL, OPTC_FGCG_REP_DIS, !enable);
632 }
633