1 /* SPDX-License-Identifier: MIT */
2 /*
3 * Copyright 2023 Advanced Micro Devices, Inc.
4 *
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the "Software"),
7 * to deal in the Software without restriction, including without limitation
8 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
9 * and/or sell copies of the Software, and to permit persons to whom the
10 * Software is furnished to do so, subject to the following conditions:
11 *
12 * The above copyright notice and this permission notice shall be included in
13 * all copies or substantial portions of the Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
19 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
20 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
21 * OTHER DEALINGS IN THE SOFTWARE.
22 *
23 * Authors: AMD
24 *
25 */
26
27 #include "dm_services.h"
28 #include "dc.h"
29
30 #include "dcn31/dcn31_init.h"
31 #include "dcn35/dcn35_init.h"
32
33 #include "resource.h"
34 #include "include/irq_service_interface.h"
35 #include "dcn35_resource.h"
36 #include "dml2_0/dml2_wrapper.h"
37
38 #include "dcn20/dcn20_resource.h"
39 #include "dcn30/dcn30_resource.h"
40 #include "dcn31/dcn31_resource.h"
41 #include "dcn32/dcn32_resource.h"
42
43 #include "dcn10/dcn10_ipp.h"
44 #include "dcn30/dcn30_hubbub.h"
45 #include "dcn31/dcn31_hubbub.h"
46 #include "dcn35/dcn35_hubbub.h"
47 #include "dcn32/dcn32_mpc.h"
48 #include "dcn35/dcn35_hubp.h"
49 #include "irq/dcn35/irq_service_dcn35.h"
50 #include "dcn35/dcn35_dpp.h"
51 #include "dcn35/dcn35_optc.h"
52 #include "dcn20/dcn20_hwseq.h"
53 #include "dcn30/dcn30_hwseq.h"
54 #include "dce110/dce110_hwseq.h"
55 #include "dcn35/dcn35_opp.h"
56 #include "dcn35/dcn35_dsc.h"
57 #include "dcn30/dcn30_vpg.h"
58 #include "dcn30/dcn30_afmt.h"
59 #include "dcn31/dcn31_dio_link_encoder.h"
60 #include "dcn35/dcn35_dio_stream_encoder.h"
61 #include "dcn31/dcn31_hpo_dp_stream_encoder.h"
62 #include "dcn31/dcn31_hpo_dp_link_encoder.h"
63 #include "dcn32/dcn32_hpo_dp_link_encoder.h"
64 #include "link_service.h"
65 #include "dcn31/dcn31_apg.h"
66 #include "dcn32/dcn32_dio_link_encoder.h"
67 #include "dcn31/dcn31_vpg.h"
68 #include "dcn31/dcn31_afmt.h"
69 #include "dce/dce_clock_source.h"
70 #include "dce/dce_audio.h"
71 #include "dce/dce_hwseq.h"
72 #include "clk_mgr.h"
73 #include "dio/virtual/virtual_stream_encoder.h"
74 #include "dio/dcn10/dcn10_dio.h"
75 #include "dce110/dce110_resource.h"
76 #include "dml/display_mode_vba.h"
77 #include "dcn35/dcn35_dccg.h"
78 #include "dcn35/dcn35_pg_cntl.h"
79 #include "dcn10/dcn10_resource.h"
80 #include "dcn31/dcn31_panel_cntl.h"
81 #include "dcn35/dcn35_hwseq.h"
82 #include "dcn35/dcn35_dio_link_encoder.h"
83 #include "dml/dcn31/dcn31_fpu.h" /*todo*/
84 #include "dml/dcn35/dcn35_fpu.h"
85 #include "dcn35/dcn35_dwb.h"
86 #include "dcn35/dcn35_mmhubbub.h"
87
88 #include "dcn/dcn_3_5_0_offset.h"
89 #include "dcn/dcn_3_5_0_sh_mask.h"
90 #include "nbio/nbio_7_11_0_offset.h"
91 #include "mmhub/mmhub_3_3_0_offset.h"
92 #include "mmhub/mmhub_3_3_0_sh_mask.h"
93
94 #define DSCC0_DSCC_CONFIG0__ICH_RESET_AT_END_OF_LINE__SHIFT 0x0
95 #define DSCC0_DSCC_CONFIG0__ICH_RESET_AT_END_OF_LINE_MASK 0x0000000FL
96
97 #include "reg_helper.h"
98 #include "dce/dmub_abm.h"
99 #include "dce/dmub_psr.h"
100 #include "dce/dmub_replay.h"
101 #include "dce/dce_aux.h"
102 #include "dce/dce_i2c.h"
103 #include "dml/dcn31/display_mode_vba_31.h" /*temp*/
104 #include "vm_helper.h"
105 #include "dcn20/dcn20_vmid.h"
106
107 #include "dc_state_priv.h"
108
109 #include "link_enc_cfg.h"
110 #define DC_LOGGER_INIT(logger)
111
112 enum dcn35_clk_src_array_id {
113 DCN35_CLK_SRC_PLL0,
114 DCN35_CLK_SRC_PLL1,
115 DCN35_CLK_SRC_PLL2,
116 DCN35_CLK_SRC_PLL3,
117 DCN35_CLK_SRC_PLL4,
118 DCN35_CLK_SRC_TOTAL
119 };
120
121 /* begin *********************
122 * macros to expend register list macro defined in HW object header file
123 */
124
125 /* DCN */
126 /* TODO awful hack. fixup dcn20_dwb.h */
127 #undef BASE_INNER
128 #define BASE_INNER(seg) ctx->dcn_reg_offsets[seg]
129
130 #define BASE(seg) BASE_INNER(seg)
131
132 #define SR(reg_name)\
133 REG_STRUCT.reg_name = BASE(reg ## reg_name ## _BASE_IDX) + \
134 reg ## reg_name
135
136 #define SR_ARR(reg_name, id) \
137 REG_STRUCT[id].reg_name = BASE(reg##reg_name##_BASE_IDX) + reg##reg_name
138
139 #define SR_ARR_INIT(reg_name, id, value) \
140 REG_STRUCT[id].reg_name = value
141
142 #define SRI(reg_name, block, id)\
143 REG_STRUCT.reg_name = BASE(reg ## block ## id ## _ ## reg_name ## _BASE_IDX) + \
144 reg ## block ## id ## _ ## reg_name
145
146 #define SRI_ARR(reg_name, block, id)\
147 REG_STRUCT[id].reg_name = BASE(reg ## block ## id ## _ ## reg_name ## _BASE_IDX) + \
148 reg ## block ## id ## _ ## reg_name
149
150 #define SR_ARR_I2C(reg_name, id) \
151 REG_STRUCT[id-1].reg_name = BASE(reg##reg_name##_BASE_IDX) + reg##reg_name
152
153 #define SRI_ARR_I2C(reg_name, block, id)\
154 REG_STRUCT[id-1].reg_name = BASE(reg ## block ## id ## _ ## reg_name ## _BASE_IDX) + \
155 reg ## block ## id ## _ ## reg_name
156
157 #define SRI_ARR_ALPHABET(reg_name, block, index, id)\
158 REG_STRUCT[index].reg_name = BASE(reg ## block ## id ## _ ## reg_name ## _BASE_IDX) + \
159 reg ## block ## id ## _ ## reg_name
160
161 #define SRI2(reg_name, block, id)\
162 .reg_name = BASE(reg ## reg_name ## _BASE_IDX) + \
163 reg ## reg_name
164
165 #define SRI2_ARR(reg_name, block, id)\
166 REG_STRUCT[id].reg_name = BASE(reg ## reg_name ## _BASE_IDX) + \
167 reg ## reg_name
168
169 #define SRIR(var_name, reg_name, block, id)\
170 .var_name = BASE(reg ## block ## id ## _ ## reg_name ## _BASE_IDX) + \
171 reg ## block ## id ## _ ## reg_name
172
173 #define SRII(reg_name, block, id)\
174 REG_STRUCT.reg_name[id] = BASE(reg ## block ## id ## _ ## reg_name ## _BASE_IDX) + \
175 reg ## block ## id ## _ ## reg_name
176
177 #define SRII_ARR_2(reg_name, block, id, inst)\
178 REG_STRUCT[inst].reg_name[id] = BASE(reg ## block ## id ## _ ## reg_name ## _BASE_IDX) + \
179 reg ## block ## id ## _ ## reg_name
180
181 #define SRII_MPC_RMU(reg_name, block, id)\
182 .RMU##_##reg_name[id] = BASE(reg ## block ## id ## _ ## reg_name ## _BASE_IDX) + \
183 reg ## block ## id ## _ ## reg_name
184
185 #define SRII_DWB(reg_name, temp_name, block, id)\
186 REG_STRUCT.reg_name[id] = BASE(reg ## block ## id ## _ ## temp_name ## _BASE_IDX) + \
187 reg ## block ## id ## _ ## temp_name
188
189 #define SF_DWB2(reg_name, block, id, field_name, post_fix) \
190 .field_name = reg_name ## __ ## field_name ## post_fix
191
192 #define DCCG_SRII(reg_name, block, id)\
193 REG_STRUCT.block ## _ ## reg_name[id] = BASE(reg ## block ## id ## _ ## reg_name ## _BASE_IDX) + \
194 reg ## block ## id ## _ ## reg_name
195
196 #define VUPDATE_SRII(reg_name, block, id)\
197 REG_STRUCT.reg_name[id] = BASE(reg ## reg_name ## _ ## block ## id ## _BASE_IDX) + \
198 reg ## reg_name ## _ ## block ## id
199
200 /* NBIO */
201 #define NBIO_BASE_INNER(seg) ctx->nbio_reg_offsets[seg]
202
203 #define NBIO_BASE(seg) \
204 NBIO_BASE_INNER(seg)
205
206 #define NBIO_SR(reg_name)\
207 REG_STRUCT.reg_name = NBIO_BASE(regBIF_BX1_ ## reg_name ## _BASE_IDX) + \
208 regBIF_BX1_ ## reg_name
209
210 #define NBIO_SR_ARR(reg_name, id)\
211 REG_STRUCT[id].reg_name = NBIO_BASE(regBIF_BX1_ ## reg_name ## _BASE_IDX) + \
212 regBIF_BX1_ ## reg_name
213
214 #define bios_regs_init() \
215 ( \
216 NBIO_SR(BIOS_SCRATCH_3),\
217 NBIO_SR(BIOS_SCRATCH_6)\
218 )
219
220 static struct bios_registers bios_regs;
221
222 #define clk_src_regs_init(index, pllid)\
223 CS_COMMON_REG_LIST_DCN3_0_RI(index, pllid)
224
225 static struct dce110_clk_src_regs clk_src_regs[5];
226
227 static const struct dce110_clk_src_shift cs_shift = {
228 CS_COMMON_MASK_SH_LIST_DCN3_1_4(__SHIFT)
229 };
230
231 static const struct dce110_clk_src_mask cs_mask = {
232 CS_COMMON_MASK_SH_LIST_DCN3_1_4(_MASK)
233 };
234
235 #define abm_regs_init(id)\
236 ABM_DCN32_REG_LIST_RI(id)
237
238 static struct dce_abm_registers abm_regs[4];
239
240 static const struct dce_abm_shift abm_shift = {
241 ABM_MASK_SH_LIST_DCN35(__SHIFT)
242 };
243
244 static const struct dce_abm_mask abm_mask = {
245 ABM_MASK_SH_LIST_DCN35(_MASK)
246 };
247
248 #define audio_regs_init(id)\
249 AUD_COMMON_REG_LIST_RI(id)
250
251 static struct dce_audio_registers audio_regs[7];
252
253
254 #define DCE120_AUD_COMMON_MASK_SH_LIST(mask_sh)\
255 SF(AZF0ENDPOINT0_AZALIA_F0_CODEC_ENDPOINT_INDEX, AZALIA_ENDPOINT_REG_INDEX, mask_sh),\
256 SF(AZF0ENDPOINT0_AZALIA_F0_CODEC_ENDPOINT_DATA, AZALIA_ENDPOINT_REG_DATA, mask_sh),\
257 AUD_COMMON_MASK_SH_LIST_BASE(mask_sh)
258
259 static const struct dce_audio_shift audio_shift = {
260 DCE120_AUD_COMMON_MASK_SH_LIST(__SHIFT)
261 };
262
263 static const struct dce_audio_mask audio_mask = {
264 DCE120_AUD_COMMON_MASK_SH_LIST(_MASK)
265 };
266
267 #define vpg_regs_init(id)\
268 VPG_DCN31_REG_LIST_RI(id)
269
270 static struct dcn31_vpg_registers vpg_regs[10];
271
272 static const struct dcn31_vpg_shift vpg_shift = {
273 DCN31_VPG_MASK_SH_LIST(__SHIFT)
274 };
275
276 static const struct dcn31_vpg_mask vpg_mask = {
277 DCN31_VPG_MASK_SH_LIST(_MASK)
278 };
279
280 #define afmt_regs_init(id)\
281 AFMT_DCN31_REG_LIST_RI(id)
282
283 static struct dcn31_afmt_registers afmt_regs[6];
284
285 static const struct dcn31_afmt_shift afmt_shift = {
286 DCN31_AFMT_MASK_SH_LIST(__SHIFT)
287 };
288
289 static const struct dcn31_afmt_mask afmt_mask = {
290 DCN31_AFMT_MASK_SH_LIST(_MASK)
291 };
292
293 #define apg_regs_init(id)\
294 APG_DCN31_REG_LIST_RI(id)
295
296 static struct dcn31_apg_registers apg_regs[4];
297
298 static const struct dcn31_apg_shift apg_shift = {
299 DCN31_APG_MASK_SH_LIST(__SHIFT)
300 };
301
302 static const struct dcn31_apg_mask apg_mask = {
303 DCN31_APG_MASK_SH_LIST(_MASK)
304 };
305
306 #define stream_enc_regs_init(id)\
307 SE_DCN35_REG_LIST_RI(id)
308
309 static struct dcn10_stream_enc_registers stream_enc_regs[5];
310
311 static const struct dcn10_stream_encoder_shift se_shift = {
312 SE_COMMON_MASK_SH_LIST_DCN35(__SHIFT)
313 };
314
315 static const struct dcn10_stream_encoder_mask se_mask = {
316 SE_COMMON_MASK_SH_LIST_DCN35(_MASK)
317 };
318
319 #define aux_regs_init(id)\
320 DCN2_AUX_REG_LIST_RI(id)
321
322 static struct dcn10_link_enc_aux_registers link_enc_aux_regs[5];
323
324 #define hpd_regs_init(id)\
325 HPD_REG_LIST_RI(id)
326
327 static struct dcn10_link_enc_hpd_registers link_enc_hpd_regs[5];
328
329
330 static const struct dce110_aux_registers_shift aux_shift = {
331 DCN_AUX_MASK_SH_LIST(__SHIFT)
332 };
333
334 static const struct dce110_aux_registers_mask aux_mask = {
335 DCN_AUX_MASK_SH_LIST(_MASK)
336 };
337
338 #define link_regs_init(id, phyid)\
339 ( \
340 LE_DCN35_REG_LIST_RI(id), \
341 UNIPHY_DCN2_REG_LIST_RI(id, phyid)\
342 )
343
344 static struct dcn10_link_enc_registers link_enc_regs[5];
345
346 static const struct dcn10_link_enc_shift le_shift = {
347 LINK_ENCODER_MASK_SH_LIST_DCN35(__SHIFT), \
348 //DPCS_DCN31_MASK_SH_LIST(__SHIFT)
349 };
350
351 static const struct dcn10_link_enc_mask le_mask = {
352 LINK_ENCODER_MASK_SH_LIST_DCN35(_MASK), \
353 //DPCS_DCN31_MASK_SH_LIST(_MASK)
354 };
355
356 #define hpo_dp_stream_encoder_reg_init(id)\
357 DCN3_1_HPO_DP_STREAM_ENC_REG_LIST_RI(id)
358
359 static struct dcn31_hpo_dp_stream_encoder_registers hpo_dp_stream_enc_regs[4];
360
361 static const struct dcn31_hpo_dp_stream_encoder_shift hpo_dp_se_shift = {
362 DCN3_1_HPO_DP_STREAM_ENC_MASK_SH_LIST(__SHIFT)
363 };
364
365 static const struct dcn31_hpo_dp_stream_encoder_mask hpo_dp_se_mask = {
366 DCN3_1_HPO_DP_STREAM_ENC_MASK_SH_LIST(_MASK)
367 };
368
369 #define hpo_dp_link_encoder_reg_init(id)\
370 DCN3_1_HPO_DP_LINK_ENC_REG_LIST_RI(id)
371 /*DCN3_1_RDPCSTX_REG_LIST(0),*/
372 /*DCN3_1_RDPCSTX_REG_LIST(1),*/
373 /*DCN3_1_RDPCSTX_REG_LIST(2),*/
374 /*DCN3_1_RDPCSTX_REG_LIST(3),*/
375
376 static struct dcn31_hpo_dp_link_encoder_registers hpo_dp_link_enc_regs[2];
377
378 static const struct dcn31_hpo_dp_link_encoder_shift hpo_dp_le_shift = {
379 DCN3_1_HPO_DP_LINK_ENC_COMMON_MASK_SH_LIST(__SHIFT)
380 };
381
382 static const struct dcn31_hpo_dp_link_encoder_mask hpo_dp_le_mask = {
383 DCN3_1_HPO_DP_LINK_ENC_COMMON_MASK_SH_LIST(_MASK)
384 };
385
386 #define dpp_regs_init(id)\
387 DPP_REG_LIST_DCN35_RI(id)
388
389 static struct dcn3_dpp_registers dpp_regs[4];
390
391 static const struct dcn35_dpp_shift tf_shift = {
392 DPP_REG_LIST_SH_MASK_DCN35(__SHIFT)
393 };
394
395 static const struct dcn35_dpp_mask tf_mask = {
396 DPP_REG_LIST_SH_MASK_DCN35(_MASK)
397 };
398
399 #define opp_regs_init(id)\
400 OPP_REG_LIST_DCN35_RI(id)
401
402 static struct dcn35_opp_registers opp_regs[4];
403
404 static const struct dcn35_opp_shift opp_shift = {
405 OPP_MASK_SH_LIST_DCN35(__SHIFT)
406 };
407
408 static const struct dcn35_opp_mask opp_mask = {
409 OPP_MASK_SH_LIST_DCN35(_MASK)
410 };
411
412 #define aux_engine_regs_init(id)\
413 ( \
414 AUX_COMMON_REG_LIST0_RI(id), \
415 SR_ARR_INIT(AUXN_IMPCAL, id, 0), \
416 SR_ARR_INIT(AUXP_IMPCAL, id, 0), \
417 SR_ARR_INIT(AUX_RESET_MASK, id, DP_AUX0_AUX_CONTROL__AUX_RESET_MASK) \
418 )
419
420 static struct dce110_aux_registers aux_engine_regs[5];
421
422 #define dwbc_regs_dcn3_init(id)\
423 DWBC_COMMON_REG_LIST_DCN30_RI(id)
424
425 static struct dcn30_dwbc_registers dwbc35_regs[1];
426
427 static const struct dcn35_dwbc_shift dwbc35_shift = {
428 DWBC_COMMON_MASK_SH_LIST_DCN35(__SHIFT)
429 };
430
431 static const struct dcn35_dwbc_mask dwbc35_mask = {
432 DWBC_COMMON_MASK_SH_LIST_DCN35(_MASK)
433 };
434
435 #define mcif_wb_regs_dcn3_init(id)\
436 MCIF_WB_COMMON_REG_LIST_DCN3_5_RI(id)
437
438 static struct dcn35_mmhubbub_registers mcif_wb35_regs[1];
439
440 static const struct dcn35_mmhubbub_shift mcif_wb35_shift = {
441 MCIF_WB_COMMON_MASK_SH_LIST_DCN3_5(__SHIFT)
442 };
443
444 static const struct dcn35_mmhubbub_mask mcif_wb35_mask = {
445 MCIF_WB_COMMON_MASK_SH_LIST_DCN3_5(_MASK)
446 };
447
448 #define dsc_regsDCN35_init(id)\
449 DSC_REG_LIST_DCN20_RI(id)
450
451 static struct dcn20_dsc_registers dsc_regs[4];
452
453 static const struct dcn35_dsc_shift dsc_shift = {
454 DSC_REG_LIST_SH_MASK_DCN35(__SHIFT)
455 };
456
457 static const struct dcn35_dsc_mask dsc_mask = {
458 DSC_REG_LIST_SH_MASK_DCN35(_MASK)
459 };
460
461 static struct dcn30_mpc_registers mpc_regs;
462
463 #define dcn_mpc_regs_init() \
464 MPC_REG_LIST_DCN3_2_RI(0),\
465 MPC_REG_LIST_DCN3_2_RI(1),\
466 MPC_REG_LIST_DCN3_2_RI(2),\
467 MPC_REG_LIST_DCN3_2_RI(3),\
468 MPC_OUT_MUX_REG_LIST_DCN3_0_RI(0),\
469 MPC_OUT_MUX_REG_LIST_DCN3_0_RI(1),\
470 MPC_OUT_MUX_REG_LIST_DCN3_0_RI(2),\
471 MPC_OUT_MUX_REG_LIST_DCN3_0_RI(3),\
472 MPC_DWB_MUX_REG_LIST_DCN3_0_RI(0)
473
474 static const struct dcn30_mpc_shift mpc_shift = {
475 MPC_COMMON_MASK_SH_LIST_DCN32(__SHIFT)
476 };
477
478 static const struct dcn30_mpc_mask mpc_mask = {
479 MPC_COMMON_MASK_SH_LIST_DCN32(_MASK)
480 };
481
482 #define optc_regs_init(id)\
483 OPTC_COMMON_REG_LIST_DCN3_5_RI(id)
484
485 static struct dcn_optc_registers optc_regs[4];
486
487 static const struct dcn_optc_shift optc_shift = {
488 OPTC_COMMON_MASK_SH_LIST_DCN3_5(__SHIFT)
489 };
490
491 static const struct dcn_optc_mask optc_mask = {
492 OPTC_COMMON_MASK_SH_LIST_DCN3_5(_MASK)
493 };
494
495 #define hubp_regs_init(id)\
496 HUBP_REG_LIST_DCN30_RI(id)
497
498 static struct dcn_hubp2_registers hubp_regs[4];
499
500
501 static const struct dcn35_hubp2_shift hubp_shift = {
502 HUBP_MASK_SH_LIST_DCN35(__SHIFT)
503 };
504
505 static const struct dcn35_hubp2_mask hubp_mask = {
506 HUBP_MASK_SH_LIST_DCN35(_MASK)
507 };
508
509 static struct dcn_hubbub_registers hubbub_reg;
510
511 #define hubbub_reg_init()\
512 HUBBUB_REG_LIST_DCN35(0)
513
514 static const struct dcn_hubbub_shift hubbub_shift = {
515 HUBBUB_MASK_SH_LIST_DCN35(__SHIFT)
516 };
517
518 static const struct dcn_hubbub_mask hubbub_mask = {
519 HUBBUB_MASK_SH_LIST_DCN35(_MASK)
520 };
521
522 static struct dccg_registers dccg_regs;
523
524 #define dccg_regs_init()\
525 DCCG_REG_LIST_DCN35()
526
527 static const struct dccg_shift dccg_shift = {
528 DCCG_MASK_SH_LIST_DCN35(__SHIFT)
529 };
530
531 static const struct dccg_mask dccg_mask = {
532 DCCG_MASK_SH_LIST_DCN35(_MASK)
533 };
534
535 static struct pg_cntl_registers pg_cntl_regs;
536
537 #define pg_cntl_dcn35_regs_init() \
538 PG_CNTL_REG_LIST_DCN35()
539
540 static const struct pg_cntl_shift pg_cntl_shift = {
541 PG_CNTL_MASK_SH_LIST_DCN35(__SHIFT)
542 };
543
544 static const struct pg_cntl_mask pg_cntl_mask = {
545 PG_CNTL_MASK_SH_LIST_DCN35(_MASK)
546 };
547
548 #define SRII2(reg_name_pre, reg_name_post, id)\
549 .reg_name_pre ## _ ## reg_name_post[id] = BASE(reg ## reg_name_pre \
550 ## id ## _ ## reg_name_post ## _BASE_IDX) + \
551 reg ## reg_name_pre ## id ## _ ## reg_name_post
552
553 static struct dce_hwseq_registers hwseq_reg;
554
555 #define hwseq_reg_init()\
556 HWSEQ_DCN35_REG_LIST()
557
558 #define HWSEQ_DCN35_MASK_SH_LIST(mask_sh)\
559 HWSEQ_DCN_MASK_SH_LIST(mask_sh), \
560 HWS_SF(, DCHUBBUB_GLOBAL_TIMER_CNTL, DCHUBBUB_GLOBAL_TIMER_REFDIV, mask_sh), \
561 HWS_SF(, DCHUBBUB_ARB_HOSTVM_CNTL, DISABLE_HOSTVM_FORCE_ALLOW_PSTATE, mask_sh), \
562 HWS_SF(, DOMAIN0_PG_CONFIG, DOMAIN_POWER_FORCEON, mask_sh), \
563 HWS_SF(, DOMAIN0_PG_CONFIG, DOMAIN_POWER_GATE, mask_sh), \
564 HWS_SF(, DOMAIN1_PG_CONFIG, DOMAIN_POWER_FORCEON, mask_sh), \
565 HWS_SF(, DOMAIN1_PG_CONFIG, DOMAIN_POWER_GATE, mask_sh), \
566 HWS_SF(, DOMAIN2_PG_CONFIG, DOMAIN_POWER_FORCEON, mask_sh), \
567 HWS_SF(, DOMAIN2_PG_CONFIG, DOMAIN_POWER_GATE, mask_sh), \
568 HWS_SF(, DOMAIN3_PG_CONFIG, DOMAIN_POWER_FORCEON, mask_sh), \
569 HWS_SF(, DOMAIN3_PG_CONFIG, DOMAIN_POWER_GATE, mask_sh), \
570 HWS_SF(, DOMAIN16_PG_CONFIG, DOMAIN_POWER_FORCEON, mask_sh), \
571 HWS_SF(, DOMAIN16_PG_CONFIG, DOMAIN_POWER_GATE, mask_sh), \
572 HWS_SF(, DOMAIN17_PG_CONFIG, DOMAIN_POWER_FORCEON, mask_sh), \
573 HWS_SF(, DOMAIN17_PG_CONFIG, DOMAIN_POWER_GATE, mask_sh), \
574 HWS_SF(, DOMAIN18_PG_CONFIG, DOMAIN_POWER_FORCEON, mask_sh), \
575 HWS_SF(, DOMAIN18_PG_CONFIG, DOMAIN_POWER_GATE, mask_sh), \
576 HWS_SF(, DOMAIN19_PG_CONFIG, DOMAIN_POWER_FORCEON, mask_sh), \
577 HWS_SF(, DOMAIN19_PG_CONFIG, DOMAIN_POWER_GATE, mask_sh), \
578 HWS_SF(, DOMAIN22_PG_CONFIG, DOMAIN_POWER_FORCEON, mask_sh), \
579 HWS_SF(, DOMAIN22_PG_CONFIG, DOMAIN_POWER_GATE, mask_sh), \
580 HWS_SF(, DOMAIN23_PG_CONFIG, DOMAIN_POWER_FORCEON, mask_sh), \
581 HWS_SF(, DOMAIN23_PG_CONFIG, DOMAIN_POWER_GATE, mask_sh), \
582 HWS_SF(, DOMAIN24_PG_CONFIG, DOMAIN_POWER_FORCEON, mask_sh), \
583 HWS_SF(, DOMAIN24_PG_CONFIG, DOMAIN_POWER_GATE, mask_sh), \
584 HWS_SF(, DOMAIN25_PG_CONFIG, DOMAIN_POWER_FORCEON, mask_sh), \
585 HWS_SF(, DOMAIN25_PG_CONFIG, DOMAIN_POWER_GATE, mask_sh), \
586 HWS_SF(, DOMAIN0_PG_STATUS, DOMAIN_PGFSM_PWR_STATUS, mask_sh), \
587 HWS_SF(, DOMAIN1_PG_STATUS, DOMAIN_PGFSM_PWR_STATUS, mask_sh), \
588 HWS_SF(, DOMAIN2_PG_STATUS, DOMAIN_PGFSM_PWR_STATUS, mask_sh), \
589 HWS_SF(, DOMAIN3_PG_STATUS, DOMAIN_PGFSM_PWR_STATUS, mask_sh), \
590 HWS_SF(, DOMAIN16_PG_STATUS, DOMAIN_PGFSM_PWR_STATUS, mask_sh), \
591 HWS_SF(, DOMAIN17_PG_STATUS, DOMAIN_PGFSM_PWR_STATUS, mask_sh), \
592 HWS_SF(, DOMAIN18_PG_STATUS, DOMAIN_PGFSM_PWR_STATUS, mask_sh), \
593 HWS_SF(, DOMAIN19_PG_STATUS, DOMAIN_PGFSM_PWR_STATUS, mask_sh), \
594 HWS_SF(, DOMAIN22_PG_STATUS, DOMAIN_PGFSM_PWR_STATUS, mask_sh), \
595 HWS_SF(, DOMAIN23_PG_STATUS, DOMAIN_PGFSM_PWR_STATUS, mask_sh), \
596 HWS_SF(, DOMAIN24_PG_STATUS, DOMAIN_PGFSM_PWR_STATUS, mask_sh), \
597 HWS_SF(, DOMAIN25_PG_STATUS, DOMAIN_PGFSM_PWR_STATUS, mask_sh), \
598 HWS_SF(, DC_IP_REQUEST_CNTL, IP_REQUEST_EN, mask_sh), \
599 HWS_SF(, AZALIA_AUDIO_DTO, AZALIA_AUDIO_DTO_MODULE, mask_sh), \
600 HWS_SF(, HPO_TOP_CLOCK_CONTROL, HPO_HDMISTREAMCLK_G_GATE_DIS, mask_sh), \
601 HWS_SF(, ODM_MEM_PWR_CTRL3, ODM_MEM_UNASSIGNED_PWR_MODE, mask_sh), \
602 HWS_SF(, ODM_MEM_PWR_CTRL3, ODM_MEM_VBLANK_PWR_MODE, mask_sh), \
603 HWS_SF(, DIO_MEM_PWR_CTRL, I2C_LIGHT_SLEEP_FORCE, mask_sh), \
604 HWS_SF(, HPO_TOP_HW_CONTROL, HPO_IO_EN, mask_sh),\
605 HWS_SF(, DMU_CLK_CNTL, DISPCLK_R_DMU_GATE_DIS, mask_sh),\
606 HWS_SF(, DMU_CLK_CNTL, DISPCLK_G_RBBMIF_GATE_DIS, mask_sh),\
607 HWS_SF(, DMU_CLK_CNTL, RBBMIF_FGCG_REP_DIS, mask_sh),\
608 HWS_SF(, DMU_CLK_CNTL, DPREFCLK_ALLOW_DS_CLKSTOP, mask_sh),\
609 HWS_SF(, DMU_CLK_CNTL, DISPCLK_ALLOW_DS_CLKSTOP, mask_sh),\
610 HWS_SF(, DMU_CLK_CNTL, DPPCLK_ALLOW_DS_CLKSTOP, mask_sh),\
611 HWS_SF(, DMU_CLK_CNTL, DTBCLK_ALLOW_DS_CLKSTOP, mask_sh),\
612 HWS_SF(, DMU_CLK_CNTL, DCFCLK_ALLOW_DS_CLKSTOP, mask_sh),\
613 HWS_SF(, DMU_CLK_CNTL, DPIACLK_ALLOW_DS_CLKSTOP, mask_sh),\
614 HWS_SF(, DMU_CLK_CNTL, LONO_FGCG_REP_DIS, mask_sh),\
615 HWS_SF(, DMU_CLK_CNTL, LONO_DISPCLK_GATE_DISABLE, mask_sh),\
616 HWS_SF(, DMU_CLK_CNTL, LONO_SOCCLK_GATE_DISABLE, mask_sh),\
617 HWS_SF(, DMU_CLK_CNTL, LONO_DMCUBCLK_GATE_DISABLE, mask_sh),\
618 HWS_SF(, DCCG_GATE_DISABLE_CNTL2, SYMCLKA_FE_GATE_DISABLE, mask_sh), \
619 HWS_SF(, DCCG_GATE_DISABLE_CNTL2, SYMCLKB_FE_GATE_DISABLE, mask_sh), \
620 HWS_SF(, DCCG_GATE_DISABLE_CNTL2, SYMCLKC_FE_GATE_DISABLE, mask_sh), \
621 HWS_SF(, DCCG_GATE_DISABLE_CNTL2, SYMCLKD_FE_GATE_DISABLE, mask_sh), \
622 HWS_SF(, DCCG_GATE_DISABLE_CNTL2, SYMCLKE_FE_GATE_DISABLE, mask_sh), \
623 HWS_SF(, DCCG_GATE_DISABLE_CNTL2, HDMICHARCLK0_GATE_DISABLE, mask_sh), \
624 HWS_SF(, DCCG_GATE_DISABLE_CNTL2, SYMCLKA_GATE_DISABLE, mask_sh), \
625 HWS_SF(, DCCG_GATE_DISABLE_CNTL2, SYMCLKB_GATE_DISABLE, mask_sh), \
626 HWS_SF(, DCCG_GATE_DISABLE_CNTL2, SYMCLKC_GATE_DISABLE, mask_sh), \
627 HWS_SF(, DCCG_GATE_DISABLE_CNTL2, SYMCLKD_GATE_DISABLE, mask_sh), \
628 HWS_SF(, DCCG_GATE_DISABLE_CNTL2, SYMCLKE_GATE_DISABLE, mask_sh), \
629 HWS_SF(, DCCG_GATE_DISABLE_CNTL2, PHYASYMCLK_ROOT_GATE_DISABLE, mask_sh), \
630 HWS_SF(, DCCG_GATE_DISABLE_CNTL2, PHYBSYMCLK_ROOT_GATE_DISABLE, mask_sh), \
631 HWS_SF(, DCCG_GATE_DISABLE_CNTL2, PHYCSYMCLK_ROOT_GATE_DISABLE, mask_sh), \
632 HWS_SF(, DCCG_GATE_DISABLE_CNTL2, PHYDSYMCLK_ROOT_GATE_DISABLE, mask_sh), \
633 HWS_SF(, DCCG_GATE_DISABLE_CNTL2, PHYESYMCLK_ROOT_GATE_DISABLE, mask_sh),\
634 HWS_SF(, DCCG_GATE_DISABLE_CNTL5, DTBCLK_P0_GATE_DISABLE, mask_sh),\
635 HWS_SF(, DCCG_GATE_DISABLE_CNTL5, DTBCLK_P1_GATE_DISABLE, mask_sh),\
636 HWS_SF(, DCCG_GATE_DISABLE_CNTL5, DTBCLK_P2_GATE_DISABLE, mask_sh),\
637 HWS_SF(, DCCG_GATE_DISABLE_CNTL5, DTBCLK_P3_GATE_DISABLE, mask_sh),\
638 HWS_SF(, DCCG_GATE_DISABLE_CNTL5, DPSTREAMCLK0_GATE_DISABLE, mask_sh),\
639 HWS_SF(, DCCG_GATE_DISABLE_CNTL5, DPSTREAMCLK1_GATE_DISABLE, mask_sh),\
640 HWS_SF(, DCCG_GATE_DISABLE_CNTL5, DPSTREAMCLK2_GATE_DISABLE, mask_sh),\
641 HWS_SF(, DCCG_GATE_DISABLE_CNTL5, DPSTREAMCLK3_GATE_DISABLE, mask_sh),\
642 HWS_SF(, DCCG_GATE_DISABLE_CNTL4, DPIASYMCLK0_GATE_DISABLE, mask_sh),\
643 HWS_SF(, DCCG_GATE_DISABLE_CNTL4, DPIASYMCLK1_GATE_DISABLE, mask_sh),\
644 HWS_SF(, DCCG_GATE_DISABLE_CNTL4, DPIASYMCLK2_GATE_DISABLE, mask_sh),\
645 HWS_SF(, DCCG_GATE_DISABLE_CNTL4, DPIASYMCLK3_GATE_DISABLE, mask_sh)
646
647 static const struct dce_hwseq_shift hwseq_shift = {
648 HWSEQ_DCN35_MASK_SH_LIST(__SHIFT)
649 };
650
651 static const struct dce_hwseq_mask hwseq_mask = {
652 HWSEQ_DCN35_MASK_SH_LIST(_MASK)
653 };
654
655 #define vmid_regs_init(id)\
656 DCN20_VMID_REG_LIST_RI(id)
657
658 static struct dcn_vmid_registers vmid_regs[16];
659
660 static const struct dcn20_vmid_shift vmid_shifts = {
661 DCN20_VMID_MASK_SH_LIST(__SHIFT)
662 };
663
664 static const struct dcn20_vmid_mask vmid_masks = {
665 DCN20_VMID_MASK_SH_LIST(_MASK)
666 };
667
668 static struct dcn_dio_registers dio_regs;
669
670 #define DIO_MASK_SH_LIST(mask_sh)\
671 HWS_SF(, DIO_MEM_PWR_CTRL, I2C_LIGHT_SLEEP_FORCE, mask_sh)
672
673 static const struct dcn_dio_shift dio_shift = {
674 DIO_MASK_SH_LIST(__SHIFT)
675 };
676
677 static const struct dcn_dio_mask dio_mask = {
678 DIO_MASK_SH_LIST(_MASK)
679 };
680
681 static const struct resource_caps res_cap_dcn35 = {
682 .num_timing_generator = 4,
683 .num_opp = 4,
684 .num_video_plane = 4,
685 .num_audio = 5,
686 .num_stream_encoder = 5,
687 .num_dig_link_enc = 5,
688 .num_hpo_dp_stream_encoder = 4,
689 .num_hpo_dp_link_encoder = 2,
690 .num_pll = 4,/*1 c10 edp, 3xc20 combo PHY*/
691 .num_dwb = 1,
692 .num_ddc = 5,
693 .num_vmid = 16,
694 .num_mpc_3dlut = 2,
695 .num_dsc = 4,
696 };
697
698 static const struct dc_plane_cap plane_cap = {
699 .type = DC_PLANE_TYPE_DCN_UNIVERSAL,
700 .per_pixel_alpha = true,
701
702 .pixel_format_support = {
703 .argb8888 = true,
704 .nv12 = true,
705 .fp16 = true,
706 .p010 = true,
707 .ayuv = false,
708 },
709
710 .max_upscale_factor = {
711 .argb8888 = 16000,
712 .nv12 = 16000,
713 .fp16 = 16000
714 },
715
716 // 6:1 downscaling ratio: 1000/6 = 166.666
717 .max_downscale_factor = {
718 .argb8888 = 250,
719 .nv12 = 167,
720 .fp16 = 167
721 },
722 64,
723 64
724 };
725
726 static const struct dc_debug_options debug_defaults_drv = {
727 .disable_dmcu = true,
728 .force_abm_enable = false,
729 .clock_trace = true,
730 .disable_pplib_clock_request = false,
731 .pipe_split_policy = MPC_SPLIT_AVOID,
732 .force_single_disp_pipe_split = false,
733 .disable_dcc = DCC_ENABLE,
734 .disable_dpp_power_gate = true,
735 .disable_hubp_power_gate = true,
736 .disable_optc_power_gate = true, /*should the same as above two*/
737 .disable_hpo_power_gate = true, /*dmubfw force domain25 on*/
738 .disable_clock_gate = false,
739 .disable_dsc_power_gate = true,
740 .vsr_support = true,
741 .performance_trace = false,
742 .max_downscale_src_width = 4096,/*upto true 4k*/
743 .disable_pplib_wm_range = false,
744 .scl_reset_length10 = true,
745 .sanity_checks = false,
746 .underflow_assert_delay_us = 0xFFFFFFFF,
747 .dwb_fi_phase = -1, // -1 = disable,
748 .dmub_command_table = true,
749 .pstate_enabled = true,
750 .use_max_lb = true,
751 .enable_mem_low_power = {
752 .bits = {
753 .vga = false,
754 .i2c = true,
755 .dmcu = false, // This is previously known to cause hang on S3 cycles if enabled
756 .dscl = true,
757 .cm = true,
758 .mpc = true,
759 .optc = true,
760 .vpg = true,
761 .afmt = true,
762 }
763 },
764 .root_clock_optimization = {
765 .bits = {
766 .dpp = true,
767 .dsc = true,/*dscclk and dsc pg*/
768 .hdmistream = true,
769 .hdmichar = true,
770 .dpstream = true,
771 .symclk32_se = true,
772 .symclk32_le = true,
773 .symclk_fe = true,
774 .physymclk = false,
775 .dpiasymclk = true,
776 }
777 },
778 .seamless_boot_odm_combine = DML_FAIL_SOURCE_PIXEL_FORMAT,
779 .enable_z9_disable_interface = true, /* Allow support for the PMFW interface for disable Z9*/
780 .minimum_z8_residency_time = 1, /* Always allow when other conditions are met */
781 .using_dml2 = true,
782 .support_eDP1_5 = true,
783 .enable_hpo_pg_support = false,
784 .enable_single_display_2to1_odm_policy = true,
785 .disable_idle_power_optimizations = false,
786 .dmcub_emulation = false,
787 .disable_boot_optimizations = false,
788 .disable_unbounded_requesting = false,
789 .disable_mem_low_power = false,
790 //must match enable_single_display_2to1_odm_policy to support dynamic ODM transitions
791 .enable_double_buffered_dsc_pg_support = true,
792 .enable_dp_dig_pixel_rate_div_policy = 1,
793 .disable_z10 = false,
794 .ignore_pg = true,
795 .psp_disabled_wa = true,
796 .ips2_eval_delay_us = 2000,
797 .ips2_entry_delay_us = 800,
798 .disable_dmub_reallow_idle = false,
799 .static_screen_wait_frames = 2,
800 .disable_timeout = true,
801 .min_disp_clk_khz = 50000,
802 };
803
804 static const struct dc_check_config config_defaults = {
805 .enable_legacy_fast_update = false,
806 };
807
808 static const struct dc_panel_config panel_config_defaults = {
809 .psr = {
810 .disable_psr = false,
811 .disallow_psrsu = false,
812 .disallow_replay = false,
813 },
814 .ilr = {
815 .optimize_edp_link_rate = true,
816 },
817 };
818
dcn35_dpp_destroy(struct dpp ** dpp)819 static void dcn35_dpp_destroy(struct dpp **dpp)
820 {
821 kfree(TO_DCN20_DPP(*dpp));
822 *dpp = NULL;
823 }
824
dcn35_dpp_create(struct dc_context * ctx,uint32_t inst)825 static struct dpp *dcn35_dpp_create(struct dc_context *ctx, uint32_t inst)
826 {
827 struct dcn3_dpp *dpp = kzalloc_obj(struct dcn3_dpp);
828 bool success = (dpp != NULL);
829
830 if (!success)
831 return NULL;
832
833 #undef REG_STRUCT
834 #define REG_STRUCT dpp_regs
835 dpp_regs_init(0),
836 dpp_regs_init(1),
837 dpp_regs_init(2),
838 dpp_regs_init(3);
839
840 success = dpp35_construct(dpp, ctx, inst, &dpp_regs[inst], &tf_shift,
841 &tf_mask);
842 if (success) {
843 dpp35_set_fgcg(
844 dpp,
845 ctx->dc->debug.enable_fine_grain_clock_gating.bits.dpp);
846 return &dpp->base;
847 }
848
849 BREAK_TO_DEBUGGER();
850 kfree(dpp);
851 return NULL;
852 }
853
dcn35_opp_create(struct dc_context * ctx,uint32_t inst)854 static struct output_pixel_processor *dcn35_opp_create(
855 struct dc_context *ctx, uint32_t inst)
856 {
857 struct dcn20_opp *opp =
858 kzalloc_obj(struct dcn20_opp);
859
860 if (!opp) {
861 BREAK_TO_DEBUGGER();
862 return NULL;
863 }
864
865 #undef REG_STRUCT
866 #define REG_STRUCT opp_regs
867 opp_regs_init(0),
868 opp_regs_init(1),
869 opp_regs_init(2),
870 opp_regs_init(3);
871
872 dcn35_opp_construct(opp, ctx, inst,
873 &opp_regs[inst], &opp_shift, &opp_mask);
874
875 dcn35_opp_set_fgcg(opp, ctx->dc->debug.enable_fine_grain_clock_gating.bits.opp);
876
877 return &opp->base;
878 }
879
dcn31_aux_engine_create(struct dc_context * ctx,uint32_t inst)880 static struct dce_aux *dcn31_aux_engine_create(
881 struct dc_context *ctx,
882 uint32_t inst)
883 {
884 struct aux_engine_dce110 *aux_engine =
885 kzalloc_obj(struct aux_engine_dce110);
886
887 if (!aux_engine)
888 return NULL;
889
890 #undef REG_STRUCT
891 #define REG_STRUCT aux_engine_regs
892 aux_engine_regs_init(0),
893 aux_engine_regs_init(1),
894 aux_engine_regs_init(2),
895 aux_engine_regs_init(3),
896 aux_engine_regs_init(4);
897
898 dce110_aux_engine_construct(aux_engine, ctx, inst,
899 SW_AUX_TIMEOUT_PERIOD_MULTIPLIER * AUX_TIMEOUT_PERIOD,
900 &aux_engine_regs[inst],
901 &aux_mask,
902 &aux_shift,
903 ctx->dc->caps.extended_aux_timeout_support);
904
905 return &aux_engine->base;
906 }
907
908 #define i2c_inst_regs_init(id)\
909 I2C_HW_ENGINE_COMMON_REG_LIST_DCN30_RI(id)
910
911 static struct dce_i2c_registers i2c_hw_regs[5];
912
913 static const struct dce_i2c_shift i2c_shifts = {
914 I2C_COMMON_MASK_SH_LIST_DCN35(__SHIFT)
915 };
916
917 static const struct dce_i2c_mask i2c_masks = {
918 I2C_COMMON_MASK_SH_LIST_DCN35(_MASK)
919 };
920
921 /* ========================================================== */
922
923 /*
924 * DPIA index | Preferred Encoder | Host Router
925 * 0 | C | 0
926 * 1 | First Available | 0
927 * 2 | D | 1
928 * 3 | First Available | 1
929 */
930 /* ========================================================== */
931 static const enum engine_id dpia_to_preferred_enc_id_table[] = {
932 ENGINE_ID_DIGC,
933 ENGINE_ID_DIGC,
934 ENGINE_ID_DIGD,
935 ENGINE_ID_DIGD
936 };
937
dcn35_get_preferred_eng_id_dpia(unsigned int dpia_index)938 static enum engine_id dcn35_get_preferred_eng_id_dpia(unsigned int dpia_index)
939 {
940 return dpia_to_preferred_enc_id_table[dpia_index];
941 }
942
dcn31_i2c_hw_create(struct dc_context * ctx,uint32_t inst)943 static struct dce_i2c_hw *dcn31_i2c_hw_create(
944 struct dc_context *ctx,
945 uint32_t inst)
946 {
947 struct dce_i2c_hw *dce_i2c_hw =
948 kzalloc_obj(struct dce_i2c_hw);
949
950 if (!dce_i2c_hw)
951 return NULL;
952
953 #undef REG_STRUCT
954 #define REG_STRUCT i2c_hw_regs
955 i2c_inst_regs_init(1),
956 i2c_inst_regs_init(2),
957 i2c_inst_regs_init(3),
958 i2c_inst_regs_init(4),
959 i2c_inst_regs_init(5);
960
961 dcn2_i2c_hw_construct(dce_i2c_hw, ctx, inst,
962 &i2c_hw_regs[inst], &i2c_shifts, &i2c_masks);
963
964 return dce_i2c_hw;
965 }
dcn35_mpc_create(struct dc_context * ctx,int num_mpcc,int num_rmu)966 static struct mpc *dcn35_mpc_create(
967 struct dc_context *ctx,
968 int num_mpcc,
969 int num_rmu)
970 {
971 struct dcn30_mpc *mpc30 = kzalloc_obj(struct dcn30_mpc);
972
973 if (!mpc30)
974 return NULL;
975
976 #undef REG_STRUCT
977 #define REG_STRUCT mpc_regs
978 dcn_mpc_regs_init();
979
980 dcn32_mpc_construct(mpc30, ctx,
981 &mpc_regs,
982 &mpc_shift,
983 &mpc_mask,
984 num_mpcc,
985 num_rmu);
986
987 return &mpc30->base;
988 }
989
dcn35_dio_create(struct dc_context * ctx)990 static struct dio *dcn35_dio_create(struct dc_context *ctx)
991 {
992 struct dcn10_dio *dio10 = kzalloc_obj(struct dcn10_dio);
993
994 if (!dio10)
995 return NULL;
996
997 #undef REG_STRUCT
998 #define REG_STRUCT dio_regs
999 DIO_REG_LIST_DCN10();
1000
1001 dcn10_dio_construct(dio10, ctx, &dio_regs, &dio_shift, &dio_mask);
1002
1003 return &dio10->base;
1004 }
1005
dcn35_hubbub_create(struct dc_context * ctx)1006 static struct hubbub *dcn35_hubbub_create(struct dc_context *ctx)
1007 {
1008 int i;
1009
1010 struct dcn20_hubbub *hubbub3 = kzalloc_obj(struct dcn20_hubbub);
1011
1012 if (!hubbub3)
1013 return NULL;
1014
1015 #undef REG_STRUCT
1016 #define REG_STRUCT hubbub_reg
1017 hubbub_reg_init();
1018
1019 #undef REG_STRUCT
1020 #define REG_STRUCT vmid_regs
1021 vmid_regs_init(0),
1022 vmid_regs_init(1),
1023 vmid_regs_init(2),
1024 vmid_regs_init(3),
1025 vmid_regs_init(4),
1026 vmid_regs_init(5),
1027 vmid_regs_init(6),
1028 vmid_regs_init(7),
1029 vmid_regs_init(8),
1030 vmid_regs_init(9),
1031 vmid_regs_init(10),
1032 vmid_regs_init(11),
1033 vmid_regs_init(12),
1034 vmid_regs_init(13),
1035 vmid_regs_init(14),
1036 vmid_regs_init(15);
1037
1038 hubbub35_construct(hubbub3, ctx,
1039 &hubbub_reg,
1040 &hubbub_shift,
1041 &hubbub_mask,
1042 384,/*ctx->dc->dml.ip.det_buffer_size_kbytes,*/
1043 8, /*ctx->dc->dml.ip.pixel_chunk_size_kbytes,*/
1044 1792 /*ctx->dc->dml.ip.config_return_buffer_size_in_kbytes*/);
1045
1046
1047 for (i = 0; i < res_cap_dcn35.num_vmid; i++) {
1048 struct dcn20_vmid *vmid = &hubbub3->vmid[i];
1049
1050 vmid->ctx = ctx;
1051
1052 vmid->regs = &vmid_regs[i];
1053 vmid->shifts = &vmid_shifts;
1054 vmid->masks = &vmid_masks;
1055 }
1056
1057 return &hubbub3->base;
1058 }
1059
dcn35_timing_generator_create(struct dc_context * ctx,uint32_t instance)1060 static struct timing_generator *dcn35_timing_generator_create(
1061 struct dc_context *ctx,
1062 uint32_t instance)
1063 {
1064 struct optc *tgn10 =
1065 kzalloc_obj(struct optc);
1066
1067 if (!tgn10)
1068 return NULL;
1069
1070 #undef REG_STRUCT
1071 #define REG_STRUCT optc_regs
1072 optc_regs_init(0),
1073 optc_regs_init(1),
1074 optc_regs_init(2),
1075 optc_regs_init(3);
1076
1077 tgn10->base.inst = instance;
1078 tgn10->base.ctx = ctx;
1079
1080 tgn10->tg_regs = &optc_regs[instance];
1081 tgn10->tg_shift = &optc_shift;
1082 tgn10->tg_mask = &optc_mask;
1083
1084 dcn35_timing_generator_init(tgn10);
1085
1086 return &tgn10->base;
1087 }
1088
1089 static const struct encoder_feature_support link_enc_feature = {
1090 .max_hdmi_deep_color = COLOR_DEPTH_121212,
1091 .max_hdmi_pixel_clock = 600000,
1092 .hdmi_ycbcr420_supported = true,
1093 .dp_ycbcr420_supported = true,
1094 .fec_supported = true,
1095 .flags.bits.IS_HBR2_CAPABLE = true,
1096 .flags.bits.IS_HBR3_CAPABLE = true,
1097 .flags.bits.IS_TPS3_CAPABLE = true,
1098 .flags.bits.IS_TPS4_CAPABLE = true
1099 };
1100
dcn35_link_encoder_create(struct dc_context * ctx,const struct encoder_init_data * enc_init_data)1101 static struct link_encoder *dcn35_link_encoder_create(
1102 struct dc_context *ctx,
1103 const struct encoder_init_data *enc_init_data)
1104 {
1105 struct dcn20_link_encoder *enc20 =
1106 kzalloc_obj(struct dcn20_link_encoder);
1107
1108 if (!enc20 || enc_init_data->hpd_source >= ARRAY_SIZE(link_enc_hpd_regs))
1109 return NULL;
1110
1111 #undef REG_STRUCT
1112 #define REG_STRUCT link_enc_aux_regs
1113 aux_regs_init(0),
1114 aux_regs_init(1),
1115 aux_regs_init(2),
1116 aux_regs_init(3),
1117 aux_regs_init(4);
1118
1119 #undef REG_STRUCT
1120 #define REG_STRUCT link_enc_hpd_regs
1121 hpd_regs_init(0),
1122 hpd_regs_init(1),
1123 hpd_regs_init(2),
1124 hpd_regs_init(3),
1125 hpd_regs_init(4);
1126
1127 #undef REG_STRUCT
1128 #define REG_STRUCT link_enc_regs
1129 link_regs_init(0, A),
1130 link_regs_init(1, B),
1131 link_regs_init(2, C),
1132 link_regs_init(3, D),
1133 link_regs_init(4, E);
1134
1135 dcn35_link_encoder_construct(enc20,
1136 enc_init_data,
1137 &link_enc_feature,
1138 &link_enc_regs[enc_init_data->transmitter],
1139 &link_enc_aux_regs[enc_init_data->channel - 1],
1140 &link_enc_hpd_regs[enc_init_data->hpd_source],
1141 &le_shift,
1142 &le_mask);
1143
1144 return &enc20->enc10.base;
1145 }
1146
1147 /* Create a minimal link encoder object not associated with a particular
1148 * physical connector.
1149 * resource_funcs.link_enc_create_minimal
1150 */
dcn31_link_enc_create_minimal(struct dc_context * ctx,enum engine_id eng_id)1151 static struct link_encoder *dcn31_link_enc_create_minimal(
1152 struct dc_context *ctx, enum engine_id eng_id)
1153 {
1154 struct dcn20_link_encoder *enc20;
1155
1156 if ((eng_id - ENGINE_ID_DIGA) > ctx->dc->res_pool->res_cap->num_dig_link_enc)
1157 return NULL;
1158
1159 enc20 = kzalloc_obj(struct dcn20_link_encoder);
1160 if (!enc20)
1161 return NULL;
1162
1163 dcn31_link_encoder_construct_minimal(
1164 enc20,
1165 ctx,
1166 &link_enc_feature,
1167 &link_enc_regs[eng_id - ENGINE_ID_DIGA],
1168 eng_id);
1169
1170 return &enc20->enc10.base;
1171 }
1172
dcn31_panel_cntl_create(const struct panel_cntl_init_data * init_data)1173 static struct panel_cntl *dcn31_panel_cntl_create(const struct panel_cntl_init_data *init_data)
1174 {
1175 struct dcn31_panel_cntl *panel_cntl =
1176 kzalloc_obj(struct dcn31_panel_cntl);
1177
1178 if (!panel_cntl)
1179 return NULL;
1180
1181 dcn31_panel_cntl_construct(panel_cntl, init_data);
1182
1183 return &panel_cntl->base;
1184 }
1185
read_dce_straps(struct dc_context * ctx,struct resource_straps * straps)1186 static void read_dce_straps(
1187 struct dc_context *ctx,
1188 struct resource_straps *straps)
1189 {
1190 generic_reg_get(ctx, regDC_PINSTRAPS + BASE(regDC_PINSTRAPS_BASE_IDX),
1191 FN(DC_PINSTRAPS, DC_PINSTRAPS_AUDIO), &straps->dc_pinstraps_audio);
1192
1193 }
1194
dcn31_create_audio(struct dc_context * ctx,unsigned int inst)1195 static struct audio *dcn31_create_audio(
1196 struct dc_context *ctx, unsigned int inst)
1197 {
1198
1199 #undef REG_STRUCT
1200 #define REG_STRUCT audio_regs
1201 audio_regs_init(0),
1202 audio_regs_init(1),
1203 audio_regs_init(2),
1204 audio_regs_init(3),
1205 audio_regs_init(4);
1206 audio_regs_init(5);
1207 audio_regs_init(6);
1208
1209 return dce_audio_create(ctx, inst,
1210 &audio_regs[inst], &audio_shift, &audio_mask);
1211 }
1212
dcn31_vpg_create(struct dc_context * ctx,uint32_t inst)1213 static struct vpg *dcn31_vpg_create(
1214 struct dc_context *ctx,
1215 uint32_t inst)
1216 {
1217 struct dcn31_vpg *vpg31 = kzalloc_obj(struct dcn31_vpg);
1218
1219 if (!vpg31)
1220 return NULL;
1221
1222 #undef REG_STRUCT
1223 #define REG_STRUCT vpg_regs
1224 vpg_regs_init(0),
1225 vpg_regs_init(1),
1226 vpg_regs_init(2),
1227 vpg_regs_init(3),
1228 vpg_regs_init(4),
1229 vpg_regs_init(5),
1230 vpg_regs_init(6),
1231 vpg_regs_init(7),
1232 vpg_regs_init(8),
1233 vpg_regs_init(9);
1234
1235 vpg31_construct(vpg31, ctx, inst,
1236 &vpg_regs[inst],
1237 &vpg_shift,
1238 &vpg_mask);
1239
1240 return &vpg31->base;
1241 }
1242
dcn31_afmt_create(struct dc_context * ctx,uint32_t inst)1243 static struct afmt *dcn31_afmt_create(
1244 struct dc_context *ctx,
1245 uint32_t inst)
1246 {
1247 struct dcn31_afmt *afmt31 = kzalloc_obj(struct dcn31_afmt);
1248
1249 if (!afmt31)
1250 return NULL;
1251
1252 #undef REG_STRUCT
1253 #define REG_STRUCT afmt_regs
1254 afmt_regs_init(0),
1255 afmt_regs_init(1),
1256 afmt_regs_init(2),
1257 afmt_regs_init(3),
1258 afmt_regs_init(4),
1259 afmt_regs_init(5);
1260
1261 afmt31_construct(afmt31, ctx, inst,
1262 &afmt_regs[inst],
1263 &afmt_shift,
1264 &afmt_mask);
1265
1266 // Light sleep by default, no need to power down here
1267
1268 return &afmt31->base;
1269 }
1270
dcn31_apg_create(struct dc_context * ctx,uint32_t inst)1271 static struct apg *dcn31_apg_create(
1272 struct dc_context *ctx,
1273 uint32_t inst)
1274 {
1275 struct dcn31_apg *apg31 = kzalloc_obj(struct dcn31_apg);
1276
1277 if (!apg31)
1278 return NULL;
1279
1280 #undef REG_STRUCT
1281 #define REG_STRUCT apg_regs
1282 apg_regs_init(0),
1283 apg_regs_init(1),
1284 apg_regs_init(2),
1285 apg_regs_init(3);
1286
1287 apg31_construct(apg31, ctx, inst,
1288 &apg_regs[inst],
1289 &apg_shift,
1290 &apg_mask);
1291
1292 return &apg31->base;
1293 }
1294
dcn35_stream_encoder_create(enum engine_id eng_id,struct dc_context * ctx)1295 static struct stream_encoder *dcn35_stream_encoder_create(
1296 enum engine_id eng_id,
1297 struct dc_context *ctx)
1298 {
1299 struct dcn10_stream_encoder *enc1;
1300 struct vpg *vpg;
1301 struct afmt *afmt;
1302 int vpg_inst;
1303 int afmt_inst;
1304
1305 /* Mapping of VPG, AFMT, DME register blocks to DIO block instance */
1306 if (eng_id < 0 || eng_id >= ARRAY_SIZE(stream_enc_regs))
1307 return NULL;
1308
1309 vpg_inst = eng_id;
1310 afmt_inst = eng_id;
1311
1312 enc1 = kzalloc_obj(struct dcn10_stream_encoder);
1313 vpg = dcn31_vpg_create(ctx, vpg_inst);
1314 afmt = dcn31_afmt_create(ctx, afmt_inst);
1315
1316 if (!enc1 || !vpg || !afmt) {
1317 kfree(enc1);
1318 kfree(vpg);
1319 kfree(afmt);
1320 return NULL;
1321 }
1322
1323 #undef REG_STRUCT
1324 #define REG_STRUCT stream_enc_regs
1325 stream_enc_regs_init(0),
1326 stream_enc_regs_init(1),
1327 stream_enc_regs_init(2),
1328 stream_enc_regs_init(3),
1329 stream_enc_regs_init(4);
1330
1331 dcn35_dio_stream_encoder_construct(enc1, ctx, ctx->dc_bios,
1332 eng_id, vpg, afmt,
1333 &stream_enc_regs[eng_id],
1334 &se_shift, &se_mask);
1335
1336 return &enc1->base;
1337 }
1338
dcn31_hpo_dp_stream_encoder_create(enum engine_id eng_id,struct dc_context * ctx)1339 static struct hpo_dp_stream_encoder *dcn31_hpo_dp_stream_encoder_create(
1340 enum engine_id eng_id,
1341 struct dc_context *ctx)
1342 {
1343 struct dcn31_hpo_dp_stream_encoder *hpo_dp_enc31;
1344 struct vpg *vpg;
1345 struct apg *apg;
1346 uint32_t hpo_dp_inst;
1347 uint32_t vpg_inst;
1348 uint32_t apg_inst;
1349
1350 ASSERT((eng_id >= ENGINE_ID_HPO_DP_0) && (eng_id <= ENGINE_ID_HPO_DP_3));
1351 hpo_dp_inst = eng_id - ENGINE_ID_HPO_DP_0;
1352
1353 /* Mapping of VPG register blocks to HPO DP block instance:
1354 * VPG[6] -> HPO_DP[0]
1355 * VPG[7] -> HPO_DP[1]
1356 * VPG[8] -> HPO_DP[2]
1357 * VPG[9] -> HPO_DP[3]
1358 */
1359 vpg_inst = hpo_dp_inst + 6;
1360
1361 /* Mapping of APG register blocks to HPO DP block instance:
1362 * APG[0] -> HPO_DP[0]
1363 * APG[1] -> HPO_DP[1]
1364 * APG[2] -> HPO_DP[2]
1365 * APG[3] -> HPO_DP[3]
1366 */
1367 apg_inst = hpo_dp_inst;
1368
1369 /* allocate HPO stream encoder and create VPG sub-block */
1370 hpo_dp_enc31 = kzalloc_obj(struct dcn31_hpo_dp_stream_encoder);
1371 vpg = dcn31_vpg_create(ctx, vpg_inst);
1372 apg = dcn31_apg_create(ctx, apg_inst);
1373
1374 if (!hpo_dp_enc31 || !vpg || !apg) {
1375 kfree(hpo_dp_enc31);
1376 kfree(vpg);
1377 kfree(apg);
1378 return NULL;
1379 }
1380
1381 #undef REG_STRUCT
1382 #define REG_STRUCT hpo_dp_stream_enc_regs
1383 hpo_dp_stream_encoder_reg_init(0),
1384 hpo_dp_stream_encoder_reg_init(1),
1385 hpo_dp_stream_encoder_reg_init(2),
1386 hpo_dp_stream_encoder_reg_init(3);
1387
1388 dcn31_hpo_dp_stream_encoder_construct(hpo_dp_enc31, ctx, ctx->dc_bios,
1389 hpo_dp_inst, eng_id, vpg, apg,
1390 &hpo_dp_stream_enc_regs[hpo_dp_inst],
1391 &hpo_dp_se_shift, &hpo_dp_se_mask);
1392
1393 return &hpo_dp_enc31->base;
1394 }
1395
dcn31_hpo_dp_link_encoder_create(uint8_t inst,struct dc_context * ctx)1396 static struct hpo_dp_link_encoder *dcn31_hpo_dp_link_encoder_create(
1397 uint8_t inst,
1398 struct dc_context *ctx)
1399 {
1400 struct dcn31_hpo_dp_link_encoder *hpo_dp_enc31;
1401
1402 /* allocate HPO link encoder */
1403 hpo_dp_enc31 = kzalloc_obj(struct dcn31_hpo_dp_link_encoder);
1404 if (!hpo_dp_enc31)
1405 return NULL; /* out of memory */
1406
1407 #undef REG_STRUCT
1408 #define REG_STRUCT hpo_dp_link_enc_regs
1409 hpo_dp_link_encoder_reg_init(0),
1410 hpo_dp_link_encoder_reg_init(1);
1411
1412 hpo_dp_link_encoder31_construct(hpo_dp_enc31, ctx, inst,
1413 &hpo_dp_link_enc_regs[inst],
1414 &hpo_dp_le_shift, &hpo_dp_le_mask);
1415
1416 return &hpo_dp_enc31->base;
1417 }
1418
dcn35_hwseq_create(struct dc_context * ctx)1419 static struct dce_hwseq *dcn35_hwseq_create(
1420 struct dc_context *ctx)
1421 {
1422 struct dce_hwseq *hws = kzalloc_obj(struct dce_hwseq);
1423
1424 #undef REG_STRUCT
1425 #define REG_STRUCT hwseq_reg
1426 hwseq_reg_init();
1427
1428 if (hws) {
1429 hws->ctx = ctx;
1430 hws->regs = &hwseq_reg;
1431 hws->shifts = &hwseq_shift;
1432 hws->masks = &hwseq_mask;
1433 }
1434 return hws;
1435 }
1436 static const struct resource_create_funcs res_create_funcs = {
1437 .read_dce_straps = read_dce_straps,
1438 .create_audio = dcn31_create_audio,
1439 .create_stream_encoder = dcn35_stream_encoder_create,
1440 .create_hpo_dp_stream_encoder = dcn31_hpo_dp_stream_encoder_create,
1441 .create_hpo_dp_link_encoder = dcn31_hpo_dp_link_encoder_create,
1442 .create_hwseq = dcn35_hwseq_create,
1443 };
1444
dcn35_resource_destruct(struct dcn35_resource_pool * pool)1445 static void dcn35_resource_destruct(struct dcn35_resource_pool *pool)
1446 {
1447 unsigned int i;
1448
1449 for (i = 0; i < pool->base.stream_enc_count; i++) {
1450 if (pool->base.stream_enc[i] != NULL) {
1451 if (pool->base.stream_enc[i]->vpg != NULL) {
1452 kfree(DCN30_VPG_FROM_VPG(pool->base.stream_enc[i]->vpg));
1453 pool->base.stream_enc[i]->vpg = NULL;
1454 }
1455 if (pool->base.stream_enc[i]->afmt != NULL) {
1456 kfree(DCN30_AFMT_FROM_AFMT(pool->base.stream_enc[i]->afmt));
1457 pool->base.stream_enc[i]->afmt = NULL;
1458 }
1459 kfree(DCN10STRENC_FROM_STRENC(pool->base.stream_enc[i]));
1460 pool->base.stream_enc[i] = NULL;
1461 }
1462 }
1463
1464 for (i = 0; i < pool->base.hpo_dp_stream_enc_count; i++) {
1465 if (pool->base.hpo_dp_stream_enc[i] != NULL) {
1466 if (pool->base.hpo_dp_stream_enc[i]->vpg != NULL) {
1467 kfree(DCN30_VPG_FROM_VPG(pool->base.hpo_dp_stream_enc[i]->vpg));
1468 pool->base.hpo_dp_stream_enc[i]->vpg = NULL;
1469 }
1470 if (pool->base.hpo_dp_stream_enc[i]->apg != NULL) {
1471 kfree(DCN31_APG_FROM_APG(pool->base.hpo_dp_stream_enc[i]->apg));
1472 pool->base.hpo_dp_stream_enc[i]->apg = NULL;
1473 }
1474 kfree(DCN3_1_HPO_DP_STREAM_ENC_FROM_HPO_STREAM_ENC(pool->base.hpo_dp_stream_enc[i]));
1475 pool->base.hpo_dp_stream_enc[i] = NULL;
1476 }
1477 }
1478
1479 for (i = 0; i < pool->base.hpo_dp_link_enc_count; i++) {
1480 if (pool->base.hpo_dp_link_enc[i] != NULL) {
1481 kfree(DCN3_1_HPO_DP_LINK_ENC_FROM_HPO_LINK_ENC(pool->base.hpo_dp_link_enc[i]));
1482 pool->base.hpo_dp_link_enc[i] = NULL;
1483 }
1484 }
1485
1486 for (i = 0; i < pool->base.res_cap->num_dsc; i++) {
1487 if (pool->base.dscs[i] != NULL)
1488 dcn20_dsc_destroy(&pool->base.dscs[i]);
1489 }
1490
1491 if (pool->base.mpc != NULL) {
1492 kfree(TO_DCN20_MPC(pool->base.mpc));
1493 pool->base.mpc = NULL;
1494 }
1495 if (pool->base.hubbub != NULL) {
1496 kfree(pool->base.hubbub);
1497 pool->base.hubbub = NULL;
1498 }
1499 for (i = 0; i < pool->base.pipe_count; i++) {
1500 if (pool->base.dpps[i] != NULL)
1501 dcn35_dpp_destroy(&pool->base.dpps[i]);
1502
1503 if (pool->base.ipps[i] != NULL)
1504 pool->base.ipps[i]->funcs->ipp_destroy(&pool->base.ipps[i]);
1505
1506 if (pool->base.hubps[i] != NULL) {
1507 kfree(TO_DCN20_HUBP(pool->base.hubps[i]));
1508 pool->base.hubps[i] = NULL;
1509 }
1510
1511 if (pool->base.irqs != NULL) {
1512 dal_irq_service_destroy(&pool->base.irqs);
1513 }
1514 }
1515
1516 for (i = 0; i < pool->base.res_cap->num_ddc; i++) {
1517 if (pool->base.engines[i] != NULL)
1518 dce110_engine_destroy(&pool->base.engines[i]);
1519 if (pool->base.hw_i2cs[i] != NULL) {
1520 kfree(pool->base.hw_i2cs[i]);
1521 pool->base.hw_i2cs[i] = NULL;
1522 }
1523 if (pool->base.sw_i2cs[i] != NULL) {
1524 kfree(pool->base.sw_i2cs[i]);
1525 pool->base.sw_i2cs[i] = NULL;
1526 }
1527 }
1528
1529 for (i = 0; i < pool->base.res_cap->num_opp; i++) {
1530 if (pool->base.opps[i] != NULL)
1531 pool->base.opps[i]->funcs->opp_destroy(&pool->base.opps[i]);
1532 }
1533
1534 for (i = 0; i < pool->base.res_cap->num_timing_generator; i++) {
1535 if (pool->base.timing_generators[i] != NULL) {
1536 kfree(DCN10TG_FROM_TG(pool->base.timing_generators[i]));
1537 pool->base.timing_generators[i] = NULL;
1538 }
1539 }
1540
1541 for (i = 0; i < pool->base.res_cap->num_dwb; i++) {
1542 if (pool->base.dwbc[i] != NULL) {
1543 kfree(TO_DCN30_DWBC(pool->base.dwbc[i]));
1544 pool->base.dwbc[i] = NULL;
1545 }
1546 if (pool->base.mcif_wb[i] != NULL) {
1547 kfree(TO_DCN30_MMHUBBUB(pool->base.mcif_wb[i]));
1548 pool->base.mcif_wb[i] = NULL;
1549 }
1550 }
1551
1552 for (i = 0; i < pool->base.audio_count; i++) {
1553 if (pool->base.audios[i])
1554 dce_aud_destroy(&pool->base.audios[i]);
1555 }
1556
1557 for (i = 0; i < pool->base.clk_src_count; i++) {
1558 if (pool->base.clock_sources[i] != NULL) {
1559 dcn20_clock_source_destroy(&pool->base.clock_sources[i]);
1560 pool->base.clock_sources[i] = NULL;
1561 }
1562 }
1563
1564 for (i = 0; i < pool->base.res_cap->num_mpc_3dlut; i++) {
1565 if (pool->base.mpc_lut[i] != NULL) {
1566 dc_3dlut_func_release(pool->base.mpc_lut[i]);
1567 pool->base.mpc_lut[i] = NULL;
1568 }
1569 if (pool->base.mpc_shaper[i] != NULL) {
1570 dc_transfer_func_release(pool->base.mpc_shaper[i]);
1571 pool->base.mpc_shaper[i] = NULL;
1572 }
1573 }
1574
1575 if (pool->base.dp_clock_source != NULL) {
1576 dcn20_clock_source_destroy(&pool->base.dp_clock_source);
1577 pool->base.dp_clock_source = NULL;
1578 }
1579
1580 for (i = 0; i < pool->base.res_cap->num_timing_generator; i++) {
1581 if (pool->base.multiple_abms[i] != NULL)
1582 dce_abm_destroy(&pool->base.multiple_abms[i]);
1583 }
1584
1585 if (pool->base.psr != NULL)
1586 dmub_psr_destroy(&pool->base.psr);
1587
1588 if (pool->base.replay != NULL)
1589 dmub_replay_destroy(&pool->base.replay);
1590
1591 if (pool->base.pg_cntl != NULL)
1592 dcn_pg_cntl_destroy(&pool->base.pg_cntl);
1593
1594 if (pool->base.dccg != NULL)
1595 dcn_dccg_destroy(&pool->base.dccg);
1596
1597 if (pool->base.dio != NULL) {
1598 kfree(TO_DCN10_DIO(pool->base.dio));
1599 pool->base.dio = NULL;
1600 }
1601 }
1602
dcn35_hubp_create(struct dc_context * ctx,uint32_t inst)1603 static struct hubp *dcn35_hubp_create(
1604 struct dc_context *ctx,
1605 uint32_t inst)
1606 {
1607 struct dcn20_hubp *hubp2 =
1608 kzalloc_obj(struct dcn20_hubp);
1609
1610 if (!hubp2)
1611 return NULL;
1612
1613 #undef REG_STRUCT
1614 #define REG_STRUCT hubp_regs
1615 hubp_regs_init(0),
1616 hubp_regs_init(1),
1617 hubp_regs_init(2),
1618 hubp_regs_init(3);
1619
1620 if (hubp35_construct(hubp2, ctx, inst,
1621 &hubp_regs[inst], &hubp_shift, &hubp_mask))
1622 return &hubp2->base;
1623
1624 BREAK_TO_DEBUGGER();
1625 kfree(hubp2);
1626 return NULL;
1627 }
1628
dcn35_dwbc_init(struct dcn30_dwbc * dwbc30,struct dc_context * ctx)1629 static void dcn35_dwbc_init(struct dcn30_dwbc *dwbc30, struct dc_context *ctx)
1630 {
1631 dcn35_dwbc_set_fgcg(
1632 dwbc30, ctx->dc->debug.enable_fine_grain_clock_gating.bits.dwb);
1633 }
1634
dcn35_dwbc_create(struct dc_context * ctx,struct resource_pool * pool)1635 static bool dcn35_dwbc_create(struct dc_context *ctx, struct resource_pool *pool)
1636 {
1637 int i;
1638 uint32_t pipe_count = pool->res_cap->num_dwb;
1639
1640 for (i = 0; i < pipe_count; i++) {
1641 struct dcn30_dwbc *dwbc30 = kzalloc_obj(struct dcn30_dwbc);
1642
1643 if (!dwbc30) {
1644 dm_error("DC: failed to create dwbc30!\n");
1645 return false;
1646 }
1647
1648 #undef REG_STRUCT
1649 #define REG_STRUCT dwbc35_regs
1650 dwbc_regs_dcn3_init(0);
1651
1652 dcn35_dwbc_construct(dwbc30, ctx,
1653 &dwbc35_regs[i],
1654 &dwbc35_shift,
1655 &dwbc35_mask,
1656 i);
1657
1658 pool->dwbc[i] = &dwbc30->base;
1659
1660 dcn35_dwbc_init(dwbc30, ctx);
1661 }
1662 return true;
1663 }
1664
dcn35_mmhubbub_init(struct dcn30_mmhubbub * mcif_wb30,struct dc_context * ctx)1665 static void dcn35_mmhubbub_init(struct dcn30_mmhubbub *mcif_wb30,
1666 struct dc_context *ctx)
1667 {
1668 dcn35_mmhubbub_set_fgcg(
1669 mcif_wb30,
1670 ctx->dc->debug.enable_fine_grain_clock_gating.bits.mmhubbub);
1671 }
1672
dcn35_mmhubbub_create(struct dc_context * ctx,struct resource_pool * pool)1673 static bool dcn35_mmhubbub_create(struct dc_context *ctx, struct resource_pool *pool)
1674 {
1675 int i;
1676 uint32_t pipe_count = pool->res_cap->num_dwb;
1677
1678 for (i = 0; i < pipe_count; i++) {
1679 struct dcn30_mmhubbub *mcif_wb30 = kzalloc_obj(struct dcn30_mmhubbub);
1680
1681 if (!mcif_wb30) {
1682 dm_error("DC: failed to create mcif_wb30!\n");
1683 return false;
1684 }
1685
1686 #undef REG_STRUCT
1687 #define REG_STRUCT mcif_wb35_regs
1688 mcif_wb_regs_dcn3_init(0);
1689
1690 dcn35_mmhubbub_construct(mcif_wb30, ctx,
1691 &mcif_wb35_regs[i],
1692 &mcif_wb35_shift,
1693 &mcif_wb35_mask,
1694 i);
1695
1696 dcn35_mmhubbub_init(mcif_wb30, ctx);
1697
1698 pool->mcif_wb[i] = &mcif_wb30->base;
1699 }
1700 return true;
1701 }
1702
dcn35_dsc_create(struct dc_context * ctx,uint32_t inst)1703 static struct display_stream_compressor *dcn35_dsc_create(
1704 struct dc_context *ctx, uint32_t inst)
1705 {
1706 struct dcn20_dsc *dsc =
1707 kzalloc_obj(struct dcn20_dsc);
1708
1709 if (!dsc) {
1710 BREAK_TO_DEBUGGER();
1711 return NULL;
1712 }
1713
1714 #undef REG_STRUCT
1715 #define REG_STRUCT dsc_regs
1716 dsc_regsDCN35_init(0),
1717 dsc_regsDCN35_init(1),
1718 dsc_regsDCN35_init(2),
1719 dsc_regsDCN35_init(3);
1720
1721 dsc35_construct(dsc, ctx, inst, &dsc_regs[inst], &dsc_shift, &dsc_mask);
1722 dsc35_set_fgcg(dsc,
1723 ctx->dc->debug.enable_fine_grain_clock_gating.bits.dsc);
1724 return &dsc->base;
1725 }
1726
dcn35_destroy_resource_pool(struct resource_pool ** pool)1727 static void dcn35_destroy_resource_pool(struct resource_pool **pool)
1728 {
1729 struct dcn35_resource_pool *dcn35_pool = TO_DCN35_RES_POOL(*pool);
1730
1731 dcn35_resource_destruct(dcn35_pool);
1732 kfree(dcn35_pool);
1733 *pool = NULL;
1734 }
1735
dcn35_clock_source_create(struct dc_context * ctx,struct dc_bios * bios,enum clock_source_id id,const struct dce110_clk_src_regs * regs,bool dp_clk_src)1736 static struct clock_source *dcn35_clock_source_create(
1737 struct dc_context *ctx,
1738 struct dc_bios *bios,
1739 enum clock_source_id id,
1740 const struct dce110_clk_src_regs *regs,
1741 bool dp_clk_src)
1742 {
1743 struct dce110_clk_src *clk_src =
1744 kzalloc_obj(struct dce110_clk_src);
1745
1746 if (!clk_src)
1747 return NULL;
1748
1749 if (dcn31_clk_src_construct(clk_src, ctx, bios, id,
1750 regs, &cs_shift, &cs_mask)) {
1751 clk_src->base.dp_clk_src = dp_clk_src;
1752 return &clk_src->base;
1753 }
1754
1755 kfree(clk_src);
1756 BREAK_TO_DEBUGGER();
1757 return NULL;
1758 }
1759
1760 static struct dc_cap_funcs cap_funcs = {
1761 .get_dcc_compression_cap = dcn20_get_dcc_compression_cap
1762 };
1763
dcn35_get_panel_config_defaults(struct dc_panel_config * panel_config)1764 static void dcn35_get_panel_config_defaults(struct dc_panel_config *panel_config)
1765 {
1766 *panel_config = panel_config_defaults;
1767 }
1768
1769
dcn35_validate_bandwidth(struct dc * dc,struct dc_state * context,enum dc_validate_mode validate_mode)1770 static enum dc_status dcn35_validate_bandwidth(struct dc *dc,
1771 struct dc_state *context,
1772 enum dc_validate_mode validate_mode)
1773 {
1774 bool out = false;
1775
1776 out = dml2_validate(dc, context,
1777 context->power_source == DC_POWER_SOURCE_DC ? context->bw_ctx.dml2_dc_power_source : context->bw_ctx.dml2,
1778 validate_mode);
1779
1780 if (validate_mode != DC_VALIDATE_MODE_AND_PROGRAMMING)
1781 return out ? DC_OK : DC_FAIL_BANDWIDTH_VALIDATE;
1782
1783 DC_FP_START();
1784 dcn35_decide_zstate_support(dc, context);
1785 DC_FP_END();
1786
1787 return out ? DC_OK : DC_FAIL_BANDWIDTH_VALIDATE;
1788 }
1789
dcn35_patch_unknown_plane_state(struct dc_plane_state * plane_state)1790 enum dc_status dcn35_patch_unknown_plane_state(struct dc_plane_state *plane_state)
1791 {
1792 plane_state->tiling_info.gfxversion = DcGfxVersion9;
1793 dcn20_patch_unknown_plane_state(plane_state);
1794 return DC_OK;
1795 }
1796
1797
populate_dml_pipes_from_context_fpu(struct dc * dc,struct dc_state * context,display_e2e_pipe_params_st * pipes,enum dc_validate_mode validate_mode)1798 static int populate_dml_pipes_from_context_fpu(struct dc *dc,
1799 struct dc_state *context,
1800 display_e2e_pipe_params_st *pipes,
1801 enum dc_validate_mode validate_mode)
1802 {
1803 int ret;
1804
1805 DC_FP_START();
1806 ret = dcn35_populate_dml_pipes_from_context_fpu(dc, context, pipes, validate_mode);
1807 DC_FP_END();
1808
1809 return ret;
1810 }
1811
1812 static struct resource_funcs dcn35_res_pool_funcs = {
1813 .destroy = dcn35_destroy_resource_pool,
1814 .link_enc_create = dcn35_link_encoder_create,
1815 .link_enc_create_minimal = dcn31_link_enc_create_minimal,
1816 .link_encs_assign = link_enc_cfg_link_encs_assign,
1817 .link_enc_unassign = link_enc_cfg_link_enc_unassign,
1818 .panel_cntl_create = dcn31_panel_cntl_create,
1819 .validate_bandwidth = dcn35_validate_bandwidth,
1820 .calculate_wm_and_dlg = NULL,
1821 .update_soc_for_wm_a = dcn31_update_soc_for_wm_a,
1822 .populate_dml_pipes = populate_dml_pipes_from_context_fpu,
1823 .acquire_free_pipe_as_secondary_dpp_pipe = dcn20_acquire_free_pipe_for_layer,
1824 .release_pipe = dcn20_release_pipe,
1825 .add_stream_to_ctx = dcn30_add_stream_to_ctx,
1826 .add_dsc_to_stream_resource = dcn20_add_dsc_to_stream_resource,
1827 .remove_stream_from_ctx = dcn20_remove_stream_from_ctx,
1828 .populate_dml_writeback_from_context = dcn30_populate_dml_writeback_from_context,
1829 .set_mcif_arb_params = dcn30_set_mcif_arb_params,
1830 .find_first_free_match_stream_enc_for_link = dcn10_find_first_free_match_stream_enc_for_link,
1831 .acquire_post_bldn_3dlut = dcn30_acquire_post_bldn_3dlut,
1832 .release_post_bldn_3dlut = dcn30_release_post_bldn_3dlut,
1833 .update_bw_bounding_box = dcn35_update_bw_bounding_box_fpu,
1834 .patch_unknown_plane_state = dcn35_patch_unknown_plane_state,
1835 .get_panel_config_defaults = dcn35_get_panel_config_defaults,
1836 .get_preferred_eng_id_dpia = dcn35_get_preferred_eng_id_dpia,
1837 .get_det_buffer_size = dcn31_get_det_buffer_size,
1838 .get_vstartup_for_pipe = dcn10_get_vstartup_for_pipe,
1839 .update_dc_state_for_encoder_switch = dcn31_update_dc_state_for_encoder_switch,
1840 .build_pipe_pix_clk_params = dcn20_build_pipe_pix_clk_params
1841 };
1842
dcn35_resource_construct(uint8_t num_virtual_links,struct dc * dc,struct dcn35_resource_pool * pool)1843 static bool dcn35_resource_construct(
1844 uint8_t num_virtual_links,
1845 struct dc *dc,
1846 struct dcn35_resource_pool *pool)
1847 {
1848 int i;
1849 struct dc_context *ctx = dc->ctx;
1850 struct irq_service_init_data init_data;
1851
1852 #undef REG_STRUCT
1853 #define REG_STRUCT bios_regs
1854 bios_regs_init();
1855
1856 #undef REG_STRUCT
1857 #define REG_STRUCT clk_src_regs
1858 clk_src_regs_init(0, A),
1859 clk_src_regs_init(1, B),
1860 clk_src_regs_init(2, C),
1861 clk_src_regs_init(3, D),
1862 clk_src_regs_init(4, E);
1863
1864 #undef REG_STRUCT
1865 #define REG_STRUCT abm_regs
1866 abm_regs_init(0),
1867 abm_regs_init(1),
1868 abm_regs_init(2),
1869 abm_regs_init(3);
1870
1871 #undef REG_STRUCT
1872 #define REG_STRUCT dccg_regs
1873 dccg_regs_init();
1874
1875 ctx->dc_bios->regs = &bios_regs;
1876
1877 pool->base.res_cap = &res_cap_dcn35;
1878
1879 pool->base.funcs = &dcn35_res_pool_funcs;
1880
1881 /*************************************************
1882 * Resource + asic cap harcoding *
1883 *************************************************/
1884 pool->base.underlay_pipe_index = NO_UNDERLAY_PIPE;
1885 pool->base.pipe_count = pool->base.res_cap->num_timing_generator;
1886 pool->base.mpcc_count = pool->base.res_cap->num_timing_generator;
1887 dc->caps.max_downscale_ratio = 600;
1888 dc->caps.i2c_speed_in_khz = 100;
1889 dc->caps.i2c_speed_in_khz_hdcp = 100;
1890 dc->caps.max_cursor_size = 256;
1891 dc->caps.min_horizontal_blanking_period = 80;
1892 dc->caps.dmdata_alloc_size = 2048;
1893 dc->caps.max_slave_planes = 3;
1894 dc->caps.max_slave_yuv_planes = 3;
1895 dc->caps.max_slave_rgb_planes = 3;
1896 dc->caps.post_blend_color_processing = true;
1897 dc->caps.force_dp_tps4_for_cp2520 = true;
1898 if (dc->config.forceHBR2CP2520)
1899 dc->caps.force_dp_tps4_for_cp2520 = false;
1900 dc->caps.dp_hpo = true;
1901 dc->caps.dp_hdmi21_pcon_support = true;
1902
1903 dc->caps.edp_dsc_support = true;
1904 dc->caps.extended_aux_timeout_support = true;
1905 dc->caps.dmcub_support = true;
1906 dc->caps.is_apu = true;
1907 dc->caps.seamless_odm = true;
1908
1909 dc->caps.zstate_support = true;
1910 dc->caps.ips_support = true;
1911 dc->caps.max_v_total = (1 << 15) - 1;
1912 dc->caps.vtotal_limited_by_fp2 = true;
1913
1914 /* Color pipeline capabilities */
1915 dc->caps.color.dpp.dcn_arch = 1;
1916 dc->caps.color.dpp.input_lut_shared = 0;
1917 dc->caps.color.dpp.icsc = 1;
1918 dc->caps.color.dpp.dgam_ram = 0; // must use gamma_corr
1919 dc->caps.color.dpp.dgam_rom_caps.srgb = 1;
1920 dc->caps.color.dpp.dgam_rom_caps.bt2020 = 1;
1921 dc->caps.color.dpp.dgam_rom_caps.gamma2_2 = 1;
1922 dc->caps.color.dpp.dgam_rom_caps.pq = 1;
1923 dc->caps.color.dpp.dgam_rom_caps.hlg = 1;
1924 dc->caps.color.dpp.post_csc = 1;
1925 dc->caps.color.dpp.gamma_corr = 1;
1926 dc->caps.color.dpp.dgam_rom_for_yuv = 0;
1927
1928 dc->caps.color.dpp.hw_3d_lut = 0;
1929 dc->caps.color.dpp.ogam_ram = 0; // no OGAM in DPP since DCN1
1930 // no OGAM ROM on DCN301
1931 dc->caps.color.dpp.ogam_rom_caps.srgb = 0;
1932 dc->caps.color.dpp.ogam_rom_caps.bt2020 = 0;
1933 dc->caps.color.dpp.ogam_rom_caps.gamma2_2 = 0;
1934 dc->caps.color.dpp.ogam_rom_caps.pq = 0;
1935 dc->caps.color.dpp.ogam_rom_caps.hlg = 0;
1936 dc->caps.color.dpp.ocsc = 0;
1937
1938 dc->caps.color.mpc.gamut_remap = 1;
1939 dc->caps.color.mpc.num_3dluts = pool->base.res_cap->num_mpc_3dlut; //2
1940 dc->caps.color.mpc.ogam_ram = 1;
1941 dc->caps.color.mpc.ogam_rom_caps.srgb = 0;
1942 dc->caps.color.mpc.ogam_rom_caps.bt2020 = 0;
1943 dc->caps.color.mpc.ogam_rom_caps.gamma2_2 = 0;
1944 dc->caps.color.mpc.ogam_rom_caps.pq = 0;
1945 dc->caps.color.mpc.ogam_rom_caps.hlg = 0;
1946 dc->caps.color.mpc.ocsc = 1;
1947 dc->caps.color.mpc.preblend = true;
1948
1949 dc->caps.num_of_host_routers = 2;
1950 dc->caps.num_of_dpias_per_host_router = 2;
1951
1952 /* max_disp_clock_khz_at_vmin is slightly lower than the STA value in order
1953 * to provide some margin.
1954 * It's expected for furture ASIC to have equal or higher value, in order to
1955 * have determinstic power improvement from generate to genration.
1956 * (i.e., we should not expect new ASIC generation with lower vmin rate)
1957 */
1958 dc->caps.max_disp_clock_khz_at_vmin = 650000;
1959
1960 /* Sequential ONO is based on ASIC. */
1961 if (dc->ctx->asic_id.hw_internal_rev >= 0x40)
1962 dc->caps.sequential_ono = true;
1963
1964 /* Use pipe context based otg sync logic */
1965 dc->config.use_pipe_ctx_sync_logic = true;
1966
1967
1968 dc->config.disable_hbr_audio_dp2 = true;
1969 /* read VBIOS LTTPR caps */
1970 {
1971 if (ctx->dc_bios->funcs->get_lttpr_caps) {
1972 enum bp_result bp_query_result;
1973 uint8_t is_vbios_lttpr_enable = 0;
1974
1975 bp_query_result = ctx->dc_bios->funcs->get_lttpr_caps(ctx->dc_bios, &is_vbios_lttpr_enable);
1976 dc->caps.vbios_lttpr_enable = (bp_query_result == BP_RESULT_OK) && !!is_vbios_lttpr_enable;
1977 }
1978
1979 /* interop bit is implicit */
1980 {
1981 dc->caps.vbios_lttpr_aware = true;
1982 }
1983 }
1984 dc->check_config = config_defaults;
1985
1986 if (dc->ctx->dce_environment == DCE_ENV_PRODUCTION_DRV)
1987 dc->debug = debug_defaults_drv;
1988 /*HW default is to have all the FGCG enabled, SW no need to program them*/
1989 dc->debug.enable_fine_grain_clock_gating.u32All = 0xFFFF;
1990 // Init the vm_helper
1991 if (dc->vm_helper)
1992 vm_helper_init(dc->vm_helper, 16);
1993
1994 /*************************************************
1995 * Create resources *
1996 *************************************************/
1997
1998 /* Clock Sources for Pixel Clock*/
1999 pool->base.clock_sources[DCN35_CLK_SRC_PLL0] =
2000 dcn35_clock_source_create(ctx, ctx->dc_bios,
2001 CLOCK_SOURCE_COMBO_PHY_PLL0,
2002 &clk_src_regs[0], false);
2003 pool->base.clock_sources[DCN35_CLK_SRC_PLL1] =
2004 dcn35_clock_source_create(ctx, ctx->dc_bios,
2005 CLOCK_SOURCE_COMBO_PHY_PLL1,
2006 &clk_src_regs[1], false);
2007 pool->base.clock_sources[DCN35_CLK_SRC_PLL2] =
2008 dcn35_clock_source_create(ctx, ctx->dc_bios,
2009 CLOCK_SOURCE_COMBO_PHY_PLL2,
2010 &clk_src_regs[2], false);
2011 pool->base.clock_sources[DCN35_CLK_SRC_PLL3] =
2012 dcn35_clock_source_create(ctx, ctx->dc_bios,
2013 CLOCK_SOURCE_COMBO_PHY_PLL3,
2014 &clk_src_regs[3], false);
2015 pool->base.clock_sources[DCN35_CLK_SRC_PLL4] =
2016 dcn35_clock_source_create(ctx, ctx->dc_bios,
2017 CLOCK_SOURCE_COMBO_PHY_PLL4,
2018 &clk_src_regs[4], false);
2019
2020 pool->base.clk_src_count = DCN35_CLK_SRC_TOTAL;
2021
2022 /* todo: not reuse phy_pll registers */
2023 pool->base.dp_clock_source =
2024 dcn35_clock_source_create(ctx, ctx->dc_bios,
2025 CLOCK_SOURCE_ID_DP_DTO,
2026 &clk_src_regs[0], true);
2027
2028 for (i = 0; i < pool->base.clk_src_count; i++) {
2029 if (pool->base.clock_sources[i] == NULL) {
2030 dm_error("DC: failed to create clock sources!\n");
2031 BREAK_TO_DEBUGGER();
2032 goto create_fail;
2033 }
2034 }
2035 /*temp till dml2 fully work without dml1*/
2036 dml_init_instance(&dc->dml, &dcn3_5_soc, &dcn3_5_ip, DML_PROJECT_DCN31);
2037
2038 /* TODO: DCCG */
2039 pool->base.dccg = dccg35_create(ctx, &dccg_regs, &dccg_shift, &dccg_mask);
2040 if (pool->base.dccg == NULL) {
2041 dm_error("DC: failed to create dccg!\n");
2042 BREAK_TO_DEBUGGER();
2043 goto create_fail;
2044 }
2045
2046 #undef REG_STRUCT
2047 #define REG_STRUCT pg_cntl_regs
2048 pg_cntl_dcn35_regs_init();
2049
2050 pool->base.pg_cntl = pg_cntl35_create(ctx, &pg_cntl_regs, &pg_cntl_shift, &pg_cntl_mask);
2051 if (pool->base.pg_cntl == NULL) {
2052 dm_error("DC: failed to create power gate control!\n");
2053 BREAK_TO_DEBUGGER();
2054 goto create_fail;
2055 }
2056
2057 /* TODO: IRQ */
2058 init_data.ctx = dc->ctx;
2059 pool->base.irqs = dal_irq_service_dcn35_create(&init_data);
2060 if (!pool->base.irqs)
2061 goto create_fail;
2062
2063 /* HUBBUB */
2064 pool->base.hubbub = dcn35_hubbub_create(ctx);
2065 if (pool->base.hubbub == NULL) {
2066 BREAK_TO_DEBUGGER();
2067 dm_error("DC: failed to create hubbub!\n");
2068 goto create_fail;
2069 }
2070
2071 /* DIO */
2072 pool->base.dio = dcn35_dio_create(ctx);
2073 if (pool->base.dio == NULL) {
2074 BREAK_TO_DEBUGGER();
2075 dm_error("DC: failed to create dio!\n");
2076 goto create_fail;
2077 }
2078
2079 /* HUBPs, DPPs, OPPs and TGs */
2080 for (i = 0; i < pool->base.pipe_count; i++) {
2081 pool->base.hubps[i] = dcn35_hubp_create(ctx, i);
2082 if (pool->base.hubps[i] == NULL) {
2083 BREAK_TO_DEBUGGER();
2084 dm_error(
2085 "DC: failed to create hubps!\n");
2086 goto create_fail;
2087 }
2088
2089 pool->base.dpps[i] = dcn35_dpp_create(ctx, i);
2090 if (pool->base.dpps[i] == NULL) {
2091 BREAK_TO_DEBUGGER();
2092 dm_error(
2093 "DC: failed to create dpps!\n");
2094 goto create_fail;
2095 }
2096 }
2097
2098 for (i = 0; i < pool->base.res_cap->num_opp; i++) {
2099 pool->base.opps[i] = dcn35_opp_create(ctx, i);
2100 if (pool->base.opps[i] == NULL) {
2101 BREAK_TO_DEBUGGER();
2102 dm_error(
2103 "DC: failed to create output pixel processor!\n");
2104 goto create_fail;
2105 }
2106 }
2107
2108 for (i = 0; i < pool->base.res_cap->num_timing_generator; i++) {
2109 pool->base.timing_generators[i] = dcn35_timing_generator_create(
2110 ctx, i);
2111 if (pool->base.timing_generators[i] == NULL) {
2112 BREAK_TO_DEBUGGER();
2113 dm_error("DC: failed to create tg!\n");
2114 goto create_fail;
2115 }
2116 }
2117 pool->base.timing_generator_count = i;
2118
2119 /* PSR */
2120 pool->base.psr = dmub_psr_create(ctx);
2121 if (pool->base.psr == NULL) {
2122 dm_error("DC: failed to create psr obj!\n");
2123 BREAK_TO_DEBUGGER();
2124 goto create_fail;
2125 }
2126
2127 /* Replay */
2128 pool->base.replay = dmub_replay_create(ctx);
2129 if (pool->base.replay == NULL) {
2130 dm_error("DC: failed to create replay obj!\n");
2131 BREAK_TO_DEBUGGER();
2132 goto create_fail;
2133 }
2134
2135 /* ABM */
2136 for (i = 0; i < pool->base.res_cap->num_timing_generator; i++) {
2137 pool->base.multiple_abms[i] = dmub_abm_create(ctx,
2138 &abm_regs[i],
2139 &abm_shift,
2140 &abm_mask);
2141 if (pool->base.multiple_abms[i] == NULL) {
2142 dm_error("DC: failed to create abm for pipe %d!\n", i);
2143 BREAK_TO_DEBUGGER();
2144 goto create_fail;
2145 }
2146 }
2147
2148 /* MPC and DSC */
2149 pool->base.mpc = dcn35_mpc_create(ctx, pool->base.mpcc_count, pool->base.res_cap->num_mpc_3dlut);
2150 if (pool->base.mpc == NULL) {
2151 BREAK_TO_DEBUGGER();
2152 dm_error("DC: failed to create mpc!\n");
2153 goto create_fail;
2154 }
2155
2156 for (i = 0; i < pool->base.res_cap->num_dsc; i++) {
2157 pool->base.dscs[i] = dcn35_dsc_create(ctx, i);
2158 if (pool->base.dscs[i] == NULL) {
2159 BREAK_TO_DEBUGGER();
2160 dm_error("DC: failed to create display stream compressor %d!\n", i);
2161 goto create_fail;
2162 }
2163 }
2164
2165 /* DWB and MMHUBBUB */
2166 if (!dcn35_dwbc_create(ctx, &pool->base)) {
2167 BREAK_TO_DEBUGGER();
2168 dm_error("DC: failed to create dwbc!\n");
2169 goto create_fail;
2170 }
2171
2172 if (!dcn35_mmhubbub_create(ctx, &pool->base)) {
2173 BREAK_TO_DEBUGGER();
2174 dm_error("DC: failed to create mcif_wb!\n");
2175 goto create_fail;
2176 }
2177
2178 /* AUX and I2C */
2179 for (i = 0; i < pool->base.res_cap->num_ddc; i++) {
2180 pool->base.engines[i] = dcn31_aux_engine_create(ctx, i);
2181 if (pool->base.engines[i] == NULL) {
2182 BREAK_TO_DEBUGGER();
2183 dm_error(
2184 "DC:failed to create aux engine!!\n");
2185 goto create_fail;
2186 }
2187 pool->base.hw_i2cs[i] = dcn31_i2c_hw_create(ctx, i);
2188 if (pool->base.hw_i2cs[i] == NULL) {
2189 BREAK_TO_DEBUGGER();
2190 dm_error(
2191 "DC:failed to create hw i2c!!\n");
2192 goto create_fail;
2193 }
2194 pool->base.sw_i2cs[i] = NULL;
2195 }
2196
2197 /* DCN3.5 has 6 DPIA */
2198 pool->base.usb4_dpia_count = 4;
2199 if (dc->debug.dpia_debug.bits.disable_dpia)
2200 pool->base.usb4_dpia_count = 0;
2201
2202 /* Audio, Stream Encoders including HPO and virtual, MPC 3D LUTs */
2203 if (!resource_construct(num_virtual_links, dc, &pool->base,
2204 &res_create_funcs))
2205 goto create_fail;
2206
2207 /* HW Sequencer and Plane caps */
2208 dcn35_hw_sequencer_construct(dc);
2209
2210 dc->caps.max_planes = pool->base.pipe_count;
2211
2212 for (i = 0; i < dc->caps.max_planes; ++i)
2213 dc->caps.planes[i] = plane_cap;
2214
2215 dc->caps.max_odm_combine_factor = 4;
2216
2217 dc->cap_funcs = cap_funcs;
2218
2219 dc->dcn_ip->max_num_dpp = pool->base.pipe_count;
2220
2221 dc->dml2_options.dcn_pipe_count = pool->base.pipe_count;
2222 dc->dml2_options.use_native_soc_bb_construction = true;
2223 dc->dml2_options.minimize_dispclk_using_odm = false;
2224 if (dc->config.EnableMinDispClkODM)
2225 dc->dml2_options.minimize_dispclk_using_odm = true;
2226 dc->dml2_options.enable_windowed_mpo_odm = dc->config.enable_windowed_mpo_odm;
2227
2228 resource_init_common_dml2_callbacks(dc, &dc->dml2_options);
2229 dc->dml2_options.callbacks.can_support_mclk_switch_using_fw_based_vblank_stretch = &dcn30_can_support_mclk_switch_using_fw_based_vblank_stretch;
2230
2231 dc->dml2_options.max_segments_per_hubp = 24;
2232 dc->dml2_options.det_segment_size = DCN3_2_DET_SEG_SIZE;/*todo*/
2233 dc->dml2_options.override_det_buffer_size_kbytes = true;
2234
2235 if (dc->config.sdpif_request_limit_words_per_umc == 0)
2236 dc->config.sdpif_request_limit_words_per_umc = 16;/*todo*/
2237
2238 return true;
2239
2240 create_fail:
2241
2242 dcn35_resource_destruct(pool);
2243
2244 return false;
2245 }
2246
dcn35_create_resource_pool(const struct dc_init_data * init_data,struct dc * dc)2247 struct resource_pool *dcn35_create_resource_pool(
2248 const struct dc_init_data *init_data,
2249 struct dc *dc)
2250 {
2251 struct dcn35_resource_pool *pool =
2252 kzalloc_obj(struct dcn35_resource_pool);
2253
2254 if (!pool)
2255 return NULL;
2256
2257 if (dcn35_resource_construct(init_data->num_virtual_links, dc, pool))
2258 return &pool->base;
2259
2260 BREAK_TO_DEBUGGER();
2261 kfree(pool);
2262 return NULL;
2263 }
2264