1 /* SPDX-License-Identifier: MIT */
2 /*
3 * Copyright 2023 Advanced Micro Devices, Inc.
4 *
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the "Software"),
7 * to deal in the Software without restriction, including without limitation
8 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
9 * and/or sell copies of the Software, and to permit persons to whom the
10 * Software is furnished to do so, subject to the following conditions:
11 *
12 * The above copyright notice and this permission notice shall be included in
13 * all copies or substantial portions of the Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
19 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
20 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
21 * OTHER DEALINGS IN THE SOFTWARE.
22 *
23 * Authors: AMD
24 *
25 */
26
27 #include "dcn35_opp.h"
28 #include "reg_helper.h"
29
30 #define REG(reg) ((const struct dcn35_opp_registers *)(oppn20->regs))->reg
31
32 #undef FN
33 #define FN(reg_name, field_name) \
34 ((const struct dcn35_opp_shift *)(oppn20->opp_shift))->field_name, \
35 ((const struct dcn35_opp_mask *)(oppn20->opp_mask))->field_name
36
37 #define CTX oppn20->base.ctx
38
dcn35_opp_construct(struct dcn20_opp * oppn20,struct dc_context * ctx,uint32_t inst,const struct dcn35_opp_registers * regs,const struct dcn35_opp_shift * opp_shift,const struct dcn35_opp_mask * opp_mask)39 void dcn35_opp_construct(struct dcn20_opp *oppn20, struct dc_context *ctx,
40 uint32_t inst, const struct dcn35_opp_registers *regs,
41 const struct dcn35_opp_shift *opp_shift,
42 const struct dcn35_opp_mask *opp_mask)
43 {
44 dcn20_opp_construct(oppn20, ctx, inst,
45 (const struct dcn20_opp_registers *)regs,
46 (const struct dcn20_opp_shift *)opp_shift,
47 (const struct dcn20_opp_mask *)opp_mask);
48 }
49
dcn35_opp_set_fgcg(struct dcn20_opp * oppn20,bool enable)50 void dcn35_opp_set_fgcg(struct dcn20_opp *oppn20, bool enable)
51 {
52 REG_UPDATE(OPP_TOP_CLK_CONTROL, OPP_FGCG_REP_DIS, !enable);
53 }
54
dcn35_opp_read_reg_state(struct output_pixel_processor * opp,struct dcn_opp_reg_state * opp_reg_state)55 void dcn35_opp_read_reg_state(struct output_pixel_processor *opp, struct dcn_opp_reg_state *opp_reg_state)
56 {
57 struct dcn20_opp *oppn20 = TO_DCN20_OPP(opp);
58
59 opp_reg_state->dpg_control = REG_READ(DPG_CONTROL);
60 opp_reg_state->fmt_control = REG_READ(FMT_CONTROL);
61 opp_reg_state->opp_abm_control = REG_READ(OPP_ABM_CONTROL);
62 opp_reg_state->opp_pipe_control = REG_READ(OPP_PIPE_CONTROL);
63 opp_reg_state->opp_pipe_crc_control = REG_READ(OPP_PIPE_CRC_CONTROL);
64 opp_reg_state->oppbuf_control = REG_READ(OPPBUF_CONTROL);
65 opp_reg_state->dscrm_dsc_forward_config = REG_READ(DSCRM_DSC_FORWARD_CONFIG);
66 }
67