1 /*
2 * Copyright 2022 Advanced Micro Devices, Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
21 *
22 * Authors: AMD
23 *
24 */
25
26
27 #include "dcn35_clk_mgr.h"
28
29 #include "dccg.h"
30 #include "clk_mgr_internal.h"
31
32 // For dce12_get_dp_ref_freq_khz
33 #include "dce100/dce_clk_mgr.h"
34
35 // For dcn20_update_clocks_update_dpp_dto
36 #include "dcn20/dcn20_clk_mgr.h"
37
38
39
40
41 #include "reg_helper.h"
42 #include "core_types.h"
43 #include "dcn35_smu.h"
44 #include "dm_helpers.h"
45
46 /* TODO: remove this include once we ported over remaining clk mgr functions*/
47 #include "dcn30/dcn30_clk_mgr.h"
48 #include "dcn31/dcn31_clk_mgr.h"
49
50 #include "dc_dmub_srv.h"
51 #include "link.h"
52 #include "logger_types.h"
53
54 #undef DC_LOGGER
55 #define DC_LOGGER \
56 clk_mgr->base.base.ctx->logger
57
58 #define regCLK1_CLK_PLL_REQ 0x0237
59 #define regCLK1_CLK_PLL_REQ_BASE_IDX 0
60
61 #define CLK1_CLK_PLL_REQ__FbMult_int__SHIFT 0x0
62 #define CLK1_CLK_PLL_REQ__PllSpineDiv__SHIFT 0xc
63 #define CLK1_CLK_PLL_REQ__FbMult_frac__SHIFT 0x10
64 #define CLK1_CLK_PLL_REQ__FbMult_int_MASK 0x000001FFL
65 #define CLK1_CLK_PLL_REQ__PllSpineDiv_MASK 0x0000F000L
66 #define CLK1_CLK_PLL_REQ__FbMult_frac_MASK 0xFFFF0000L
67
68 #define regCLK1_CLK2_BYPASS_CNTL 0x029c
69 #define regCLK1_CLK2_BYPASS_CNTL_BASE_IDX 0
70
71 #define CLK1_CLK2_BYPASS_CNTL__CLK2_BYPASS_SEL__SHIFT 0x0
72 #define CLK1_CLK2_BYPASS_CNTL__CLK2_BYPASS_DIV__SHIFT 0x10
73 #define CLK1_CLK2_BYPASS_CNTL__CLK2_BYPASS_SEL_MASK 0x00000007L
74 #define CLK1_CLK2_BYPASS_CNTL__CLK2_BYPASS_DIV_MASK 0x000F0000L
75
76 #define REG(reg_name) \
77 (ctx->clk_reg_offsets[reg ## reg_name ## _BASE_IDX] + reg ## reg_name)
78
79 #define TO_CLK_MGR_DCN35(clk_mgr)\
80 container_of(clk_mgr, struct clk_mgr_dcn35, base)
81
dcn35_get_active_display_cnt_wa(struct dc * dc,struct dc_state * context,int * all_active_disps)82 static int dcn35_get_active_display_cnt_wa(
83 struct dc *dc,
84 struct dc_state *context,
85 int *all_active_disps)
86 {
87 int i, display_count = 0;
88 bool tmds_present = false;
89
90 for (i = 0; i < context->stream_count; i++) {
91 const struct dc_stream_state *stream = context->streams[i];
92
93 if (stream->signal == SIGNAL_TYPE_HDMI_TYPE_A ||
94 stream->signal == SIGNAL_TYPE_DVI_SINGLE_LINK ||
95 stream->signal == SIGNAL_TYPE_DVI_DUAL_LINK)
96 tmds_present = true;
97 }
98
99 for (i = 0; i < dc->link_count; i++) {
100 const struct dc_link *link = dc->links[i];
101
102 /* abusing the fact that the dig and phy are coupled to see if the phy is enabled */
103 if (link->link_enc && link->link_enc->funcs->is_dig_enabled &&
104 link->link_enc->funcs->is_dig_enabled(link->link_enc))
105 display_count++;
106 }
107 if (all_active_disps != NULL)
108 *all_active_disps = display_count;
109 /* WA for hang on HDMI after display off back on*/
110 if (display_count == 0 && tmds_present)
111 display_count = 1;
112
113 return display_count;
114 }
115
dcn35_disable_otg_wa(struct clk_mgr * clk_mgr_base,struct dc_state * context,bool safe_to_lower,bool disable)116 static void dcn35_disable_otg_wa(struct clk_mgr *clk_mgr_base, struct dc_state *context,
117 bool safe_to_lower, bool disable)
118 {
119 struct dc *dc = clk_mgr_base->ctx->dc;
120 int i;
121
122 for (i = 0; i < dc->res_pool->pipe_count; ++i) {
123 struct pipe_ctx *pipe = safe_to_lower
124 ? &context->res_ctx.pipe_ctx[i]
125 : &dc->current_state->res_ctx.pipe_ctx[i];
126
127 if (pipe->top_pipe || pipe->prev_odm_pipe)
128 continue;
129 if (pipe->stream && (pipe->stream->dpms_off || dc_is_virtual_signal(pipe->stream->signal) ||
130 !pipe->stream->link_enc)) {
131 if (disable) {
132 if (pipe->stream_res.tg && pipe->stream_res.tg->funcs->immediate_disable_crtc)
133 pipe->stream_res.tg->funcs->immediate_disable_crtc(pipe->stream_res.tg);
134
135 reset_sync_context_for_pipe(dc, context, i);
136 } else {
137 pipe->stream_res.tg->funcs->enable_crtc(pipe->stream_res.tg);
138 }
139 }
140 }
141 }
142
dcn35_update_clocks_update_dtb_dto(struct clk_mgr_internal * clk_mgr,struct dc_state * context,int ref_dtbclk_khz)143 static void dcn35_update_clocks_update_dtb_dto(struct clk_mgr_internal *clk_mgr,
144 struct dc_state *context,
145 int ref_dtbclk_khz)
146 {
147 struct dccg *dccg = clk_mgr->dccg;
148 uint32_t tg_mask = 0;
149 int i;
150
151 for (i = 0; i < clk_mgr->base.ctx->dc->res_pool->pipe_count; i++) {
152 struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[i];
153 struct dtbclk_dto_params dto_params = {0};
154
155 /* use mask to program DTO once per tg */
156 if (pipe_ctx->stream_res.tg &&
157 !(tg_mask & (1 << pipe_ctx->stream_res.tg->inst))) {
158 tg_mask |= (1 << pipe_ctx->stream_res.tg->inst);
159
160 dto_params.otg_inst = pipe_ctx->stream_res.tg->inst;
161 dto_params.ref_dtbclk_khz = ref_dtbclk_khz;
162
163 dccg->funcs->set_dtbclk_dto(clk_mgr->dccg, &dto_params);
164 //dccg->funcs->set_audio_dtbclk_dto(clk_mgr->dccg, &dto_params);
165 }
166 }
167 }
168
dcn35_update_clocks_update_dpp_dto(struct clk_mgr_internal * clk_mgr,struct dc_state * context,bool safe_to_lower)169 static void dcn35_update_clocks_update_dpp_dto(struct clk_mgr_internal *clk_mgr,
170 struct dc_state *context, bool safe_to_lower)
171 {
172 int i;
173 bool dppclk_active[MAX_PIPES] = {0};
174
175
176 clk_mgr->dccg->ref_dppclk = clk_mgr->base.clks.dppclk_khz;
177 for (i = 0; i < clk_mgr->base.ctx->dc->res_pool->pipe_count; i++) {
178 int dpp_inst = 0, dppclk_khz, prev_dppclk_khz;
179
180 dppclk_khz = context->res_ctx.pipe_ctx[i].plane_res.bw.dppclk_khz;
181
182 if (context->res_ctx.pipe_ctx[i].plane_res.dpp)
183 dpp_inst = context->res_ctx.pipe_ctx[i].plane_res.dpp->inst;
184 else if (!context->res_ctx.pipe_ctx[i].plane_res.dpp && dppclk_khz == 0) {
185 /* dpp == NULL && dppclk_khz == 0 is valid because of pipe harvesting.
186 * In this case just continue in loop
187 */
188 continue;
189 } else if (!context->res_ctx.pipe_ctx[i].plane_res.dpp && dppclk_khz > 0) {
190 /* The software state is not valid if dpp resource is NULL and
191 * dppclk_khz > 0.
192 */
193 ASSERT(false);
194 continue;
195 }
196
197 prev_dppclk_khz = clk_mgr->dccg->pipe_dppclk_khz[i];
198
199 if (safe_to_lower || prev_dppclk_khz < dppclk_khz)
200 clk_mgr->dccg->funcs->update_dpp_dto(
201 clk_mgr->dccg, dpp_inst, dppclk_khz);
202 dppclk_active[dpp_inst] = true;
203 }
204 if (safe_to_lower)
205 for (i = 0; i < clk_mgr->base.ctx->dc->res_pool->pipe_count; i++) {
206 struct dpp *old_dpp = clk_mgr->base.ctx->dc->current_state->res_ctx.pipe_ctx[i].plane_res.dpp;
207
208 if (old_dpp && !dppclk_active[old_dpp->inst])
209 clk_mgr->dccg->funcs->update_dpp_dto(clk_mgr->dccg, old_dpp->inst, 0);
210 }
211 }
212
dcn35_update_clocks(struct clk_mgr * clk_mgr_base,struct dc_state * context,bool safe_to_lower)213 void dcn35_update_clocks(struct clk_mgr *clk_mgr_base,
214 struct dc_state *context,
215 bool safe_to_lower)
216 {
217 union dmub_rb_cmd cmd;
218 struct clk_mgr_internal *clk_mgr = TO_CLK_MGR_INTERNAL(clk_mgr_base);
219 struct dc_clocks *new_clocks = &context->bw_ctx.bw.dcn.clk;
220 struct dc *dc = clk_mgr_base->ctx->dc;
221 int display_count = 0;
222 bool update_dppclk = false;
223 bool update_dispclk = false;
224 bool dpp_clock_lowered = false;
225 int all_active_disps = 0;
226
227 if (dc->work_arounds.skip_clock_update)
228 return;
229
230 display_count = dcn35_get_active_display_cnt_wa(dc, context, &all_active_disps);
231 if (new_clocks->dtbclk_en && !new_clocks->ref_dtbclk_khz)
232 new_clocks->ref_dtbclk_khz = 600000;
233
234 /*
235 * if it is safe to lower, but we are already in the lower state, we don't have to do anything
236 * also if safe to lower is false, we just go in the higher state
237 */
238 if (safe_to_lower) {
239 if (new_clocks->zstate_support != DCN_ZSTATE_SUPPORT_DISALLOW &&
240 new_clocks->zstate_support != clk_mgr_base->clks.zstate_support) {
241 dcn35_smu_set_zstate_support(clk_mgr, new_clocks->zstate_support);
242 dm_helpers_enable_periodic_detection(clk_mgr_base->ctx, true);
243 clk_mgr_base->clks.zstate_support = new_clocks->zstate_support;
244 }
245
246 if (clk_mgr_base->clks.dtbclk_en && !new_clocks->dtbclk_en) {
247 dcn35_smu_set_dtbclk(clk_mgr, false);
248 clk_mgr_base->clks.dtbclk_en = new_clocks->dtbclk_en;
249 }
250 /* check that we're not already in lower */
251 if (clk_mgr_base->clks.pwr_state != DCN_PWR_STATE_LOW_POWER) {
252 /* if we can go lower, go lower */
253 if (display_count == 0)
254 clk_mgr_base->clks.pwr_state = DCN_PWR_STATE_LOW_POWER;
255 }
256 } else {
257 if (new_clocks->zstate_support == DCN_ZSTATE_SUPPORT_DISALLOW &&
258 new_clocks->zstate_support != clk_mgr_base->clks.zstate_support) {
259 dcn35_smu_set_zstate_support(clk_mgr, DCN_ZSTATE_SUPPORT_DISALLOW);
260 dm_helpers_enable_periodic_detection(clk_mgr_base->ctx, false);
261 clk_mgr_base->clks.zstate_support = new_clocks->zstate_support;
262 }
263
264 if (!clk_mgr_base->clks.dtbclk_en && new_clocks->dtbclk_en) {
265 dcn35_smu_set_dtbclk(clk_mgr, true);
266 clk_mgr_base->clks.dtbclk_en = new_clocks->dtbclk_en;
267
268 dcn35_update_clocks_update_dtb_dto(clk_mgr, context, new_clocks->ref_dtbclk_khz);
269 clk_mgr_base->clks.ref_dtbclk_khz = new_clocks->ref_dtbclk_khz;
270 }
271
272 /* check that we're not already in D0 */
273 if (clk_mgr_base->clks.pwr_state != DCN_PWR_STATE_MISSION_MODE) {
274 union display_idle_optimization_u idle_info = { 0 };
275
276 dcn35_smu_set_display_idle_optimization(clk_mgr, idle_info.data);
277 /* update power state */
278 clk_mgr_base->clks.pwr_state = DCN_PWR_STATE_MISSION_MODE;
279 }
280 }
281 if (dc->debug.force_min_dcfclk_mhz > 0)
282 new_clocks->dcfclk_khz = (new_clocks->dcfclk_khz > (dc->debug.force_min_dcfclk_mhz * 1000)) ?
283 new_clocks->dcfclk_khz : (dc->debug.force_min_dcfclk_mhz * 1000);
284
285 if (should_set_clock(safe_to_lower, new_clocks->dcfclk_khz, clk_mgr_base->clks.dcfclk_khz)) {
286 clk_mgr_base->clks.dcfclk_khz = new_clocks->dcfclk_khz;
287 dcn35_smu_set_hard_min_dcfclk(clk_mgr, clk_mgr_base->clks.dcfclk_khz);
288 }
289
290 if (should_set_clock(safe_to_lower,
291 new_clocks->dcfclk_deep_sleep_khz, clk_mgr_base->clks.dcfclk_deep_sleep_khz)) {
292 clk_mgr_base->clks.dcfclk_deep_sleep_khz = new_clocks->dcfclk_deep_sleep_khz;
293 dcn35_smu_set_min_deep_sleep_dcfclk(clk_mgr, clk_mgr_base->clks.dcfclk_deep_sleep_khz);
294 }
295
296 // workaround: Limit dppclk to 100Mhz to avoid lower eDP panel switch to plus 4K monitor underflow.
297 if (new_clocks->dppclk_khz < 100000)
298 new_clocks->dppclk_khz = 100000;
299
300 if (should_set_clock(safe_to_lower, new_clocks->dppclk_khz, clk_mgr->base.clks.dppclk_khz)) {
301 if (clk_mgr->base.clks.dppclk_khz > new_clocks->dppclk_khz)
302 dpp_clock_lowered = true;
303 clk_mgr_base->clks.dppclk_khz = new_clocks->dppclk_khz;
304 update_dppclk = true;
305 }
306
307 if (should_set_clock(safe_to_lower, new_clocks->dispclk_khz, clk_mgr_base->clks.dispclk_khz)) {
308 dcn35_disable_otg_wa(clk_mgr_base, context, safe_to_lower, true);
309
310 clk_mgr_base->clks.dispclk_khz = new_clocks->dispclk_khz;
311 dcn35_smu_set_dispclk(clk_mgr, clk_mgr_base->clks.dispclk_khz);
312 dcn35_disable_otg_wa(clk_mgr_base, context, safe_to_lower, false);
313
314 update_dispclk = true;
315 }
316
317 /* clock limits are received with MHz precision, divide by 1000 to prevent setting clocks at every call */
318 if (!dc->debug.disable_dtb_ref_clk_switch &&
319 should_set_clock(safe_to_lower, new_clocks->ref_dtbclk_khz / 1000,
320 clk_mgr_base->clks.ref_dtbclk_khz / 1000)) {
321 dcn35_update_clocks_update_dtb_dto(clk_mgr, context, new_clocks->ref_dtbclk_khz);
322 clk_mgr_base->clks.ref_dtbclk_khz = new_clocks->ref_dtbclk_khz;
323 }
324
325 if (dpp_clock_lowered) {
326 // increase per DPP DTO before lowering global dppclk
327 dcn35_update_clocks_update_dpp_dto(clk_mgr, context, safe_to_lower);
328 dcn35_smu_set_dppclk(clk_mgr, clk_mgr_base->clks.dppclk_khz);
329 } else {
330 // increase global DPPCLK before lowering per DPP DTO
331 if (update_dppclk || update_dispclk)
332 dcn35_smu_set_dppclk(clk_mgr, clk_mgr_base->clks.dppclk_khz);
333 dcn35_update_clocks_update_dpp_dto(clk_mgr, context, safe_to_lower);
334 }
335
336 // notify DMCUB of latest clocks
337 memset(&cmd, 0, sizeof(cmd));
338 cmd.notify_clocks.header.type = DMUB_CMD__CLK_MGR;
339 cmd.notify_clocks.header.sub_type = DMUB_CMD__CLK_MGR_NOTIFY_CLOCKS;
340 cmd.notify_clocks.clocks.dcfclk_khz = clk_mgr_base->clks.dcfclk_khz;
341 cmd.notify_clocks.clocks.dcfclk_deep_sleep_khz =
342 clk_mgr_base->clks.dcfclk_deep_sleep_khz;
343 cmd.notify_clocks.clocks.dispclk_khz = clk_mgr_base->clks.dispclk_khz;
344 cmd.notify_clocks.clocks.dppclk_khz = clk_mgr_base->clks.dppclk_khz;
345
346 dc_wake_and_execute_dmub_cmd(dc->ctx, &cmd, DM_DMUB_WAIT_TYPE_WAIT);
347 }
348
get_vco_frequency_from_reg(struct clk_mgr_internal * clk_mgr)349 static int get_vco_frequency_from_reg(struct clk_mgr_internal *clk_mgr)
350 {
351 /* get FbMult value */
352 struct fixed31_32 pll_req;
353 unsigned int fbmult_frac_val = 0;
354 unsigned int fbmult_int_val = 0;
355 struct dc_context *ctx = clk_mgr->base.ctx;
356
357 /*
358 * Register value of fbmult is in 8.16 format, we are converting to 314.32
359 * to leverage the fix point operations available in driver
360 */
361
362 REG_GET(CLK1_CLK_PLL_REQ, FbMult_frac, &fbmult_frac_val); /* 16 bit fractional part*/
363 REG_GET(CLK1_CLK_PLL_REQ, FbMult_int, &fbmult_int_val); /* 8 bit integer part */
364
365 pll_req = dc_fixpt_from_int(fbmult_int_val);
366
367 /*
368 * since fractional part is only 16 bit in register definition but is 32 bit
369 * in our fix point definiton, need to shift left by 16 to obtain correct value
370 */
371 pll_req.value |= fbmult_frac_val << 16;
372
373 /* multiply by REFCLK period */
374 pll_req = dc_fixpt_mul_int(pll_req, clk_mgr->dfs_ref_freq_khz);
375
376 /* integer part is now VCO frequency in kHz */
377 return dc_fixpt_floor(pll_req);
378 }
379
dcn35_enable_pme_wa(struct clk_mgr * clk_mgr_base)380 static void dcn35_enable_pme_wa(struct clk_mgr *clk_mgr_base)
381 {
382 struct clk_mgr_internal *clk_mgr = TO_CLK_MGR_INTERNAL(clk_mgr_base);
383
384 dcn35_smu_enable_pme_wa(clk_mgr);
385 }
386
dcn35_init_clocks(struct clk_mgr * clk_mgr)387 void dcn35_init_clocks(struct clk_mgr *clk_mgr)
388 {
389 uint32_t ref_dtbclk = clk_mgr->clks.ref_dtbclk_khz;
390
391 memset(&(clk_mgr->clks), 0, sizeof(struct dc_clocks));
392
393 // Assumption is that boot state always supports pstate
394 clk_mgr->clks.ref_dtbclk_khz = ref_dtbclk; // restore ref_dtbclk
395 clk_mgr->clks.p_state_change_support = true;
396 clk_mgr->clks.prev_p_state_change_support = true;
397 clk_mgr->clks.pwr_state = DCN_PWR_STATE_UNKNOWN;
398 clk_mgr->clks.zstate_support = DCN_ZSTATE_SUPPORT_UNKNOWN;
399 }
400
dcn35_are_clock_states_equal(struct dc_clocks * a,struct dc_clocks * b)401 bool dcn35_are_clock_states_equal(struct dc_clocks *a,
402 struct dc_clocks *b)
403 {
404 if (a->dispclk_khz != b->dispclk_khz)
405 return false;
406 else if (a->dppclk_khz != b->dppclk_khz)
407 return false;
408 else if (a->dcfclk_khz != b->dcfclk_khz)
409 return false;
410 else if (a->dcfclk_deep_sleep_khz != b->dcfclk_deep_sleep_khz)
411 return false;
412 else if (a->zstate_support != b->zstate_support)
413 return false;
414 else if (a->dtbclk_en != b->dtbclk_en)
415 return false;
416
417 return true;
418 }
419
dcn35_dump_clk_registers(struct clk_state_registers_and_bypass * regs_and_bypass,struct clk_mgr_dcn35 * clk_mgr)420 static void dcn35_dump_clk_registers(struct clk_state_registers_and_bypass *regs_and_bypass,
421 struct clk_mgr_dcn35 *clk_mgr)
422 {
423 }
424
425 static struct clk_bw_params dcn35_bw_params = {
426 .vram_type = Ddr4MemType,
427 .num_channels = 1,
428 .clk_table = {
429 .num_entries = 4,
430 },
431
432 };
433
434 static struct wm_table ddr5_wm_table = {
435 .entries = {
436 {
437 .wm_inst = WM_A,
438 .wm_type = WM_TYPE_PSTATE_CHG,
439 .pstate_latency_us = 11.72,
440 .sr_exit_time_us = 28.0,
441 .sr_enter_plus_exit_time_us = 30.0,
442 .valid = true,
443 },
444 {
445 .wm_inst = WM_B,
446 .wm_type = WM_TYPE_PSTATE_CHG,
447 .pstate_latency_us = 11.72,
448 .sr_exit_time_us = 28.0,
449 .sr_enter_plus_exit_time_us = 30.0,
450 .valid = true,
451 },
452 {
453 .wm_inst = WM_C,
454 .wm_type = WM_TYPE_PSTATE_CHG,
455 .pstate_latency_us = 11.72,
456 .sr_exit_time_us = 28.0,
457 .sr_enter_plus_exit_time_us = 30.0,
458 .valid = true,
459 },
460 {
461 .wm_inst = WM_D,
462 .wm_type = WM_TYPE_PSTATE_CHG,
463 .pstate_latency_us = 11.72,
464 .sr_exit_time_us = 28.0,
465 .sr_enter_plus_exit_time_us = 30.0,
466 .valid = true,
467 },
468 }
469 };
470
471 static struct wm_table lpddr5_wm_table = {
472 .entries = {
473 {
474 .wm_inst = WM_A,
475 .wm_type = WM_TYPE_PSTATE_CHG,
476 .pstate_latency_us = 11.65333,
477 .sr_exit_time_us = 28.0,
478 .sr_enter_plus_exit_time_us = 30.0,
479 .valid = true,
480 },
481 {
482 .wm_inst = WM_B,
483 .wm_type = WM_TYPE_PSTATE_CHG,
484 .pstate_latency_us = 11.65333,
485 .sr_exit_time_us = 28.0,
486 .sr_enter_plus_exit_time_us = 30.0,
487 .valid = true,
488 },
489 {
490 .wm_inst = WM_C,
491 .wm_type = WM_TYPE_PSTATE_CHG,
492 .pstate_latency_us = 11.65333,
493 .sr_exit_time_us = 28.0,
494 .sr_enter_plus_exit_time_us = 30.0,
495 .valid = true,
496 },
497 {
498 .wm_inst = WM_D,
499 .wm_type = WM_TYPE_PSTATE_CHG,
500 .pstate_latency_us = 11.65333,
501 .sr_exit_time_us = 28.0,
502 .sr_enter_plus_exit_time_us = 30.0,
503 .valid = true,
504 },
505 }
506 };
507
508 static DpmClocks_t_dcn35 dummy_clocks;
509
510 static struct dcn35_watermarks dummy_wms = { 0 };
511
dcn35_build_watermark_ranges(struct clk_bw_params * bw_params,struct dcn35_watermarks * table)512 static void dcn35_build_watermark_ranges(struct clk_bw_params *bw_params, struct dcn35_watermarks *table)
513 {
514 int i, num_valid_sets;
515
516 num_valid_sets = 0;
517
518 for (i = 0; i < WM_SET_COUNT; i++) {
519 /* skip empty entries, the smu array has no holes*/
520 if (!bw_params->wm_table.entries[i].valid)
521 continue;
522
523 table->WatermarkRow[WM_DCFCLK][num_valid_sets].WmSetting = bw_params->wm_table.entries[i].wm_inst;
524 table->WatermarkRow[WM_DCFCLK][num_valid_sets].WmType = bw_params->wm_table.entries[i].wm_type;
525 /* We will not select WM based on fclk, so leave it as unconstrained */
526 table->WatermarkRow[WM_DCFCLK][num_valid_sets].MinClock = 0;
527 table->WatermarkRow[WM_DCFCLK][num_valid_sets].MaxClock = 0xFFFF;
528
529 if (table->WatermarkRow[WM_DCFCLK][num_valid_sets].WmType == WM_TYPE_PSTATE_CHG) {
530 if (i == 0)
531 table->WatermarkRow[WM_DCFCLK][num_valid_sets].MinMclk = 0;
532 else {
533 /* add 1 to make it non-overlapping with next lvl */
534 table->WatermarkRow[WM_DCFCLK][num_valid_sets].MinMclk =
535 bw_params->clk_table.entries[i - 1].dcfclk_mhz + 1;
536 }
537 table->WatermarkRow[WM_DCFCLK][num_valid_sets].MaxMclk =
538 bw_params->clk_table.entries[i].dcfclk_mhz;
539
540 } else {
541 /* unconstrained for memory retraining */
542 table->WatermarkRow[WM_DCFCLK][num_valid_sets].MinClock = 0;
543 table->WatermarkRow[WM_DCFCLK][num_valid_sets].MaxClock = 0xFFFF;
544
545 /* Modify previous watermark range to cover up to max */
546 table->WatermarkRow[WM_DCFCLK][num_valid_sets - 1].MaxClock = 0xFFFF;
547 }
548 num_valid_sets++;
549 }
550
551 ASSERT(num_valid_sets != 0); /* Must have at least one set of valid watermarks */
552
553 /* modify the min and max to make sure we cover the whole range*/
554 table->WatermarkRow[WM_DCFCLK][0].MinMclk = 0;
555 table->WatermarkRow[WM_DCFCLK][0].MinClock = 0;
556 table->WatermarkRow[WM_DCFCLK][num_valid_sets - 1].MaxMclk = 0xFFFF;
557 table->WatermarkRow[WM_DCFCLK][num_valid_sets - 1].MaxClock = 0xFFFF;
558
559 /* This is for writeback only, does not matter currently as no writeback support*/
560 table->WatermarkRow[WM_SOCCLK][0].WmSetting = WM_A;
561 table->WatermarkRow[WM_SOCCLK][0].MinClock = 0;
562 table->WatermarkRow[WM_SOCCLK][0].MaxClock = 0xFFFF;
563 table->WatermarkRow[WM_SOCCLK][0].MinMclk = 0;
564 table->WatermarkRow[WM_SOCCLK][0].MaxMclk = 0xFFFF;
565 }
566
dcn35_notify_wm_ranges(struct clk_mgr * clk_mgr_base)567 static void dcn35_notify_wm_ranges(struct clk_mgr *clk_mgr_base)
568 {
569 struct clk_mgr_internal *clk_mgr = TO_CLK_MGR_INTERNAL(clk_mgr_base);
570 struct clk_mgr_dcn35 *clk_mgr_dcn35 = TO_CLK_MGR_DCN35(clk_mgr);
571 struct dcn35_watermarks *table = clk_mgr_dcn35->smu_wm_set.wm_set;
572
573 if (!clk_mgr->smu_ver)
574 return;
575
576 if (!table || clk_mgr_dcn35->smu_wm_set.mc_address.quad_part == 0)
577 return;
578
579 memset(table, 0, sizeof(*table));
580
581 dcn35_build_watermark_ranges(clk_mgr_base->bw_params, table);
582
583 dcn35_smu_set_dram_addr_high(clk_mgr,
584 clk_mgr_dcn35->smu_wm_set.mc_address.high_part);
585 dcn35_smu_set_dram_addr_low(clk_mgr,
586 clk_mgr_dcn35->smu_wm_set.mc_address.low_part);
587 dcn35_smu_transfer_wm_table_dram_2_smu(clk_mgr);
588 }
589
dcn35_get_dpm_table_from_smu(struct clk_mgr_internal * clk_mgr,struct dcn35_smu_dpm_clks * smu_dpm_clks)590 static void dcn35_get_dpm_table_from_smu(struct clk_mgr_internal *clk_mgr,
591 struct dcn35_smu_dpm_clks *smu_dpm_clks)
592 {
593 DpmClocks_t_dcn35 *table = smu_dpm_clks->dpm_clks;
594
595 if (!clk_mgr->smu_ver)
596 return;
597
598 if (!table || smu_dpm_clks->mc_address.quad_part == 0)
599 return;
600
601 memset(table, 0, sizeof(*table));
602
603 dcn35_smu_set_dram_addr_high(clk_mgr,
604 smu_dpm_clks->mc_address.high_part);
605 dcn35_smu_set_dram_addr_low(clk_mgr,
606 smu_dpm_clks->mc_address.low_part);
607 dcn35_smu_transfer_dpm_table_smu_2_dram(clk_mgr);
608 }
609
find_max_clk_value(const uint32_t clocks[],uint32_t num_clocks)610 static uint32_t find_max_clk_value(const uint32_t clocks[], uint32_t num_clocks)
611 {
612 uint32_t max = 0;
613 int i;
614
615 for (i = 0; i < num_clocks; ++i) {
616 if (clocks[i] > max)
617 max = clocks[i];
618 }
619
620 return max;
621 }
622
is_valid_clock_value(uint32_t clock_value)623 static inline bool is_valid_clock_value(uint32_t clock_value)
624 {
625 return clock_value > 1 && clock_value < 100000;
626 }
627
convert_wck_ratio(uint8_t wck_ratio)628 static unsigned int convert_wck_ratio(uint8_t wck_ratio)
629 {
630 switch (wck_ratio) {
631 case WCK_RATIO_1_2:
632 return 2;
633
634 case WCK_RATIO_1_4:
635 return 4;
636 /* Find lowest DPM, FCLK is filled in reverse order*/
637
638 default:
639 break;
640 }
641
642 return 1;
643 }
644
calc_dram_speed_mts(const MemPstateTable_t * entry)645 static inline uint32_t calc_dram_speed_mts(const MemPstateTable_t *entry)
646 {
647 return entry->UClk * convert_wck_ratio(entry->WckRatio) * 2;
648 }
649
dcn35_clk_mgr_helper_populate_bw_params(struct clk_mgr_internal * clk_mgr,struct integrated_info * bios_info,DpmClocks_t_dcn35 * clock_table)650 static void dcn35_clk_mgr_helper_populate_bw_params(struct clk_mgr_internal *clk_mgr,
651 struct integrated_info *bios_info,
652 DpmClocks_t_dcn35 *clock_table)
653 {
654 struct clk_bw_params *bw_params = clk_mgr->base.bw_params;
655 struct clk_limit_table_entry def_max = bw_params->clk_table.entries[bw_params->clk_table.num_entries - 1];
656 uint32_t max_fclk = 0, min_pstate = 0, max_dispclk = 0, max_dppclk = 0;
657 uint32_t max_pstate = 0, max_dram_speed_mts = 0, min_dram_speed_mts = 0;
658 uint32_t num_memps, num_fclk, num_dcfclk;
659 int i;
660
661 /* Determine min/max p-state values. */
662 num_memps = (clock_table->NumMemPstatesEnabled > NUM_MEM_PSTATE_LEVELS) ? NUM_MEM_PSTATE_LEVELS :
663 clock_table->NumMemPstatesEnabled;
664 for (i = 0; i < num_memps; i++) {
665 uint32_t dram_speed_mts = calc_dram_speed_mts(&clock_table->MemPstateTable[i]);
666
667 if (is_valid_clock_value(dram_speed_mts) && dram_speed_mts > max_dram_speed_mts) {
668 max_dram_speed_mts = dram_speed_mts;
669 max_pstate = i;
670 }
671 }
672
673 min_dram_speed_mts = max_dram_speed_mts;
674 min_pstate = max_pstate;
675
676 for (i = 0; i < num_memps; i++) {
677 uint32_t dram_speed_mts = calc_dram_speed_mts(&clock_table->MemPstateTable[i]);
678
679 if (is_valid_clock_value(dram_speed_mts) && dram_speed_mts < min_dram_speed_mts) {
680 min_dram_speed_mts = dram_speed_mts;
681 min_pstate = i;
682 }
683 }
684
685 /* We expect the table to contain at least one valid P-state entry. */
686 ASSERT(clock_table->NumMemPstatesEnabled &&
687 is_valid_clock_value(max_dram_speed_mts) &&
688 is_valid_clock_value(min_dram_speed_mts));
689
690 /* dispclk and dppclk can be max at any voltage, same number of levels for both */
691 if (clock_table->NumDispClkLevelsEnabled <= NUM_DISPCLK_DPM_LEVELS &&
692 clock_table->NumDispClkLevelsEnabled <= NUM_DPPCLK_DPM_LEVELS) {
693 max_dispclk = find_max_clk_value(clock_table->DispClocks,
694 clock_table->NumDispClkLevelsEnabled);
695 max_dppclk = find_max_clk_value(clock_table->DppClocks,
696 clock_table->NumDispClkLevelsEnabled);
697 } else {
698 /* Invalid number of entries in the table from PMFW. */
699 ASSERT(0);
700 }
701
702 /* Base the clock table on dcfclk, need at least one entry regardless of pmfw table */
703 ASSERT(clock_table->NumDcfClkLevelsEnabled > 0);
704
705 num_fclk = (clock_table->NumFclkLevelsEnabled > NUM_FCLK_DPM_LEVELS) ? NUM_FCLK_DPM_LEVELS :
706 clock_table->NumFclkLevelsEnabled;
707 max_fclk = find_max_clk_value(clock_table->FclkClocks_Freq, num_fclk);
708
709 num_dcfclk = (clock_table->NumFclkLevelsEnabled > NUM_DCFCLK_DPM_LEVELS) ? NUM_DCFCLK_DPM_LEVELS :
710 clock_table->NumDcfClkLevelsEnabled;
711 for (i = 0; i < num_dcfclk; i++) {
712 int j;
713
714 /* First search defaults for the clocks we don't read using closest lower or equal default dcfclk */
715 for (j = bw_params->clk_table.num_entries - 1; j > 0; j--)
716 if (bw_params->clk_table.entries[j].dcfclk_mhz <= clock_table->DcfClocks[i])
717 break;
718
719 bw_params->clk_table.entries[i].phyclk_mhz = bw_params->clk_table.entries[j].phyclk_mhz;
720 bw_params->clk_table.entries[i].phyclk_d18_mhz = bw_params->clk_table.entries[j].phyclk_d18_mhz;
721 bw_params->clk_table.entries[i].dtbclk_mhz = bw_params->clk_table.entries[j].dtbclk_mhz;
722
723 /* Now update clocks we do read */
724 bw_params->clk_table.entries[i].memclk_mhz = clock_table->MemPstateTable[min_pstate].MemClk;
725 bw_params->clk_table.entries[i].voltage = clock_table->MemPstateTable[min_pstate].Voltage;
726 bw_params->clk_table.entries[i].dcfclk_mhz = clock_table->DcfClocks[i];
727 bw_params->clk_table.entries[i].socclk_mhz = clock_table->SocClocks[i];
728 bw_params->clk_table.entries[i].dispclk_mhz = max_dispclk;
729 bw_params->clk_table.entries[i].dppclk_mhz = max_dppclk;
730 bw_params->clk_table.entries[i].wck_ratio =
731 convert_wck_ratio(clock_table->MemPstateTable[min_pstate].WckRatio);
732
733 /* Dcfclk and Fclk are tied, but at a different ratio */
734 bw_params->clk_table.entries[i].fclk_mhz = min(max_fclk, 2 * clock_table->DcfClocks[i]);
735 }
736
737 /* Make sure to include at least one entry at highest pstate */
738 if (max_pstate != min_pstate || i == 0) {
739 if (i > MAX_NUM_DPM_LVL - 1)
740 i = MAX_NUM_DPM_LVL - 1;
741
742 bw_params->clk_table.entries[i].fclk_mhz = max_fclk;
743 bw_params->clk_table.entries[i].memclk_mhz = clock_table->MemPstateTable[max_pstate].MemClk;
744 bw_params->clk_table.entries[i].voltage = clock_table->MemPstateTable[max_pstate].Voltage;
745 bw_params->clk_table.entries[i].dcfclk_mhz =
746 find_max_clk_value(clock_table->DcfClocks, NUM_DCFCLK_DPM_LEVELS);
747 bw_params->clk_table.entries[i].socclk_mhz =
748 find_max_clk_value(clock_table->SocClocks, NUM_SOCCLK_DPM_LEVELS);
749 bw_params->clk_table.entries[i].dispclk_mhz = max_dispclk;
750 bw_params->clk_table.entries[i].dppclk_mhz = max_dppclk;
751 bw_params->clk_table.entries[i].wck_ratio = convert_wck_ratio(
752 clock_table->MemPstateTable[max_pstate].WckRatio);
753 i++;
754 }
755 bw_params->clk_table.num_entries = i--;
756
757 /* Make sure all highest clocks are included*/
758 bw_params->clk_table.entries[i].socclk_mhz =
759 find_max_clk_value(clock_table->SocClocks, NUM_SOCCLK_DPM_LEVELS);
760 bw_params->clk_table.entries[i].dispclk_mhz =
761 find_max_clk_value(clock_table->DispClocks, NUM_DISPCLK_DPM_LEVELS);
762 bw_params->clk_table.entries[i].dppclk_mhz =
763 find_max_clk_value(clock_table->DppClocks, NUM_DPPCLK_DPM_LEVELS);
764 bw_params->clk_table.entries[i].fclk_mhz =
765 find_max_clk_value(clock_table->FclkClocks_Freq, NUM_FCLK_DPM_LEVELS);
766 ASSERT(clock_table->DcfClocks[i] == find_max_clk_value(clock_table->DcfClocks, NUM_DCFCLK_DPM_LEVELS));
767 bw_params->clk_table.entries[i].phyclk_mhz = def_max.phyclk_mhz;
768 bw_params->clk_table.entries[i].phyclk_d18_mhz = def_max.phyclk_d18_mhz;
769 bw_params->clk_table.entries[i].dtbclk_mhz = def_max.dtbclk_mhz;
770 bw_params->clk_table.num_entries_per_clk.num_dcfclk_levels = clock_table->NumDcfClkLevelsEnabled;
771 bw_params->clk_table.num_entries_per_clk.num_dispclk_levels = clock_table->NumDispClkLevelsEnabled;
772 bw_params->clk_table.num_entries_per_clk.num_dppclk_levels = clock_table->NumDispClkLevelsEnabled;
773 bw_params->clk_table.num_entries_per_clk.num_fclk_levels = clock_table->NumFclkLevelsEnabled;
774 bw_params->clk_table.num_entries_per_clk.num_memclk_levels = clock_table->NumMemPstatesEnabled;
775 bw_params->clk_table.num_entries_per_clk.num_socclk_levels = clock_table->NumSocClkLevelsEnabled;
776
777 /*
778 * Set any 0 clocks to max default setting. Not an issue for
779 * power since we aren't doing switching in such case anyway
780 */
781 for (i = 0; i < bw_params->clk_table.num_entries; i++) {
782 if (!bw_params->clk_table.entries[i].fclk_mhz) {
783 bw_params->clk_table.entries[i].fclk_mhz = def_max.fclk_mhz;
784 bw_params->clk_table.entries[i].memclk_mhz = def_max.memclk_mhz;
785 bw_params->clk_table.entries[i].voltage = def_max.voltage;
786 }
787 if (!bw_params->clk_table.entries[i].dcfclk_mhz)
788 bw_params->clk_table.entries[i].dcfclk_mhz = def_max.dcfclk_mhz;
789 if (!bw_params->clk_table.entries[i].socclk_mhz)
790 bw_params->clk_table.entries[i].socclk_mhz = def_max.socclk_mhz;
791 if (!bw_params->clk_table.entries[i].dispclk_mhz)
792 bw_params->clk_table.entries[i].dispclk_mhz = def_max.dispclk_mhz;
793 if (!bw_params->clk_table.entries[i].dppclk_mhz)
794 bw_params->clk_table.entries[i].dppclk_mhz = def_max.dppclk_mhz;
795 if (!bw_params->clk_table.entries[i].fclk_mhz)
796 bw_params->clk_table.entries[i].fclk_mhz = def_max.fclk_mhz;
797 if (!bw_params->clk_table.entries[i].phyclk_mhz)
798 bw_params->clk_table.entries[i].phyclk_mhz = def_max.phyclk_mhz;
799 if (!bw_params->clk_table.entries[i].phyclk_d18_mhz)
800 bw_params->clk_table.entries[i].phyclk_d18_mhz = def_max.phyclk_d18_mhz;
801 if (!bw_params->clk_table.entries[i].dtbclk_mhz)
802 bw_params->clk_table.entries[i].dtbclk_mhz = def_max.dtbclk_mhz;
803 }
804 ASSERT(bw_params->clk_table.entries[i-1].dcfclk_mhz);
805 bw_params->vram_type = bios_info->memory_type;
806 bw_params->dram_channel_width_bytes = bios_info->memory_type == 0x22 ? 8 : 4;
807 bw_params->num_channels = bios_info->ma_channel_number ? bios_info->ma_channel_number : 4;
808
809 for (i = 0; i < WM_SET_COUNT; i++) {
810 bw_params->wm_table.entries[i].wm_inst = i;
811
812 if (i >= bw_params->clk_table.num_entries) {
813 bw_params->wm_table.entries[i].valid = false;
814 continue;
815 }
816
817 bw_params->wm_table.entries[i].wm_type = WM_TYPE_PSTATE_CHG;
818 bw_params->wm_table.entries[i].valid = true;
819 }
820 }
821
dcn35_set_low_power_state(struct clk_mgr * clk_mgr_base)822 static void dcn35_set_low_power_state(struct clk_mgr *clk_mgr_base)
823 {
824 int display_count;
825 struct dc *dc = clk_mgr_base->ctx->dc;
826 struct dc_state *context = dc->current_state;
827
828 if (clk_mgr_base->clks.pwr_state != DCN_PWR_STATE_LOW_POWER) {
829 display_count = dcn35_get_active_display_cnt_wa(dc, context, NULL);
830 /* if we can go lower, go lower */
831 if (display_count == 0)
832 clk_mgr_base->clks.pwr_state = DCN_PWR_STATE_LOW_POWER;
833 }
834 }
835
dcn35_set_idle_state(struct clk_mgr * clk_mgr_base,bool allow_idle)836 static void dcn35_set_idle_state(struct clk_mgr *clk_mgr_base, bool allow_idle)
837 {
838 struct clk_mgr_internal *clk_mgr = TO_CLK_MGR_INTERNAL(clk_mgr_base);
839 struct dc *dc = clk_mgr_base->ctx->dc;
840 uint32_t val = dcn35_smu_read_ips_scratch(clk_mgr);
841
842 if (dc->config.disable_ips == DMUB_IPS_ENABLE ||
843 dc->config.disable_ips == DMUB_IPS_DISABLE_DYNAMIC) {
844 val = val & ~DMUB_IPS1_ALLOW_MASK;
845 val = val & ~DMUB_IPS2_ALLOW_MASK;
846 } else if (dc->config.disable_ips == DMUB_IPS_DISABLE_IPS1) {
847 val |= DMUB_IPS1_ALLOW_MASK;
848 val |= DMUB_IPS2_ALLOW_MASK;
849 } else if (dc->config.disable_ips == DMUB_IPS_DISABLE_IPS2) {
850 val = val & ~DMUB_IPS1_ALLOW_MASK;
851 val |= DMUB_IPS2_ALLOW_MASK;
852 } else if (dc->config.disable_ips == DMUB_IPS_DISABLE_IPS2_Z10) {
853 val = val & ~DMUB_IPS1_ALLOW_MASK;
854 val = val & ~DMUB_IPS2_ALLOW_MASK;
855 }
856
857 if (!allow_idle) {
858 val |= DMUB_IPS1_ALLOW_MASK;
859 val |= DMUB_IPS2_ALLOW_MASK;
860 }
861
862 dcn35_smu_write_ips_scratch(clk_mgr, val);
863 }
864
dcn35_exit_low_power_state(struct clk_mgr * clk_mgr_base)865 static void dcn35_exit_low_power_state(struct clk_mgr *clk_mgr_base)
866 {
867 struct clk_mgr_internal *clk_mgr = TO_CLK_MGR_INTERNAL(clk_mgr_base);
868
869 //SMU optimization is performed part of low power state exit.
870 dcn35_smu_exit_low_power_state(clk_mgr);
871
872 }
873
dcn35_is_ips_supported(struct clk_mgr * clk_mgr_base)874 static bool dcn35_is_ips_supported(struct clk_mgr *clk_mgr_base)
875 {
876 struct clk_mgr_internal *clk_mgr = TO_CLK_MGR_INTERNAL(clk_mgr_base);
877 bool ips_supported = true;
878
879 ips_supported = dcn35_smu_get_ips_supported(clk_mgr) ? true : false;
880
881 return ips_supported;
882 }
883
dcn35_get_idle_state(struct clk_mgr * clk_mgr_base)884 static uint32_t dcn35_get_idle_state(struct clk_mgr *clk_mgr_base)
885 {
886 struct clk_mgr_internal *clk_mgr = TO_CLK_MGR_INTERNAL(clk_mgr_base);
887
888 return dcn35_smu_read_ips_scratch(clk_mgr);
889 }
890
dcn35_init_clocks_fpga(struct clk_mgr * clk_mgr)891 static void dcn35_init_clocks_fpga(struct clk_mgr *clk_mgr)
892 {
893 dcn35_init_clocks(clk_mgr);
894
895 /* TODO: Implement the functions and remove the ifndef guard */
896 }
897
dcn35_update_clocks_fpga(struct clk_mgr * clk_mgr,struct dc_state * context,bool safe_to_lower)898 static void dcn35_update_clocks_fpga(struct clk_mgr *clk_mgr,
899 struct dc_state *context,
900 bool safe_to_lower)
901 {
902 struct clk_mgr_internal *clk_mgr_int = TO_CLK_MGR_INTERNAL(clk_mgr);
903 struct dc_clocks *new_clocks = &context->bw_ctx.bw.dcn.clk;
904 int fclk_adj = new_clocks->fclk_khz;
905
906 /* TODO: remove this after correctly set by DML */
907 new_clocks->dcfclk_khz = 400000;
908 new_clocks->socclk_khz = 400000;
909
910 /* Min fclk = 1.2GHz since all the extra scemi logic seems to run off of it */
911 //int fclk_adj = new_clocks->fclk_khz > 1200000 ? new_clocks->fclk_khz : 1200000;
912 new_clocks->fclk_khz = 4320000;
913
914 if (should_set_clock(safe_to_lower, new_clocks->phyclk_khz, clk_mgr->clks.phyclk_khz)) {
915 clk_mgr->clks.phyclk_khz = new_clocks->phyclk_khz;
916 }
917
918 if (should_set_clock(safe_to_lower, new_clocks->dcfclk_khz, clk_mgr->clks.dcfclk_khz)) {
919 clk_mgr->clks.dcfclk_khz = new_clocks->dcfclk_khz;
920 }
921
922 if (should_set_clock(safe_to_lower,
923 new_clocks->dcfclk_deep_sleep_khz, clk_mgr->clks.dcfclk_deep_sleep_khz)) {
924 clk_mgr->clks.dcfclk_deep_sleep_khz = new_clocks->dcfclk_deep_sleep_khz;
925 }
926
927 if (should_set_clock(safe_to_lower, new_clocks->socclk_khz, clk_mgr->clks.socclk_khz)) {
928 clk_mgr->clks.socclk_khz = new_clocks->socclk_khz;
929 }
930
931 if (should_set_clock(safe_to_lower, new_clocks->dramclk_khz, clk_mgr->clks.dramclk_khz)) {
932 clk_mgr->clks.dramclk_khz = new_clocks->dramclk_khz;
933 }
934
935 if (should_set_clock(safe_to_lower, new_clocks->dppclk_khz, clk_mgr->clks.dppclk_khz)) {
936 clk_mgr->clks.dppclk_khz = new_clocks->dppclk_khz;
937 }
938
939 if (should_set_clock(safe_to_lower, fclk_adj, clk_mgr->clks.fclk_khz)) {
940 clk_mgr->clks.fclk_khz = fclk_adj;
941 }
942
943 if (should_set_clock(safe_to_lower, new_clocks->dispclk_khz, clk_mgr->clks.dispclk_khz)) {
944 clk_mgr->clks.dispclk_khz = new_clocks->dispclk_khz;
945 }
946
947 /* Both fclk and ref_dppclk run on the same scemi clock.
948 * So take the higher value since the DPP DTO is typically programmed
949 * such that max dppclk is 1:1 with ref_dppclk.
950 */
951 if (clk_mgr->clks.fclk_khz > clk_mgr->clks.dppclk_khz)
952 clk_mgr->clks.dppclk_khz = clk_mgr->clks.fclk_khz;
953 if (clk_mgr->clks.dppclk_khz > clk_mgr->clks.fclk_khz)
954 clk_mgr->clks.fclk_khz = clk_mgr->clks.dppclk_khz;
955
956 // Both fclk and ref_dppclk run on the same scemi clock.
957 clk_mgr_int->dccg->ref_dppclk = clk_mgr->clks.fclk_khz;
958
959 /* TODO: set dtbclk in correct place */
960 clk_mgr->clks.dtbclk_en = true;
961 dm_set_dcn_clocks(clk_mgr->ctx, &clk_mgr->clks);
962 dcn35_update_clocks_update_dpp_dto(clk_mgr_int, context, safe_to_lower);
963
964 dcn35_update_clocks_update_dtb_dto(clk_mgr_int, context, clk_mgr->clks.ref_dtbclk_khz);
965 }
966
967 static struct clk_mgr_funcs dcn35_funcs = {
968 .get_dp_ref_clk_frequency = dce12_get_dp_ref_freq_khz,
969 .get_dtb_ref_clk_frequency = dcn31_get_dtb_ref_freq_khz,
970 .update_clocks = dcn35_update_clocks,
971 .init_clocks = dcn35_init_clocks,
972 .enable_pme_wa = dcn35_enable_pme_wa,
973 .are_clock_states_equal = dcn35_are_clock_states_equal,
974 .notify_wm_ranges = dcn35_notify_wm_ranges,
975 .set_low_power_state = dcn35_set_low_power_state,
976 .exit_low_power_state = dcn35_exit_low_power_state,
977 .is_ips_supported = dcn35_is_ips_supported,
978 .set_idle_state = dcn35_set_idle_state,
979 .get_idle_state = dcn35_get_idle_state
980 };
981
982 struct clk_mgr_funcs dcn35_fpga_funcs = {
983 .get_dp_ref_clk_frequency = dce12_get_dp_ref_freq_khz,
984 .update_clocks = dcn35_update_clocks_fpga,
985 .init_clocks = dcn35_init_clocks_fpga,
986 .get_dtb_ref_clk_frequency = dcn31_get_dtb_ref_freq_khz,
987 };
988
dcn35_clk_mgr_construct(struct dc_context * ctx,struct clk_mgr_dcn35 * clk_mgr,struct pp_smu_funcs * pp_smu,struct dccg * dccg)989 void dcn35_clk_mgr_construct(
990 struct dc_context *ctx,
991 struct clk_mgr_dcn35 *clk_mgr,
992 struct pp_smu_funcs *pp_smu,
993 struct dccg *dccg)
994 {
995 struct dcn35_smu_dpm_clks smu_dpm_clks = { 0 };
996 clk_mgr->base.base.ctx = ctx;
997 clk_mgr->base.base.funcs = &dcn35_funcs;
998
999 clk_mgr->base.pp_smu = pp_smu;
1000
1001 clk_mgr->base.dccg = dccg;
1002 clk_mgr->base.dfs_bypass_disp_clk = 0;
1003
1004 clk_mgr->base.dprefclk_ss_percentage = 0;
1005 clk_mgr->base.dprefclk_ss_divider = 1000;
1006 clk_mgr->base.ss_on_dprefclk = false;
1007 clk_mgr->base.dfs_ref_freq_khz = 48000;
1008
1009 clk_mgr->smu_wm_set.wm_set = (struct dcn35_watermarks *)dm_helpers_allocate_gpu_mem(
1010 clk_mgr->base.base.ctx,
1011 DC_MEM_ALLOC_TYPE_FRAME_BUFFER,
1012 sizeof(struct dcn35_watermarks),
1013 &clk_mgr->smu_wm_set.mc_address.quad_part);
1014
1015 if (!clk_mgr->smu_wm_set.wm_set) {
1016 clk_mgr->smu_wm_set.wm_set = &dummy_wms;
1017 clk_mgr->smu_wm_set.mc_address.quad_part = 0;
1018 }
1019 ASSERT(clk_mgr->smu_wm_set.wm_set);
1020
1021 smu_dpm_clks.dpm_clks = (DpmClocks_t_dcn35 *)dm_helpers_allocate_gpu_mem(
1022 clk_mgr->base.base.ctx,
1023 DC_MEM_ALLOC_TYPE_FRAME_BUFFER,
1024 sizeof(DpmClocks_t_dcn35),
1025 &smu_dpm_clks.mc_address.quad_part);
1026
1027 if (smu_dpm_clks.dpm_clks == NULL) {
1028 smu_dpm_clks.dpm_clks = &dummy_clocks;
1029 smu_dpm_clks.mc_address.quad_part = 0;
1030 }
1031
1032 ASSERT(smu_dpm_clks.dpm_clks);
1033
1034 clk_mgr->base.smu_ver = dcn35_smu_get_smu_version(&clk_mgr->base);
1035
1036 if (clk_mgr->base.smu_ver)
1037 clk_mgr->base.smu_present = true;
1038
1039 /* TODO: Check we get what we expect during bringup */
1040 clk_mgr->base.base.dentist_vco_freq_khz = get_vco_frequency_from_reg(&clk_mgr->base);
1041
1042 if (ctx->dc_bios->integrated_info->memory_type == LpDdr5MemType) {
1043 dcn35_bw_params.wm_table = lpddr5_wm_table;
1044 } else {
1045 dcn35_bw_params.wm_table = ddr5_wm_table;
1046 }
1047 /* Saved clocks configured at boot for debug purposes */
1048 dcn35_dump_clk_registers(&clk_mgr->base.base.boot_snapshot, clk_mgr);
1049
1050 clk_mgr->base.base.dprefclk_khz = dcn35_smu_get_dprefclk(&clk_mgr->base);
1051 clk_mgr->base.base.clks.ref_dtbclk_khz = 600000;
1052
1053 dce_clock_read_ss_info(&clk_mgr->base);
1054 /*when clk src is from FCH, it could have ss, same clock src as DPREF clk*/
1055
1056 clk_mgr->base.base.bw_params = &dcn35_bw_params;
1057
1058 if (clk_mgr->base.base.ctx->dc->debug.pstate_enabled) {
1059 int i;
1060 dcn35_get_dpm_table_from_smu(&clk_mgr->base, &smu_dpm_clks);
1061 DC_LOG_SMU("NumDcfClkLevelsEnabled: %d\n"
1062 "NumDispClkLevelsEnabled: %d\n"
1063 "NumSocClkLevelsEnabled: %d\n"
1064 "VcnClkLevelsEnabled: %d\n"
1065 "FClkLevelsEnabled: %d\n"
1066 "NumMemPstatesEnabled: %d\n"
1067 "MinGfxClk: %d\n"
1068 "MaxGfxClk: %d\n",
1069 smu_dpm_clks.dpm_clks->NumDcfClkLevelsEnabled,
1070 smu_dpm_clks.dpm_clks->NumDispClkLevelsEnabled,
1071 smu_dpm_clks.dpm_clks->NumSocClkLevelsEnabled,
1072 smu_dpm_clks.dpm_clks->VcnClkLevelsEnabled,
1073 smu_dpm_clks.dpm_clks->NumFclkLevelsEnabled,
1074 smu_dpm_clks.dpm_clks->NumMemPstatesEnabled,
1075 smu_dpm_clks.dpm_clks->MinGfxClk,
1076 smu_dpm_clks.dpm_clks->MaxGfxClk);
1077 for (i = 0; i < smu_dpm_clks.dpm_clks->NumDcfClkLevelsEnabled; i++) {
1078 DC_LOG_SMU("smu_dpm_clks.dpm_clks->DcfClocks[%d] = %d\n",
1079 i,
1080 smu_dpm_clks.dpm_clks->DcfClocks[i]);
1081 }
1082 for (i = 0; i < smu_dpm_clks.dpm_clks->NumDispClkLevelsEnabled; i++) {
1083 DC_LOG_SMU("smu_dpm_clks.dpm_clks->DispClocks[%d] = %d\n",
1084 i, smu_dpm_clks.dpm_clks->DispClocks[i]);
1085 }
1086 for (i = 0; i < smu_dpm_clks.dpm_clks->NumSocClkLevelsEnabled; i++) {
1087 DC_LOG_SMU("smu_dpm_clks.dpm_clks->SocClocks[%d] = %d\n",
1088 i, smu_dpm_clks.dpm_clks->SocClocks[i]);
1089 }
1090 for (i = 0; i < smu_dpm_clks.dpm_clks->NumFclkLevelsEnabled; i++) {
1091 DC_LOG_SMU("smu_dpm_clks.dpm_clks->FclkClocks_Freq[%d] = %d\n",
1092 i, smu_dpm_clks.dpm_clks->FclkClocks_Freq[i]);
1093 DC_LOG_SMU("smu_dpm_clks.dpm_clks->FclkClocks_Voltage[%d] = %d\n",
1094 i, smu_dpm_clks.dpm_clks->FclkClocks_Voltage[i]);
1095 }
1096 for (i = 0; i < smu_dpm_clks.dpm_clks->NumSocClkLevelsEnabled; i++)
1097 DC_LOG_SMU("smu_dpm_clks.dpm_clks->SocVoltage[%d] = %d\n",
1098 i, smu_dpm_clks.dpm_clks->SocVoltage[i]);
1099
1100 for (i = 0; i < smu_dpm_clks.dpm_clks->NumMemPstatesEnabled; i++) {
1101 DC_LOG_SMU("smu_dpm_clks.dpm_clks.MemPstateTable[%d].UClk = %d\n"
1102 "smu_dpm_clks.dpm_clks->MemPstateTable[%d].MemClk= %d\n"
1103 "smu_dpm_clks.dpm_clks->MemPstateTable[%d].Voltage = %d\n",
1104 i, smu_dpm_clks.dpm_clks->MemPstateTable[i].UClk,
1105 i, smu_dpm_clks.dpm_clks->MemPstateTable[i].MemClk,
1106 i, smu_dpm_clks.dpm_clks->MemPstateTable[i].Voltage);
1107 }
1108
1109 if (ctx->dc_bios && ctx->dc_bios->integrated_info && ctx->dc->config.use_default_clock_table == false) {
1110 dcn35_clk_mgr_helper_populate_bw_params(
1111 &clk_mgr->base,
1112 ctx->dc_bios->integrated_info,
1113 smu_dpm_clks.dpm_clks);
1114 }
1115 }
1116
1117 if (smu_dpm_clks.dpm_clks && smu_dpm_clks.mc_address.quad_part != 0)
1118 dm_helpers_free_gpu_mem(clk_mgr->base.base.ctx, DC_MEM_ALLOC_TYPE_FRAME_BUFFER,
1119 smu_dpm_clks.dpm_clks);
1120
1121 if (ctx->dc->config.disable_ips != DMUB_IPS_DISABLE_ALL) {
1122 bool ips_support = false;
1123
1124 /*avoid call pmfw at init*/
1125 ips_support = dcn35_smu_get_ips_supported(&clk_mgr->base);
1126 if (ips_support) {
1127 ctx->dc->debug.ignore_pg = false;
1128 ctx->dc->debug.disable_dpp_power_gate = false;
1129 ctx->dc->debug.disable_hubp_power_gate = false;
1130 ctx->dc->debug.disable_dsc_power_gate = false;
1131 } else {
1132 /*let's reset the config control flag*/
1133 ctx->dc->config.disable_ips = DMUB_IPS_DISABLE_ALL; /*pmfw not support it, disable it all*/
1134 }
1135 }
1136 }
1137
dcn35_clk_mgr_destroy(struct clk_mgr_internal * clk_mgr_int)1138 void dcn35_clk_mgr_destroy(struct clk_mgr_internal *clk_mgr_int)
1139 {
1140 struct clk_mgr_dcn35 *clk_mgr = TO_CLK_MGR_DCN35(clk_mgr_int);
1141
1142 if (clk_mgr->smu_wm_set.wm_set && clk_mgr->smu_wm_set.mc_address.quad_part != 0)
1143 dm_helpers_free_gpu_mem(clk_mgr_int->base.ctx, DC_MEM_ALLOC_TYPE_FRAME_BUFFER,
1144 clk_mgr->smu_wm_set.wm_set);
1145 }
1146