1 /*
2 * Copyright 2022 Advanced Micro Devices, Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
21 *
22 * Authors: AMD
23 *
24 */
25
26
27 #include "dcn35_clk_mgr.h"
28
29 #include "dccg.h"
30 #include "clk_mgr_internal.h"
31
32 // For dce12_get_dp_ref_freq_khz
33 #include "dce100/dce_clk_mgr.h"
34
35 // For dcn20_update_clocks_update_dpp_dto
36 #include "dcn20/dcn20_clk_mgr.h"
37
38
39 #include "reg_helper.h"
40 #include "core_types.h"
41 #include "dcn35_smu.h"
42 #include "dm_helpers.h"
43
44 #include "dcn31/dcn31_clk_mgr.h"
45
46 #include "dc_dmub_srv.h"
47 #include "link.h"
48 #include "logger_types.h"
49
50 #undef DC_LOGGER
51 #define DC_LOGGER \
52 clk_mgr->base.base.ctx->logger
53
54 #define DCN_BASE__INST0_SEG1 0x000000C0
55 #define mmCLK1_CLK_PLL_REQ 0x16E37
56
57 #define mmCLK1_CLK0_DFS_CNTL 0x16E69
58 #define mmCLK1_CLK1_DFS_CNTL 0x16E6C
59 #define mmCLK1_CLK2_DFS_CNTL 0x16E6F
60 #define mmCLK1_CLK3_DFS_CNTL 0x16E72
61 #define mmCLK1_CLK4_DFS_CNTL 0x16E75
62 #define mmCLK1_CLK5_DFS_CNTL 0x16E78
63
64 #define mmCLK1_CLK0_CURRENT_CNT 0x16EFB
65 #define mmCLK1_CLK1_CURRENT_CNT 0x16EFC
66 #define mmCLK1_CLK2_CURRENT_CNT 0x16EFD
67 #define mmCLK1_CLK3_CURRENT_CNT 0x16EFE
68 #define mmCLK1_CLK4_CURRENT_CNT 0x16EFF
69 #define mmCLK1_CLK5_CURRENT_CNT 0x16F00
70
71 #define mmCLK1_CLK0_BYPASS_CNTL 0x16E8A
72 #define mmCLK1_CLK1_BYPASS_CNTL 0x16E93
73 #define mmCLK1_CLK2_BYPASS_CNTL 0x16E9C
74 #define mmCLK1_CLK3_BYPASS_CNTL 0x16EA5
75 #define mmCLK1_CLK4_BYPASS_CNTL 0x16EAE
76 #define mmCLK1_CLK5_BYPASS_CNTL 0x16EB7
77
78 #define mmCLK1_CLK0_DS_CNTL 0x16E83
79 #define mmCLK1_CLK1_DS_CNTL 0x16E8C
80 #define mmCLK1_CLK2_DS_CNTL 0x16E95
81 #define mmCLK1_CLK3_DS_CNTL 0x16E9E
82 #define mmCLK1_CLK4_DS_CNTL 0x16EA7
83 #define mmCLK1_CLK5_DS_CNTL 0x16EB0
84
85 #define mmCLK1_CLK0_ALLOW_DS 0x16E84
86 #define mmCLK1_CLK1_ALLOW_DS 0x16E8D
87 #define mmCLK1_CLK2_ALLOW_DS 0x16E96
88 #define mmCLK1_CLK3_ALLOW_DS 0x16E9F
89 #define mmCLK1_CLK4_ALLOW_DS 0x16EA8
90 #define mmCLK1_CLK5_ALLOW_DS 0x16EB1
91
92 #define mmCLK5_spll_field_8 0x1B24B
93 #define mmDENTIST_DISPCLK_CNTL 0x0124
94 #define regDENTIST_DISPCLK_CNTL 0x0064
95 #define regDENTIST_DISPCLK_CNTL_BASE_IDX 1
96
97 #define CLK1_CLK_PLL_REQ__FbMult_int__SHIFT 0x0
98 #define CLK1_CLK_PLL_REQ__PllSpineDiv__SHIFT 0xc
99 #define CLK1_CLK_PLL_REQ__FbMult_frac__SHIFT 0x10
100 #define CLK1_CLK_PLL_REQ__FbMult_int_MASK 0x000001FFL
101 #define CLK1_CLK_PLL_REQ__PllSpineDiv_MASK 0x0000F000L
102 #define CLK1_CLK_PLL_REQ__FbMult_frac_MASK 0xFFFF0000L
103
104 #define CLK1_CLK2_BYPASS_CNTL__CLK2_BYPASS_SEL_MASK 0x00000007L
105 #define CLK1_CLK2_BYPASS_CNTL__CLK2_BYPASS_DIV_MASK 0x000F0000L
106 // DENTIST_DISPCLK_CNTL
107 #define DENTIST_DISPCLK_CNTL__DENTIST_DISPCLK_WDIVIDER__SHIFT 0x0
108 #define DENTIST_DISPCLK_CNTL__DENTIST_DISPCLK_RDIVIDER__SHIFT 0x8
109 #define DENTIST_DISPCLK_CNTL__DENTIST_DISPCLK_CHG_DONE__SHIFT 0x13
110 #define DENTIST_DISPCLK_CNTL__DENTIST_DPPCLK_CHG_DONE__SHIFT 0x14
111 #define DENTIST_DISPCLK_CNTL__DENTIST_DPPCLK_WDIVIDER__SHIFT 0x18
112 #define DENTIST_DISPCLK_CNTL__DENTIST_DISPCLK_WDIVIDER_MASK 0x0000007FL
113 #define DENTIST_DISPCLK_CNTL__DENTIST_DISPCLK_RDIVIDER_MASK 0x00007F00L
114 #define DENTIST_DISPCLK_CNTL__DENTIST_DISPCLK_CHG_DONE_MASK 0x00080000L
115 #define DENTIST_DISPCLK_CNTL__DENTIST_DPPCLK_CHG_DONE_MASK 0x00100000L
116 #define DENTIST_DISPCLK_CNTL__DENTIST_DPPCLK_WDIVIDER_MASK 0x7F000000L
117
118 #define CLK5_spll_field_8__spll_ssc_en_MASK 0x00002000L
119
120 #define SMU_VER_THRESHOLD 0x5D4A00 //93.74.0
121 #undef FN
122 #define FN(reg_name, field_name) \
123 clk_mgr->clk_mgr_shift->field_name, clk_mgr->clk_mgr_mask->field_name
124
125 #define REG(reg) \
126 (clk_mgr->regs->reg)
127
128 #define BASE_INNER(seg) DCN_BASE__INST0_SEG ## seg
129
130 #define BASE(seg) BASE_INNER(seg)
131
132 #define SR(reg_name)\
133 .reg_name = BASE(reg ## reg_name ## _BASE_IDX) + \
134 reg ## reg_name
135
136 #define CLK_SR_DCN35(reg_name)\
137 .reg_name = mm ## reg_name
138
139 static const struct clk_mgr_registers clk_mgr_regs_dcn35 = {
140 CLK_REG_LIST_DCN35()
141 };
142
143 static const struct clk_mgr_shift clk_mgr_shift_dcn35 = {
144 CLK_COMMON_MASK_SH_LIST_DCN32(__SHIFT)
145 };
146
147 static const struct clk_mgr_mask clk_mgr_mask_dcn35 = {
148 CLK_COMMON_MASK_SH_LIST_DCN32(_MASK)
149 };
150
151 #define TO_CLK_MGR_DCN35(clk_mgr)\
152 container_of(clk_mgr, struct clk_mgr_dcn35, base)
153
dcn35_get_active_display_cnt_wa(struct dc * dc,struct dc_state * context,int * all_active_disps)154 static int dcn35_get_active_display_cnt_wa(
155 struct dc *dc,
156 struct dc_state *context,
157 int *all_active_disps)
158 {
159 int i, display_count = 0;
160 bool tmds_present = false;
161
162 for (i = 0; i < context->stream_count; i++) {
163 const struct dc_stream_state *stream = context->streams[i];
164
165 if (stream->signal == SIGNAL_TYPE_HDMI_TYPE_A ||
166 stream->signal == SIGNAL_TYPE_DVI_SINGLE_LINK ||
167 stream->signal == SIGNAL_TYPE_DVI_DUAL_LINK)
168 tmds_present = true;
169 }
170
171 for (i = 0; i < dc->link_count; i++) {
172 const struct dc_link *link = dc->links[i];
173
174 /* abusing the fact that the dig and phy are coupled to see if the phy is enabled */
175 if (link->link_enc && link->link_enc->funcs->is_dig_enabled &&
176 link->link_enc->funcs->is_dig_enabled(link->link_enc))
177 display_count++;
178 }
179 if (all_active_disps != NULL)
180 *all_active_disps = display_count;
181 /* WA for hang on HDMI after display off back on*/
182 if (display_count == 0 && tmds_present)
183 display_count = 1;
184
185 return display_count;
186 }
dcn35_disable_otg_wa(struct clk_mgr * clk_mgr_base,struct dc_state * context,bool safe_to_lower,bool disable)187 static void dcn35_disable_otg_wa(struct clk_mgr *clk_mgr_base, struct dc_state *context,
188 bool safe_to_lower, bool disable)
189 {
190 struct dc *dc = clk_mgr_base->ctx->dc;
191 int i;
192
193 if (dc->ctx->dce_environment == DCE_ENV_DIAG)
194 return;
195
196 for (i = 0; i < dc->res_pool->pipe_count; ++i) {
197 struct pipe_ctx *old_pipe = &dc->current_state->res_ctx.pipe_ctx[i];
198 struct pipe_ctx *new_pipe = &context->res_ctx.pipe_ctx[i];
199 struct clk_mgr_internal *clk_mgr_internal = TO_CLK_MGR_INTERNAL(clk_mgr_base);
200 struct dccg *dccg = clk_mgr_internal->dccg;
201 struct pipe_ctx *pipe = safe_to_lower
202 ? &context->res_ctx.pipe_ctx[i]
203 : &dc->current_state->res_ctx.pipe_ctx[i];
204 struct link_encoder *new_pipe_link_enc = new_pipe->link_res.dio_link_enc;
205 struct link_encoder *pipe_link_enc = pipe->link_res.dio_link_enc;
206 bool stream_changed_otg_dig_on = false;
207 bool has_active_hpo = false;
208
209 if (pipe->top_pipe || pipe->prev_odm_pipe)
210 continue;
211
212 if (!dc->config.unify_link_enc_assignment) {
213 if (new_pipe->stream)
214 new_pipe_link_enc = new_pipe->stream->link_enc;
215 if (pipe->stream)
216 pipe_link_enc = pipe->stream->link_enc;
217 }
218
219 stream_changed_otg_dig_on = old_pipe->stream && new_pipe->stream &&
220 old_pipe->stream != new_pipe->stream &&
221 old_pipe->stream_res.tg == new_pipe->stream_res.tg &&
222 new_pipe_link_enc && !new_pipe->stream->dpms_off &&
223 new_pipe_link_enc->funcs->is_dig_enabled &&
224 new_pipe_link_enc->funcs->is_dig_enabled(
225 new_pipe_link_enc) &&
226 new_pipe->stream_res.stream_enc &&
227 new_pipe->stream_res.stream_enc->funcs->is_fifo_enabled &&
228 new_pipe->stream_res.stream_enc->funcs->is_fifo_enabled(new_pipe->stream_res.stream_enc);
229
230 if (old_pipe->stream && new_pipe->stream && old_pipe->stream == new_pipe->stream) {
231 has_active_hpo = dccg->ctx->dc->link_srv->dp_is_128b_132b_signal(old_pipe) &&
232 dccg->ctx->dc->link_srv->dp_is_128b_132b_signal(new_pipe);
233
234 }
235
236 if (!has_active_hpo && !stream_changed_otg_dig_on && pipe->stream &&
237 (pipe->stream->dpms_off || dc_is_virtual_signal(pipe->stream->signal) || !pipe_link_enc) &&
238 !dccg->ctx->dc->link_srv->dp_is_128b_132b_signal(pipe)) {
239 /* This w/a should not trigger when we have a dig active */
240 if (disable) {
241 if (pipe->stream_res.tg && pipe->stream_res.tg->funcs->immediate_disable_crtc)
242 pipe->stream_res.tg->funcs->immediate_disable_crtc(pipe->stream_res.tg);
243
244 reset_sync_context_for_pipe(dc, context, i);
245 } else {
246 pipe->stream_res.tg->funcs->enable_crtc(pipe->stream_res.tg);
247 }
248 }
249 }
250 }
251
dcn35_update_clocks_update_dtb_dto(struct clk_mgr_internal * clk_mgr,struct dc_state * context,int ref_dtbclk_khz)252 static void dcn35_update_clocks_update_dtb_dto(struct clk_mgr_internal *clk_mgr,
253 struct dc_state *context,
254 int ref_dtbclk_khz)
255 {
256 struct dccg *dccg = clk_mgr->dccg;
257 uint32_t tg_mask = 0;
258 int i;
259
260 for (i = 0; i < clk_mgr->base.ctx->dc->res_pool->pipe_count; i++) {
261 struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[i];
262 struct dtbclk_dto_params dto_params = {0};
263
264 /* use mask to program DTO once per tg */
265 if (pipe_ctx->stream_res.tg &&
266 !(tg_mask & (1 << pipe_ctx->stream_res.tg->inst))) {
267 tg_mask |= (1 << pipe_ctx->stream_res.tg->inst);
268
269 dto_params.otg_inst = pipe_ctx->stream_res.tg->inst;
270 dto_params.ref_dtbclk_khz = ref_dtbclk_khz;
271
272 dccg->funcs->set_dtbclk_dto(clk_mgr->dccg, &dto_params);
273 //dccg->funcs->set_audio_dtbclk_dto(clk_mgr->dccg, &dto_params);
274 }
275 }
276 }
277
dcn35_update_clocks_update_dpp_dto(struct clk_mgr_internal * clk_mgr,struct dc_state * context,bool safe_to_lower)278 static void dcn35_update_clocks_update_dpp_dto(struct clk_mgr_internal *clk_mgr,
279 struct dc_state *context, bool safe_to_lower)
280 {
281 int i;
282 bool dppclk_active[MAX_PIPES] = {0};
283
284
285 clk_mgr->dccg->ref_dppclk = clk_mgr->base.clks.dppclk_khz;
286 for (i = 0; i < clk_mgr->base.ctx->dc->res_pool->pipe_count; i++) {
287 int dpp_inst = 0, dppclk_khz, prev_dppclk_khz;
288
289 dppclk_khz = context->res_ctx.pipe_ctx[i].plane_res.bw.dppclk_khz;
290
291 if (context->res_ctx.pipe_ctx[i].plane_res.dpp)
292 dpp_inst = context->res_ctx.pipe_ctx[i].plane_res.dpp->inst;
293 else if (!context->res_ctx.pipe_ctx[i].plane_res.dpp && dppclk_khz == 0) {
294 /* dpp == NULL && dppclk_khz == 0 is valid because of pipe harvesting.
295 * In this case just continue in loop
296 */
297 continue;
298 } else if (!context->res_ctx.pipe_ctx[i].plane_res.dpp && dppclk_khz > 0) {
299 /* The software state is not valid if dpp resource is NULL and
300 * dppclk_khz > 0.
301 */
302 ASSERT(false);
303 continue;
304 }
305
306 prev_dppclk_khz = clk_mgr->dccg->pipe_dppclk_khz[i];
307
308 if (safe_to_lower || prev_dppclk_khz < dppclk_khz)
309 clk_mgr->dccg->funcs->update_dpp_dto(
310 clk_mgr->dccg, dpp_inst, dppclk_khz);
311 dppclk_active[dpp_inst] = true;
312 }
313 if (safe_to_lower)
314 for (i = 0; i < clk_mgr->base.ctx->dc->res_pool->pipe_count; i++) {
315 struct dpp *old_dpp = clk_mgr->base.ctx->dc->current_state->res_ctx.pipe_ctx[i].plane_res.dpp;
316
317 if (old_dpp && !dppclk_active[old_dpp->inst])
318 clk_mgr->dccg->funcs->update_dpp_dto(clk_mgr->dccg, old_dpp->inst, 0);
319 }
320 }
321
get_lowest_dpia_index(const struct dc_link * link)322 static uint8_t get_lowest_dpia_index(const struct dc_link *link)
323 {
324 const struct dc *dc_struct = link->dc;
325 uint8_t idx = 0xFF;
326 int i;
327
328 for (i = 0; i < MAX_PIPES * 2; ++i) {
329 if (!dc_struct->links[i] || dc_struct->links[i]->ep_type != DISPLAY_ENDPOINT_USB4_DPIA)
330 continue;
331
332 if (idx > dc_struct->links[i]->link_index)
333 idx = dc_struct->links[i]->link_index;
334 }
335
336 return idx;
337 }
338
dcn35_notify_host_router_bw(struct clk_mgr * clk_mgr_base,struct dc_state * context,bool safe_to_lower)339 static void dcn35_notify_host_router_bw(struct clk_mgr *clk_mgr_base, struct dc_state *context,
340 bool safe_to_lower)
341 {
342 struct dc_clocks *new_clocks = &context->bw_ctx.bw.dcn.clk;
343 struct clk_mgr_internal *clk_mgr = TO_CLK_MGR_INTERNAL(clk_mgr_base);
344 uint32_t host_router_bw_kbps[MAX_HOST_ROUTERS_NUM] = { 0 };
345 int i;
346 for (i = 0; i < context->stream_count; ++i) {
347 const struct dc_stream_state *stream = context->streams[i];
348 const struct dc_link *link = stream->link;
349 uint8_t lowest_dpia_index = 0;
350 unsigned int hr_index = 0;
351
352 if (!link)
353 continue;
354
355 lowest_dpia_index = get_lowest_dpia_index(link);
356 if (link->link_index < lowest_dpia_index)
357 continue;
358
359 hr_index = (link->link_index - lowest_dpia_index) / 2;
360 if (hr_index >= MAX_HOST_ROUTERS_NUM)
361 continue;
362 host_router_bw_kbps[hr_index] += dc_bandwidth_in_kbps_from_timing(
363 &stream->timing, dc_link_get_highest_encoding_format(link));
364 }
365
366 for (i = 0; i < MAX_HOST_ROUTERS_NUM; ++i) {
367 new_clocks->host_router_bw_kbps[i] = host_router_bw_kbps[i];
368 if (should_set_clock(safe_to_lower, new_clocks->host_router_bw_kbps[i], clk_mgr_base->clks.host_router_bw_kbps[i])) {
369 clk_mgr_base->clks.host_router_bw_kbps[i] = new_clocks->host_router_bw_kbps[i];
370 dcn35_smu_notify_host_router_bw(clk_mgr, i, new_clocks->host_router_bw_kbps[i]);
371 }
372 }
373 }
374
dcn35_update_clocks(struct clk_mgr * clk_mgr_base,struct dc_state * context,bool safe_to_lower)375 void dcn35_update_clocks(struct clk_mgr *clk_mgr_base,
376 struct dc_state *context,
377 bool safe_to_lower)
378 {
379 union dmub_rb_cmd cmd;
380 struct clk_mgr_internal *clk_mgr = TO_CLK_MGR_INTERNAL(clk_mgr_base);
381 struct dc_clocks *new_clocks = &context->bw_ctx.bw.dcn.clk;
382 struct dc *dc = clk_mgr_base->ctx->dc;
383 int display_count = 0;
384 bool update_dppclk = false;
385 bool update_dispclk = false;
386 bool dpp_clock_lowered = false;
387 int all_active_disps = 0;
388
389 if (dc->work_arounds.skip_clock_update)
390 return;
391
392 display_count = dcn35_get_active_display_cnt_wa(dc, context, &all_active_disps);
393 if (new_clocks->dtbclk_en && !new_clocks->ref_dtbclk_khz)
394 new_clocks->ref_dtbclk_khz = 600000;
395
396 /*
397 * if it is safe to lower, but we are already in the lower state, we don't have to do anything
398 * also if safe to lower is false, we just go in the higher state
399 */
400 if (safe_to_lower) {
401 if (new_clocks->zstate_support != DCN_ZSTATE_SUPPORT_DISALLOW &&
402 new_clocks->zstate_support != clk_mgr_base->clks.zstate_support) {
403 dcn35_smu_set_zstate_support(clk_mgr, new_clocks->zstate_support);
404 dm_helpers_enable_periodic_detection(clk_mgr_base->ctx, true);
405 clk_mgr_base->clks.zstate_support = new_clocks->zstate_support;
406 }
407
408 if (clk_mgr_base->clks.dtbclk_en && !new_clocks->dtbclk_en) {
409 if (clk_mgr->base.ctx->dc->config.allow_0_dtb_clk)
410 dcn35_smu_set_dtbclk(clk_mgr, false);
411
412 clk_mgr_base->clks.dtbclk_en = new_clocks->dtbclk_en;
413 }
414 /* check that we're not already in lower */
415 if (clk_mgr_base->clks.pwr_state != DCN_PWR_STATE_LOW_POWER) {
416 /* if we can go lower, go lower */
417 if (display_count == 0)
418 clk_mgr_base->clks.pwr_state = DCN_PWR_STATE_LOW_POWER;
419 }
420 } else {
421 if (new_clocks->zstate_support == DCN_ZSTATE_SUPPORT_DISALLOW &&
422 new_clocks->zstate_support != clk_mgr_base->clks.zstate_support) {
423 dcn35_smu_set_zstate_support(clk_mgr, DCN_ZSTATE_SUPPORT_DISALLOW);
424 dm_helpers_enable_periodic_detection(clk_mgr_base->ctx, false);
425 clk_mgr_base->clks.zstate_support = new_clocks->zstate_support;
426 }
427
428 if (!clk_mgr_base->clks.dtbclk_en && new_clocks->dtbclk_en) {
429 int actual_dtbclk = 0;
430
431 dcn35_update_clocks_update_dtb_dto(clk_mgr, context, new_clocks->ref_dtbclk_khz);
432 dcn35_smu_set_dtbclk(clk_mgr, true);
433
434 actual_dtbclk = REG_READ(CLK1_CLK4_CURRENT_CNT);
435
436 if (actual_dtbclk) {
437 clk_mgr_base->clks.ref_dtbclk_khz = new_clocks->ref_dtbclk_khz;
438 clk_mgr_base->clks.dtbclk_en = new_clocks->dtbclk_en;
439 }
440 }
441
442 /* check that we're not already in D0 */
443 if (clk_mgr_base->clks.pwr_state != DCN_PWR_STATE_MISSION_MODE) {
444 union display_idle_optimization_u idle_info = { 0 };
445
446 dcn35_smu_set_display_idle_optimization(clk_mgr, idle_info.data);
447 /* update power state */
448 clk_mgr_base->clks.pwr_state = DCN_PWR_STATE_MISSION_MODE;
449 }
450 }
451 if (dc->debug.force_min_dcfclk_mhz > 0)
452 new_clocks->dcfclk_khz = (new_clocks->dcfclk_khz > (dc->debug.force_min_dcfclk_mhz * 1000)) ?
453 new_clocks->dcfclk_khz : (dc->debug.force_min_dcfclk_mhz * 1000);
454
455 if (should_set_clock(safe_to_lower, new_clocks->dcfclk_khz, clk_mgr_base->clks.dcfclk_khz)) {
456 clk_mgr_base->clks.dcfclk_khz = new_clocks->dcfclk_khz;
457 dcn35_smu_set_hard_min_dcfclk(clk_mgr, clk_mgr_base->clks.dcfclk_khz);
458 }
459
460 if (should_set_clock(safe_to_lower,
461 new_clocks->dcfclk_deep_sleep_khz, clk_mgr_base->clks.dcfclk_deep_sleep_khz)) {
462 clk_mgr_base->clks.dcfclk_deep_sleep_khz = new_clocks->dcfclk_deep_sleep_khz;
463 dcn35_smu_set_min_deep_sleep_dcfclk(clk_mgr, clk_mgr_base->clks.dcfclk_deep_sleep_khz);
464 }
465
466 // workaround: Limit dppclk to 100Mhz to avoid lower eDP panel switch to plus 4K monitor underflow.
467 if (new_clocks->dppclk_khz < 100000)
468 new_clocks->dppclk_khz = 100000;
469
470 if (should_set_clock(safe_to_lower, new_clocks->dppclk_khz, clk_mgr->base.clks.dppclk_khz)) {
471 if (clk_mgr->base.clks.dppclk_khz > new_clocks->dppclk_khz)
472 dpp_clock_lowered = true;
473 clk_mgr_base->clks.dppclk_khz = new_clocks->dppclk_khz;
474 update_dppclk = true;
475 }
476
477 if (should_set_clock(safe_to_lower, new_clocks->dispclk_khz, clk_mgr_base->clks.dispclk_khz) &&
478 (new_clocks->dispclk_khz > 0 || (safe_to_lower && display_count == 0))) {
479 int requested_dispclk_khz = new_clocks->dispclk_khz;
480
481 dcn35_disable_otg_wa(clk_mgr_base, context, safe_to_lower, true);
482
483 /* Clamp the requested clock to PMFW based on their limit. */
484 if (dc->debug.min_disp_clk_khz > 0 && requested_dispclk_khz < dc->debug.min_disp_clk_khz)
485 requested_dispclk_khz = dc->debug.min_disp_clk_khz;
486
487 dcn35_smu_set_dispclk(clk_mgr, requested_dispclk_khz);
488 clk_mgr_base->clks.dispclk_khz = new_clocks->dispclk_khz;
489
490 dcn35_disable_otg_wa(clk_mgr_base, context, safe_to_lower, false);
491
492 update_dispclk = true;
493 }
494
495 /* clock limits are received with MHz precision, divide by 1000 to prevent setting clocks at every call */
496 if (!dc->debug.disable_dtb_ref_clk_switch &&
497 should_set_clock(safe_to_lower, new_clocks->ref_dtbclk_khz / 1000,
498 clk_mgr_base->clks.ref_dtbclk_khz / 1000)) {
499 dcn35_update_clocks_update_dtb_dto(clk_mgr, context, new_clocks->ref_dtbclk_khz);
500 clk_mgr_base->clks.ref_dtbclk_khz = new_clocks->ref_dtbclk_khz;
501 }
502
503 if (dpp_clock_lowered) {
504 // increase per DPP DTO before lowering global dppclk
505 dcn35_update_clocks_update_dpp_dto(clk_mgr, context, safe_to_lower);
506 dcn35_smu_set_dppclk(clk_mgr, clk_mgr_base->clks.dppclk_khz);
507 } else {
508 // increase global DPPCLK before lowering per DPP DTO
509 if (update_dppclk || update_dispclk)
510 dcn35_smu_set_dppclk(clk_mgr, clk_mgr_base->clks.dppclk_khz);
511 dcn35_update_clocks_update_dpp_dto(clk_mgr, context, safe_to_lower);
512 }
513
514 // notify PMFW of bandwidth per DPIA tunnel
515 if (dc->debug.notify_dpia_hr_bw)
516 dcn35_notify_host_router_bw(clk_mgr_base, context, safe_to_lower);
517
518 // notify DMCUB of latest clocks
519 memset(&cmd, 0, sizeof(cmd));
520 cmd.notify_clocks.header.type = DMUB_CMD__CLK_MGR;
521 cmd.notify_clocks.header.sub_type = DMUB_CMD__CLK_MGR_NOTIFY_CLOCKS;
522 cmd.notify_clocks.clocks.dcfclk_khz = clk_mgr_base->clks.dcfclk_khz;
523 cmd.notify_clocks.clocks.dcfclk_deep_sleep_khz =
524 clk_mgr_base->clks.dcfclk_deep_sleep_khz;
525 cmd.notify_clocks.clocks.dispclk_khz = clk_mgr_base->clks.dispclk_khz;
526 cmd.notify_clocks.clocks.dppclk_khz = clk_mgr_base->clks.dppclk_khz;
527
528 dc_wake_and_execute_dmub_cmd(dc->ctx, &cmd, DM_DMUB_WAIT_TYPE_WAIT);
529 }
530
get_vco_frequency_from_reg(struct clk_mgr_internal * clk_mgr)531 static int get_vco_frequency_from_reg(struct clk_mgr_internal *clk_mgr)
532 {
533 /* get FbMult value */
534 struct fixed31_32 pll_req;
535 unsigned int fbmult_frac_val = 0;
536 unsigned int fbmult_int_val = 0;
537
538 /*
539 * Register value of fbmult is in 8.16 format, we are converting to 314.32
540 * to leverage the fix point operations available in driver
541 */
542
543 REG_GET(CLK1_CLK_PLL_REQ, FbMult_frac, &fbmult_frac_val); /* 16 bit fractional part*/
544 REG_GET(CLK1_CLK_PLL_REQ, FbMult_int, &fbmult_int_val); /* 8 bit integer part */
545
546 pll_req = dc_fixpt_from_int(fbmult_int_val);
547
548 /*
549 * since fractional part is only 16 bit in register definition but is 32 bit
550 * in our fix point definiton, need to shift left by 16 to obtain correct value
551 */
552 pll_req.value |= fbmult_frac_val << 16;
553
554 /* multiply by REFCLK period */
555 pll_req = dc_fixpt_mul_int(pll_req, clk_mgr->dfs_ref_freq_khz);
556
557 /* integer part is now VCO frequency in kHz */
558 return dc_fixpt_floor(pll_req);
559 }
560
dcn35_enable_pme_wa(struct clk_mgr * clk_mgr_base)561 static void dcn35_enable_pme_wa(struct clk_mgr *clk_mgr_base)
562 {
563 struct clk_mgr_internal *clk_mgr = TO_CLK_MGR_INTERNAL(clk_mgr_base);
564
565 dcn35_smu_enable_pme_wa(clk_mgr);
566 }
567
568
dcn35_are_clock_states_equal(struct dc_clocks * a,struct dc_clocks * b)569 bool dcn35_are_clock_states_equal(struct dc_clocks *a,
570 struct dc_clocks *b)
571 {
572 if (a->dispclk_khz != b->dispclk_khz)
573 return false;
574 else if (a->dppclk_khz != b->dppclk_khz)
575 return false;
576 else if (a->dcfclk_khz != b->dcfclk_khz)
577 return false;
578 else if (a->dcfclk_deep_sleep_khz != b->dcfclk_deep_sleep_khz)
579 return false;
580 else if (a->zstate_support != b->zstate_support)
581 return false;
582 else if (a->dtbclk_en != b->dtbclk_en)
583 return false;
584
585 return true;
586 }
587
dcn35_dump_clk_registers(struct clk_state_registers_and_bypass * regs_and_bypass,struct clk_mgr_dcn35 * clk_mgr)588 static void dcn35_dump_clk_registers(struct clk_state_registers_and_bypass *regs_and_bypass,
589 struct clk_mgr_dcn35 *clk_mgr)
590 {
591 }
592
dcn35_is_spll_ssc_enabled(struct clk_mgr * clk_mgr_base)593 static bool dcn35_is_spll_ssc_enabled(struct clk_mgr *clk_mgr_base)
594 {
595 struct clk_mgr_internal *clk_mgr = TO_CLK_MGR_INTERNAL(clk_mgr_base);
596
597 uint32_t ssc_enable;
598
599 ssc_enable = REG_READ(CLK5_spll_field_8) & CLK5_spll_field_8__spll_ssc_en_MASK;
600
601 return ssc_enable != 0;
602 }
603
init_clk_states(struct clk_mgr * clk_mgr)604 static void init_clk_states(struct clk_mgr *clk_mgr)
605 {
606 uint32_t ref_dtbclk = clk_mgr->clks.ref_dtbclk_khz;
607
608 memset(&(clk_mgr->clks), 0, sizeof(struct dc_clocks));
609
610 clk_mgr->clks.ref_dtbclk_khz = ref_dtbclk; // restore ref_dtbclk
611 clk_mgr->clks.p_state_change_support = true;
612 clk_mgr->clks.prev_p_state_change_support = true;
613 clk_mgr->clks.pwr_state = DCN_PWR_STATE_UNKNOWN;
614 clk_mgr->clks.zstate_support = DCN_ZSTATE_SUPPORT_UNKNOWN;
615 }
616
dcn35_init_clocks(struct clk_mgr * clk_mgr)617 void dcn35_init_clocks(struct clk_mgr *clk_mgr)
618 {
619 struct clk_mgr_internal *clk_mgr_int = TO_CLK_MGR_INTERNAL(clk_mgr);
620
621 init_clk_states(clk_mgr);
622
623 // to adjust dp_dto reference clock if ssc is enable otherwise to apply dprefclk
624 if (dcn35_is_spll_ssc_enabled(clk_mgr))
625 clk_mgr->dp_dto_source_clock_in_khz =
626 dce_adjust_dp_ref_freq_for_ss(clk_mgr_int, clk_mgr->dprefclk_khz);
627 else
628 clk_mgr->dp_dto_source_clock_in_khz = clk_mgr->dprefclk_khz;
629
630 }
631 static struct clk_bw_params dcn35_bw_params = {
632 .vram_type = Ddr4MemType,
633 .num_channels = 1,
634 .clk_table = {
635 .num_entries = 4,
636 },
637
638 };
639
640 static struct wm_table ddr5_wm_table = {
641 .entries = {
642 {
643 .wm_inst = WM_A,
644 .wm_type = WM_TYPE_PSTATE_CHG,
645 .pstate_latency_us = 11.72,
646 .sr_exit_time_us = 28.0,
647 .sr_enter_plus_exit_time_us = 30.0,
648 .valid = true,
649 },
650 {
651 .wm_inst = WM_B,
652 .wm_type = WM_TYPE_PSTATE_CHG,
653 .pstate_latency_us = 11.72,
654 .sr_exit_time_us = 28.0,
655 .sr_enter_plus_exit_time_us = 30.0,
656 .valid = true,
657 },
658 {
659 .wm_inst = WM_C,
660 .wm_type = WM_TYPE_PSTATE_CHG,
661 .pstate_latency_us = 11.72,
662 .sr_exit_time_us = 28.0,
663 .sr_enter_plus_exit_time_us = 30.0,
664 .valid = true,
665 },
666 {
667 .wm_inst = WM_D,
668 .wm_type = WM_TYPE_PSTATE_CHG,
669 .pstate_latency_us = 11.72,
670 .sr_exit_time_us = 28.0,
671 .sr_enter_plus_exit_time_us = 30.0,
672 .valid = true,
673 },
674 }
675 };
676
677 static struct wm_table lpddr5_wm_table = {
678 .entries = {
679 {
680 .wm_inst = WM_A,
681 .wm_type = WM_TYPE_PSTATE_CHG,
682 .pstate_latency_us = 11.65333,
683 .sr_exit_time_us = 28.0,
684 .sr_enter_plus_exit_time_us = 30.0,
685 .valid = true,
686 },
687 {
688 .wm_inst = WM_B,
689 .wm_type = WM_TYPE_PSTATE_CHG,
690 .pstate_latency_us = 11.65333,
691 .sr_exit_time_us = 28.0,
692 .sr_enter_plus_exit_time_us = 30.0,
693 .valid = true,
694 },
695 {
696 .wm_inst = WM_C,
697 .wm_type = WM_TYPE_PSTATE_CHG,
698 .pstate_latency_us = 11.65333,
699 .sr_exit_time_us = 28.0,
700 .sr_enter_plus_exit_time_us = 30.0,
701 .valid = true,
702 },
703 {
704 .wm_inst = WM_D,
705 .wm_type = WM_TYPE_PSTATE_CHG,
706 .pstate_latency_us = 11.65333,
707 .sr_exit_time_us = 28.0,
708 .sr_enter_plus_exit_time_us = 30.0,
709 .valid = true,
710 },
711 }
712 };
713
714 static DpmClocks_t_dcn35 dummy_clocks;
715 static DpmClocks_t_dcn351 dummy_clocks_dcn351;
716
717 static struct dcn35_watermarks dummy_wms = { 0 };
718
719 static struct dcn35_ss_info_table ss_info_table = {
720 .ss_divider = 1000,
721 .ss_percentage = {0, 0, 375, 375, 375}
722 };
723
dcn35_read_ss_info_from_lut(struct clk_mgr_internal * clk_mgr)724 static void dcn35_read_ss_info_from_lut(struct clk_mgr_internal *clk_mgr)
725 {
726 uint32_t clock_source = 0;
727
728 clock_source = REG_READ(CLK1_CLK2_BYPASS_CNTL) & CLK1_CLK2_BYPASS_CNTL__CLK2_BYPASS_SEL_MASK;
729
730 // If it's DFS mode, clock_source is 0.
731 if (dcn35_is_spll_ssc_enabled(&clk_mgr->base) && (clock_source < ARRAY_SIZE(ss_info_table.ss_percentage))) {
732 clk_mgr->dprefclk_ss_percentage = ss_info_table.ss_percentage[clock_source];
733
734 if (clk_mgr->dprefclk_ss_percentage != 0) {
735 clk_mgr->ss_on_dprefclk = true;
736 clk_mgr->dprefclk_ss_divider = ss_info_table.ss_divider;
737 }
738 }
739 }
740
dcn35_build_watermark_ranges(struct clk_bw_params * bw_params,struct dcn35_watermarks * table)741 static void dcn35_build_watermark_ranges(struct clk_bw_params *bw_params, struct dcn35_watermarks *table)
742 {
743 int i, num_valid_sets;
744
745 num_valid_sets = 0;
746
747 for (i = 0; i < WM_SET_COUNT; i++) {
748 /* skip empty entries, the smu array has no holes*/
749 if (!bw_params->wm_table.entries[i].valid)
750 continue;
751
752 table->WatermarkRow[WM_DCFCLK][num_valid_sets].WmSetting = bw_params->wm_table.entries[i].wm_inst;
753 table->WatermarkRow[WM_DCFCLK][num_valid_sets].WmType = bw_params->wm_table.entries[i].wm_type;
754 /* We will not select WM based on fclk, so leave it as unconstrained */
755 table->WatermarkRow[WM_DCFCLK][num_valid_sets].MinClock = 0;
756 table->WatermarkRow[WM_DCFCLK][num_valid_sets].MaxClock = 0xFFFF;
757
758 if (table->WatermarkRow[WM_DCFCLK][num_valid_sets].WmType == WM_TYPE_PSTATE_CHG) {
759 if (i == 0)
760 table->WatermarkRow[WM_DCFCLK][num_valid_sets].MinMclk = 0;
761 else {
762 /* add 1 to make it non-overlapping with next lvl */
763 table->WatermarkRow[WM_DCFCLK][num_valid_sets].MinMclk =
764 bw_params->clk_table.entries[i - 1].dcfclk_mhz + 1;
765 }
766 table->WatermarkRow[WM_DCFCLK][num_valid_sets].MaxMclk =
767 bw_params->clk_table.entries[i].dcfclk_mhz;
768
769 } else {
770 /* unconstrained for memory retraining */
771 table->WatermarkRow[WM_DCFCLK][num_valid_sets].MinClock = 0;
772 table->WatermarkRow[WM_DCFCLK][num_valid_sets].MaxClock = 0xFFFF;
773
774 /* Modify previous watermark range to cover up to max */
775 table->WatermarkRow[WM_DCFCLK][num_valid_sets - 1].MaxClock = 0xFFFF;
776 }
777 num_valid_sets++;
778 }
779
780 ASSERT(num_valid_sets != 0); /* Must have at least one set of valid watermarks */
781
782 /* modify the min and max to make sure we cover the whole range*/
783 table->WatermarkRow[WM_DCFCLK][0].MinMclk = 0;
784 table->WatermarkRow[WM_DCFCLK][0].MinClock = 0;
785 table->WatermarkRow[WM_DCFCLK][num_valid_sets - 1].MaxMclk = 0xFFFF;
786 table->WatermarkRow[WM_DCFCLK][num_valid_sets - 1].MaxClock = 0xFFFF;
787
788 /* This is for writeback only, does not matter currently as no writeback support*/
789 table->WatermarkRow[WM_SOCCLK][0].WmSetting = WM_A;
790 table->WatermarkRow[WM_SOCCLK][0].MinClock = 0;
791 table->WatermarkRow[WM_SOCCLK][0].MaxClock = 0xFFFF;
792 table->WatermarkRow[WM_SOCCLK][0].MinMclk = 0;
793 table->WatermarkRow[WM_SOCCLK][0].MaxMclk = 0xFFFF;
794 }
795
dcn35_notify_wm_ranges(struct clk_mgr * clk_mgr_base)796 static void dcn35_notify_wm_ranges(struct clk_mgr *clk_mgr_base)
797 {
798 struct clk_mgr_internal *clk_mgr = TO_CLK_MGR_INTERNAL(clk_mgr_base);
799 struct clk_mgr_dcn35 *clk_mgr_dcn35 = TO_CLK_MGR_DCN35(clk_mgr);
800 struct dcn35_watermarks *table = clk_mgr_dcn35->smu_wm_set.wm_set;
801
802 if (!clk_mgr->smu_ver)
803 return;
804
805 if (!table || clk_mgr_dcn35->smu_wm_set.mc_address.quad_part == 0)
806 return;
807
808 memset(table, 0, sizeof(*table));
809
810 dcn35_build_watermark_ranges(clk_mgr_base->bw_params, table);
811
812 dcn35_smu_set_dram_addr_high(clk_mgr,
813 clk_mgr_dcn35->smu_wm_set.mc_address.high_part);
814 dcn35_smu_set_dram_addr_low(clk_mgr,
815 clk_mgr_dcn35->smu_wm_set.mc_address.low_part);
816 dcn35_smu_transfer_wm_table_dram_2_smu(clk_mgr);
817 }
818
dcn35_get_dpm_table_from_smu(struct clk_mgr_internal * clk_mgr,struct dcn35_smu_dpm_clks * smu_dpm_clks)819 static void dcn35_get_dpm_table_from_smu(struct clk_mgr_internal *clk_mgr,
820 struct dcn35_smu_dpm_clks *smu_dpm_clks)
821 {
822 DpmClocks_t_dcn35 *table = smu_dpm_clks->dpm_clks;
823
824 if (!clk_mgr->smu_ver)
825 return;
826
827 if (!table || smu_dpm_clks->mc_address.quad_part == 0)
828 return;
829
830 memset(table, 0, sizeof(*table));
831
832 dcn35_smu_set_dram_addr_high(clk_mgr,
833 smu_dpm_clks->mc_address.high_part);
834 dcn35_smu_set_dram_addr_low(clk_mgr,
835 smu_dpm_clks->mc_address.low_part);
836 dcn35_smu_transfer_dpm_table_smu_2_dram(clk_mgr);
837 }
838
dcn351_get_dpm_table_from_smu(struct clk_mgr_internal * clk_mgr,struct dcn351_smu_dpm_clks * smu_dpm_clks)839 static void dcn351_get_dpm_table_from_smu(struct clk_mgr_internal *clk_mgr,
840 struct dcn351_smu_dpm_clks *smu_dpm_clks)
841 {
842 DpmClocks_t_dcn351 *table = smu_dpm_clks->dpm_clks;
843
844 if (!clk_mgr->smu_ver)
845 return;
846 if (!table || smu_dpm_clks->mc_address.quad_part == 0)
847 return;
848 memset(table, 0, sizeof(*table));
849 dcn35_smu_set_dram_addr_high(clk_mgr,
850 smu_dpm_clks->mc_address.high_part);
851 dcn35_smu_set_dram_addr_low(clk_mgr,
852 smu_dpm_clks->mc_address.low_part);
853 dcn35_smu_transfer_dpm_table_smu_2_dram(clk_mgr);
854 }
find_max_clk_value(const uint32_t clocks[],uint32_t num_clocks)855 static uint32_t find_max_clk_value(const uint32_t clocks[], uint32_t num_clocks)
856 {
857 uint32_t max = 0;
858 int i;
859
860 for (i = 0; i < num_clocks; ++i) {
861 if (clocks[i] > max)
862 max = clocks[i];
863 }
864
865 return max;
866 }
867
is_valid_clock_value(uint32_t clock_value)868 static inline bool is_valid_clock_value(uint32_t clock_value)
869 {
870 return clock_value > 1 && clock_value < 100000;
871 }
872
convert_wck_ratio(uint8_t wck_ratio)873 static unsigned int convert_wck_ratio(uint8_t wck_ratio)
874 {
875 switch (wck_ratio) {
876 case WCK_RATIO_1_2:
877 return 2;
878
879 case WCK_RATIO_1_4:
880 return 4;
881 /* Find lowest DPM, FCLK is filled in reverse order*/
882
883 default:
884 break;
885 }
886
887 return 1;
888 }
889
calc_dram_speed_mts(const MemPstateTable_t * entry)890 static inline uint32_t calc_dram_speed_mts(const MemPstateTable_t *entry)
891 {
892 return entry->UClk * convert_wck_ratio(entry->WckRatio) * 2;
893 }
894
dcn35_clk_mgr_helper_populate_bw_params(struct clk_mgr_internal * clk_mgr,struct integrated_info * bios_info,DpmClocks_t_dcn35 * clock_table)895 static void dcn35_clk_mgr_helper_populate_bw_params(struct clk_mgr_internal *clk_mgr,
896 struct integrated_info *bios_info,
897 DpmClocks_t_dcn35 *clock_table)
898 {
899 struct clk_bw_params *bw_params = clk_mgr->base.bw_params;
900 struct clk_limit_table_entry def_max = bw_params->clk_table.entries[bw_params->clk_table.num_entries - 1];
901 uint32_t max_fclk = 0, min_pstate = 0, max_dispclk = 0, max_dppclk = 0;
902 uint32_t max_pstate = 0, max_dram_speed_mts = 0, min_dram_speed_mts = 0;
903 uint32_t num_memps, num_fclk, num_dcfclk;
904 int i;
905
906 /* Determine min/max p-state values. */
907 num_memps = (clock_table->NumMemPstatesEnabled > NUM_MEM_PSTATE_LEVELS) ? NUM_MEM_PSTATE_LEVELS :
908 clock_table->NumMemPstatesEnabled;
909 for (i = 0; i < num_memps; i++) {
910 uint32_t dram_speed_mts = calc_dram_speed_mts(&clock_table->MemPstateTable[i]);
911
912 if (is_valid_clock_value(dram_speed_mts) && dram_speed_mts > max_dram_speed_mts) {
913 max_dram_speed_mts = dram_speed_mts;
914 max_pstate = i;
915 }
916 }
917
918 min_dram_speed_mts = max_dram_speed_mts;
919 min_pstate = max_pstate;
920
921 for (i = 0; i < num_memps; i++) {
922 uint32_t dram_speed_mts = calc_dram_speed_mts(&clock_table->MemPstateTable[i]);
923
924 if (is_valid_clock_value(dram_speed_mts) && dram_speed_mts < min_dram_speed_mts) {
925 min_dram_speed_mts = dram_speed_mts;
926 min_pstate = i;
927 }
928 }
929
930 /* We expect the table to contain at least one valid P-state entry. */
931 ASSERT(clock_table->NumMemPstatesEnabled &&
932 is_valid_clock_value(max_dram_speed_mts) &&
933 is_valid_clock_value(min_dram_speed_mts));
934
935 /* dispclk and dppclk can be max at any voltage, same number of levels for both */
936 if (clock_table->NumDispClkLevelsEnabled <= NUM_DISPCLK_DPM_LEVELS &&
937 clock_table->NumDispClkLevelsEnabled <= NUM_DPPCLK_DPM_LEVELS) {
938 max_dispclk = find_max_clk_value(clock_table->DispClocks,
939 clock_table->NumDispClkLevelsEnabled);
940 max_dppclk = find_max_clk_value(clock_table->DppClocks,
941 clock_table->NumDispClkLevelsEnabled);
942 } else {
943 /* Invalid number of entries in the table from PMFW. */
944 ASSERT(0);
945 }
946
947 /* Base the clock table on dcfclk, need at least one entry regardless of pmfw table */
948 ASSERT(clock_table->NumDcfClkLevelsEnabled > 0);
949
950 num_fclk = (clock_table->NumFclkLevelsEnabled > NUM_FCLK_DPM_LEVELS) ? NUM_FCLK_DPM_LEVELS :
951 clock_table->NumFclkLevelsEnabled;
952 max_fclk = find_max_clk_value(clock_table->FclkClocks_Freq, num_fclk);
953
954 num_dcfclk = (clock_table->NumDcfClkLevelsEnabled > NUM_DCFCLK_DPM_LEVELS) ? NUM_DCFCLK_DPM_LEVELS :
955 clock_table->NumDcfClkLevelsEnabled;
956 for (i = 0; i < num_dcfclk; i++) {
957 int j;
958
959 /* First search defaults for the clocks we don't read using closest lower or equal default dcfclk */
960 for (j = bw_params->clk_table.num_entries - 1; j > 0; j--)
961 if (bw_params->clk_table.entries[j].dcfclk_mhz <= clock_table->DcfClocks[i])
962 break;
963
964 bw_params->clk_table.entries[i].phyclk_mhz = bw_params->clk_table.entries[j].phyclk_mhz;
965 bw_params->clk_table.entries[i].phyclk_d18_mhz = bw_params->clk_table.entries[j].phyclk_d18_mhz;
966 bw_params->clk_table.entries[i].dtbclk_mhz = bw_params->clk_table.entries[j].dtbclk_mhz;
967
968 /* Now update clocks we do read */
969 bw_params->clk_table.entries[i].memclk_mhz = clock_table->MemPstateTable[min_pstate].MemClk;
970 bw_params->clk_table.entries[i].voltage = clock_table->MemPstateTable[min_pstate].Voltage;
971 bw_params->clk_table.entries[i].dcfclk_mhz = clock_table->DcfClocks[i];
972 bw_params->clk_table.entries[i].socclk_mhz = clock_table->SocClocks[i];
973 bw_params->clk_table.entries[i].dispclk_mhz = max_dispclk;
974 bw_params->clk_table.entries[i].dppclk_mhz = max_dppclk;
975 bw_params->clk_table.entries[i].wck_ratio =
976 convert_wck_ratio(clock_table->MemPstateTable[min_pstate].WckRatio);
977
978 /* Dcfclk and Fclk are tied, but at a different ratio */
979 bw_params->clk_table.entries[i].fclk_mhz = min(max_fclk, 2 * clock_table->DcfClocks[i]);
980 }
981
982 /* Make sure to include at least one entry at highest pstate */
983 if (max_pstate != min_pstate || i == 0) {
984 if (i > MAX_NUM_DPM_LVL - 1)
985 i = MAX_NUM_DPM_LVL - 1;
986
987 bw_params->clk_table.entries[i].fclk_mhz = max_fclk;
988 bw_params->clk_table.entries[i].memclk_mhz = clock_table->MemPstateTable[max_pstate].MemClk;
989 bw_params->clk_table.entries[i].voltage = clock_table->MemPstateTable[max_pstate].Voltage;
990 bw_params->clk_table.entries[i].dcfclk_mhz =
991 find_max_clk_value(clock_table->DcfClocks, NUM_DCFCLK_DPM_LEVELS);
992 bw_params->clk_table.entries[i].socclk_mhz =
993 find_max_clk_value(clock_table->SocClocks, NUM_SOCCLK_DPM_LEVELS);
994 bw_params->clk_table.entries[i].dispclk_mhz = max_dispclk;
995 bw_params->clk_table.entries[i].dppclk_mhz = max_dppclk;
996 bw_params->clk_table.entries[i].wck_ratio = convert_wck_ratio(
997 clock_table->MemPstateTable[max_pstate].WckRatio);
998 i++;
999 }
1000 bw_params->clk_table.num_entries = i--;
1001
1002 /* Make sure all highest clocks are included*/
1003 bw_params->clk_table.entries[i].socclk_mhz =
1004 find_max_clk_value(clock_table->SocClocks, NUM_SOCCLK_DPM_LEVELS);
1005 bw_params->clk_table.entries[i].dispclk_mhz =
1006 find_max_clk_value(clock_table->DispClocks, NUM_DISPCLK_DPM_LEVELS);
1007 bw_params->clk_table.entries[i].dppclk_mhz =
1008 find_max_clk_value(clock_table->DppClocks, NUM_DPPCLK_DPM_LEVELS);
1009 bw_params->clk_table.entries[i].fclk_mhz =
1010 find_max_clk_value(clock_table->FclkClocks_Freq, NUM_FCLK_DPM_LEVELS);
1011 ASSERT(clock_table->DcfClocks[i] == find_max_clk_value(clock_table->DcfClocks, NUM_DCFCLK_DPM_LEVELS));
1012 bw_params->clk_table.entries[i].phyclk_mhz = def_max.phyclk_mhz;
1013 bw_params->clk_table.entries[i].phyclk_d18_mhz = def_max.phyclk_d18_mhz;
1014 bw_params->clk_table.entries[i].dtbclk_mhz = def_max.dtbclk_mhz;
1015 bw_params->clk_table.num_entries_per_clk.num_dcfclk_levels = clock_table->NumDcfClkLevelsEnabled;
1016 bw_params->clk_table.num_entries_per_clk.num_dispclk_levels = clock_table->NumDispClkLevelsEnabled;
1017 bw_params->clk_table.num_entries_per_clk.num_dppclk_levels = clock_table->NumDispClkLevelsEnabled;
1018 bw_params->clk_table.num_entries_per_clk.num_fclk_levels = clock_table->NumFclkLevelsEnabled;
1019 bw_params->clk_table.num_entries_per_clk.num_memclk_levels = clock_table->NumMemPstatesEnabled;
1020 bw_params->clk_table.num_entries_per_clk.num_socclk_levels = clock_table->NumSocClkLevelsEnabled;
1021
1022 /*
1023 * Set any 0 clocks to max default setting. Not an issue for
1024 * power since we aren't doing switching in such case anyway
1025 */
1026 for (i = 0; i < bw_params->clk_table.num_entries; i++) {
1027 if (!bw_params->clk_table.entries[i].fclk_mhz) {
1028 bw_params->clk_table.entries[i].fclk_mhz = def_max.fclk_mhz;
1029 bw_params->clk_table.entries[i].memclk_mhz = def_max.memclk_mhz;
1030 bw_params->clk_table.entries[i].voltage = def_max.voltage;
1031 }
1032 if (!bw_params->clk_table.entries[i].dcfclk_mhz)
1033 bw_params->clk_table.entries[i].dcfclk_mhz = def_max.dcfclk_mhz;
1034 if (!bw_params->clk_table.entries[i].socclk_mhz)
1035 bw_params->clk_table.entries[i].socclk_mhz = def_max.socclk_mhz;
1036 if (!bw_params->clk_table.entries[i].dispclk_mhz)
1037 bw_params->clk_table.entries[i].dispclk_mhz = def_max.dispclk_mhz;
1038 if (!bw_params->clk_table.entries[i].dppclk_mhz)
1039 bw_params->clk_table.entries[i].dppclk_mhz = def_max.dppclk_mhz;
1040 if (!bw_params->clk_table.entries[i].fclk_mhz)
1041 bw_params->clk_table.entries[i].fclk_mhz = def_max.fclk_mhz;
1042 if (!bw_params->clk_table.entries[i].phyclk_mhz)
1043 bw_params->clk_table.entries[i].phyclk_mhz = def_max.phyclk_mhz;
1044 if (!bw_params->clk_table.entries[i].phyclk_d18_mhz)
1045 bw_params->clk_table.entries[i].phyclk_d18_mhz = def_max.phyclk_d18_mhz;
1046 if (!bw_params->clk_table.entries[i].dtbclk_mhz)
1047 bw_params->clk_table.entries[i].dtbclk_mhz = def_max.dtbclk_mhz;
1048 }
1049 ASSERT(bw_params->clk_table.entries[i-1].dcfclk_mhz);
1050 bw_params->vram_type = bios_info->memory_type;
1051 bw_params->dram_channel_width_bytes = bios_info->memory_type == 0x22 ? 8 : 4;
1052 bw_params->num_channels = bios_info->ma_channel_number ? bios_info->ma_channel_number : 4;
1053
1054 for (i = 0; i < WM_SET_COUNT; i++) {
1055 bw_params->wm_table.entries[i].wm_inst = i;
1056
1057 if (i >= bw_params->clk_table.num_entries) {
1058 bw_params->wm_table.entries[i].valid = false;
1059 continue;
1060 }
1061
1062 bw_params->wm_table.entries[i].wm_type = WM_TYPE_PSTATE_CHG;
1063 bw_params->wm_table.entries[i].valid = true;
1064 }
1065 }
1066
dcn35_set_low_power_state(struct clk_mgr * clk_mgr_base)1067 static void dcn35_set_low_power_state(struct clk_mgr *clk_mgr_base)
1068 {
1069 int display_count;
1070 struct dc *dc = clk_mgr_base->ctx->dc;
1071 struct dc_state *context = dc->current_state;
1072
1073 if (clk_mgr_base->clks.pwr_state != DCN_PWR_STATE_LOW_POWER) {
1074 display_count = dcn35_get_active_display_cnt_wa(dc, context, NULL);
1075 /* if we can go lower, go lower */
1076 if (display_count == 0)
1077 clk_mgr_base->clks.pwr_state = DCN_PWR_STATE_LOW_POWER;
1078 }
1079 }
1080
dcn35_exit_low_power_state(struct clk_mgr * clk_mgr_base)1081 static void dcn35_exit_low_power_state(struct clk_mgr *clk_mgr_base)
1082 {
1083 struct clk_mgr_internal *clk_mgr = TO_CLK_MGR_INTERNAL(clk_mgr_base);
1084
1085 //SMU optimization is performed part of low power state exit.
1086 dcn35_smu_exit_low_power_state(clk_mgr);
1087
1088 }
1089
dcn35_is_ips_supported(struct clk_mgr * clk_mgr_base)1090 static bool dcn35_is_ips_supported(struct clk_mgr *clk_mgr_base)
1091 {
1092 struct clk_mgr_internal *clk_mgr = TO_CLK_MGR_INTERNAL(clk_mgr_base);
1093
1094 return dcn35_smu_get_ips_supported(clk_mgr) ? true : false;
1095 }
1096
dcn35_init_clocks_fpga(struct clk_mgr * clk_mgr)1097 static void dcn35_init_clocks_fpga(struct clk_mgr *clk_mgr)
1098 {
1099 init_clk_states(clk_mgr);
1100
1101 /* TODO: Implement the functions and remove the ifndef guard */
1102 }
1103
dcn35_update_clocks_fpga(struct clk_mgr * clk_mgr,struct dc_state * context,bool safe_to_lower)1104 static void dcn35_update_clocks_fpga(struct clk_mgr *clk_mgr,
1105 struct dc_state *context,
1106 bool safe_to_lower)
1107 {
1108 struct clk_mgr_internal *clk_mgr_int = TO_CLK_MGR_INTERNAL(clk_mgr);
1109 struct dc_clocks *new_clocks = &context->bw_ctx.bw.dcn.clk;
1110 int fclk_adj = new_clocks->fclk_khz;
1111
1112 /* TODO: remove this after correctly set by DML */
1113 new_clocks->dcfclk_khz = 400000;
1114 new_clocks->socclk_khz = 400000;
1115
1116 /* Min fclk = 1.2GHz since all the extra scemi logic seems to run off of it */
1117 //int fclk_adj = new_clocks->fclk_khz > 1200000 ? new_clocks->fclk_khz : 1200000;
1118 new_clocks->fclk_khz = 4320000;
1119
1120 if (should_set_clock(safe_to_lower, new_clocks->phyclk_khz, clk_mgr->clks.phyclk_khz)) {
1121 clk_mgr->clks.phyclk_khz = new_clocks->phyclk_khz;
1122 }
1123
1124 if (should_set_clock(safe_to_lower, new_clocks->dcfclk_khz, clk_mgr->clks.dcfclk_khz)) {
1125 clk_mgr->clks.dcfclk_khz = new_clocks->dcfclk_khz;
1126 }
1127
1128 if (should_set_clock(safe_to_lower,
1129 new_clocks->dcfclk_deep_sleep_khz, clk_mgr->clks.dcfclk_deep_sleep_khz)) {
1130 clk_mgr->clks.dcfclk_deep_sleep_khz = new_clocks->dcfclk_deep_sleep_khz;
1131 }
1132
1133 if (should_set_clock(safe_to_lower, new_clocks->socclk_khz, clk_mgr->clks.socclk_khz)) {
1134 clk_mgr->clks.socclk_khz = new_clocks->socclk_khz;
1135 }
1136
1137 if (should_set_clock(safe_to_lower, new_clocks->dramclk_khz, clk_mgr->clks.dramclk_khz)) {
1138 clk_mgr->clks.dramclk_khz = new_clocks->dramclk_khz;
1139 }
1140
1141 if (should_set_clock(safe_to_lower, new_clocks->dppclk_khz, clk_mgr->clks.dppclk_khz)) {
1142 clk_mgr->clks.dppclk_khz = new_clocks->dppclk_khz;
1143 }
1144
1145 if (should_set_clock(safe_to_lower, fclk_adj, clk_mgr->clks.fclk_khz)) {
1146 clk_mgr->clks.fclk_khz = fclk_adj;
1147 }
1148
1149 if (should_set_clock(safe_to_lower, new_clocks->dispclk_khz, clk_mgr->clks.dispclk_khz)) {
1150 clk_mgr->clks.dispclk_khz = new_clocks->dispclk_khz;
1151 }
1152
1153 /* Both fclk and ref_dppclk run on the same scemi clock.
1154 * So take the higher value since the DPP DTO is typically programmed
1155 * such that max dppclk is 1:1 with ref_dppclk.
1156 */
1157 if (clk_mgr->clks.fclk_khz > clk_mgr->clks.dppclk_khz)
1158 clk_mgr->clks.dppclk_khz = clk_mgr->clks.fclk_khz;
1159 if (clk_mgr->clks.dppclk_khz > clk_mgr->clks.fclk_khz)
1160 clk_mgr->clks.fclk_khz = clk_mgr->clks.dppclk_khz;
1161
1162 // Both fclk and ref_dppclk run on the same scemi clock.
1163 clk_mgr_int->dccg->ref_dppclk = clk_mgr->clks.fclk_khz;
1164
1165 /* TODO: set dtbclk in correct place */
1166 clk_mgr->clks.dtbclk_en = true;
1167 dm_set_dcn_clocks(clk_mgr->ctx, &clk_mgr->clks);
1168 dcn35_update_clocks_update_dpp_dto(clk_mgr_int, context, safe_to_lower);
1169
1170 dcn35_update_clocks_update_dtb_dto(clk_mgr_int, context, clk_mgr->clks.ref_dtbclk_khz);
1171 }
1172
1173 static struct clk_mgr_funcs dcn35_funcs = {
1174 .get_dp_ref_clk_frequency = dce12_get_dp_ref_freq_khz,
1175 .get_dtb_ref_clk_frequency = dcn31_get_dtb_ref_freq_khz,
1176 .update_clocks = dcn35_update_clocks,
1177 .init_clocks = dcn35_init_clocks,
1178 .enable_pme_wa = dcn35_enable_pme_wa,
1179 .are_clock_states_equal = dcn35_are_clock_states_equal,
1180 .notify_wm_ranges = dcn35_notify_wm_ranges,
1181 .set_low_power_state = dcn35_set_low_power_state,
1182 .exit_low_power_state = dcn35_exit_low_power_state,
1183 .is_ips_supported = dcn35_is_ips_supported,
1184 };
1185
1186 struct clk_mgr_funcs dcn35_fpga_funcs = {
1187 .get_dp_ref_clk_frequency = dce12_get_dp_ref_freq_khz,
1188 .update_clocks = dcn35_update_clocks_fpga,
1189 .init_clocks = dcn35_init_clocks_fpga,
1190 .get_dtb_ref_clk_frequency = dcn31_get_dtb_ref_freq_khz,
1191 };
1192
translate_to_DpmClocks_t_dcn35(struct dcn351_smu_dpm_clks * smu_dpm_clks_a,struct dcn35_smu_dpm_clks * smu_dpm_clks_b)1193 static void translate_to_DpmClocks_t_dcn35(struct dcn351_smu_dpm_clks *smu_dpm_clks_a,
1194 struct dcn35_smu_dpm_clks *smu_dpm_clks_b)
1195 {
1196 /*translate two structures and only take need clock tables*/
1197 uint8_t i;
1198
1199 if (smu_dpm_clks_a == NULL || smu_dpm_clks_b == NULL ||
1200 smu_dpm_clks_a->dpm_clks == NULL || smu_dpm_clks_b->dpm_clks == NULL)
1201 return;
1202
1203 for (i = 0; i < NUM_DCFCLK_DPM_LEVELS; i++)
1204 smu_dpm_clks_b->dpm_clks->DcfClocks[i] = smu_dpm_clks_a->dpm_clks->DcfClocks[i];
1205
1206 for (i = 0; i < NUM_DISPCLK_DPM_LEVELS; i++)
1207 smu_dpm_clks_b->dpm_clks->DispClocks[i] = smu_dpm_clks_a->dpm_clks->DispClocks[i];
1208
1209 for (i = 0; i < NUM_DPPCLK_DPM_LEVELS; i++)
1210 smu_dpm_clks_b->dpm_clks->DppClocks[i] = smu_dpm_clks_a->dpm_clks->DppClocks[i];
1211
1212 for (i = 0; i < NUM_FCLK_DPM_LEVELS; i++) {
1213 smu_dpm_clks_b->dpm_clks->FclkClocks_Freq[i] = smu_dpm_clks_a->dpm_clks->FclkClocks_Freq[i];
1214 smu_dpm_clks_b->dpm_clks->FclkClocks_Voltage[i] = smu_dpm_clks_a->dpm_clks->FclkClocks_Voltage[i];
1215 }
1216 for (i = 0; i < NUM_MEM_PSTATE_LEVELS; i++) {
1217 smu_dpm_clks_b->dpm_clks->MemPstateTable[i].MemClk =
1218 smu_dpm_clks_a->dpm_clks->MemPstateTable[i].MemClk;
1219 smu_dpm_clks_b->dpm_clks->MemPstateTable[i].UClk =
1220 smu_dpm_clks_a->dpm_clks->MemPstateTable[i].UClk;
1221 smu_dpm_clks_b->dpm_clks->MemPstateTable[i].Voltage =
1222 smu_dpm_clks_a->dpm_clks->MemPstateTable[i].Voltage;
1223 smu_dpm_clks_b->dpm_clks->MemPstateTable[i].WckRatio =
1224 smu_dpm_clks_a->dpm_clks->MemPstateTable[i].WckRatio;
1225 }
1226 smu_dpm_clks_b->dpm_clks->MaxGfxClk = smu_dpm_clks_a->dpm_clks->MaxGfxClk;
1227 smu_dpm_clks_b->dpm_clks->MinGfxClk = smu_dpm_clks_a->dpm_clks->MinGfxClk;
1228 smu_dpm_clks_b->dpm_clks->NumDcfClkLevelsEnabled =
1229 smu_dpm_clks_a->dpm_clks->NumDcfClkLevelsEnabled;
1230 smu_dpm_clks_b->dpm_clks->NumDispClkLevelsEnabled =
1231 smu_dpm_clks_a->dpm_clks->NumDispClkLevelsEnabled;
1232 smu_dpm_clks_b->dpm_clks->NumFclkLevelsEnabled =
1233 smu_dpm_clks_a->dpm_clks->NumFclkLevelsEnabled;
1234 smu_dpm_clks_b->dpm_clks->NumMemPstatesEnabled =
1235 smu_dpm_clks_a->dpm_clks->NumMemPstatesEnabled;
1236 smu_dpm_clks_b->dpm_clks->NumSocClkLevelsEnabled =
1237 smu_dpm_clks_a->dpm_clks->NumSocClkLevelsEnabled;
1238
1239 for (i = 0; i < NUM_SOC_VOLTAGE_LEVELS; i++) {
1240 smu_dpm_clks_b->dpm_clks->SocClocks[i] = smu_dpm_clks_a->dpm_clks->SocClocks[i];
1241 smu_dpm_clks_b->dpm_clks->SocVoltage[i] = smu_dpm_clks_a->dpm_clks->SocVoltage[i];
1242 }
1243 }
dcn35_clk_mgr_construct(struct dc_context * ctx,struct clk_mgr_dcn35 * clk_mgr,struct pp_smu_funcs * pp_smu,struct dccg * dccg)1244 void dcn35_clk_mgr_construct(
1245 struct dc_context *ctx,
1246 struct clk_mgr_dcn35 *clk_mgr,
1247 struct pp_smu_funcs *pp_smu,
1248 struct dccg *dccg)
1249 {
1250 struct dcn35_smu_dpm_clks smu_dpm_clks = { 0 };
1251 struct dcn351_smu_dpm_clks smu_dpm_clks_dcn351 = { 0 };
1252 clk_mgr->base.base.ctx = ctx;
1253 clk_mgr->base.base.funcs = &dcn35_funcs;
1254
1255 clk_mgr->base.pp_smu = pp_smu;
1256
1257 clk_mgr->base.dccg = dccg;
1258 clk_mgr->base.dfs_bypass_disp_clk = 0;
1259
1260 clk_mgr->base.dprefclk_ss_percentage = 0;
1261 clk_mgr->base.dprefclk_ss_divider = 1000;
1262 clk_mgr->base.ss_on_dprefclk = false;
1263 clk_mgr->base.dfs_ref_freq_khz = 48000;
1264 if (ctx->dce_version != DCN_VERSION_3_51) {
1265 clk_mgr->base.regs = &clk_mgr_regs_dcn35;
1266 clk_mgr->base.clk_mgr_shift = &clk_mgr_shift_dcn35;
1267 clk_mgr->base.clk_mgr_mask = &clk_mgr_mask_dcn35;
1268 }
1269
1270
1271 clk_mgr->smu_wm_set.wm_set = (struct dcn35_watermarks *)dm_helpers_allocate_gpu_mem(
1272 clk_mgr->base.base.ctx,
1273 DC_MEM_ALLOC_TYPE_GART,
1274 sizeof(struct dcn35_watermarks),
1275 &clk_mgr->smu_wm_set.mc_address.quad_part);
1276
1277 if (!clk_mgr->smu_wm_set.wm_set) {
1278 clk_mgr->smu_wm_set.wm_set = &dummy_wms;
1279 clk_mgr->smu_wm_set.mc_address.quad_part = 0;
1280 }
1281 ASSERT(clk_mgr->smu_wm_set.wm_set);
1282
1283 smu_dpm_clks.dpm_clks = (DpmClocks_t_dcn35 *)dm_helpers_allocate_gpu_mem(
1284 clk_mgr->base.base.ctx,
1285 DC_MEM_ALLOC_TYPE_GART,
1286 sizeof(DpmClocks_t_dcn35),
1287 &smu_dpm_clks.mc_address.quad_part);
1288 if (smu_dpm_clks.dpm_clks == NULL) {
1289 smu_dpm_clks.dpm_clks = &dummy_clocks;
1290 smu_dpm_clks.mc_address.quad_part = 0;
1291 }
1292 ASSERT(smu_dpm_clks.dpm_clks);
1293
1294 if (ctx->dce_version == DCN_VERSION_3_51) {
1295 smu_dpm_clks_dcn351.dpm_clks = (DpmClocks_t_dcn351 *)dm_helpers_allocate_gpu_mem(
1296 clk_mgr->base.base.ctx,
1297 DC_MEM_ALLOC_TYPE_GART,
1298 sizeof(DpmClocks_t_dcn351),
1299 &smu_dpm_clks_dcn351.mc_address.quad_part);
1300 if (smu_dpm_clks_dcn351.dpm_clks == NULL) {
1301 smu_dpm_clks_dcn351.dpm_clks = &dummy_clocks_dcn351;
1302 smu_dpm_clks_dcn351.mc_address.quad_part = 0;
1303 }
1304 }
1305
1306 clk_mgr->base.smu_ver = dcn35_smu_get_smu_version(&clk_mgr->base);
1307
1308 if (clk_mgr->base.smu_ver)
1309 clk_mgr->base.smu_present = true;
1310
1311 /* TODO: Check we get what we expect during bringup */
1312 clk_mgr->base.base.dentist_vco_freq_khz = get_vco_frequency_from_reg(&clk_mgr->base);
1313
1314 if (ctx->dc_bios->integrated_info->memory_type == LpDdr5MemType) {
1315 dcn35_bw_params.wm_table = lpddr5_wm_table;
1316 } else {
1317 dcn35_bw_params.wm_table = ddr5_wm_table;
1318 }
1319 /* Saved clocks configured at boot for debug purposes */
1320 dcn35_dump_clk_registers(&clk_mgr->base.base.boot_snapshot, clk_mgr);
1321
1322 clk_mgr->base.base.dprefclk_khz = dcn35_smu_get_dprefclk(&clk_mgr->base);
1323 clk_mgr->base.base.clks.ref_dtbclk_khz = 600000;
1324
1325 dce_clock_read_ss_info(&clk_mgr->base);
1326 /*when clk src is from FCH, it could have ss, same clock src as DPREF clk*/
1327
1328 dcn35_read_ss_info_from_lut(&clk_mgr->base);
1329
1330 clk_mgr->base.base.bw_params = &dcn35_bw_params;
1331
1332 if (clk_mgr->base.base.ctx->dc->debug.pstate_enabled) {
1333 int i;
1334 if (ctx->dce_version == DCN_VERSION_3_51) {
1335 dcn351_get_dpm_table_from_smu(&clk_mgr->base, &smu_dpm_clks_dcn351);
1336 translate_to_DpmClocks_t_dcn35(&smu_dpm_clks_dcn351, &smu_dpm_clks);
1337 } else
1338 dcn35_get_dpm_table_from_smu(&clk_mgr->base, &smu_dpm_clks);
1339 DC_LOG_SMU("NumDcfClkLevelsEnabled: %d\n"
1340 "NumDispClkLevelsEnabled: %d\n"
1341 "NumSocClkLevelsEnabled: %d\n"
1342 "VcnClkLevelsEnabled: %d\n"
1343 "FClkLevelsEnabled: %d\n"
1344 "NumMemPstatesEnabled: %d\n"
1345 "MinGfxClk: %d\n"
1346 "MaxGfxClk: %d\n",
1347 smu_dpm_clks.dpm_clks->NumDcfClkLevelsEnabled,
1348 smu_dpm_clks.dpm_clks->NumDispClkLevelsEnabled,
1349 smu_dpm_clks.dpm_clks->NumSocClkLevelsEnabled,
1350 smu_dpm_clks.dpm_clks->VcnClkLevelsEnabled,
1351 smu_dpm_clks.dpm_clks->NumFclkLevelsEnabled,
1352 smu_dpm_clks.dpm_clks->NumMemPstatesEnabled,
1353 smu_dpm_clks.dpm_clks->MinGfxClk,
1354 smu_dpm_clks.dpm_clks->MaxGfxClk);
1355 for (i = 0; i < smu_dpm_clks.dpm_clks->NumDcfClkLevelsEnabled; i++) {
1356 DC_LOG_SMU("smu_dpm_clks.dpm_clks->DcfClocks[%d] = %d\n",
1357 i,
1358 smu_dpm_clks.dpm_clks->DcfClocks[i]);
1359 }
1360 for (i = 0; i < smu_dpm_clks.dpm_clks->NumDispClkLevelsEnabled; i++) {
1361 DC_LOG_SMU("smu_dpm_clks.dpm_clks->DispClocks[%d] = %d\n",
1362 i, smu_dpm_clks.dpm_clks->DispClocks[i]);
1363 }
1364 for (i = 0; i < smu_dpm_clks.dpm_clks->NumSocClkLevelsEnabled; i++) {
1365 DC_LOG_SMU("smu_dpm_clks.dpm_clks->SocClocks[%d] = %d\n",
1366 i, smu_dpm_clks.dpm_clks->SocClocks[i]);
1367 }
1368 for (i = 0; i < smu_dpm_clks.dpm_clks->NumFclkLevelsEnabled; i++) {
1369 DC_LOG_SMU("smu_dpm_clks.dpm_clks->FclkClocks_Freq[%d] = %d\n",
1370 i, smu_dpm_clks.dpm_clks->FclkClocks_Freq[i]);
1371 DC_LOG_SMU("smu_dpm_clks.dpm_clks->FclkClocks_Voltage[%d] = %d\n",
1372 i, smu_dpm_clks.dpm_clks->FclkClocks_Voltage[i]);
1373 }
1374 for (i = 0; i < smu_dpm_clks.dpm_clks->NumSocClkLevelsEnabled; i++)
1375 DC_LOG_SMU("smu_dpm_clks.dpm_clks->SocVoltage[%d] = %d\n",
1376 i, smu_dpm_clks.dpm_clks->SocVoltage[i]);
1377
1378 for (i = 0; i < smu_dpm_clks.dpm_clks->NumMemPstatesEnabled; i++) {
1379 DC_LOG_SMU("smu_dpm_clks.dpm_clks.MemPstateTable[%d].UClk = %d\n"
1380 "smu_dpm_clks.dpm_clks->MemPstateTable[%d].MemClk= %d\n"
1381 "smu_dpm_clks.dpm_clks->MemPstateTable[%d].Voltage = %d\n",
1382 i, smu_dpm_clks.dpm_clks->MemPstateTable[i].UClk,
1383 i, smu_dpm_clks.dpm_clks->MemPstateTable[i].MemClk,
1384 i, smu_dpm_clks.dpm_clks->MemPstateTable[i].Voltage);
1385 }
1386
1387 if (ctx->dc_bios->integrated_info && ctx->dc->config.use_default_clock_table == false) {
1388 dcn35_clk_mgr_helper_populate_bw_params(
1389 &clk_mgr->base,
1390 ctx->dc_bios->integrated_info,
1391 smu_dpm_clks.dpm_clks);
1392 }
1393 }
1394
1395 if (smu_dpm_clks.dpm_clks && smu_dpm_clks.mc_address.quad_part != 0)
1396 dm_helpers_free_gpu_mem(clk_mgr->base.base.ctx, DC_MEM_ALLOC_TYPE_GART,
1397 smu_dpm_clks.dpm_clks);
1398
1399 if (smu_dpm_clks_dcn351.dpm_clks && smu_dpm_clks_dcn351.mc_address.quad_part != 0)
1400 dm_helpers_free_gpu_mem(clk_mgr->base.base.ctx, DC_MEM_ALLOC_TYPE_GART,
1401 smu_dpm_clks_dcn351.dpm_clks);
1402
1403 if (ctx->dc->config.disable_ips != DMUB_IPS_DISABLE_ALL) {
1404 bool ips_support = false;
1405
1406 /*avoid call pmfw at init*/
1407 ips_support = dcn35_smu_get_ips_supported(&clk_mgr->base);
1408 if (ips_support) {
1409 ctx->dc->debug.ignore_pg = false;
1410 ctx->dc->debug.disable_dpp_power_gate = false;
1411 ctx->dc->debug.disable_hubp_power_gate = false;
1412 ctx->dc->debug.disable_dsc_power_gate = false;
1413
1414 /* Disable dynamic IPS2 in older PMFW (93.12) for Z8 interop. */
1415 if (ctx->dc->config.disable_ips == DMUB_IPS_ENABLE &&
1416 ctx->dce_version != DCN_VERSION_3_51 &&
1417 ((clk_mgr->base.smu_ver & 0x00FFFFFF) <= 0x005d0c00))
1418 ctx->dc->config.disable_ips = DMUB_IPS_RCG_IN_ACTIVE_IPS2_IN_OFF;
1419 } else {
1420 /*let's reset the config control flag*/
1421 ctx->dc->config.disable_ips = DMUB_IPS_DISABLE_ALL; /*pmfw not support it, disable it all*/
1422 }
1423 }
1424 }
1425
dcn35_clk_mgr_destroy(struct clk_mgr_internal * clk_mgr_int)1426 void dcn35_clk_mgr_destroy(struct clk_mgr_internal *clk_mgr_int)
1427 {
1428 struct clk_mgr_dcn35 *clk_mgr = TO_CLK_MGR_DCN35(clk_mgr_int);
1429
1430 if (clk_mgr->smu_wm_set.wm_set && clk_mgr->smu_wm_set.mc_address.quad_part != 0)
1431 dm_helpers_free_gpu_mem(clk_mgr_int->base.ctx, DC_MEM_ALLOC_TYPE_FRAME_BUFFER,
1432 clk_mgr->smu_wm_set.wm_set);
1433 }
1434