1 /*
2 * Copyright 2021 Advanced Micro Devices, Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
21 *
22 * Authors: AMD
23 *
24 */
25
26 #include "dccg.h"
27 #include "clk_mgr_internal.h"
28 #include "dcn32/dcn32_clk_mgr_smu_msg.h"
29 #include "dcn20/dcn20_clk_mgr.h"
30 #include "dce100/dce_clk_mgr.h"
31 #include "dcn31/dcn31_clk_mgr.h"
32 #include "reg_helper.h"
33 #include "core_types.h"
34 #include "dm_helpers.h"
35 #include "link.h"
36 #include "dc_state_priv.h"
37 #include "atomfirmware.h"
38 #include "smu13_driver_if.h"
39
40 #include "dcn/dcn_3_2_0_offset.h"
41 #include "dcn/dcn_3_2_0_sh_mask.h"
42
43 #include "dcn32/dcn32_clk_mgr.h"
44 #include "dml/dcn32/dcn32_fpu.h"
45
46 #define DCN_BASE__INST0_SEG1 0x000000C0
47
48 #define mmCLK1_CLK_PLL_REQ 0x16E37
49 #define mmCLK1_CLK0_DFS_CNTL 0x16E69
50 #define mmCLK1_CLK1_DFS_CNTL 0x16E6C
51 #define mmCLK1_CLK2_DFS_CNTL 0x16E6F
52 #define mmCLK1_CLK3_DFS_CNTL 0x16E72
53 #define mmCLK1_CLK4_DFS_CNTL 0x16E75
54
55 #define mmCLK1_CLK0_CURRENT_CNT 0x16EE7
56 #define mmCLK1_CLK1_CURRENT_CNT 0x16EE8
57 #define mmCLK1_CLK2_CURRENT_CNT 0x16EE9
58 #define mmCLK1_CLK3_CURRENT_CNT 0x16EEA
59 #define mmCLK1_CLK4_CURRENT_CNT 0x16EEB
60
61 #define mmCLK4_CLK0_CURRENT_CNT 0x1B0C9
62
63 #define CLK1_CLK_PLL_REQ__FbMult_int_MASK 0x000001ffUL
64 #define CLK1_CLK_PLL_REQ__PllSpineDiv_MASK 0x0000f000UL
65 #define CLK1_CLK_PLL_REQ__FbMult_frac_MASK 0xffff0000UL
66 #define CLK1_CLK_PLL_REQ__FbMult_int__SHIFT 0x00000000
67 #define CLK1_CLK_PLL_REQ__PllSpineDiv__SHIFT 0x0000000c
68 #define CLK1_CLK_PLL_REQ__FbMult_frac__SHIFT 0x00000010
69
70 #define mmCLK01_CLK0_CLK_PLL_REQ 0x16E37
71 #define mmCLK01_CLK0_CLK0_DFS_CNTL 0x16E64
72 #define mmCLK01_CLK0_CLK1_DFS_CNTL 0x16E67
73 #define mmCLK01_CLK0_CLK2_DFS_CNTL 0x16E6A
74 #define mmCLK01_CLK0_CLK3_DFS_CNTL 0x16E6D
75 #define mmCLK01_CLK0_CLK4_DFS_CNTL 0x16E70
76
77 #define CLK0_CLK_PLL_REQ__FbMult_int_MASK 0x000001ffL
78 #define CLK0_CLK_PLL_REQ__PllSpineDiv_MASK 0x0000f000L
79 #define CLK0_CLK_PLL_REQ__FbMult_frac_MASK 0xffff0000L
80 #define CLK0_CLK_PLL_REQ__FbMult_int__SHIFT 0x00000000
81 #define CLK0_CLK_PLL_REQ__PllSpineDiv__SHIFT 0x0000000c
82 #define CLK0_CLK_PLL_REQ__FbMult_frac__SHIFT 0x00000010
83
84 #undef FN
85 #define FN(reg_name, field_name) \
86 clk_mgr->clk_mgr_shift->field_name, clk_mgr->clk_mgr_mask->field_name
87
88 #define REG(reg) \
89 (clk_mgr->regs->reg)
90
91 #define BASE_INNER(seg) DCN_BASE__INST0_SEG ## seg
92
93 #define BASE(seg) BASE_INNER(seg)
94
95 #define SR(reg_name)\
96 .reg_name = BASE(reg ## reg_name ## _BASE_IDX) + \
97 reg ## reg_name
98
99 #define CLK_SR_DCN32(reg_name)\
100 .reg_name = mm ## reg_name
101
102 static const struct clk_mgr_registers clk_mgr_regs_dcn32 = {
103 CLK_REG_LIST_DCN32()
104 };
105
106 static const struct clk_mgr_shift clk_mgr_shift_dcn32 = {
107 CLK_COMMON_MASK_SH_LIST_DCN32(__SHIFT)
108 };
109
110 static const struct clk_mgr_mask clk_mgr_mask_dcn32 = {
111 CLK_COMMON_MASK_SH_LIST_DCN32(_MASK)
112 };
113
114
115 #define CLK_SR_DCN321(reg_name, block, inst)\
116 .reg_name = mm ## block ## _ ## reg_name
117
118 static const struct clk_mgr_registers clk_mgr_regs_dcn321 = {
119 CLK_REG_LIST_DCN321()
120 };
121
122 static const struct clk_mgr_shift clk_mgr_shift_dcn321 = {
123 CLK_COMMON_MASK_SH_LIST_DCN321(__SHIFT)
124 };
125
126 static const struct clk_mgr_mask clk_mgr_mask_dcn321 = {
127 CLK_COMMON_MASK_SH_LIST_DCN321(_MASK)
128 };
129
130
131 /* Query SMU for all clock states for a particular clock */
dcn32_init_single_clock(struct clk_mgr_internal * clk_mgr,PPCLK_e clk,unsigned int * entry_0,unsigned int * num_levels)132 static void dcn32_init_single_clock(struct clk_mgr_internal *clk_mgr, PPCLK_e clk, unsigned int *entry_0,
133 unsigned int *num_levels)
134 {
135 unsigned int i;
136 char *entry_i = (char *)entry_0;
137
138 uint32_t ret = dcn30_smu_get_dpm_freq_by_index(clk_mgr, clk, 0xFF);
139
140 if (ret & (1 << 31))
141 /* fine-grained, only min and max */
142 *num_levels = 2;
143 else
144 /* discrete, a number of fixed states */
145 /* will set num_levels to 0 on failure */
146 *num_levels = ret & 0xFF;
147
148 /* if the initial message failed, num_levels will be 0 */
149 for (i = 0; i < *num_levels; i++) {
150 *((unsigned int *)entry_i) = (dcn30_smu_get_dpm_freq_by_index(clk_mgr, clk, i) & 0xFFFF);
151 entry_i += sizeof(clk_mgr->base.bw_params->clk_table.entries[0]);
152 }
153 }
154
dcn32_build_wm_range_table(struct clk_mgr_internal * clk_mgr)155 static void dcn32_build_wm_range_table(struct clk_mgr_internal *clk_mgr)
156 {
157 DC_FP_START();
158 dcn32_build_wm_range_table_fpu(clk_mgr);
159 DC_FP_END();
160 }
161
dcn32_init_clocks(struct clk_mgr * clk_mgr_base)162 void dcn32_init_clocks(struct clk_mgr *clk_mgr_base)
163 {
164 struct clk_mgr_internal *clk_mgr = TO_CLK_MGR_INTERNAL(clk_mgr_base);
165 unsigned int num_levels;
166 struct clk_limit_num_entries *num_entries_per_clk = &clk_mgr_base->bw_params->clk_table.num_entries_per_clk;
167 unsigned int i;
168
169 memset(&(clk_mgr_base->clks), 0, sizeof(struct dc_clocks));
170 clk_mgr_base->clks.p_state_change_support = true;
171 clk_mgr_base->clks.prev_p_state_change_support = true;
172 clk_mgr_base->clks.fclk_prev_p_state_change_support = true;
173 clk_mgr->smu_present = false;
174 clk_mgr->dpm_present = false;
175
176 if (!clk_mgr_base->bw_params)
177 return;
178
179 if (!clk_mgr_base->force_smu_not_present && dcn30_smu_get_smu_version(clk_mgr, &clk_mgr->smu_ver))
180 clk_mgr->smu_present = true;
181
182 if (!clk_mgr->smu_present)
183 return;
184
185 dcn30_smu_check_driver_if_version(clk_mgr);
186 dcn30_smu_check_msg_header_version(clk_mgr);
187
188 /* DCFCLK */
189 dcn32_init_single_clock(clk_mgr, PPCLK_DCFCLK,
190 &clk_mgr_base->bw_params->clk_table.entries[0].dcfclk_mhz,
191 &num_entries_per_clk->num_dcfclk_levels);
192 clk_mgr_base->bw_params->dc_mode_limit.dcfclk_mhz = dcn30_smu_get_dc_mode_max_dpm_freq(clk_mgr, PPCLK_DCFCLK);
193
194 /* SOCCLK */
195 dcn32_init_single_clock(clk_mgr, PPCLK_SOCCLK,
196 &clk_mgr_base->bw_params->clk_table.entries[0].socclk_mhz,
197 &num_entries_per_clk->num_socclk_levels);
198 clk_mgr_base->bw_params->dc_mode_limit.socclk_mhz = dcn30_smu_get_dc_mode_max_dpm_freq(clk_mgr, PPCLK_SOCCLK);
199
200 /* DTBCLK */
201 if (!clk_mgr->base.ctx->dc->debug.disable_dtb_ref_clk_switch) {
202 dcn32_init_single_clock(clk_mgr, PPCLK_DTBCLK,
203 &clk_mgr_base->bw_params->clk_table.entries[0].dtbclk_mhz,
204 &num_entries_per_clk->num_dtbclk_levels);
205 clk_mgr_base->bw_params->dc_mode_limit.dtbclk_mhz =
206 dcn30_smu_get_dc_mode_max_dpm_freq(clk_mgr, PPCLK_DTBCLK);
207 }
208
209 /* DISPCLK */
210 dcn32_init_single_clock(clk_mgr, PPCLK_DISPCLK,
211 &clk_mgr_base->bw_params->clk_table.entries[0].dispclk_mhz,
212 &num_entries_per_clk->num_dispclk_levels);
213 num_levels = num_entries_per_clk->num_dispclk_levels;
214 clk_mgr_base->bw_params->dc_mode_limit.dispclk_mhz = dcn30_smu_get_dc_mode_max_dpm_freq(clk_mgr, PPCLK_DISPCLK);
215 //HW recommends limit of 1950 MHz in display clock for all DCN3.2.x
216 if (clk_mgr_base->bw_params->dc_mode_limit.dispclk_mhz > 1950)
217 clk_mgr_base->bw_params->dc_mode_limit.dispclk_mhz = 1950;
218
219 if (num_entries_per_clk->num_dcfclk_levels &&
220 num_entries_per_clk->num_dtbclk_levels &&
221 num_entries_per_clk->num_dispclk_levels)
222 clk_mgr->dpm_present = true;
223
224 if (clk_mgr_base->ctx->dc->debug.min_disp_clk_khz) {
225 for (i = 0; i < num_levels; i++)
226 if (clk_mgr_base->bw_params->clk_table.entries[i].dispclk_mhz
227 < khz_to_mhz_ceil(clk_mgr_base->ctx->dc->debug.min_disp_clk_khz))
228 clk_mgr_base->bw_params->clk_table.entries[i].dispclk_mhz
229 = khz_to_mhz_ceil(clk_mgr_base->ctx->dc->debug.min_disp_clk_khz);
230 }
231 for (i = 0; i < num_levels; i++)
232 if (clk_mgr_base->bw_params->clk_table.entries[i].dispclk_mhz > 1950)
233 clk_mgr_base->bw_params->clk_table.entries[i].dispclk_mhz = 1950;
234
235 if (clk_mgr_base->ctx->dc->debug.min_dpp_clk_khz) {
236 for (i = 0; i < num_levels; i++)
237 if (clk_mgr_base->bw_params->clk_table.entries[i].dppclk_mhz
238 < khz_to_mhz_ceil(clk_mgr_base->ctx->dc->debug.min_dpp_clk_khz))
239 clk_mgr_base->bw_params->clk_table.entries[i].dppclk_mhz
240 = khz_to_mhz_ceil(clk_mgr_base->ctx->dc->debug.min_dpp_clk_khz);
241 }
242
243 /* Get UCLK, update bounding box */
244 clk_mgr_base->funcs->get_memclk_states_from_smu(clk_mgr_base);
245
246 DC_FP_START();
247 /* WM range table */
248 dcn32_build_wm_range_table(clk_mgr);
249 DC_FP_END();
250 }
251
dcn32_update_clocks_update_dtb_dto(struct clk_mgr_internal * clk_mgr,struct dc_state * context,int ref_dtbclk_khz)252 static void dcn32_update_clocks_update_dtb_dto(struct clk_mgr_internal *clk_mgr,
253 struct dc_state *context,
254 int ref_dtbclk_khz)
255 {
256 struct dccg *dccg = clk_mgr->dccg;
257 uint32_t tg_mask = 0;
258 int i;
259
260 for (i = 0; i < clk_mgr->base.ctx->dc->res_pool->pipe_count; i++) {
261 struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[i];
262 struct dtbclk_dto_params dto_params = {0};
263
264 /* use mask to program DTO once per tg */
265 if (pipe_ctx->stream_res.tg &&
266 !(tg_mask & (1 << pipe_ctx->stream_res.tg->inst))) {
267 tg_mask |= (1 << pipe_ctx->stream_res.tg->inst);
268
269 dto_params.otg_inst = pipe_ctx->stream_res.tg->inst;
270 dto_params.ref_dtbclk_khz = ref_dtbclk_khz;
271
272 dccg->funcs->set_dtbclk_dto(clk_mgr->dccg, &dto_params);
273 //dccg->funcs->set_audio_dtbclk_dto(clk_mgr->dccg, &dto_params);
274 }
275 }
276 }
277
278 /* Since DPPCLK request to PMFW needs to be exact (due to DPP DTO programming),
279 * update DPPCLK to be the exact frequency that will be set after the DPPCLK
280 * divider is updated. This will prevent rounding issues that could cause DPP
281 * refclk and DPP DTO to not match up.
282 */
dcn32_update_dppclk_dispclk_freq(struct clk_mgr_internal * clk_mgr,struct dc_clocks * new_clocks)283 static void dcn32_update_dppclk_dispclk_freq(struct clk_mgr_internal *clk_mgr, struct dc_clocks *new_clocks)
284 {
285 int dpp_divider = 0;
286 int disp_divider = 0;
287
288 if (new_clocks->dppclk_khz) {
289 dpp_divider = DENTIST_DIVIDER_RANGE_SCALE_FACTOR
290 * clk_mgr->base.dentist_vco_freq_khz / new_clocks->dppclk_khz;
291 new_clocks->dppclk_khz = (DENTIST_DIVIDER_RANGE_SCALE_FACTOR * clk_mgr->base.dentist_vco_freq_khz) / dpp_divider;
292 }
293 if (new_clocks->dispclk_khz > 0) {
294 disp_divider = DENTIST_DIVIDER_RANGE_SCALE_FACTOR
295 * clk_mgr->base.dentist_vco_freq_khz / new_clocks->dispclk_khz;
296 new_clocks->dispclk_khz = (DENTIST_DIVIDER_RANGE_SCALE_FACTOR * clk_mgr->base.dentist_vco_freq_khz) / disp_divider;
297 }
298 }
299
dcn32_update_clocks_update_dpp_dto(struct clk_mgr_internal * clk_mgr,struct dc_state * context,bool safe_to_lower)300 void dcn32_update_clocks_update_dpp_dto(struct clk_mgr_internal *clk_mgr,
301 struct dc_state *context, bool safe_to_lower)
302 {
303 int i;
304
305 clk_mgr->dccg->ref_dppclk = clk_mgr->base.clks.dppclk_khz;
306 for (i = 0; i < clk_mgr->base.ctx->dc->res_pool->pipe_count; i++) {
307 int dpp_inst = 0, dppclk_khz, prev_dppclk_khz;
308
309 dppclk_khz = context->res_ctx.pipe_ctx[i].plane_res.bw.dppclk_khz;
310
311 if (context->res_ctx.pipe_ctx[i].plane_res.dpp)
312 dpp_inst = context->res_ctx.pipe_ctx[i].plane_res.dpp->inst;
313 else if (!context->res_ctx.pipe_ctx[i].plane_res.dpp && dppclk_khz == 0) {
314 /* dpp == NULL && dppclk_khz == 0 is valid because of pipe harvesting.
315 * In this case just continue in loop
316 */
317 continue;
318 } else if (!context->res_ctx.pipe_ctx[i].plane_res.dpp && dppclk_khz > 0) {
319 /* The software state is not valid if dpp resource is NULL and
320 * dppclk_khz > 0.
321 */
322 ASSERT(false);
323 continue;
324 }
325
326 prev_dppclk_khz = clk_mgr->dccg->pipe_dppclk_khz[i];
327
328 if (safe_to_lower || prev_dppclk_khz < dppclk_khz)
329 clk_mgr->dccg->funcs->update_dpp_dto(
330 clk_mgr->dccg, dpp_inst, dppclk_khz);
331 }
332 }
333
dcn32_update_clocks_update_dentist(struct clk_mgr_internal * clk_mgr,struct dc_state * context)334 static void dcn32_update_clocks_update_dentist(
335 struct clk_mgr_internal *clk_mgr,
336 struct dc_state *context)
337 {
338 uint32_t new_disp_divider = 0;
339 uint32_t new_dispclk_wdivider = 0;
340 uint32_t old_dispclk_wdivider = 0;
341 uint32_t i;
342 uint32_t dentist_dispclk_wdivider_readback = 0;
343 struct dc *dc = clk_mgr->base.ctx->dc;
344
345 if (clk_mgr->base.clks.dispclk_khz == 0)
346 return;
347
348 new_disp_divider = DENTIST_DIVIDER_RANGE_SCALE_FACTOR
349 * clk_mgr->base.dentist_vco_freq_khz / clk_mgr->base.clks.dispclk_khz;
350
351 new_dispclk_wdivider = dentist_get_did_from_divider(new_disp_divider);
352 REG_GET(DENTIST_DISPCLK_CNTL,
353 DENTIST_DISPCLK_WDIVIDER, &old_dispclk_wdivider);
354
355 /* When changing divider to or from 127, some extra programming is required to prevent corruption */
356 if (old_dispclk_wdivider == 127 && new_dispclk_wdivider != 127) {
357 for (i = 0; i < clk_mgr->base.ctx->dc->res_pool->pipe_count; i++) {
358 struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[i];
359 uint32_t fifo_level;
360 struct dccg *dccg = clk_mgr->base.ctx->dc->res_pool->dccg;
361 struct stream_encoder *stream_enc = pipe_ctx->stream_res.stream_enc;
362 int32_t N;
363 int32_t j;
364
365 if (!resource_is_pipe_type(pipe_ctx, OTG_MASTER))
366 continue;
367 /* Virtual encoders don't have this function */
368 if (!stream_enc->funcs->get_fifo_cal_average_level)
369 continue;
370 fifo_level = stream_enc->funcs->get_fifo_cal_average_level(
371 stream_enc);
372 N = fifo_level / 4;
373 dccg->funcs->set_fifo_errdet_ovr_en(
374 dccg,
375 true);
376 for (j = 0; j < N - 4; j++)
377 dccg->funcs->otg_drop_pixel(
378 dccg,
379 pipe_ctx->stream_res.tg->inst);
380 dccg->funcs->set_fifo_errdet_ovr_en(
381 dccg,
382 false);
383 }
384 } else if (new_dispclk_wdivider == 127 && old_dispclk_wdivider != 127) {
385 /* request clock with 126 divider first */
386 uint32_t temp_disp_divider = dentist_get_divider_from_did(126);
387 uint32_t temp_dispclk_khz = (DENTIST_DIVIDER_RANGE_SCALE_FACTOR * clk_mgr->base.dentist_vco_freq_khz) / temp_disp_divider;
388
389 if (clk_mgr->smu_present)
390 dcn32_smu_set_hard_min_by_freq(clk_mgr, PPCLK_DISPCLK, khz_to_mhz_ceil(temp_dispclk_khz));
391
392 if (dc->debug.override_dispclk_programming) {
393 REG_GET(DENTIST_DISPCLK_CNTL,
394 DENTIST_DISPCLK_WDIVIDER, &dentist_dispclk_wdivider_readback);
395
396 if (dentist_dispclk_wdivider_readback != 126) {
397 REG_UPDATE(DENTIST_DISPCLK_CNTL,
398 DENTIST_DISPCLK_WDIVIDER, 126);
399 REG_WAIT(DENTIST_DISPCLK_CNTL, DENTIST_DISPCLK_CHG_DONE, 1, 50, 2000);
400 }
401 }
402
403 for (i = 0; i < clk_mgr->base.ctx->dc->res_pool->pipe_count; i++) {
404 struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[i];
405 struct dccg *dccg = clk_mgr->base.ctx->dc->res_pool->dccg;
406 struct stream_encoder *stream_enc = pipe_ctx->stream_res.stream_enc;
407 uint32_t fifo_level;
408 int32_t N;
409 int32_t j;
410
411 if (!resource_is_pipe_type(pipe_ctx, OTG_MASTER))
412 continue;
413 /* Virtual encoders don't have this function */
414 if (!stream_enc->funcs->get_fifo_cal_average_level)
415 continue;
416 fifo_level = stream_enc->funcs->get_fifo_cal_average_level(
417 stream_enc);
418 N = fifo_level / 4;
419 dccg->funcs->set_fifo_errdet_ovr_en(dccg, true);
420 for (j = 0; j < 12 - N; j++)
421 dccg->funcs->otg_add_pixel(dccg,
422 pipe_ctx->stream_res.tg->inst);
423 dccg->funcs->set_fifo_errdet_ovr_en(dccg, false);
424 }
425 }
426
427 /* do requested DISPCLK updates*/
428 if (clk_mgr->smu_present)
429 dcn32_smu_set_hard_min_by_freq(clk_mgr, PPCLK_DISPCLK, khz_to_mhz_ceil(clk_mgr->base.clks.dispclk_khz));
430
431 if (dc->debug.override_dispclk_programming) {
432 REG_GET(DENTIST_DISPCLK_CNTL,
433 DENTIST_DISPCLK_WDIVIDER, &dentist_dispclk_wdivider_readback);
434
435 if (dentist_dispclk_wdivider_readback > new_dispclk_wdivider) {
436 REG_UPDATE(DENTIST_DISPCLK_CNTL,
437 DENTIST_DISPCLK_WDIVIDER, new_dispclk_wdivider);
438 REG_WAIT(DENTIST_DISPCLK_CNTL, DENTIST_DISPCLK_CHG_DONE, 1, 50, 2000);
439 }
440 }
441
442 }
443
dcn32_get_dispclk_from_dentist(struct clk_mgr * clk_mgr_base)444 static int dcn32_get_dispclk_from_dentist(struct clk_mgr *clk_mgr_base)
445 {
446 struct clk_mgr_internal *clk_mgr = TO_CLK_MGR_INTERNAL(clk_mgr_base);
447 uint32_t dispclk_wdivider;
448 int disp_divider;
449
450 REG_GET(DENTIST_DISPCLK_CNTL, DENTIST_DISPCLK_WDIVIDER, &dispclk_wdivider);
451 disp_divider = dentist_get_divider_from_did(dispclk_wdivider);
452
453 /* Return DISPCLK freq in Khz */
454 if (disp_divider)
455 return (DENTIST_DIVIDER_RANGE_SCALE_FACTOR * clk_mgr->base.dentist_vco_freq_khz) / disp_divider;
456
457 return 0;
458 }
459
dcn32_check_native_scaling(struct pipe_ctx * pipe)460 static bool dcn32_check_native_scaling(struct pipe_ctx *pipe)
461 {
462 bool is_native_scaling = false;
463 int width = pipe->plane_state->src_rect.width;
464 int height = pipe->plane_state->src_rect.height;
465
466 if (pipe->stream->timing.h_addressable == width &&
467 pipe->stream->timing.v_addressable == height &&
468 pipe->plane_state->dst_rect.width == width &&
469 pipe->plane_state->dst_rect.height == height)
470 is_native_scaling = true;
471
472 return is_native_scaling;
473 }
474
dcn32_auto_dpm_test_log(struct dc_clocks * new_clocks,struct clk_mgr_internal * clk_mgr,struct dc_state * context)475 static void dcn32_auto_dpm_test_log(
476 struct dc_clocks *new_clocks,
477 struct clk_mgr_internal *clk_mgr,
478 struct dc_state *context)
479 {
480 unsigned int dispclk_khz_reg, dppclk_khz_reg, dprefclk_khz_reg, dcfclk_khz_reg, dtbclk_khz_reg,
481 fclk_khz_reg, mall_ss_size_bytes;
482 int dramclk_khz_override, fclk_khz_override, num_fclk_levels;
483
484 struct pipe_ctx *pipe_ctx_list[MAX_PIPES];
485 int active_pipe_count = 0;
486
487 for (int i = 0; i < MAX_PIPES; i++) {
488 struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[i];
489
490 if (pipe_ctx->stream && dc_state_get_pipe_subvp_type(context, pipe_ctx) != SUBVP_PHANTOM) {
491 pipe_ctx_list[active_pipe_count] = pipe_ctx;
492 active_pipe_count++;
493 }
494 }
495
496 mall_ss_size_bytes = context->bw_ctx.bw.dcn.mall_ss_size_bytes;
497
498 dispclk_khz_reg = REG_READ(CLK1_CLK0_CURRENT_CNT); // DISPCLK
499 dppclk_khz_reg = REG_READ(CLK1_CLK1_CURRENT_CNT); // DPPCLK
500 dprefclk_khz_reg = REG_READ(CLK1_CLK2_CURRENT_CNT); // DPREFCLK
501 dcfclk_khz_reg = REG_READ(CLK1_CLK3_CURRENT_CNT); // DCFCLK
502 dtbclk_khz_reg = REG_READ(CLK1_CLK4_CURRENT_CNT); // DTBCLK
503 fclk_khz_reg = REG_READ(CLK4_CLK0_CURRENT_CNT); // FCLK
504
505 // Overrides for these clocks in case there is no p_state change support
506 dramclk_khz_override = new_clocks->dramclk_khz;
507 fclk_khz_override = new_clocks->fclk_khz;
508
509 num_fclk_levels = clk_mgr->base.bw_params->clk_table.num_entries_per_clk.num_fclk_levels - 1;
510
511 if (!new_clocks->p_state_change_support) {
512 dramclk_khz_override = clk_mgr->base.bw_params->max_memclk_mhz * 1000;
513 }
514 if (!new_clocks->fclk_p_state_change_support) {
515 fclk_khz_override = clk_mgr->base.bw_params->clk_table.entries[num_fclk_levels].fclk_mhz * 1000;
516 }
517
518 ////////////////////////////////////////////////////////////////////////////
519 // IMPORTANT: When adding more clocks to these logs, do NOT put a newline
520 // anywhere other than at the very end of the string.
521 //
522 // Formatting example (make sure to have " - " between each entry):
523 //
524 // AutoDPMTest: clk1:%d - clk2:%d - clk3:%d - clk4:%d\n"
525 ////////////////////////////////////////////////////////////////////////////
526 if (new_clocks && active_pipe_count > 0 &&
527 new_clocks->dramclk_khz > 0 &&
528 new_clocks->fclk_khz > 0 &&
529 new_clocks->dcfclk_khz > 0 &&
530 new_clocks->dppclk_khz > 0) {
531
532 uint32_t pix_clk_list[MAX_PIPES] = {0};
533 int p_state_list[MAX_PIPES] = {0};
534 int disp_src_width_list[MAX_PIPES] = {0};
535 int disp_src_height_list[MAX_PIPES] = {0};
536 uint64_t disp_src_refresh_list[MAX_PIPES] = {0};
537 bool is_scaled_list[MAX_PIPES] = {0};
538
539 for (int i = 0; i < active_pipe_count; i++) {
540 struct pipe_ctx *curr_pipe_ctx = pipe_ctx_list[i];
541 uint64_t refresh_rate;
542
543 pix_clk_list[i] = curr_pipe_ctx->stream->timing.pix_clk_100hz;
544 p_state_list[i] = curr_pipe_ctx->p_state_type;
545
546 refresh_rate = (curr_pipe_ctx->stream->timing.pix_clk_100hz * (uint64_t)100 +
547 curr_pipe_ctx->stream->timing.v_total * curr_pipe_ctx->stream->timing.h_total - (uint64_t)1);
548 refresh_rate = div_u64(refresh_rate, curr_pipe_ctx->stream->timing.v_total);
549 refresh_rate = div_u64(refresh_rate, curr_pipe_ctx->stream->timing.h_total);
550 disp_src_refresh_list[i] = refresh_rate;
551
552 if (curr_pipe_ctx->plane_state) {
553 is_scaled_list[i] = !(dcn32_check_native_scaling(curr_pipe_ctx));
554 disp_src_width_list[i] = curr_pipe_ctx->plane_state->src_rect.width;
555 disp_src_height_list[i] = curr_pipe_ctx->plane_state->src_rect.height;
556 }
557 }
558
559 DC_LOG_AUTO_DPM_TEST("AutoDPMTest: dramclk:%d - fclk:%d - "
560 "dcfclk:%d - dppclk:%d - dispclk_hw:%d - "
561 "dppclk_hw:%d - dprefclk_hw:%d - dcfclk_hw:%d - "
562 "dtbclk_hw:%d - fclk_hw:%d - pix_clk_0:%d - pix_clk_1:%d - "
563 "pix_clk_2:%d - pix_clk_3:%d - mall_ss_size:%d - p_state_type_0:%d - "
564 "p_state_type_1:%d - p_state_type_2:%d - p_state_type_3:%d - "
565 "pix_width_0:%d - pix_height_0:%d - refresh_rate_0:%lld - is_scaled_0:%d - "
566 "pix_width_1:%d - pix_height_1:%d - refresh_rate_1:%lld - is_scaled_1:%d - "
567 "pix_width_2:%d - pix_height_2:%d - refresh_rate_2:%lld - is_scaled_2:%d - "
568 "pix_width_3:%d - pix_height_3:%d - refresh_rate_3:%lld - is_scaled_3:%d - LOG_END\n",
569 dramclk_khz_override,
570 fclk_khz_override,
571 new_clocks->dcfclk_khz,
572 new_clocks->dppclk_khz,
573 dispclk_khz_reg,
574 dppclk_khz_reg,
575 dprefclk_khz_reg,
576 dcfclk_khz_reg,
577 dtbclk_khz_reg,
578 fclk_khz_reg,
579 pix_clk_list[0], pix_clk_list[1], pix_clk_list[3], pix_clk_list[2],
580 mall_ss_size_bytes,
581 p_state_list[0], p_state_list[1], p_state_list[2], p_state_list[3],
582 disp_src_width_list[0], disp_src_height_list[0], disp_src_refresh_list[0], is_scaled_list[0],
583 disp_src_width_list[1], disp_src_height_list[1], disp_src_refresh_list[1], is_scaled_list[1],
584 disp_src_width_list[2], disp_src_height_list[2], disp_src_refresh_list[2], is_scaled_list[2],
585 disp_src_width_list[3], disp_src_height_list[3], disp_src_refresh_list[3], is_scaled_list[3]);
586 }
587 }
588
dcn32_update_clocks(struct clk_mgr * clk_mgr_base,struct dc_state * context,bool safe_to_lower)589 static void dcn32_update_clocks(struct clk_mgr *clk_mgr_base,
590 struct dc_state *context,
591 bool safe_to_lower)
592 {
593 struct clk_mgr_internal *clk_mgr = TO_CLK_MGR_INTERNAL(clk_mgr_base);
594 struct dc_clocks *new_clocks = &context->bw_ctx.bw.dcn.clk;
595 struct dc *dc = clk_mgr_base->ctx->dc;
596 int display_count;
597 bool update_dppclk = false;
598 bool update_dispclk = false;
599 bool enter_display_off = false;
600 bool dpp_clock_lowered = false;
601 struct dmcu *dmcu = clk_mgr_base->ctx->dc->res_pool->dmcu;
602 bool force_reset = false;
603 bool update_uclk = false, update_fclk = false;
604 bool p_state_change_support;
605 bool fclk_p_state_change_support;
606
607 if (clk_mgr_base->clks.dispclk_khz == 0 ||
608 (dc->debug.force_clock_mode & 0x1)) {
609 /* This is from resume or boot up, if forced_clock cfg option used,
610 * we bypass program dispclk and DPPCLK, but need set them for S3.
611 */
612 force_reset = true;
613
614 dcn2_read_clocks_from_hw_dentist(clk_mgr_base);
615
616 /* Force_clock_mode 0x1: force reset the clock even it is the same clock
617 * as long as it is in Passive level.
618 */
619 }
620 display_count = clk_mgr_helper_get_active_display_cnt(dc, context);
621
622 if (display_count == 0)
623 enter_display_off = true;
624
625 if (clk_mgr->smu_present) {
626 if (enter_display_off == safe_to_lower)
627 dcn30_smu_set_num_of_displays(clk_mgr, display_count);
628
629 clk_mgr_base->clks.fclk_prev_p_state_change_support = clk_mgr_base->clks.fclk_p_state_change_support;
630
631 fclk_p_state_change_support = new_clocks->fclk_p_state_change_support;
632
633 if (should_update_pstate_support(safe_to_lower, fclk_p_state_change_support, clk_mgr_base->clks.fclk_p_state_change_support) &&
634 !dc->work_arounds.clock_update_disable_mask.fclk) {
635 clk_mgr_base->clks.fclk_p_state_change_support = fclk_p_state_change_support;
636
637 /* To enable FCLK P-state switching, send FCLK_PSTATE_SUPPORTED message to PMFW */
638 if (clk_mgr_base->ctx->dce_version != DCN_VERSION_3_21 && clk_mgr_base->clks.fclk_p_state_change_support) {
639 /* Handle the code for sending a message to PMFW that FCLK P-state change is supported */
640 dcn32_smu_send_fclk_pstate_message(clk_mgr, FCLK_PSTATE_SUPPORTED);
641 }
642 }
643
644 if (dc->debug.force_min_dcfclk_mhz > 0)
645 new_clocks->dcfclk_khz = (new_clocks->dcfclk_khz > (dc->debug.force_min_dcfclk_mhz * 1000)) ?
646 new_clocks->dcfclk_khz : (dc->debug.force_min_dcfclk_mhz * 1000);
647
648 if (should_set_clock(safe_to_lower, new_clocks->dcfclk_khz, clk_mgr_base->clks.dcfclk_khz) &&
649 !dc->work_arounds.clock_update_disable_mask.dcfclk) {
650 clk_mgr_base->clks.dcfclk_khz = new_clocks->dcfclk_khz;
651 dcn32_smu_set_hard_min_by_freq(clk_mgr, PPCLK_DCFCLK, khz_to_mhz_ceil(clk_mgr_base->clks.dcfclk_khz));
652 }
653
654 if (should_set_clock(safe_to_lower, new_clocks->dcfclk_deep_sleep_khz, clk_mgr_base->clks.dcfclk_deep_sleep_khz) &&
655 !dc->work_arounds.clock_update_disable_mask.dcfclk_ds) {
656 clk_mgr_base->clks.dcfclk_deep_sleep_khz = new_clocks->dcfclk_deep_sleep_khz;
657 dcn30_smu_set_min_deep_sleep_dcef_clk(clk_mgr, khz_to_mhz_ceil(clk_mgr_base->clks.dcfclk_deep_sleep_khz));
658 }
659
660 if (should_set_clock(safe_to_lower, new_clocks->socclk_khz, clk_mgr_base->clks.socclk_khz))
661 /* We don't actually care about socclk, don't notify SMU of hard min */
662 clk_mgr_base->clks.socclk_khz = new_clocks->socclk_khz;
663
664 clk_mgr_base->clks.prev_p_state_change_support = clk_mgr_base->clks.p_state_change_support;
665 clk_mgr_base->clks.prev_num_ways = clk_mgr_base->clks.num_ways;
666
667 if (clk_mgr_base->clks.num_ways != new_clocks->num_ways &&
668 clk_mgr_base->clks.num_ways < new_clocks->num_ways) {
669 clk_mgr_base->clks.num_ways = new_clocks->num_ways;
670 dcn32_smu_send_cab_for_uclk_message(clk_mgr, clk_mgr_base->clks.num_ways);
671 }
672
673 p_state_change_support = new_clocks->p_state_change_support;
674 if (should_update_pstate_support(safe_to_lower, p_state_change_support, clk_mgr_base->clks.p_state_change_support) &&
675 !dc->work_arounds.clock_update_disable_mask.uclk) {
676 clk_mgr_base->clks.p_state_change_support = p_state_change_support;
677
678 /* to disable P-State switching, set UCLK min = max */
679 if (!clk_mgr_base->clks.p_state_change_support) {
680 if (dc->clk_mgr->dc_mode_softmax_enabled) {
681 /* On DCN32x we will never have the functional UCLK min above the softmax
682 * since we calculate mode support based on softmax being the max UCLK
683 * frequency.
684 */
685 dcn32_smu_set_hard_min_by_freq(clk_mgr, PPCLK_UCLK,
686 dc->clk_mgr->bw_params->dc_mode_softmax_memclk);
687 } else {
688 dcn32_smu_set_hard_min_by_freq(clk_mgr, PPCLK_UCLK, dc->clk_mgr->bw_params->max_memclk_mhz);
689 }
690 }
691 }
692
693 if (context->bw_ctx.bw.dcn.clk.fw_based_mclk_switching)
694 dcn32_smu_wait_for_dmub_ack_mclk(clk_mgr, true);
695 else
696 dcn32_smu_wait_for_dmub_ack_mclk(clk_mgr, false);
697
698 /* Always update saved value, even if new value not set due to P-State switching unsupported. Also check safe_to_lower for FCLK */
699 if (safe_to_lower && (clk_mgr_base->clks.fclk_p_state_change_support != clk_mgr_base->clks.fclk_prev_p_state_change_support)) {
700 update_fclk = true;
701 }
702
703 if (clk_mgr_base->ctx->dce_version != DCN_VERSION_3_21 && !clk_mgr_base->clks.fclk_p_state_change_support && update_fclk &&
704 !dc->work_arounds.clock_update_disable_mask.fclk) {
705 /* Handle code for sending a message to PMFW that FCLK P-state change is not supported */
706 dcn32_smu_send_fclk_pstate_message(clk_mgr, FCLK_PSTATE_NOTSUPPORTED);
707 }
708
709 /* Always update saved value, even if new value not set due to P-State switching unsupported */
710 if (should_set_clock(safe_to_lower, new_clocks->dramclk_khz, clk_mgr_base->clks.dramclk_khz) &&
711 !dc->work_arounds.clock_update_disable_mask.uclk) {
712 clk_mgr_base->clks.dramclk_khz = new_clocks->dramclk_khz;
713 update_uclk = true;
714 }
715
716 /* set UCLK to requested value if P-State switching is supported, or to re-enable P-State switching */
717 if (clk_mgr_base->clks.p_state_change_support &&
718 (update_uclk || !clk_mgr_base->clks.prev_p_state_change_support) &&
719 !dc->work_arounds.clock_update_disable_mask.uclk)
720 dcn32_smu_set_hard_min_by_freq(clk_mgr, PPCLK_UCLK, khz_to_mhz_ceil(clk_mgr_base->clks.dramclk_khz));
721
722 if (clk_mgr_base->clks.num_ways != new_clocks->num_ways &&
723 clk_mgr_base->clks.num_ways > new_clocks->num_ways) {
724 clk_mgr_base->clks.num_ways = new_clocks->num_ways;
725 dcn32_smu_send_cab_for_uclk_message(clk_mgr, clk_mgr_base->clks.num_ways);
726 }
727 }
728
729 dcn32_update_dppclk_dispclk_freq(clk_mgr, new_clocks);
730 if (should_set_clock(safe_to_lower, new_clocks->dppclk_khz, clk_mgr_base->clks.dppclk_khz)) {
731 if (clk_mgr_base->clks.dppclk_khz > new_clocks->dppclk_khz)
732 dpp_clock_lowered = true;
733
734 clk_mgr_base->clks.dppclk_khz = new_clocks->dppclk_khz;
735
736 if (clk_mgr->smu_present && !dpp_clock_lowered)
737 dcn32_smu_set_hard_min_by_freq(clk_mgr, PPCLK_DPPCLK, khz_to_mhz_ceil(clk_mgr_base->clks.dppclk_khz));
738
739 update_dppclk = true;
740 }
741
742 if (should_set_clock(safe_to_lower, new_clocks->dispclk_khz, clk_mgr_base->clks.dispclk_khz)) {
743 clk_mgr_base->clks.dispclk_khz = new_clocks->dispclk_khz;
744
745 update_dispclk = true;
746 }
747
748 if (!new_clocks->dtbclk_en) {
749 new_clocks->ref_dtbclk_khz = clk_mgr_base->bw_params->clk_table.entries[0].dtbclk_mhz * 1000;
750 }
751
752 /* clock limits are received with MHz precision, divide by 1000 to prevent setting clocks at every call */
753 if (!dc->debug.disable_dtb_ref_clk_switch &&
754 should_set_clock(safe_to_lower, new_clocks->ref_dtbclk_khz / 1000, clk_mgr_base->clks.ref_dtbclk_khz / 1000)) {
755 /* DCCG requires KHz precision for DTBCLK */
756 clk_mgr_base->clks.ref_dtbclk_khz =
757 dcn32_smu_set_hard_min_by_freq(clk_mgr, PPCLK_DTBCLK, khz_to_mhz_ceil(new_clocks->ref_dtbclk_khz));
758
759 dcn32_update_clocks_update_dtb_dto(clk_mgr, context, clk_mgr_base->clks.ref_dtbclk_khz);
760 }
761
762 if (dc->config.forced_clocks == false || (force_reset && safe_to_lower)) {
763 if (dpp_clock_lowered) {
764 /* if clock is being lowered, increase DTO before lowering refclk */
765 dcn32_update_clocks_update_dpp_dto(clk_mgr, context, safe_to_lower);
766 dcn32_update_clocks_update_dentist(clk_mgr, context);
767 if (clk_mgr->smu_present)
768 dcn32_smu_set_hard_min_by_freq(clk_mgr, PPCLK_DPPCLK, khz_to_mhz_ceil(clk_mgr_base->clks.dppclk_khz));
769 } else {
770 /* if clock is being raised, increase refclk before lowering DTO */
771 if (update_dppclk || update_dispclk)
772 dcn32_update_clocks_update_dentist(clk_mgr, context);
773 /* There is a check inside dcn20_update_clocks_update_dpp_dto which ensures
774 * that we do not lower dto when it is not safe to lower. We do not need to
775 * compare the current and new dppclk before calling this function.
776 */
777 dcn32_update_clocks_update_dpp_dto(clk_mgr, context, safe_to_lower);
778 }
779 }
780
781 if (update_dispclk && dmcu && dmcu->funcs->is_dmcu_initialized(dmcu))
782 /*update dmcu for wait_loop count*/
783 dmcu->funcs->set_psr_wait_loop(dmcu,
784 clk_mgr_base->clks.dispclk_khz / 1000 / 7);
785
786 if (dc->config.enable_auto_dpm_test_logs) {
787 dcn32_auto_dpm_test_log(new_clocks, clk_mgr, context);
788 }
789 }
790
dcn32_get_vco_frequency_from_reg(struct clk_mgr_internal * clk_mgr)791 static uint32_t dcn32_get_vco_frequency_from_reg(struct clk_mgr_internal *clk_mgr)
792 {
793 struct fixed31_32 pll_req;
794 uint32_t pll_req_reg = 0;
795
796 /* get FbMult value */
797 if (ASICREV_IS_GC_11_0_2(clk_mgr->base.ctx->asic_id.hw_internal_rev))
798 pll_req_reg = REG_READ(CLK0_CLK_PLL_REQ);
799 else
800 pll_req_reg = REG_READ(CLK1_CLK_PLL_REQ);
801
802 /* set up a fixed-point number
803 * this works because the int part is on the right edge of the register
804 * and the frac part is on the left edge
805 */
806 pll_req = dc_fixpt_from_int(pll_req_reg & clk_mgr->clk_mgr_mask->FbMult_int);
807 pll_req.value |= pll_req_reg & clk_mgr->clk_mgr_mask->FbMult_frac;
808
809 /* multiply by REFCLK period */
810 pll_req = dc_fixpt_mul_int(pll_req, clk_mgr->dfs_ref_freq_khz);
811
812 return dc_fixpt_floor(pll_req);
813 }
814
dcn32_dump_clk_registers(struct clk_state_registers_and_bypass * regs_and_bypass,struct clk_mgr * clk_mgr_base,struct clk_log_info * log_info)815 static void dcn32_dump_clk_registers(struct clk_state_registers_and_bypass *regs_and_bypass,
816 struct clk_mgr *clk_mgr_base, struct clk_log_info *log_info)
817 {
818 struct clk_mgr_internal *clk_mgr = TO_CLK_MGR_INTERNAL(clk_mgr_base);
819 uint32_t dprefclk_did = 0;
820 uint32_t dcfclk_did = 0;
821 uint32_t dtbclk_did = 0;
822 uint32_t dispclk_did = 0;
823 uint32_t dppclk_did = 0;
824 uint32_t target_div = 0;
825
826 if (ASICREV_IS_GC_11_0_2(clk_mgr->base.ctx->asic_id.hw_internal_rev)) {
827 /* DFS Slice 0 is used for DISPCLK */
828 dispclk_did = REG_READ(CLK0_CLK0_DFS_CNTL);
829 /* DFS Slice 1 is used for DPPCLK */
830 dppclk_did = REG_READ(CLK0_CLK1_DFS_CNTL);
831 /* DFS Slice 2 is used for DPREFCLK */
832 dprefclk_did = REG_READ(CLK0_CLK2_DFS_CNTL);
833 /* DFS Slice 3 is used for DCFCLK */
834 dcfclk_did = REG_READ(CLK0_CLK3_DFS_CNTL);
835 /* DFS Slice 4 is used for DTBCLK */
836 dtbclk_did = REG_READ(CLK0_CLK4_DFS_CNTL);
837 } else {
838 /* DFS Slice 0 is used for DISPCLK */
839 dispclk_did = REG_READ(CLK1_CLK0_DFS_CNTL);
840 /* DFS Slice 1 is used for DPPCLK */
841 dppclk_did = REG_READ(CLK1_CLK1_DFS_CNTL);
842 /* DFS Slice 2 is used for DPREFCLK */
843 dprefclk_did = REG_READ(CLK1_CLK2_DFS_CNTL);
844 /* DFS Slice 3 is used for DCFCLK */
845 dcfclk_did = REG_READ(CLK1_CLK3_DFS_CNTL);
846 /* DFS Slice 4 is used for DTBCLK */
847 dtbclk_did = REG_READ(CLK1_CLK4_DFS_CNTL);
848 }
849
850 /* Convert DISPCLK DFS Slice DID to divider*/
851 target_div = dentist_get_divider_from_did(dispclk_did);
852 //Get dispclk in khz
853 regs_and_bypass->dispclk = (DENTIST_DIVIDER_RANGE_SCALE_FACTOR
854 * clk_mgr->base.dentist_vco_freq_khz) / target_div;
855
856 /* Convert DISPCLK DFS Slice DID to divider*/
857 target_div = dentist_get_divider_from_did(dppclk_did);
858 //Get dppclk in khz
859 regs_and_bypass->dppclk = (DENTIST_DIVIDER_RANGE_SCALE_FACTOR
860 * clk_mgr->base.dentist_vco_freq_khz) / target_div;
861
862 /* Convert DPREFCLK DFS Slice DID to divider*/
863 target_div = dentist_get_divider_from_did(dprefclk_did);
864 //Get dprefclk in khz
865 regs_and_bypass->dprefclk = (DENTIST_DIVIDER_RANGE_SCALE_FACTOR
866 * clk_mgr->base.dentist_vco_freq_khz) / target_div;
867
868 /* Convert DCFCLK DFS Slice DID to divider*/
869 target_div = dentist_get_divider_from_did(dcfclk_did);
870 //Get dcfclk in khz
871 regs_and_bypass->dcfclk = (DENTIST_DIVIDER_RANGE_SCALE_FACTOR
872 * clk_mgr->base.dentist_vco_freq_khz) / target_div;
873
874 /* Convert DTBCLK DFS Slice DID to divider*/
875 target_div = dentist_get_divider_from_did(dtbclk_did);
876 //Get dtbclk in khz
877 regs_and_bypass->dtbclk = (DENTIST_DIVIDER_RANGE_SCALE_FACTOR
878 * clk_mgr->base.dentist_vco_freq_khz) / target_div;
879 }
880
dcn32_clock_read_ss_info(struct clk_mgr_internal * clk_mgr)881 static void dcn32_clock_read_ss_info(struct clk_mgr_internal *clk_mgr)
882 {
883 struct dc_bios *bp = clk_mgr->base.ctx->dc_bios;
884 int ss_info_num = bp->funcs->get_ss_entry_number(
885 bp, AS_SIGNAL_TYPE_GPU_PLL);
886
887 if (ss_info_num) {
888 struct spread_spectrum_info info = { { 0 } };
889 enum bp_result result = bp->funcs->get_spread_spectrum_info(
890 bp, AS_SIGNAL_TYPE_GPU_PLL, 0, &info);
891
892 /* SSInfo.spreadSpectrumPercentage !=0 would be sign
893 * that SS is enabled
894 */
895 if (result == BP_RESULT_OK &&
896 info.spread_spectrum_percentage != 0) {
897 clk_mgr->ss_on_dprefclk = true;
898 clk_mgr->dprefclk_ss_divider = info.spread_percentage_divider;
899
900 if (info.type.CENTER_MODE == 0) {
901 /* Currently for DP Reference clock we
902 * need only SS percentage for
903 * downspread
904 */
905 clk_mgr->dprefclk_ss_percentage =
906 info.spread_spectrum_percentage;
907 }
908 }
909 }
910 }
dcn32_notify_wm_ranges(struct clk_mgr * clk_mgr_base)911 static void dcn32_notify_wm_ranges(struct clk_mgr *clk_mgr_base)
912 {
913 unsigned int i;
914 struct clk_mgr_internal *clk_mgr = TO_CLK_MGR_INTERNAL(clk_mgr_base);
915 WatermarksExternal_t *table = (WatermarksExternal_t *) clk_mgr->wm_range_table;
916
917 if (!clk_mgr->smu_present)
918 return;
919
920 if (!table)
921 return;
922
923 memset(table, 0, sizeof(*table));
924
925 /* collect valid ranges, place in pmfw table */
926 for (i = 0; i < WM_SET_COUNT; i++)
927 if (clk_mgr->base.bw_params->wm_table.nv_entries[i].valid) {
928 table->Watermarks.WatermarkRow[i].WmSetting = i;
929 table->Watermarks.WatermarkRow[i].Flags = clk_mgr->base.bw_params->wm_table.nv_entries[i].pmfw_breakdown.wm_type;
930 }
931 dcn30_smu_set_dram_addr_high(clk_mgr, clk_mgr->wm_range_table_addr >> 32);
932 dcn30_smu_set_dram_addr_low(clk_mgr, clk_mgr->wm_range_table_addr & 0xFFFFFFFF);
933 dcn32_smu_transfer_wm_table_dram_2_smu(clk_mgr);
934 }
935
936 /* Set min memclk to minimum, either constrained by the current mode or DPM0 */
dcn32_set_hard_min_memclk(struct clk_mgr * clk_mgr_base,bool current_mode)937 static void dcn32_set_hard_min_memclk(struct clk_mgr *clk_mgr_base, bool current_mode)
938 {
939 struct clk_mgr_internal *clk_mgr = TO_CLK_MGR_INTERNAL(clk_mgr_base);
940
941 if (!clk_mgr->smu_present)
942 return;
943
944 if (current_mode) {
945 if (clk_mgr_base->clks.p_state_change_support)
946 dcn32_smu_set_hard_min_by_freq(clk_mgr, PPCLK_UCLK,
947 khz_to_mhz_ceil(clk_mgr_base->clks.dramclk_khz));
948 else
949 dcn32_smu_set_hard_min_by_freq(clk_mgr, PPCLK_UCLK,
950 clk_mgr_base->bw_params->max_memclk_mhz);
951 } else {
952 dcn32_smu_set_hard_min_by_freq(clk_mgr, PPCLK_UCLK,
953 clk_mgr_base->bw_params->clk_table.entries[0].memclk_mhz);
954 }
955 }
956
957 /* Set max memclk to highest DPM value */
dcn32_set_hard_max_memclk(struct clk_mgr * clk_mgr_base)958 static void dcn32_set_hard_max_memclk(struct clk_mgr *clk_mgr_base)
959 {
960 struct clk_mgr_internal *clk_mgr = TO_CLK_MGR_INTERNAL(clk_mgr_base);
961
962 if (!clk_mgr->smu_present)
963 return;
964
965 dcn30_smu_set_hard_max_by_freq(clk_mgr, PPCLK_UCLK, clk_mgr_base->bw_params->max_memclk_mhz);
966 }
967
968 /* Get current memclk states, update bounding box */
dcn32_get_memclk_states_from_smu(struct clk_mgr * clk_mgr_base)969 static void dcn32_get_memclk_states_from_smu(struct clk_mgr *clk_mgr_base)
970 {
971 struct clk_mgr_internal *clk_mgr = TO_CLK_MGR_INTERNAL(clk_mgr_base);
972 struct clk_limit_num_entries *num_entries_per_clk = &clk_mgr_base->bw_params->clk_table.num_entries_per_clk;
973 unsigned int num_levels;
974
975 if (!clk_mgr->smu_present)
976 return;
977
978 /* Refresh memclk and fclk states */
979 dcn32_init_single_clock(clk_mgr, PPCLK_UCLK,
980 &clk_mgr_base->bw_params->clk_table.entries[0].memclk_mhz,
981 &num_entries_per_clk->num_memclk_levels);
982 clk_mgr_base->bw_params->dc_mode_limit.memclk_mhz = dcn30_smu_get_dc_mode_max_dpm_freq(clk_mgr, PPCLK_UCLK);
983 clk_mgr_base->bw_params->dc_mode_softmax_memclk = clk_mgr_base->bw_params->dc_mode_limit.memclk_mhz;
984
985 /* memclk must have at least one level */
986 num_entries_per_clk->num_memclk_levels = num_entries_per_clk->num_memclk_levels ? num_entries_per_clk->num_memclk_levels : 1;
987
988 dcn32_init_single_clock(clk_mgr, PPCLK_FCLK,
989 &clk_mgr_base->bw_params->clk_table.entries[0].fclk_mhz,
990 &num_entries_per_clk->num_fclk_levels);
991 clk_mgr_base->bw_params->dc_mode_limit.fclk_mhz = dcn30_smu_get_dc_mode_max_dpm_freq(clk_mgr, PPCLK_FCLK);
992
993 if (num_entries_per_clk->num_memclk_levels >= num_entries_per_clk->num_fclk_levels) {
994 num_levels = num_entries_per_clk->num_memclk_levels;
995 } else {
996 num_levels = num_entries_per_clk->num_fclk_levels;
997 }
998 clk_mgr_base->bw_params->max_memclk_mhz =
999 clk_mgr_base->bw_params->clk_table.entries[num_entries_per_clk->num_memclk_levels - 1].memclk_mhz;
1000 clk_mgr_base->bw_params->clk_table.num_entries = num_levels ? num_levels : 1;
1001
1002 if (clk_mgr->dpm_present && !num_levels)
1003 clk_mgr->dpm_present = false;
1004
1005 if (!clk_mgr->dpm_present)
1006 dcn32_patch_dpm_table(clk_mgr_base->bw_params);
1007
1008 DC_FP_START();
1009 /* Refresh bounding box */
1010 clk_mgr_base->ctx->dc->res_pool->funcs->update_bw_bounding_box(
1011 clk_mgr->base.ctx->dc, clk_mgr_base->bw_params);
1012 DC_FP_END();
1013 }
1014
dcn32_are_clock_states_equal(struct dc_clocks * a,struct dc_clocks * b)1015 static bool dcn32_are_clock_states_equal(struct dc_clocks *a,
1016 struct dc_clocks *b)
1017 {
1018 if (a->dispclk_khz != b->dispclk_khz)
1019 return false;
1020 else if (a->dppclk_khz != b->dppclk_khz)
1021 return false;
1022 else if (a->dcfclk_khz != b->dcfclk_khz)
1023 return false;
1024 else if (a->dcfclk_deep_sleep_khz != b->dcfclk_deep_sleep_khz)
1025 return false;
1026 else if (a->dramclk_khz != b->dramclk_khz)
1027 return false;
1028 else if (a->p_state_change_support != b->p_state_change_support)
1029 return false;
1030 else if (a->fclk_p_state_change_support != b->fclk_p_state_change_support)
1031 return false;
1032
1033 return true;
1034 }
1035
dcn32_enable_pme_wa(struct clk_mgr * clk_mgr_base)1036 static void dcn32_enable_pme_wa(struct clk_mgr *clk_mgr_base)
1037 {
1038 struct clk_mgr_internal *clk_mgr = TO_CLK_MGR_INTERNAL(clk_mgr_base);
1039
1040 if (!clk_mgr->smu_present)
1041 return;
1042
1043 dcn32_smu_set_pme_workaround(clk_mgr);
1044 }
1045
dcn32_is_smu_present(struct clk_mgr * clk_mgr_base)1046 static bool dcn32_is_smu_present(struct clk_mgr *clk_mgr_base)
1047 {
1048 struct clk_mgr_internal *clk_mgr = TO_CLK_MGR_INTERNAL(clk_mgr_base);
1049 return clk_mgr->smu_present;
1050 }
1051
dcn32_set_max_memclk(struct clk_mgr * clk_mgr_base,unsigned int memclk_mhz)1052 static void dcn32_set_max_memclk(struct clk_mgr *clk_mgr_base, unsigned int memclk_mhz)
1053 {
1054 struct clk_mgr_internal *clk_mgr = TO_CLK_MGR_INTERNAL(clk_mgr_base);
1055
1056 if (!clk_mgr->smu_present)
1057 return;
1058
1059 dcn30_smu_set_hard_max_by_freq(clk_mgr, PPCLK_UCLK, memclk_mhz);
1060 }
1061
dcn32_set_min_memclk(struct clk_mgr * clk_mgr_base,unsigned int memclk_mhz)1062 static void dcn32_set_min_memclk(struct clk_mgr *clk_mgr_base, unsigned int memclk_mhz)
1063 {
1064 struct clk_mgr_internal *clk_mgr = TO_CLK_MGR_INTERNAL(clk_mgr_base);
1065
1066 if (!clk_mgr->smu_present)
1067 return;
1068
1069 dcn32_smu_set_hard_min_by_freq(clk_mgr, PPCLK_UCLK, memclk_mhz);
1070 }
1071
1072 static struct clk_mgr_funcs dcn32_funcs = {
1073 .get_dp_ref_clk_frequency = dce12_get_dp_ref_freq_khz,
1074 .get_dtb_ref_clk_frequency = dcn31_get_dtb_ref_freq_khz,
1075 .update_clocks = dcn32_update_clocks,
1076 .dump_clk_registers = dcn32_dump_clk_registers,
1077 .init_clocks = dcn32_init_clocks,
1078 .notify_wm_ranges = dcn32_notify_wm_ranges,
1079 .set_hard_min_memclk = dcn32_set_hard_min_memclk,
1080 .set_hard_max_memclk = dcn32_set_hard_max_memclk,
1081 .set_max_memclk = dcn32_set_max_memclk,
1082 .set_min_memclk = dcn32_set_min_memclk,
1083 .get_memclk_states_from_smu = dcn32_get_memclk_states_from_smu,
1084 .are_clock_states_equal = dcn32_are_clock_states_equal,
1085 .enable_pme_wa = dcn32_enable_pme_wa,
1086 .is_smu_present = dcn32_is_smu_present,
1087 .get_dispclk_from_dentist = dcn32_get_dispclk_from_dentist,
1088 };
1089
dcn32_clk_mgr_construct(struct dc_context * ctx,struct clk_mgr_internal * clk_mgr,struct pp_smu_funcs * pp_smu,struct dccg * dccg)1090 void dcn32_clk_mgr_construct(
1091 struct dc_context *ctx,
1092 struct clk_mgr_internal *clk_mgr,
1093 struct pp_smu_funcs *pp_smu,
1094 struct dccg *dccg)
1095 {
1096 struct clk_log_info log_info = {0};
1097
1098 clk_mgr->base.ctx = ctx;
1099 clk_mgr->base.funcs = &dcn32_funcs;
1100 if (ASICREV_IS_GC_11_0_2(clk_mgr->base.ctx->asic_id.hw_internal_rev)) {
1101 clk_mgr->regs = &clk_mgr_regs_dcn321;
1102 clk_mgr->clk_mgr_shift = &clk_mgr_shift_dcn321;
1103 clk_mgr->clk_mgr_mask = &clk_mgr_mask_dcn321;
1104 } else {
1105 clk_mgr->regs = &clk_mgr_regs_dcn32;
1106 clk_mgr->clk_mgr_shift = &clk_mgr_shift_dcn32;
1107 clk_mgr->clk_mgr_mask = &clk_mgr_mask_dcn32;
1108 }
1109
1110 clk_mgr->dccg = dccg;
1111 clk_mgr->dfs_bypass_disp_clk = 0;
1112
1113 clk_mgr->dprefclk_ss_percentage = 0;
1114 clk_mgr->dprefclk_ss_divider = 1000;
1115 clk_mgr->ss_on_dprefclk = false;
1116 clk_mgr->dfs_ref_freq_khz = 100000;
1117
1118 /* Changed from DCN3.2_clock_frequency doc to match
1119 * dcn32_dump_clk_registers from 4 * dentist_vco_freq_khz /
1120 * dprefclk DID divider
1121 */
1122 clk_mgr->base.dprefclk_khz = 716666;
1123 if (ctx->dc->debug.disable_dtb_ref_clk_switch) {
1124 //initialize DTB ref clock value if DPM disabled
1125 if (ctx->dce_version == DCN_VERSION_3_21)
1126 clk_mgr->base.clks.ref_dtbclk_khz = 477800;
1127 else
1128 clk_mgr->base.clks.ref_dtbclk_khz = 268750;
1129 }
1130
1131
1132 /* integer part is now VCO frequency in kHz */
1133 clk_mgr->base.dentist_vco_freq_khz = dcn32_get_vco_frequency_from_reg(clk_mgr);
1134
1135 /* in case we don't get a value from the register, use default */
1136 if (clk_mgr->base.dentist_vco_freq_khz == 0)
1137 clk_mgr->base.dentist_vco_freq_khz = 4300000; /* Updated as per HW docs */
1138
1139 dcn32_dump_clk_registers(&clk_mgr->base.boot_snapshot, &clk_mgr->base, &log_info);
1140
1141 if (ctx->dc->debug.disable_dtb_ref_clk_switch &&
1142 clk_mgr->base.clks.ref_dtbclk_khz != clk_mgr->base.boot_snapshot.dtbclk) {
1143 clk_mgr->base.clks.ref_dtbclk_khz = clk_mgr->base.boot_snapshot.dtbclk;
1144 }
1145
1146 if (clk_mgr->base.boot_snapshot.dprefclk != 0) {
1147 clk_mgr->base.dprefclk_khz = clk_mgr->base.boot_snapshot.dprefclk;
1148 }
1149 dcn32_clock_read_ss_info(clk_mgr);
1150
1151 clk_mgr->dfs_bypass_enabled = false;
1152
1153 clk_mgr->smu_present = false;
1154
1155 clk_mgr->base.bw_params = kzalloc(sizeof(*clk_mgr->base.bw_params), GFP_KERNEL);
1156
1157 /* need physical address of table to give to PMFW */
1158 clk_mgr->wm_range_table = dm_helpers_allocate_gpu_mem(clk_mgr->base.ctx,
1159 DC_MEM_ALLOC_TYPE_GART, sizeof(WatermarksExternal_t),
1160 &clk_mgr->wm_range_table_addr);
1161 }
1162
dcn32_clk_mgr_destroy(struct clk_mgr_internal * clk_mgr)1163 void dcn32_clk_mgr_destroy(struct clk_mgr_internal *clk_mgr)
1164 {
1165 kfree(clk_mgr->base.bw_params);
1166
1167 if (clk_mgr->wm_range_table)
1168 dm_helpers_free_gpu_mem(clk_mgr->base.ctx, DC_MEM_ALLOC_TYPE_GART,
1169 clk_mgr->wm_range_table);
1170 }
1171
1172