1 // SPDX-License-Identifier: MIT
2 /*
3 * Copyright 2022 Advanced Micro Devices, Inc.
4 *
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the "Software"),
7 * to deal in the Software without restriction, including without limitation
8 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
9 * and/or sell copies of the Software, and to permit persons to whom the
10 * Software is furnished to do so, subject to the following conditions:
11 *
12 * The above copyright notice and this permission notice shall be included in
13 * all copies or substantial portions of the Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
19 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
20 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
21 * OTHER DEALINGS IN THE SOFTWARE.
22 *
23 * Authors: AMD
24 *
25 */
26
27
28 #include "dm_services.h"
29 #include "dc.h"
30
31 #include "dcn31/dcn31_init.h"
32 #include "dcn314/dcn314_init.h"
33
34 #include "resource.h"
35 #include "include/irq_service_interface.h"
36 #include "dcn314_resource.h"
37
38 #include "dcn20/dcn20_resource.h"
39 #include "dcn30/dcn30_resource.h"
40 #include "dcn31/dcn31_resource.h"
41
42 #include "dcn10/dcn10_ipp.h"
43 #include "dcn30/dcn30_hubbub.h"
44 #include "dcn31/dcn31_hubbub.h"
45 #include "dcn30/dcn30_mpc.h"
46 #include "dcn31/dcn31_hubp.h"
47 #include "irq/dcn31/irq_service_dcn31.h"
48 #include "irq/dcn314/irq_service_dcn314.h"
49 #include "dcn30/dcn30_dpp.h"
50 #include "dcn314/dcn314_optc.h"
51 #include "dcn20/dcn20_hwseq.h"
52 #include "dcn30/dcn30_hwseq.h"
53 #include "dce110/dce110_hwseq.h"
54 #include "dcn30/dcn30_opp.h"
55 #include "dcn20/dcn20_dsc.h"
56 #include "dcn30/dcn30_vpg.h"
57 #include "dcn30/dcn30_afmt.h"
58 #include "dcn31/dcn31_dio_link_encoder.h"
59 #include "dcn314/dcn314_dio_stream_encoder.h"
60 #include "dcn31/dcn31_hpo_dp_stream_encoder.h"
61 #include "dcn31/dcn31_hpo_dp_link_encoder.h"
62 #include "dcn31/dcn31_apg.h"
63 #include "dcn31/dcn31_vpg.h"
64 #include "dcn31/dcn31_afmt.h"
65 #include "dce/dce_clock_source.h"
66 #include "dce/dce_audio.h"
67 #include "dce/dce_hwseq.h"
68 #include "clk_mgr.h"
69 #include "dio/dcn10/dcn10_dio.h"
70 #include "dio/virtual/virtual_stream_encoder.h"
71 #include "dce110/dce110_resource.h"
72 #include "dml/display_mode_vba.h"
73 #include "dml/dcn31/dcn31_fpu.h"
74 #include "dml/dcn314/dcn314_fpu.h"
75 #include "dcn314/dcn314_dccg.h"
76 #include "dcn10/dcn10_resource.h"
77 #include "dcn31/dcn31_panel_cntl.h"
78 #include "dcn314/dcn314_hwseq.h"
79
80 #include "dcn30/dcn30_dwb.h"
81 #include "dcn30/dcn30_mmhubbub.h"
82
83 #include "dcn/dcn_3_1_4_offset.h"
84 #include "dcn/dcn_3_1_4_sh_mask.h"
85 #include "dpcs/dpcs_3_1_4_offset.h"
86 #include "dpcs/dpcs_3_1_4_sh_mask.h"
87
88 #define DCHUBBUB_DEBUG_CTRL_0__DET_DEPTH__SHIFT 0x10
89 #define DCHUBBUB_DEBUG_CTRL_0__DET_DEPTH_MASK 0x01FF0000L
90
91 #define DSCC0_DSCC_CONFIG0__ICH_RESET_AT_END_OF_LINE__SHIFT 0x0
92 #define DSCC0_DSCC_CONFIG0__ICH_RESET_AT_END_OF_LINE_MASK 0x0000000FL
93
94 #include "reg_helper.h"
95 #include "dce/dmub_abm.h"
96 #include "dce/dmub_psr.h"
97 #include "dce/dmub_replay.h"
98 #include "dce/dce_aux.h"
99 #include "dce/dce_i2c.h"
100 #include "dml/dcn314/display_mode_vba_314.h"
101 #include "vm_helper.h"
102 #include "dcn20/dcn20_vmid.h"
103
104 #include "link_enc_cfg.h"
105
106 #define DCN_BASE__INST0_SEG1 0x000000C0
107 #define DCN_BASE__INST0_SEG2 0x000034C0
108 #define DCN_BASE__INST0_SEG3 0x00009000
109
110 #define NBIO_BASE__INST0_SEG1 0x00000014
111
112 #define MAX_INSTANCE 7
113 #define MAX_SEGMENT 8
114
115 #define regBIF_BX2_BIOS_SCRATCH_2 0x003a
116 #define regBIF_BX2_BIOS_SCRATCH_2_BASE_IDX 1
117 #define regBIF_BX2_BIOS_SCRATCH_3 0x003b
118 #define regBIF_BX2_BIOS_SCRATCH_3_BASE_IDX 1
119 #define regBIF_BX2_BIOS_SCRATCH_6 0x003e
120 #define regBIF_BX2_BIOS_SCRATCH_6_BASE_IDX 1
121
122 #define DC_LOGGER \
123 dc->ctx->logger
124 #define DC_LOGGER_INIT(logger)
125
126 enum dcn31_clk_src_array_id {
127 DCN31_CLK_SRC_PLL0,
128 DCN31_CLK_SRC_PLL1,
129 DCN31_CLK_SRC_PLL2,
130 DCN31_CLK_SRC_PLL3,
131 DCN31_CLK_SRC_PLL4,
132 DCN30_CLK_SRC_TOTAL
133 };
134
135 /* begin *********************
136 * macros to expend register list macro defined in HW object header file
137 */
138
139 /* DCN */
140 /* TODO awful hack. fixup dcn20_dwb.h */
141 #undef BASE_INNER
142 #define BASE_INNER(seg) DCN_BASE__INST0_SEG ## seg
143
144 #define BASE(seg) BASE_INNER(seg)
145
146 #define SR(reg_name)\
147 .reg_name = BASE(reg ## reg_name ## _BASE_IDX) + \
148 reg ## reg_name
149
150 #define SRI(reg_name, block, id)\
151 .reg_name = BASE(reg ## block ## id ## _ ## reg_name ## _BASE_IDX) + \
152 reg ## block ## id ## _ ## reg_name
153
154 #define SRI2(reg_name, block, id)\
155 .reg_name = BASE(reg ## reg_name ## _BASE_IDX) + \
156 reg ## reg_name
157
158 #define SRIR(var_name, reg_name, block, id)\
159 .var_name = BASE(reg ## block ## id ## _ ## reg_name ## _BASE_IDX) + \
160 reg ## block ## id ## _ ## reg_name
161
162 #define SRII(reg_name, block, id)\
163 .reg_name[id] = BASE(reg ## block ## id ## _ ## reg_name ## _BASE_IDX) + \
164 reg ## block ## id ## _ ## reg_name
165
166 #define SRII_MPC_RMU(reg_name, block, id)\
167 .RMU##_##reg_name[id] = BASE(reg ## block ## id ## _ ## reg_name ## _BASE_IDX) + \
168 reg ## block ## id ## _ ## reg_name
169
170 #define SRII_DWB(reg_name, temp_name, block, id)\
171 .reg_name[id] = BASE(reg ## block ## id ## _ ## temp_name ## _BASE_IDX) + \
172 reg ## block ## id ## _ ## temp_name
173
174 #define SF_DWB2(reg_name, block, id, field_name, post_fix) \
175 .field_name = reg_name ## __ ## field_name ## post_fix
176
177 #define DCCG_SRII(reg_name, block, id)\
178 .block ## _ ## reg_name[id] = BASE(reg ## block ## id ## _ ## reg_name ## _BASE_IDX) + \
179 reg ## block ## id ## _ ## reg_name
180
181 #define VUPDATE_SRII(reg_name, block, id)\
182 .reg_name[id] = BASE(reg ## reg_name ## _ ## block ## id ## _BASE_IDX) + \
183 reg ## reg_name ## _ ## block ## id
184
185 /* NBIO */
186 #define NBIO_BASE_INNER(seg) \
187 NBIO_BASE__INST0_SEG ## seg
188
189 #define NBIO_BASE(seg) \
190 NBIO_BASE_INNER(seg)
191
192 #define NBIO_SR(reg_name)\
193 .reg_name = NBIO_BASE(regBIF_BX2_ ## reg_name ## _BASE_IDX) + \
194 regBIF_BX2_ ## reg_name
195
196 /* MMHUB */
197 #define MMHUB_BASE_INNER(seg) \
198 MMHUB_BASE__INST0_SEG ## seg
199
200 #define MMHUB_BASE(seg) \
201 MMHUB_BASE_INNER(seg)
202
203 #define MMHUB_SR(reg_name)\
204 .reg_name = MMHUB_BASE(reg ## reg_name ## _BASE_IDX) + \
205 reg ## reg_name
206
207 /* CLOCK */
208 #define CLK_BASE_INNER(seg) \
209 CLK_BASE__INST0_SEG ## seg
210
211 #define CLK_BASE(seg) \
212 CLK_BASE_INNER(seg)
213
214 #define CLK_SRI(reg_name, block, inst)\
215 .reg_name = CLK_BASE(reg ## block ## _ ## inst ## _ ## reg_name ## _BASE_IDX) + \
216 reg ## block ## _ ## inst ## _ ## reg_name
217
218
219 static const struct bios_registers bios_regs = {
220 NBIO_SR(BIOS_SCRATCH_3),
221 NBIO_SR(BIOS_SCRATCH_6)
222 };
223
224 #define clk_src_regs(index, pllid)\
225 [index] = {\
226 CS_COMMON_REG_LIST_DCN3_0(index, pllid),\
227 }
228
229 static const struct dce110_clk_src_regs clk_src_regs[] = {
230 clk_src_regs(0, A),
231 clk_src_regs(1, B),
232 clk_src_regs(2, C),
233 clk_src_regs(3, D),
234 clk_src_regs(4, E)
235 };
236
237 static const struct dce110_clk_src_shift cs_shift = {
238 CS_COMMON_MASK_SH_LIST_DCN3_1_4(__SHIFT)
239 };
240
241 static const struct dce110_clk_src_mask cs_mask = {
242 CS_COMMON_MASK_SH_LIST_DCN3_1_4(_MASK)
243 };
244
245 #define abm_regs(id)\
246 [id] = {\
247 ABM_DCN302_REG_LIST(id)\
248 }
249
250 static const struct dce_abm_registers abm_regs[] = {
251 abm_regs(0),
252 abm_regs(1),
253 abm_regs(2),
254 abm_regs(3),
255 };
256
257 static const struct dce_abm_shift abm_shift = {
258 ABM_MASK_SH_LIST_DCN30(__SHIFT)
259 };
260
261 static const struct dce_abm_mask abm_mask = {
262 ABM_MASK_SH_LIST_DCN30(_MASK)
263 };
264
265 #define audio_regs(id)\
266 [id] = {\
267 AUD_COMMON_REG_LIST(id)\
268 }
269
270 static const struct dce_audio_registers audio_regs[] = {
271 audio_regs(0),
272 audio_regs(1),
273 audio_regs(2),
274 audio_regs(3),
275 audio_regs(4),
276 audio_regs(5),
277 audio_regs(6)
278 };
279
280 #define DCE120_AUD_COMMON_MASK_SH_LIST(mask_sh)\
281 SF(AZF0ENDPOINT0_AZALIA_F0_CODEC_ENDPOINT_INDEX, AZALIA_ENDPOINT_REG_INDEX, mask_sh),\
282 SF(AZF0ENDPOINT0_AZALIA_F0_CODEC_ENDPOINT_DATA, AZALIA_ENDPOINT_REG_DATA, mask_sh),\
283 AUD_COMMON_MASK_SH_LIST_BASE(mask_sh)
284
285 static const struct dce_audio_shift audio_shift = {
286 DCE120_AUD_COMMON_MASK_SH_LIST(__SHIFT)
287 };
288
289 static const struct dce_audio_mask audio_mask = {
290 DCE120_AUD_COMMON_MASK_SH_LIST(_MASK)
291 };
292
293 #define vpg_regs(id)\
294 [id] = {\
295 VPG_DCN31_REG_LIST(id)\
296 }
297
298 static const struct dcn31_vpg_registers vpg_regs[] = {
299 vpg_regs(0),
300 vpg_regs(1),
301 vpg_regs(2),
302 vpg_regs(3),
303 vpg_regs(4),
304 vpg_regs(5),
305 vpg_regs(6),
306 vpg_regs(7),
307 vpg_regs(8),
308 vpg_regs(9),
309 };
310
311 static const struct dcn31_vpg_shift vpg_shift = {
312 DCN31_VPG_MASK_SH_LIST(__SHIFT)
313 };
314
315 static const struct dcn31_vpg_mask vpg_mask = {
316 DCN31_VPG_MASK_SH_LIST(_MASK)
317 };
318
319 #define afmt_regs(id)\
320 [id] = {\
321 AFMT_DCN31_REG_LIST(id)\
322 }
323
324 static const struct dcn31_afmt_registers afmt_regs[] = {
325 afmt_regs(0),
326 afmt_regs(1),
327 afmt_regs(2),
328 afmt_regs(3),
329 afmt_regs(4),
330 afmt_regs(5)
331 };
332
333 static const struct dcn31_afmt_shift afmt_shift = {
334 DCN31_AFMT_MASK_SH_LIST(__SHIFT)
335 };
336
337 static const struct dcn31_afmt_mask afmt_mask = {
338 DCN31_AFMT_MASK_SH_LIST(_MASK)
339 };
340
341 #define apg_regs(id)\
342 [id] = {\
343 APG_DCN31_REG_LIST(id)\
344 }
345
346 static const struct dcn31_apg_registers apg_regs[] = {
347 apg_regs(0),
348 apg_regs(1),
349 apg_regs(2),
350 apg_regs(3)
351 };
352
353 static const struct dcn31_apg_shift apg_shift = {
354 DCN31_APG_MASK_SH_LIST(__SHIFT)
355 };
356
357 static const struct dcn31_apg_mask apg_mask = {
358 DCN31_APG_MASK_SH_LIST(_MASK)
359 };
360
361 #define stream_enc_regs(id)\
362 [id] = {\
363 SE_DCN314_REG_LIST(id)\
364 }
365
366 static const struct dcn10_stream_enc_registers stream_enc_regs[] = {
367 stream_enc_regs(0),
368 stream_enc_regs(1),
369 stream_enc_regs(2),
370 stream_enc_regs(3),
371 stream_enc_regs(4)
372 };
373
374 static const struct dcn10_stream_encoder_shift se_shift = {
375 SE_COMMON_MASK_SH_LIST_DCN314(__SHIFT)
376 };
377
378 static const struct dcn10_stream_encoder_mask se_mask = {
379 SE_COMMON_MASK_SH_LIST_DCN314(_MASK)
380 };
381
382
383 #define aux_regs(id)\
384 [id] = {\
385 DCN2_AUX_REG_LIST(id)\
386 }
387
388 static const struct dcn10_link_enc_aux_registers link_enc_aux_regs[] = {
389 aux_regs(0),
390 aux_regs(1),
391 aux_regs(2),
392 aux_regs(3),
393 aux_regs(4)
394 };
395
396 #define hpd_regs(id)\
397 [id] = {\
398 HPD_REG_LIST(id)\
399 }
400
401 static const struct dcn10_link_enc_hpd_registers link_enc_hpd_regs[] = {
402 hpd_regs(0),
403 hpd_regs(1),
404 hpd_regs(2),
405 hpd_regs(3),
406 hpd_regs(4)
407 };
408
409 #define link_regs(id, phyid)\
410 [id] = {\
411 LE_DCN31_REG_LIST(id), \
412 UNIPHY_DCN2_REG_LIST(phyid), \
413 }
414
415 static const struct dce110_aux_registers_shift aux_shift = {
416 DCN_AUX_MASK_SH_LIST(__SHIFT)
417 };
418
419 static const struct dce110_aux_registers_mask aux_mask = {
420 DCN_AUX_MASK_SH_LIST(_MASK)
421 };
422
423 static const struct dcn10_link_enc_registers link_enc_regs[] = {
424 link_regs(0, A),
425 link_regs(1, B),
426 link_regs(2, C),
427 link_regs(3, D),
428 link_regs(4, E)
429 };
430
431 static const struct dcn10_link_enc_shift le_shift = {
432 LINK_ENCODER_MASK_SH_LIST_DCN31(__SHIFT),
433 DPCS_DCN31_MASK_SH_LIST(__SHIFT)
434 };
435
436 static const struct dcn10_link_enc_mask le_mask = {
437 LINK_ENCODER_MASK_SH_LIST_DCN31(_MASK),
438 DPCS_DCN31_MASK_SH_LIST(_MASK)
439 };
440
441 #define hpo_dp_stream_encoder_reg_list(id)\
442 [id] = {\
443 DCN3_1_HPO_DP_STREAM_ENC_REG_LIST(id)\
444 }
445
446 static const struct dcn31_hpo_dp_stream_encoder_registers hpo_dp_stream_enc_regs[] = {
447 hpo_dp_stream_encoder_reg_list(0),
448 hpo_dp_stream_encoder_reg_list(1),
449 hpo_dp_stream_encoder_reg_list(2),
450 hpo_dp_stream_encoder_reg_list(3)
451 };
452
453 static const struct dcn31_hpo_dp_stream_encoder_shift hpo_dp_se_shift = {
454 DCN3_1_HPO_DP_STREAM_ENC_MASK_SH_LIST(__SHIFT)
455 };
456
457 static const struct dcn31_hpo_dp_stream_encoder_mask hpo_dp_se_mask = {
458 DCN3_1_HPO_DP_STREAM_ENC_MASK_SH_LIST(_MASK)
459 };
460
461
462 #define hpo_dp_link_encoder_reg_list(id)\
463 [id] = {\
464 DCN3_1_HPO_DP_LINK_ENC_REG_LIST(id),\
465 DCN3_1_RDPCSTX_REG_LIST(0),\
466 DCN3_1_RDPCSTX_REG_LIST(1),\
467 DCN3_1_RDPCSTX_REG_LIST(2),\
468 }
469
470 static const struct dcn31_hpo_dp_link_encoder_registers hpo_dp_link_enc_regs[] = {
471 hpo_dp_link_encoder_reg_list(0),
472 hpo_dp_link_encoder_reg_list(1),
473 };
474
475 static const struct dcn31_hpo_dp_link_encoder_shift hpo_dp_le_shift = {
476 DCN3_1_HPO_DP_LINK_ENC_MASK_SH_LIST(__SHIFT)
477 };
478
479 static const struct dcn31_hpo_dp_link_encoder_mask hpo_dp_le_mask = {
480 DCN3_1_HPO_DP_LINK_ENC_MASK_SH_LIST(_MASK)
481 };
482
483 #define dpp_regs(id)\
484 [id] = {\
485 DPP_REG_LIST_DCN30(id),\
486 }
487
488 static const struct dcn3_dpp_registers dpp_regs[] = {
489 dpp_regs(0),
490 dpp_regs(1),
491 dpp_regs(2),
492 dpp_regs(3)
493 };
494
495 static const struct dcn3_dpp_shift tf_shift = {
496 DPP_REG_LIST_SH_MASK_DCN30(__SHIFT)
497 };
498
499 static const struct dcn3_dpp_mask tf_mask = {
500 DPP_REG_LIST_SH_MASK_DCN30(_MASK)
501 };
502
503 #define opp_regs(id)\
504 [id] = {\
505 OPP_REG_LIST_DCN30(id),\
506 }
507
508 static const struct dcn20_opp_registers opp_regs[] = {
509 opp_regs(0),
510 opp_regs(1),
511 opp_regs(2),
512 opp_regs(3)
513 };
514
515 static const struct dcn20_opp_shift opp_shift = {
516 OPP_MASK_SH_LIST_DCN20(__SHIFT)
517 };
518
519 static const struct dcn20_opp_mask opp_mask = {
520 OPP_MASK_SH_LIST_DCN20(_MASK)
521 };
522
523 #define aux_engine_regs(id)\
524 [id] = {\
525 AUX_COMMON_REG_LIST0(id), \
526 .AUXN_IMPCAL = 0, \
527 .AUXP_IMPCAL = 0, \
528 .AUX_RESET_MASK = DP_AUX0_AUX_CONTROL__AUX_RESET_MASK, \
529 }
530
531 static const struct dce110_aux_registers aux_engine_regs[] = {
532 aux_engine_regs(0),
533 aux_engine_regs(1),
534 aux_engine_regs(2),
535 aux_engine_regs(3),
536 aux_engine_regs(4)
537 };
538
539 #define dwbc_regs_dcn3(id)\
540 [id] = {\
541 DWBC_COMMON_REG_LIST_DCN30(id),\
542 }
543
544 static const struct dcn30_dwbc_registers dwbc30_regs[] = {
545 dwbc_regs_dcn3(0),
546 };
547
548 static const struct dcn30_dwbc_shift dwbc30_shift = {
549 DWBC_COMMON_MASK_SH_LIST_DCN30(__SHIFT)
550 };
551
552 static const struct dcn30_dwbc_mask dwbc30_mask = {
553 DWBC_COMMON_MASK_SH_LIST_DCN30(_MASK)
554 };
555
556 #define mcif_wb_regs_dcn3(id)\
557 [id] = {\
558 MCIF_WB_COMMON_REG_LIST_DCN30(id),\
559 }
560
561 static const struct dcn30_mmhubbub_registers mcif_wb30_regs[] = {
562 mcif_wb_regs_dcn3(0)
563 };
564
565 static const struct dcn30_mmhubbub_shift mcif_wb30_shift = {
566 MCIF_WB_COMMON_MASK_SH_LIST_DCN30(__SHIFT)
567 };
568
569 static const struct dcn30_mmhubbub_mask mcif_wb30_mask = {
570 MCIF_WB_COMMON_MASK_SH_LIST_DCN30(_MASK)
571 };
572
573 #define dsc_regsDCN314(id)\
574 [id] = {\
575 DSC_REG_LIST_DCN20(id)\
576 }
577
578 static const struct dcn20_dsc_registers dsc_regs[] = {
579 dsc_regsDCN314(0),
580 dsc_regsDCN314(1),
581 dsc_regsDCN314(2),
582 dsc_regsDCN314(3)
583 };
584
585 static const struct dcn20_dsc_shift dsc_shift = {
586 DSC_REG_LIST_SH_MASK_DCN20(__SHIFT)
587 };
588
589 static const struct dcn20_dsc_mask dsc_mask = {
590 DSC_REG_LIST_SH_MASK_DCN20(_MASK)
591 };
592
593 static const struct dcn30_mpc_registers mpc_regs = {
594 MPC_REG_LIST_DCN3_0(0),
595 MPC_REG_LIST_DCN3_0(1),
596 MPC_REG_LIST_DCN3_0(2),
597 MPC_REG_LIST_DCN3_0(3),
598 MPC_OUT_MUX_REG_LIST_DCN3_0(0),
599 MPC_OUT_MUX_REG_LIST_DCN3_0(1),
600 MPC_OUT_MUX_REG_LIST_DCN3_0(2),
601 MPC_OUT_MUX_REG_LIST_DCN3_0(3),
602 MPC_RMU_GLOBAL_REG_LIST_DCN3AG,
603 MPC_RMU_REG_LIST_DCN3AG(0),
604 MPC_RMU_REG_LIST_DCN3AG(1),
605 //MPC_RMU_REG_LIST_DCN3AG(2),
606 MPC_DWB_MUX_REG_LIST_DCN3_0(0),
607 };
608
609 static const struct dcn30_mpc_shift mpc_shift = {
610 MPC_COMMON_MASK_SH_LIST_DCN30(__SHIFT)
611 };
612
613 static const struct dcn30_mpc_mask mpc_mask = {
614 MPC_COMMON_MASK_SH_LIST_DCN30(_MASK)
615 };
616
617 #define optc_regs(id)\
618 [id] = {OPTC_COMMON_REG_LIST_DCN3_14(id)}
619
620 static const struct dcn_optc_registers optc_regs[] = {
621 optc_regs(0),
622 optc_regs(1),
623 optc_regs(2),
624 optc_regs(3)
625 };
626
627 static const struct dcn_optc_shift optc_shift = {
628 OPTC_COMMON_MASK_SH_LIST_DCN3_14(__SHIFT)
629 };
630
631 static const struct dcn_optc_mask optc_mask = {
632 OPTC_COMMON_MASK_SH_LIST_DCN3_14(_MASK)
633 };
634
635 #define hubp_regs(id)\
636 [id] = {\
637 HUBP_REG_LIST_DCN30(id)\
638 }
639
640 static const struct dcn_hubp2_registers hubp_regs[] = {
641 hubp_regs(0),
642 hubp_regs(1),
643 hubp_regs(2),
644 hubp_regs(3)
645 };
646
647
648 static const struct dcn_hubp2_shift hubp_shift = {
649 HUBP_MASK_SH_LIST_DCN31(__SHIFT)
650 };
651
652 static const struct dcn_hubp2_mask hubp_mask = {
653 HUBP_MASK_SH_LIST_DCN31(_MASK)
654 };
655 static const struct dcn_hubbub_registers hubbub_reg = {
656 HUBBUB_REG_LIST_DCN31(0)
657 };
658
659 static const struct dcn_hubbub_shift hubbub_shift = {
660 HUBBUB_MASK_SH_LIST_DCN31(__SHIFT)
661 };
662
663 static const struct dcn_hubbub_mask hubbub_mask = {
664 HUBBUB_MASK_SH_LIST_DCN31(_MASK)
665 };
666
667 static const struct dccg_registers dccg_regs = {
668 DCCG_REG_LIST_DCN314()
669 };
670
671 static const struct dccg_shift dccg_shift = {
672 DCCG_MASK_SH_LIST_DCN314(__SHIFT)
673 };
674
675 static const struct dccg_mask dccg_mask = {
676 DCCG_MASK_SH_LIST_DCN314(_MASK)
677 };
678
679
680 #define SRII2(reg_name_pre, reg_name_post, id)\
681 .reg_name_pre ## _ ## reg_name_post[id] = BASE(reg ## reg_name_pre \
682 ## id ## _ ## reg_name_post ## _BASE_IDX) + \
683 reg ## reg_name_pre ## id ## _ ## reg_name_post
684
685
686 #define HWSEQ_DCN31_REG_LIST()\
687 SR(DCHUBBUB_GLOBAL_TIMER_CNTL), \
688 SR(DCHUBBUB_ARB_HOSTVM_CNTL), \
689 SR(DIO_MEM_PWR_CTRL), \
690 SR(ODM_MEM_PWR_CTRL3), \
691 SR(DMU_MEM_PWR_CNTL), \
692 SR(MMHUBBUB_MEM_PWR_CNTL), \
693 SR(DCCG_GATE_DISABLE_CNTL), \
694 SR(DCCG_GATE_DISABLE_CNTL2), \
695 SR(DCFCLK_CNTL),\
696 SR(DC_MEM_GLOBAL_PWR_REQ_CNTL), \
697 SRII(PIXEL_RATE_CNTL, OTG, 0), \
698 SRII(PIXEL_RATE_CNTL, OTG, 1),\
699 SRII(PIXEL_RATE_CNTL, OTG, 2),\
700 SRII(PIXEL_RATE_CNTL, OTG, 3),\
701 SRII(PHYPLL_PIXEL_RATE_CNTL, OTG, 0),\
702 SRII(PHYPLL_PIXEL_RATE_CNTL, OTG, 1),\
703 SRII(PHYPLL_PIXEL_RATE_CNTL, OTG, 2),\
704 SRII(PHYPLL_PIXEL_RATE_CNTL, OTG, 3),\
705 SR(MICROSECOND_TIME_BASE_DIV), \
706 SR(MILLISECOND_TIME_BASE_DIV), \
707 SR(DISPCLK_FREQ_CHANGE_CNTL), \
708 SR(RBBMIF_TIMEOUT_DIS), \
709 SR(RBBMIF_TIMEOUT_DIS_2), \
710 SR(DCHUBBUB_CRC_CTRL), \
711 SR(DPP_TOP0_DPP_CRC_CTRL), \
712 SR(DPP_TOP0_DPP_CRC_VAL_B_A), \
713 SR(DPP_TOP0_DPP_CRC_VAL_R_G), \
714 SR(MPC_CRC_CTRL), \
715 SR(MPC_CRC_RESULT_GB), \
716 SR(MPC_CRC_RESULT_C), \
717 SR(MPC_CRC_RESULT_AR), \
718 SR(DOMAIN0_PG_CONFIG), \
719 SR(DOMAIN1_PG_CONFIG), \
720 SR(DOMAIN2_PG_CONFIG), \
721 SR(DOMAIN3_PG_CONFIG), \
722 SR(DOMAIN16_PG_CONFIG), \
723 SR(DOMAIN17_PG_CONFIG), \
724 SR(DOMAIN18_PG_CONFIG), \
725 SR(DOMAIN19_PG_CONFIG), \
726 SR(DOMAIN0_PG_STATUS), \
727 SR(DOMAIN1_PG_STATUS), \
728 SR(DOMAIN2_PG_STATUS), \
729 SR(DOMAIN3_PG_STATUS), \
730 SR(DOMAIN16_PG_STATUS), \
731 SR(DOMAIN17_PG_STATUS), \
732 SR(DOMAIN18_PG_STATUS), \
733 SR(DOMAIN19_PG_STATUS), \
734 SR(D1VGA_CONTROL), \
735 SR(D2VGA_CONTROL), \
736 SR(D3VGA_CONTROL), \
737 SR(D4VGA_CONTROL), \
738 SR(D5VGA_CONTROL), \
739 SR(D6VGA_CONTROL), \
740 SR(DC_IP_REQUEST_CNTL), \
741 SR(AZALIA_AUDIO_DTO), \
742 SR(AZALIA_CONTROLLER_CLOCK_GATING), \
743 SR(HPO_TOP_HW_CONTROL)
744
745 static const struct dce_hwseq_registers hwseq_reg = {
746 HWSEQ_DCN31_REG_LIST()
747 };
748
749 #define HWSEQ_DCN31_MASK_SH_LIST(mask_sh)\
750 HWSEQ_DCN_MASK_SH_LIST(mask_sh), \
751 HWS_SF(, DCHUBBUB_GLOBAL_TIMER_CNTL, DCHUBBUB_GLOBAL_TIMER_REFDIV, mask_sh), \
752 HWS_SF(, DCHUBBUB_ARB_HOSTVM_CNTL, DISABLE_HOSTVM_FORCE_ALLOW_PSTATE, mask_sh), \
753 HWS_SF(, DOMAIN0_PG_CONFIG, DOMAIN_POWER_FORCEON, mask_sh), \
754 HWS_SF(, DOMAIN0_PG_CONFIG, DOMAIN_POWER_GATE, mask_sh), \
755 HWS_SF(, DOMAIN1_PG_CONFIG, DOMAIN_POWER_FORCEON, mask_sh), \
756 HWS_SF(, DOMAIN1_PG_CONFIG, DOMAIN_POWER_GATE, mask_sh), \
757 HWS_SF(, DOMAIN2_PG_CONFIG, DOMAIN_POWER_FORCEON, mask_sh), \
758 HWS_SF(, DOMAIN2_PG_CONFIG, DOMAIN_POWER_GATE, mask_sh), \
759 HWS_SF(, DOMAIN3_PG_CONFIG, DOMAIN_POWER_FORCEON, mask_sh), \
760 HWS_SF(, DOMAIN3_PG_CONFIG, DOMAIN_POWER_GATE, mask_sh), \
761 HWS_SF(, DOMAIN16_PG_CONFIG, DOMAIN_POWER_FORCEON, mask_sh), \
762 HWS_SF(, DOMAIN16_PG_CONFIG, DOMAIN_POWER_GATE, mask_sh), \
763 HWS_SF(, DOMAIN17_PG_CONFIG, DOMAIN_POWER_FORCEON, mask_sh), \
764 HWS_SF(, DOMAIN17_PG_CONFIG, DOMAIN_POWER_GATE, mask_sh), \
765 HWS_SF(, DOMAIN18_PG_CONFIG, DOMAIN_POWER_FORCEON, mask_sh), \
766 HWS_SF(, DOMAIN18_PG_CONFIG, DOMAIN_POWER_GATE, mask_sh), \
767 HWS_SF(, DOMAIN19_PG_CONFIG, DOMAIN_POWER_FORCEON, mask_sh), \
768 HWS_SF(, DOMAIN19_PG_CONFIG, DOMAIN_POWER_GATE, mask_sh), \
769 HWS_SF(, DOMAIN0_PG_STATUS, DOMAIN_PGFSM_PWR_STATUS, mask_sh), \
770 HWS_SF(, DOMAIN1_PG_STATUS, DOMAIN_PGFSM_PWR_STATUS, mask_sh), \
771 HWS_SF(, DOMAIN2_PG_STATUS, DOMAIN_PGFSM_PWR_STATUS, mask_sh), \
772 HWS_SF(, DOMAIN3_PG_STATUS, DOMAIN_PGFSM_PWR_STATUS, mask_sh), \
773 HWS_SF(, DOMAIN16_PG_STATUS, DOMAIN_PGFSM_PWR_STATUS, mask_sh), \
774 HWS_SF(, DOMAIN17_PG_STATUS, DOMAIN_PGFSM_PWR_STATUS, mask_sh), \
775 HWS_SF(, DOMAIN18_PG_STATUS, DOMAIN_PGFSM_PWR_STATUS, mask_sh), \
776 HWS_SF(, DOMAIN19_PG_STATUS, DOMAIN_PGFSM_PWR_STATUS, mask_sh), \
777 HWS_SF(, DC_IP_REQUEST_CNTL, IP_REQUEST_EN, mask_sh), \
778 HWS_SF(, AZALIA_AUDIO_DTO, AZALIA_AUDIO_DTO_MODULE, mask_sh), \
779 HWS_SF(, HPO_TOP_CLOCK_CONTROL, HPO_HDMISTREAMCLK_G_GATE_DIS, mask_sh), \
780 HWS_SF(, DMU_MEM_PWR_CNTL, DMCU_ERAM_MEM_PWR_FORCE, mask_sh), \
781 HWS_SF(, ODM_MEM_PWR_CTRL3, ODM_MEM_UNASSIGNED_PWR_MODE, mask_sh), \
782 HWS_SF(, ODM_MEM_PWR_CTRL3, ODM_MEM_VBLANK_PWR_MODE, mask_sh), \
783 HWS_SF(, MMHUBBUB_MEM_PWR_CNTL, VGA_MEM_PWR_FORCE, mask_sh), \
784 HWS_SF(, DIO_MEM_PWR_CTRL, I2C_LIGHT_SLEEP_FORCE, mask_sh), \
785 HWS_SF(, HPO_TOP_HW_CONTROL, HPO_IO_EN, mask_sh)
786
787 static const struct dce_hwseq_shift hwseq_shift = {
788 HWSEQ_DCN31_MASK_SH_LIST(__SHIFT)
789 };
790
791 static const struct dce_hwseq_mask hwseq_mask = {
792 HWSEQ_DCN31_MASK_SH_LIST(_MASK)
793 };
794 #define vmid_regs(id)\
795 [id] = {\
796 DCN20_VMID_REG_LIST(id)\
797 }
798
799 static const struct dcn_vmid_registers vmid_regs[] = {
800 vmid_regs(0),
801 vmid_regs(1),
802 vmid_regs(2),
803 vmid_regs(3),
804 vmid_regs(4),
805 vmid_regs(5),
806 vmid_regs(6),
807 vmid_regs(7),
808 vmid_regs(8),
809 vmid_regs(9),
810 vmid_regs(10),
811 vmid_regs(11),
812 vmid_regs(12),
813 vmid_regs(13),
814 vmid_regs(14),
815 vmid_regs(15)
816 };
817
818 static const struct dcn20_vmid_shift vmid_shifts = {
819 DCN20_VMID_MASK_SH_LIST(__SHIFT)
820 };
821
822 static const struct dcn20_vmid_mask vmid_masks = {
823 DCN20_VMID_MASK_SH_LIST(_MASK)
824 };
825
826 static const struct dcn_dio_registers dio_regs = {
827 DIO_REG_LIST_DCN10()
828 };
829
830 #define DIO_MASK_SH_LIST(mask_sh)\
831 HWS_SF(, DIO_MEM_PWR_CTRL, I2C_LIGHT_SLEEP_FORCE, mask_sh)
832
833 static const struct dcn_dio_shift dio_shift = {
834 DIO_MASK_SH_LIST(__SHIFT)
835 };
836
837 static const struct dcn_dio_mask dio_mask = {
838 DIO_MASK_SH_LIST(_MASK)
839 };
840
841 static const struct resource_caps res_cap_dcn314 = {
842 .num_timing_generator = 4,
843 .num_opp = 4,
844 .num_video_plane = 4,
845 .num_audio = 5,
846 .num_stream_encoder = 5,
847 .num_dig_link_enc = 5,
848 .num_hpo_dp_stream_encoder = 4,
849 .num_hpo_dp_link_encoder = 2,
850 .num_pll = 5,
851 .num_dwb = 1,
852 .num_ddc = 5,
853 .num_vmid = 16,
854 .num_mpc_3dlut = 2,
855 .num_dsc = 4,
856 };
857
858 static const struct dc_plane_cap plane_cap = {
859 .type = DC_PLANE_TYPE_DCN_UNIVERSAL,
860 .per_pixel_alpha = true,
861
862 .pixel_format_support = {
863 .argb8888 = true,
864 .nv12 = true,
865 .fp16 = true,
866 .p010 = true,
867 .ayuv = false,
868 },
869
870 .max_upscale_factor = {
871 .argb8888 = 16000,
872 .nv12 = 16000,
873 .fp16 = 16000
874 },
875
876 // 6:1 downscaling ratio: 1000/6 = 166.666
877 // 4:1 downscaling ratio for ARGB888 to prevent underflow during P010 playback: 1000/4 = 250
878 .max_downscale_factor = {
879 .argb8888 = 250,
880 .nv12 = 167,
881 .fp16 = 167
882 },
883 64,
884 64
885 };
886
887 static const struct dc_debug_options debug_defaults_drv = {
888 .disable_z10 = false,
889 .enable_z9_disable_interface = true,
890 .minimum_z8_residency_time = 2100,
891 .psr_skip_crtc_disable = true,
892 .replay_skip_crtc_disabled = true,
893 .disable_dmcu = true,
894 .force_abm_enable = false,
895 .clock_trace = true,
896 .disable_dpp_power_gate = false,
897 .disable_hubp_power_gate = false,
898 .disable_pplib_clock_request = false,
899 .pipe_split_policy = MPC_SPLIT_DYNAMIC,
900 .force_single_disp_pipe_split = false,
901 .disable_dcc = DCC_ENABLE,
902 .vsr_support = true,
903 .performance_trace = false,
904 .max_downscale_src_width = 4096,/*upto true 4k*/
905 .disable_pplib_wm_range = false,
906 .scl_reset_length10 = true,
907 .sanity_checks = false,
908 .underflow_assert_delay_us = 0xFFFFFFFF,
909 .dwb_fi_phase = -1, // -1 = disable,
910 .dmub_command_table = true,
911 .pstate_enabled = true,
912 .use_max_lb = true,
913 .enable_mem_low_power = {
914 .bits = {
915 .vga = true,
916 .i2c = true,
917 .dmcu = false, // This is previously known to cause hang on S3 cycles if enabled
918 .dscl = true,
919 .cm = true,
920 .mpc = true,
921 .optc = true,
922 .vpg = true,
923 .afmt = true,
924 }
925 },
926
927 .root_clock_optimization = {
928 .bits = {
929 .dpp = true,
930 .dsc = true,
931 .hdmistream = true,
932 .hdmichar = true,
933 .dpstream = true,
934 .symclk32_se = false,
935 .symclk32_le = true,
936 .symclk_fe = true,
937 .physymclk = true,
938 .dpiasymclk = true,
939 }
940 },
941
942 .seamless_boot_odm_combine = true,
943 .using_dml2 = false,
944 .disable_dsc_power_gate = true,
945 .min_disp_clk_khz = 100000,
946 };
947
948 static const struct dc_check_config config_defaults = {
949 .enable_legacy_fast_update = true,
950 };
951
952 static const struct dc_panel_config panel_config_defaults = {
953 .psr = {
954 .disable_psr = false,
955 .disallow_psrsu = false,
956 .disallow_replay = false,
957 },
958 .ilr = {
959 .optimize_edp_link_rate = true,
960 },
961 };
962
dcn31_dpp_destroy(struct dpp ** dpp)963 static void dcn31_dpp_destroy(struct dpp **dpp)
964 {
965 kfree(TO_DCN20_DPP(*dpp));
966 *dpp = NULL;
967 }
968
dcn31_dpp_create(struct dc_context * ctx,uint32_t inst)969 static struct dpp *dcn31_dpp_create(
970 struct dc_context *ctx,
971 uint32_t inst)
972 {
973 struct dcn3_dpp *dpp =
974 kzalloc_obj(struct dcn3_dpp);
975
976 if (!dpp)
977 return NULL;
978
979 if (dpp3_construct(dpp, ctx, inst,
980 &dpp_regs[inst], &tf_shift, &tf_mask))
981 return &dpp->base;
982
983 BREAK_TO_DEBUGGER();
984 kfree(dpp);
985 return NULL;
986 }
987
dcn31_opp_create(struct dc_context * ctx,uint32_t inst)988 static struct output_pixel_processor *dcn31_opp_create(
989 struct dc_context *ctx, uint32_t inst)
990 {
991 struct dcn20_opp *opp =
992 kzalloc_obj(struct dcn20_opp);
993
994 if (!opp) {
995 BREAK_TO_DEBUGGER();
996 return NULL;
997 }
998
999 dcn20_opp_construct(opp, ctx, inst,
1000 &opp_regs[inst], &opp_shift, &opp_mask);
1001 return &opp->base;
1002 }
1003
dcn31_aux_engine_create(struct dc_context * ctx,uint32_t inst)1004 static struct dce_aux *dcn31_aux_engine_create(
1005 struct dc_context *ctx,
1006 uint32_t inst)
1007 {
1008 struct aux_engine_dce110 *aux_engine =
1009 kzalloc_obj(struct aux_engine_dce110);
1010
1011 if (!aux_engine)
1012 return NULL;
1013
1014 dce110_aux_engine_construct(aux_engine, ctx, inst,
1015 SW_AUX_TIMEOUT_PERIOD_MULTIPLIER * AUX_TIMEOUT_PERIOD,
1016 &aux_engine_regs[inst],
1017 &aux_mask,
1018 &aux_shift,
1019 ctx->dc->caps.extended_aux_timeout_support);
1020
1021 return &aux_engine->base;
1022 }
1023 #define i2c_inst_regs(id) { I2C_HW_ENGINE_COMMON_REG_LIST_DCN30(id) }
1024
1025 static const struct dce_i2c_registers i2c_hw_regs[] = {
1026 i2c_inst_regs(1),
1027 i2c_inst_regs(2),
1028 i2c_inst_regs(3),
1029 i2c_inst_regs(4),
1030 i2c_inst_regs(5),
1031 };
1032
1033 static const struct dce_i2c_shift i2c_shifts = {
1034 I2C_COMMON_MASK_SH_LIST_DCN30(__SHIFT)
1035 };
1036
1037 static const struct dce_i2c_mask i2c_masks = {
1038 I2C_COMMON_MASK_SH_LIST_DCN30(_MASK)
1039 };
1040
1041 /* ========================================================== */
1042
1043 /*
1044 * DPIA index | Preferred Encoder | Host Router
1045 * 0 | C | 0
1046 * 1 | First Available | 0
1047 * 2 | D | 1
1048 * 3 | First Available | 1
1049 */
1050 /* ========================================================== */
1051 static const enum engine_id dpia_to_preferred_enc_id_table[] = {
1052 ENGINE_ID_DIGC,
1053 ENGINE_ID_DIGC,
1054 ENGINE_ID_DIGD,
1055 ENGINE_ID_DIGD
1056 };
1057
dcn314_get_preferred_eng_id_dpia(unsigned int dpia_index)1058 static enum engine_id dcn314_get_preferred_eng_id_dpia(unsigned int dpia_index)
1059 {
1060 return dpia_to_preferred_enc_id_table[dpia_index];
1061 }
1062
dcn31_i2c_hw_create(struct dc_context * ctx,uint32_t inst)1063 static struct dce_i2c_hw *dcn31_i2c_hw_create(
1064 struct dc_context *ctx,
1065 uint32_t inst)
1066 {
1067 struct dce_i2c_hw *dce_i2c_hw =
1068 kzalloc_obj(struct dce_i2c_hw);
1069
1070 if (!dce_i2c_hw)
1071 return NULL;
1072
1073 dcn2_i2c_hw_construct(dce_i2c_hw, ctx, inst,
1074 &i2c_hw_regs[inst], &i2c_shifts, &i2c_masks);
1075
1076 return dce_i2c_hw;
1077 }
dcn31_mpc_create(struct dc_context * ctx,int num_mpcc,int num_rmu)1078 static struct mpc *dcn31_mpc_create(
1079 struct dc_context *ctx,
1080 int num_mpcc,
1081 int num_rmu)
1082 {
1083 struct dcn30_mpc *mpc30 = kzalloc_obj(struct dcn30_mpc);
1084
1085 if (!mpc30)
1086 return NULL;
1087
1088 dcn30_mpc_construct(mpc30, ctx,
1089 &mpc_regs,
1090 &mpc_shift,
1091 &mpc_mask,
1092 num_mpcc,
1093 num_rmu);
1094
1095 return &mpc30->base;
1096 }
1097
dcn314_dio_create(struct dc_context * ctx)1098 static struct dio *dcn314_dio_create(struct dc_context *ctx)
1099 {
1100 struct dcn10_dio *dio10 = kzalloc_obj(struct dcn10_dio);
1101
1102 if (!dio10)
1103 return NULL;
1104
1105 dcn10_dio_construct(dio10, ctx, &dio_regs, &dio_shift, &dio_mask);
1106
1107 return &dio10->base;
1108 }
1109
dcn31_hubbub_create(struct dc_context * ctx)1110 static struct hubbub *dcn31_hubbub_create(struct dc_context *ctx)
1111 {
1112 int i;
1113
1114 struct dcn20_hubbub *hubbub3 = kzalloc_obj(struct dcn20_hubbub);
1115
1116 if (!hubbub3)
1117 return NULL;
1118
1119 hubbub31_construct(hubbub3, ctx,
1120 &hubbub_reg,
1121 &hubbub_shift,
1122 &hubbub_mask,
1123 dcn3_14_ip.det_buffer_size_kbytes,
1124 dcn3_14_ip.pixel_chunk_size_kbytes,
1125 dcn3_14_ip.config_return_buffer_size_in_kbytes);
1126
1127
1128 for (i = 0; i < res_cap_dcn314.num_vmid; i++) {
1129 struct dcn20_vmid *vmid = &hubbub3->vmid[i];
1130
1131 vmid->ctx = ctx;
1132
1133 vmid->regs = &vmid_regs[i];
1134 vmid->shifts = &vmid_shifts;
1135 vmid->masks = &vmid_masks;
1136 }
1137
1138 return &hubbub3->base;
1139 }
1140
dcn31_timing_generator_create(struct dc_context * ctx,uint32_t instance)1141 static struct timing_generator *dcn31_timing_generator_create(
1142 struct dc_context *ctx,
1143 uint32_t instance)
1144 {
1145 struct optc *tgn10 =
1146 kzalloc_obj(struct optc);
1147
1148 if (!tgn10)
1149 return NULL;
1150
1151 tgn10->base.inst = instance;
1152 tgn10->base.ctx = ctx;
1153
1154 tgn10->tg_regs = &optc_regs[instance];
1155 tgn10->tg_shift = &optc_shift;
1156 tgn10->tg_mask = &optc_mask;
1157
1158 dcn314_timing_generator_init(tgn10);
1159
1160 return &tgn10->base;
1161 }
1162
1163 static const struct encoder_feature_support link_enc_feature = {
1164 .max_hdmi_deep_color = COLOR_DEPTH_121212,
1165 .max_hdmi_pixel_clock = 600000,
1166 .hdmi_ycbcr420_supported = true,
1167 .dp_ycbcr420_supported = true,
1168 .fec_supported = true,
1169 .flags.bits.IS_HBR2_CAPABLE = true,
1170 .flags.bits.IS_HBR3_CAPABLE = true,
1171 .flags.bits.IS_TPS3_CAPABLE = true,
1172 .flags.bits.IS_TPS4_CAPABLE = true
1173 };
1174
dcn31_link_encoder_create(struct dc_context * ctx,const struct encoder_init_data * enc_init_data)1175 static struct link_encoder *dcn31_link_encoder_create(
1176 struct dc_context *ctx,
1177 const struct encoder_init_data *enc_init_data)
1178 {
1179 struct dcn20_link_encoder *enc20 =
1180 kzalloc_obj(struct dcn20_link_encoder);
1181
1182 if (!enc20 || enc_init_data->hpd_source >= ARRAY_SIZE(link_enc_hpd_regs))
1183 return NULL;
1184
1185 dcn31_link_encoder_construct(enc20,
1186 enc_init_data,
1187 &link_enc_feature,
1188 &link_enc_regs[enc_init_data->transmitter],
1189 &link_enc_aux_regs[enc_init_data->channel - 1],
1190 &link_enc_hpd_regs[enc_init_data->hpd_source],
1191 &le_shift,
1192 &le_mask);
1193
1194 return &enc20->enc10.base;
1195 }
1196
1197 /* Create a minimal link encoder object not associated with a particular
1198 * physical connector.
1199 * resource_funcs.link_enc_create_minimal
1200 */
dcn31_link_enc_create_minimal(struct dc_context * ctx,enum engine_id eng_id)1201 static struct link_encoder *dcn31_link_enc_create_minimal(
1202 struct dc_context *ctx, enum engine_id eng_id)
1203 {
1204 struct dcn20_link_encoder *enc20;
1205
1206 if ((eng_id - ENGINE_ID_DIGA) > ctx->dc->res_pool->res_cap->num_dig_link_enc)
1207 return NULL;
1208
1209 enc20 = kzalloc_obj(struct dcn20_link_encoder);
1210 if (!enc20)
1211 return NULL;
1212
1213 dcn31_link_encoder_construct_minimal(
1214 enc20,
1215 ctx,
1216 &link_enc_feature,
1217 &link_enc_regs[eng_id - ENGINE_ID_DIGA],
1218 eng_id);
1219
1220 return &enc20->enc10.base;
1221 }
1222
dcn31_panel_cntl_create(const struct panel_cntl_init_data * init_data)1223 static struct panel_cntl *dcn31_panel_cntl_create(const struct panel_cntl_init_data *init_data)
1224 {
1225 struct dcn31_panel_cntl *panel_cntl =
1226 kzalloc_obj(struct dcn31_panel_cntl);
1227
1228 if (!panel_cntl)
1229 return NULL;
1230
1231 dcn31_panel_cntl_construct(panel_cntl, init_data);
1232
1233 return &panel_cntl->base;
1234 }
1235
read_dce_straps(struct dc_context * ctx,struct resource_straps * straps)1236 static void read_dce_straps(
1237 struct dc_context *ctx,
1238 struct resource_straps *straps)
1239 {
1240 generic_reg_get(ctx, regDC_PINSTRAPS + BASE(regDC_PINSTRAPS_BASE_IDX),
1241 FN(DC_PINSTRAPS, DC_PINSTRAPS_AUDIO), &straps->dc_pinstraps_audio);
1242
1243 }
1244
dcn31_create_audio(struct dc_context * ctx,unsigned int inst)1245 static struct audio *dcn31_create_audio(
1246 struct dc_context *ctx, unsigned int inst)
1247 {
1248 return dce_audio_create(ctx, inst,
1249 &audio_regs[inst], &audio_shift, &audio_mask);
1250 }
1251
dcn31_vpg_create(struct dc_context * ctx,uint32_t inst)1252 static struct vpg *dcn31_vpg_create(
1253 struct dc_context *ctx,
1254 uint32_t inst)
1255 {
1256 struct dcn31_vpg *vpg31 = kzalloc_obj(struct dcn31_vpg);
1257
1258 if (!vpg31)
1259 return NULL;
1260
1261 vpg31_construct(vpg31, ctx, inst,
1262 &vpg_regs[inst],
1263 &vpg_shift,
1264 &vpg_mask);
1265
1266 return &vpg31->base;
1267 }
1268
dcn31_afmt_create(struct dc_context * ctx,uint32_t inst)1269 static struct afmt *dcn31_afmt_create(
1270 struct dc_context *ctx,
1271 uint32_t inst)
1272 {
1273 struct dcn31_afmt *afmt31 = kzalloc_obj(struct dcn31_afmt);
1274
1275 if (!afmt31)
1276 return NULL;
1277
1278 afmt31_construct(afmt31, ctx, inst,
1279 &afmt_regs[inst],
1280 &afmt_shift,
1281 &afmt_mask);
1282
1283 // Light sleep by default, no need to power down here
1284
1285 return &afmt31->base;
1286 }
1287
dcn31_apg_create(struct dc_context * ctx,uint32_t inst)1288 static struct apg *dcn31_apg_create(
1289 struct dc_context *ctx,
1290 uint32_t inst)
1291 {
1292 struct dcn31_apg *apg31 = kzalloc_obj(struct dcn31_apg);
1293
1294 if (!apg31)
1295 return NULL;
1296
1297 apg31_construct(apg31, ctx, inst,
1298 &apg_regs[inst],
1299 &apg_shift,
1300 &apg_mask);
1301
1302 return &apg31->base;
1303 }
1304
dcn314_stream_encoder_create(enum engine_id eng_id,struct dc_context * ctx)1305 static struct stream_encoder *dcn314_stream_encoder_create(
1306 enum engine_id eng_id,
1307 struct dc_context *ctx)
1308 {
1309 struct dcn10_stream_encoder *enc1;
1310 struct vpg *vpg;
1311 struct afmt *afmt;
1312 int vpg_inst;
1313 int afmt_inst;
1314
1315 /* Mapping of VPG, AFMT, DME register blocks to DIO block instance */
1316 if (eng_id < ENGINE_ID_DIGF) {
1317 vpg_inst = eng_id;
1318 afmt_inst = eng_id;
1319 } else
1320 return NULL;
1321
1322 enc1 = kzalloc_obj(struct dcn10_stream_encoder);
1323 vpg = dcn31_vpg_create(ctx, vpg_inst);
1324 afmt = dcn31_afmt_create(ctx, afmt_inst);
1325
1326 if (!enc1 || !vpg || !afmt) {
1327 kfree(enc1);
1328 kfree(vpg);
1329 kfree(afmt);
1330 return NULL;
1331 }
1332
1333 dcn314_dio_stream_encoder_construct(enc1, ctx, ctx->dc_bios,
1334 eng_id, vpg, afmt,
1335 &stream_enc_regs[eng_id],
1336 &se_shift, &se_mask);
1337
1338 return &enc1->base;
1339 }
1340
dcn31_hpo_dp_stream_encoder_create(enum engine_id eng_id,struct dc_context * ctx)1341 static struct hpo_dp_stream_encoder *dcn31_hpo_dp_stream_encoder_create(
1342 enum engine_id eng_id,
1343 struct dc_context *ctx)
1344 {
1345 struct dcn31_hpo_dp_stream_encoder *hpo_dp_enc31;
1346 struct vpg *vpg;
1347 struct apg *apg;
1348 uint32_t hpo_dp_inst;
1349 uint32_t vpg_inst;
1350 uint32_t apg_inst;
1351
1352 ASSERT((eng_id >= ENGINE_ID_HPO_DP_0) && (eng_id <= ENGINE_ID_HPO_DP_3));
1353 hpo_dp_inst = eng_id - ENGINE_ID_HPO_DP_0;
1354
1355 /* Mapping of VPG register blocks to HPO DP block instance:
1356 * VPG[6] -> HPO_DP[0]
1357 * VPG[7] -> HPO_DP[1]
1358 * VPG[8] -> HPO_DP[2]
1359 * VPG[9] -> HPO_DP[3]
1360 */
1361 //Uses offset index 5-8, but actually maps to vpg_inst 6-9
1362 vpg_inst = hpo_dp_inst + 5;
1363
1364 /* Mapping of APG register blocks to HPO DP block instance:
1365 * APG[0] -> HPO_DP[0]
1366 * APG[1] -> HPO_DP[1]
1367 * APG[2] -> HPO_DP[2]
1368 * APG[3] -> HPO_DP[3]
1369 */
1370 apg_inst = hpo_dp_inst;
1371
1372 /* allocate HPO stream encoder and create VPG sub-block */
1373 hpo_dp_enc31 = kzalloc_obj(struct dcn31_hpo_dp_stream_encoder);
1374 vpg = dcn31_vpg_create(ctx, vpg_inst);
1375 apg = dcn31_apg_create(ctx, apg_inst);
1376
1377 if (!hpo_dp_enc31 || !vpg || !apg) {
1378 kfree(hpo_dp_enc31);
1379 kfree(vpg);
1380 kfree(apg);
1381 return NULL;
1382 }
1383
1384 dcn31_hpo_dp_stream_encoder_construct(hpo_dp_enc31, ctx, ctx->dc_bios,
1385 hpo_dp_inst, eng_id, vpg, apg,
1386 &hpo_dp_stream_enc_regs[hpo_dp_inst],
1387 &hpo_dp_se_shift, &hpo_dp_se_mask);
1388
1389 return &hpo_dp_enc31->base;
1390 }
1391
dcn31_hpo_dp_link_encoder_create(uint8_t inst,struct dc_context * ctx)1392 static struct hpo_dp_link_encoder *dcn31_hpo_dp_link_encoder_create(
1393 uint8_t inst,
1394 struct dc_context *ctx)
1395 {
1396 struct dcn31_hpo_dp_link_encoder *hpo_dp_enc31;
1397
1398 /* allocate HPO link encoder */
1399 hpo_dp_enc31 = kzalloc_obj(struct dcn31_hpo_dp_link_encoder);
1400 if (!hpo_dp_enc31)
1401 return NULL; /* out of memory */
1402
1403 hpo_dp_link_encoder31_construct(hpo_dp_enc31, ctx, inst,
1404 &hpo_dp_link_enc_regs[inst],
1405 &hpo_dp_le_shift, &hpo_dp_le_mask);
1406
1407 return &hpo_dp_enc31->base;
1408 }
1409
dcn314_hwseq_create(struct dc_context * ctx)1410 static struct dce_hwseq *dcn314_hwseq_create(
1411 struct dc_context *ctx)
1412 {
1413 struct dce_hwseq *hws = kzalloc_obj(struct dce_hwseq);
1414
1415 if (hws) {
1416 hws->ctx = ctx;
1417 hws->regs = &hwseq_reg;
1418 hws->shifts = &hwseq_shift;
1419 hws->masks = &hwseq_mask;
1420 }
1421 return hws;
1422 }
1423 static const struct resource_create_funcs res_create_funcs = {
1424 .read_dce_straps = read_dce_straps,
1425 .create_audio = dcn31_create_audio,
1426 .create_stream_encoder = dcn314_stream_encoder_create,
1427 .create_hpo_dp_stream_encoder = dcn31_hpo_dp_stream_encoder_create,
1428 .create_hpo_dp_link_encoder = dcn31_hpo_dp_link_encoder_create,
1429 .create_hwseq = dcn314_hwseq_create,
1430 };
1431
dcn314_resource_destruct(struct dcn314_resource_pool * pool)1432 static void dcn314_resource_destruct(struct dcn314_resource_pool *pool)
1433 {
1434 unsigned int i;
1435
1436 for (i = 0; i < pool->base.stream_enc_count; i++) {
1437 if (pool->base.stream_enc[i] != NULL) {
1438 if (pool->base.stream_enc[i]->vpg != NULL) {
1439 kfree(DCN30_VPG_FROM_VPG(pool->base.stream_enc[i]->vpg));
1440 pool->base.stream_enc[i]->vpg = NULL;
1441 }
1442 if (pool->base.stream_enc[i]->afmt != NULL) {
1443 kfree(DCN30_AFMT_FROM_AFMT(pool->base.stream_enc[i]->afmt));
1444 pool->base.stream_enc[i]->afmt = NULL;
1445 }
1446 kfree(DCN10STRENC_FROM_STRENC(pool->base.stream_enc[i]));
1447 pool->base.stream_enc[i] = NULL;
1448 }
1449 }
1450
1451 for (i = 0; i < pool->base.hpo_dp_stream_enc_count; i++) {
1452 if (pool->base.hpo_dp_stream_enc[i] != NULL) {
1453 if (pool->base.hpo_dp_stream_enc[i]->vpg != NULL) {
1454 kfree(DCN30_VPG_FROM_VPG(pool->base.hpo_dp_stream_enc[i]->vpg));
1455 pool->base.hpo_dp_stream_enc[i]->vpg = NULL;
1456 }
1457 if (pool->base.hpo_dp_stream_enc[i]->apg != NULL) {
1458 kfree(DCN31_APG_FROM_APG(pool->base.hpo_dp_stream_enc[i]->apg));
1459 pool->base.hpo_dp_stream_enc[i]->apg = NULL;
1460 }
1461 kfree(DCN3_1_HPO_DP_STREAM_ENC_FROM_HPO_STREAM_ENC(pool->base.hpo_dp_stream_enc[i]));
1462 pool->base.hpo_dp_stream_enc[i] = NULL;
1463 }
1464 }
1465
1466 for (i = 0; i < pool->base.hpo_dp_link_enc_count; i++) {
1467 if (pool->base.hpo_dp_link_enc[i] != NULL) {
1468 kfree(DCN3_1_HPO_DP_LINK_ENC_FROM_HPO_LINK_ENC(pool->base.hpo_dp_link_enc[i]));
1469 pool->base.hpo_dp_link_enc[i] = NULL;
1470 }
1471 }
1472
1473 for (i = 0; i < pool->base.res_cap->num_dsc; i++) {
1474 if (pool->base.dscs[i] != NULL)
1475 dcn20_dsc_destroy(&pool->base.dscs[i]);
1476 }
1477
1478 if (pool->base.mpc != NULL) {
1479 kfree(TO_DCN20_MPC(pool->base.mpc));
1480 pool->base.mpc = NULL;
1481 }
1482 if (pool->base.hubbub != NULL) {
1483 kfree(pool->base.hubbub);
1484 pool->base.hubbub = NULL;
1485 }
1486 if (pool->base.dio != NULL) {
1487 kfree(TO_DCN10_DIO(pool->base.dio));
1488 pool->base.dio = NULL;
1489 }
1490 for (i = 0; i < pool->base.pipe_count; i++) {
1491 if (pool->base.dpps[i] != NULL)
1492 dcn31_dpp_destroy(&pool->base.dpps[i]);
1493
1494 if (pool->base.ipps[i] != NULL)
1495 pool->base.ipps[i]->funcs->ipp_destroy(&pool->base.ipps[i]);
1496
1497 if (pool->base.hubps[i] != NULL) {
1498 kfree(TO_DCN20_HUBP(pool->base.hubps[i]));
1499 pool->base.hubps[i] = NULL;
1500 }
1501
1502 if (pool->base.irqs != NULL)
1503 dal_irq_service_destroy(&pool->base.irqs);
1504 }
1505
1506 for (i = 0; i < pool->base.res_cap->num_ddc; i++) {
1507 if (pool->base.engines[i] != NULL)
1508 dce110_engine_destroy(&pool->base.engines[i]);
1509 if (pool->base.hw_i2cs[i] != NULL) {
1510 kfree(pool->base.hw_i2cs[i]);
1511 pool->base.hw_i2cs[i] = NULL;
1512 }
1513 if (pool->base.sw_i2cs[i] != NULL) {
1514 kfree(pool->base.sw_i2cs[i]);
1515 pool->base.sw_i2cs[i] = NULL;
1516 }
1517 }
1518
1519 for (i = 0; i < pool->base.res_cap->num_opp; i++) {
1520 if (pool->base.opps[i] != NULL)
1521 pool->base.opps[i]->funcs->opp_destroy(&pool->base.opps[i]);
1522 }
1523
1524 for (i = 0; i < pool->base.res_cap->num_timing_generator; i++) {
1525 if (pool->base.timing_generators[i] != NULL) {
1526 kfree(DCN10TG_FROM_TG(pool->base.timing_generators[i]));
1527 pool->base.timing_generators[i] = NULL;
1528 }
1529 }
1530
1531 for (i = 0; i < pool->base.res_cap->num_dwb; i++) {
1532 if (pool->base.dwbc[i] != NULL) {
1533 kfree(TO_DCN30_DWBC(pool->base.dwbc[i]));
1534 pool->base.dwbc[i] = NULL;
1535 }
1536 if (pool->base.mcif_wb[i] != NULL) {
1537 kfree(TO_DCN30_MMHUBBUB(pool->base.mcif_wb[i]));
1538 pool->base.mcif_wb[i] = NULL;
1539 }
1540 }
1541
1542 for (i = 0; i < pool->base.audio_count; i++) {
1543 if (pool->base.audios[i])
1544 dce_aud_destroy(&pool->base.audios[i]);
1545 }
1546
1547 for (i = 0; i < pool->base.clk_src_count; i++) {
1548 if (pool->base.clock_sources[i] != NULL) {
1549 dcn20_clock_source_destroy(&pool->base.clock_sources[i]);
1550 pool->base.clock_sources[i] = NULL;
1551 }
1552 }
1553
1554 for (i = 0; i < pool->base.res_cap->num_mpc_3dlut; i++) {
1555 if (pool->base.mpc_lut[i] != NULL) {
1556 dc_3dlut_func_release(pool->base.mpc_lut[i]);
1557 pool->base.mpc_lut[i] = NULL;
1558 }
1559 if (pool->base.mpc_shaper[i] != NULL) {
1560 dc_transfer_func_release(pool->base.mpc_shaper[i]);
1561 pool->base.mpc_shaper[i] = NULL;
1562 }
1563 }
1564
1565 if (pool->base.dp_clock_source != NULL) {
1566 dcn20_clock_source_destroy(&pool->base.dp_clock_source);
1567 pool->base.dp_clock_source = NULL;
1568 }
1569
1570 for (i = 0; i < pool->base.res_cap->num_timing_generator; i++) {
1571 if (pool->base.multiple_abms[i] != NULL)
1572 dce_abm_destroy(&pool->base.multiple_abms[i]);
1573 }
1574
1575 if (pool->base.psr != NULL)
1576 dmub_psr_destroy(&pool->base.psr);
1577
1578 if (pool->base.replay != NULL)
1579 dmub_replay_destroy(&pool->base.replay);
1580
1581 if (pool->base.dccg != NULL)
1582 dcn_dccg_destroy(&pool->base.dccg);
1583 }
1584
dcn31_hubp_create(struct dc_context * ctx,uint32_t inst)1585 static struct hubp *dcn31_hubp_create(
1586 struct dc_context *ctx,
1587 uint32_t inst)
1588 {
1589 struct dcn20_hubp *hubp2 =
1590 kzalloc_obj(struct dcn20_hubp);
1591
1592 if (!hubp2)
1593 return NULL;
1594
1595 if (hubp31_construct(hubp2, ctx, inst,
1596 &hubp_regs[inst], &hubp_shift, &hubp_mask))
1597 return &hubp2->base;
1598
1599 BREAK_TO_DEBUGGER();
1600 kfree(hubp2);
1601 return NULL;
1602 }
1603
dcn31_dwbc_create(struct dc_context * ctx,struct resource_pool * pool)1604 static bool dcn31_dwbc_create(struct dc_context *ctx, struct resource_pool *pool)
1605 {
1606 int i;
1607 uint32_t pipe_count = pool->res_cap->num_dwb;
1608
1609 for (i = 0; i < pipe_count; i++) {
1610 struct dcn30_dwbc *dwbc30 = kzalloc_obj(struct dcn30_dwbc);
1611
1612 if (!dwbc30) {
1613 dm_error("DC: failed to create dwbc30!\n");
1614 return false;
1615 }
1616
1617 dcn30_dwbc_construct(dwbc30, ctx,
1618 &dwbc30_regs[i],
1619 &dwbc30_shift,
1620 &dwbc30_mask,
1621 i);
1622
1623 pool->dwbc[i] = &dwbc30->base;
1624 }
1625 return true;
1626 }
1627
dcn31_mmhubbub_create(struct dc_context * ctx,struct resource_pool * pool)1628 static bool dcn31_mmhubbub_create(struct dc_context *ctx, struct resource_pool *pool)
1629 {
1630 int i;
1631 uint32_t pipe_count = pool->res_cap->num_dwb;
1632
1633 for (i = 0; i < pipe_count; i++) {
1634 struct dcn30_mmhubbub *mcif_wb30 = kzalloc_obj(struct dcn30_mmhubbub);
1635
1636 if (!mcif_wb30) {
1637 dm_error("DC: failed to create mcif_wb30!\n");
1638 return false;
1639 }
1640
1641 dcn30_mmhubbub_construct(mcif_wb30, ctx,
1642 &mcif_wb30_regs[i],
1643 &mcif_wb30_shift,
1644 &mcif_wb30_mask,
1645 i);
1646
1647 pool->mcif_wb[i] = &mcif_wb30->base;
1648 }
1649 return true;
1650 }
1651
dcn314_dsc_create(struct dc_context * ctx,uint32_t inst)1652 static struct display_stream_compressor *dcn314_dsc_create(
1653 struct dc_context *ctx, uint32_t inst)
1654 {
1655 struct dcn20_dsc *dsc =
1656 kzalloc_obj(struct dcn20_dsc);
1657
1658 if (!dsc) {
1659 BREAK_TO_DEBUGGER();
1660 return NULL;
1661 }
1662
1663 dsc2_construct(dsc, ctx, inst, &dsc_regs[inst], &dsc_shift, &dsc_mask);
1664 return &dsc->base;
1665 }
1666
dcn314_destroy_resource_pool(struct resource_pool ** pool)1667 static void dcn314_destroy_resource_pool(struct resource_pool **pool)
1668 {
1669 struct dcn314_resource_pool *dcn314_pool = TO_DCN314_RES_POOL(*pool);
1670
1671 dcn314_resource_destruct(dcn314_pool);
1672 kfree(dcn314_pool);
1673 *pool = NULL;
1674 }
1675
dcn31_clock_source_create(struct dc_context * ctx,struct dc_bios * bios,enum clock_source_id id,const struct dce110_clk_src_regs * regs,bool dp_clk_src)1676 static struct clock_source *dcn31_clock_source_create(
1677 struct dc_context *ctx,
1678 struct dc_bios *bios,
1679 enum clock_source_id id,
1680 const struct dce110_clk_src_regs *regs,
1681 bool dp_clk_src)
1682 {
1683 struct dce110_clk_src *clk_src =
1684 kzalloc_obj(struct dce110_clk_src);
1685
1686 if (!clk_src)
1687 return NULL;
1688
1689 if (dcn31_clk_src_construct(clk_src, ctx, bios, id,
1690 regs, &cs_shift, &cs_mask)) {
1691 clk_src->base.dp_clk_src = dp_clk_src;
1692 return &clk_src->base;
1693 }
1694
1695 kfree(clk_src);
1696 BREAK_TO_DEBUGGER();
1697 return NULL;
1698 }
1699
dcn314_populate_dml_pipes_from_context(struct dc * dc,struct dc_state * context,display_e2e_pipe_params_st * pipes,enum dc_validate_mode validate_mode)1700 static int dcn314_populate_dml_pipes_from_context(
1701 struct dc *dc, struct dc_state *context,
1702 display_e2e_pipe_params_st *pipes,
1703 enum dc_validate_mode validate_mode)
1704 {
1705 int pipe_cnt;
1706
1707 DC_FP_START();
1708 pipe_cnt = dcn314_populate_dml_pipes_from_context_fpu(dc, context, pipes, validate_mode);
1709 DC_FP_END();
1710
1711 return pipe_cnt;
1712 }
1713
1714 static struct dc_cap_funcs cap_funcs = {
1715 .get_dcc_compression_cap = dcn20_get_dcc_compression_cap
1716 };
1717
dcn314_update_bw_bounding_box(struct dc * dc,struct clk_bw_params * bw_params)1718 static void dcn314_update_bw_bounding_box(struct dc *dc, struct clk_bw_params *bw_params)
1719 {
1720 DC_FP_START();
1721 dcn314_update_bw_bounding_box_fpu(dc, bw_params);
1722 DC_FP_END();
1723 }
1724
dcn314_get_panel_config_defaults(struct dc_panel_config * panel_config)1725 static void dcn314_get_panel_config_defaults(struct dc_panel_config *panel_config)
1726 {
1727 *panel_config = panel_config_defaults;
1728 }
1729
dcn314_validate_bandwidth(struct dc * dc,struct dc_state * context,enum dc_validate_mode validate_mode)1730 enum dc_status dcn314_validate_bandwidth(struct dc *dc,
1731 struct dc_state *context,
1732 enum dc_validate_mode validate_mode)
1733 {
1734 bool out = false;
1735
1736 BW_VAL_TRACE_SETUP();
1737
1738 int vlevel = 0;
1739 int pipe_cnt = 0;
1740 display_e2e_pipe_params_st *pipes = kzalloc_objs(display_e2e_pipe_params_st,
1741 dc->res_pool->pipe_count);
1742 DC_LOGGER_INIT(dc->ctx->logger);
1743
1744 BW_VAL_TRACE_COUNT();
1745
1746 if (!pipes)
1747 goto validate_fail;
1748
1749 DC_FP_START();
1750 // do not support self refresh only
1751 out = dcn30_internal_validate_bw(dc, context, pipes, &pipe_cnt, &vlevel, validate_mode, false);
1752 DC_FP_END();
1753
1754 // Disable DC_VALIDATE_MODE_ONLY and DC_VALIDATE_MODE_AND_STATE_INDEX to set min dcfclk in calculate_wm_and_dlg
1755 if (pipe_cnt == 0)
1756 validate_mode = DC_VALIDATE_MODE_AND_PROGRAMMING;
1757
1758 if (!out)
1759 goto validate_fail;
1760
1761 BW_VAL_TRACE_END_VOLTAGE_LEVEL();
1762
1763 if (validate_mode != DC_VALIDATE_MODE_AND_PROGRAMMING) {
1764 BW_VAL_TRACE_SKIP(fast);
1765 goto validate_out;
1766 }
1767 if (dc->res_pool->funcs->calculate_wm_and_dlg)
1768 dc->res_pool->funcs->calculate_wm_and_dlg(dc, context, pipes, pipe_cnt, vlevel);
1769
1770 BW_VAL_TRACE_END_WATERMARKS();
1771
1772 goto validate_out;
1773
1774 validate_fail:
1775 DC_LOG_WARNING("Mode Validation Warning: %s failed validation.\n",
1776 dml_get_status_message(context->bw_ctx.dml.vba.ValidationStatus[context->bw_ctx.dml.vba.soc.num_states]));
1777
1778 BW_VAL_TRACE_SKIP(fail);
1779 out = false;
1780
1781 validate_out:
1782 kfree(pipes);
1783
1784 BW_VAL_TRACE_FINISH();
1785
1786 return out ? DC_OK : DC_FAIL_BANDWIDTH_VALIDATE;
1787 }
1788
1789 static struct resource_funcs dcn314_res_pool_funcs = {
1790 .destroy = dcn314_destroy_resource_pool,
1791 .link_enc_create = dcn31_link_encoder_create,
1792 .link_enc_create_minimal = dcn31_link_enc_create_minimal,
1793 .link_encs_assign = link_enc_cfg_link_encs_assign,
1794 .link_enc_unassign = link_enc_cfg_link_enc_unassign,
1795 .panel_cntl_create = dcn31_panel_cntl_create,
1796 .validate_bandwidth = dcn314_validate_bandwidth,
1797 .calculate_wm_and_dlg = dcn31_calculate_wm_and_dlg,
1798 .update_soc_for_wm_a = dcn31_update_soc_for_wm_a,
1799 .populate_dml_pipes = dcn314_populate_dml_pipes_from_context,
1800 .acquire_free_pipe_as_secondary_dpp_pipe = dcn20_acquire_free_pipe_for_layer,
1801 .release_pipe = dcn20_release_pipe,
1802 .add_stream_to_ctx = dcn30_add_stream_to_ctx,
1803 .add_dsc_to_stream_resource = dcn20_add_dsc_to_stream_resource,
1804 .remove_stream_from_ctx = dcn20_remove_stream_from_ctx,
1805 .populate_dml_writeback_from_context = dcn30_populate_dml_writeback_from_context,
1806 .set_mcif_arb_params = dcn30_set_mcif_arb_params,
1807 .find_first_free_match_stream_enc_for_link = dcn10_find_first_free_match_stream_enc_for_link,
1808 .acquire_post_bldn_3dlut = dcn30_acquire_post_bldn_3dlut,
1809 .release_post_bldn_3dlut = dcn30_release_post_bldn_3dlut,
1810 .update_bw_bounding_box = dcn314_update_bw_bounding_box,
1811 .patch_unknown_plane_state = dcn20_patch_unknown_plane_state,
1812 .get_panel_config_defaults = dcn314_get_panel_config_defaults,
1813 .get_preferred_eng_id_dpia = dcn314_get_preferred_eng_id_dpia,
1814 .get_det_buffer_size = dcn31_get_det_buffer_size,
1815 .get_vstartup_for_pipe = dcn10_get_vstartup_for_pipe,
1816 .update_dc_state_for_encoder_switch = dcn31_update_dc_state_for_encoder_switch,
1817 .build_pipe_pix_clk_params = dcn20_build_pipe_pix_clk_params
1818 };
1819
dcn30_clock_source_create(struct dc_context * ctx,struct dc_bios * bios,enum clock_source_id id,const struct dce110_clk_src_regs * regs,bool dp_clk_src)1820 static struct clock_source *dcn30_clock_source_create(
1821 struct dc_context *ctx,
1822 struct dc_bios *bios,
1823 enum clock_source_id id,
1824 const struct dce110_clk_src_regs *regs,
1825 bool dp_clk_src)
1826 {
1827 struct dce110_clk_src *clk_src =
1828 kzalloc_obj(struct dce110_clk_src);
1829
1830 if (!clk_src)
1831 return NULL;
1832
1833 if (dcn31_clk_src_construct(clk_src, ctx, bios, id,
1834 regs, &cs_shift, &cs_mask)) {
1835 clk_src->base.dp_clk_src = dp_clk_src;
1836 return &clk_src->base;
1837 }
1838
1839 kfree(clk_src);
1840 BREAK_TO_DEBUGGER();
1841 return NULL;
1842 }
1843
dcn314_resource_construct(uint8_t num_virtual_links,struct dc * dc,struct dcn314_resource_pool * pool)1844 static bool dcn314_resource_construct(
1845 uint8_t num_virtual_links,
1846 struct dc *dc,
1847 struct dcn314_resource_pool *pool)
1848 {
1849 int i;
1850 struct dc_context *ctx = dc->ctx;
1851 struct irq_service_init_data init_data;
1852
1853 ctx->dc_bios->regs = &bios_regs;
1854
1855 pool->base.res_cap = &res_cap_dcn314;
1856 pool->base.funcs = &dcn314_res_pool_funcs;
1857
1858 /*************************************************
1859 * Resource + asic cap harcoding *
1860 *************************************************/
1861 pool->base.underlay_pipe_index = NO_UNDERLAY_PIPE;
1862 pool->base.pipe_count = pool->base.res_cap->num_timing_generator;
1863 pool->base.mpcc_count = pool->base.res_cap->num_timing_generator;
1864 dc->caps.max_downscale_ratio = 400;
1865 dc->caps.i2c_speed_in_khz = 100;
1866 dc->caps.i2c_speed_in_khz_hdcp = 100;
1867 dc->caps.max_cursor_size = 256;
1868 dc->caps.min_horizontal_blanking_period = 80;
1869 dc->caps.dmdata_alloc_size = 2048;
1870 dc->caps.max_slave_planes = 2;
1871 dc->caps.max_slave_yuv_planes = 2;
1872 dc->caps.max_slave_rgb_planes = 2;
1873 dc->caps.post_blend_color_processing = true;
1874 dc->caps.force_dp_tps4_for_cp2520 = true;
1875 if (dc->config.forceHBR2CP2520)
1876 dc->caps.force_dp_tps4_for_cp2520 = false;
1877 dc->caps.dp_hpo = true;
1878 dc->caps.dp_hdmi21_pcon_support = true;
1879 dc->caps.edp_dsc_support = true;
1880 dc->caps.extended_aux_timeout_support = true;
1881 dc->caps.dmcub_support = true;
1882 dc->caps.is_apu = true;
1883 dc->caps.seamless_odm = true;
1884
1885 dc->caps.zstate_support = true;
1886
1887 /* Color pipeline capabilities */
1888 dc->caps.color.dpp.dcn_arch = 1;
1889 dc->caps.color.dpp.input_lut_shared = 0;
1890 dc->caps.color.dpp.icsc = 1;
1891 dc->caps.color.dpp.dgam_ram = 0; // must use gamma_corr
1892 dc->caps.color.dpp.dgam_rom_caps.srgb = 1;
1893 dc->caps.color.dpp.dgam_rom_caps.bt2020 = 1;
1894 dc->caps.color.dpp.dgam_rom_caps.gamma2_2 = 1;
1895 dc->caps.color.dpp.dgam_rom_caps.pq = 1;
1896 dc->caps.color.dpp.dgam_rom_caps.hlg = 1;
1897 dc->caps.color.dpp.post_csc = 1;
1898 dc->caps.color.dpp.gamma_corr = 1;
1899 dc->caps.color.dpp.dgam_rom_for_yuv = 0;
1900
1901 dc->caps.color.dpp.hw_3d_lut = 1;
1902 dc->caps.color.dpp.ogam_ram = 1;
1903 // no OGAM ROM on DCN301
1904 dc->caps.color.dpp.ogam_rom_caps.srgb = 0;
1905 dc->caps.color.dpp.ogam_rom_caps.bt2020 = 0;
1906 dc->caps.color.dpp.ogam_rom_caps.gamma2_2 = 0;
1907 dc->caps.color.dpp.ogam_rom_caps.pq = 0;
1908 dc->caps.color.dpp.ogam_rom_caps.hlg = 0;
1909 dc->caps.color.dpp.ocsc = 0;
1910
1911 dc->caps.color.mpc.gamut_remap = 1;
1912 dc->caps.color.mpc.num_3dluts = pool->base.res_cap->num_mpc_3dlut; //2
1913 dc->caps.color.mpc.ogam_ram = 1;
1914 dc->caps.color.mpc.ogam_rom_caps.srgb = 0;
1915 dc->caps.color.mpc.ogam_rom_caps.bt2020 = 0;
1916 dc->caps.color.mpc.ogam_rom_caps.gamma2_2 = 0;
1917 dc->caps.color.mpc.ogam_rom_caps.pq = 0;
1918 dc->caps.color.mpc.ogam_rom_caps.hlg = 0;
1919 dc->caps.color.mpc.ocsc = 1;
1920
1921 dc->caps.max_disp_clock_khz_at_vmin = 650000;
1922
1923 dc->caps.num_of_host_routers = 2;
1924 dc->caps.num_of_dpias_per_host_router = 2;
1925
1926 /* Use pipe context based otg sync logic */
1927 dc->config.use_pipe_ctx_sync_logic = true;
1928
1929 /* read VBIOS LTTPR caps */
1930 {
1931 if (ctx->dc_bios->funcs->get_lttpr_caps) {
1932 enum bp_result bp_query_result;
1933 uint8_t is_vbios_lttpr_enable = 0;
1934
1935 bp_query_result = ctx->dc_bios->funcs->get_lttpr_caps(ctx->dc_bios, &is_vbios_lttpr_enable);
1936 dc->caps.vbios_lttpr_enable = (bp_query_result == BP_RESULT_OK) && !!is_vbios_lttpr_enable;
1937 }
1938
1939 /* interop bit is implicit */
1940 {
1941 dc->caps.vbios_lttpr_aware = true;
1942 }
1943 }
1944 dc->check_config = config_defaults;
1945
1946 if (dc->ctx->dce_environment == DCE_ENV_PRODUCTION_DRV)
1947 dc->debug = debug_defaults_drv;
1948
1949 /* Disable pipe power gating */
1950 dc->debug.disable_dpp_power_gate = true;
1951 dc->debug.disable_hubp_power_gate = true;
1952
1953 /* Disable root clock optimization */
1954 dc->debug.root_clock_optimization.u32All = 0;
1955
1956 // Init the vm_helper
1957 if (dc->vm_helper)
1958 vm_helper_init(dc->vm_helper, 16);
1959
1960 /*************************************************
1961 * Create resources *
1962 *************************************************/
1963
1964 /* Clock Sources for Pixel Clock*/
1965 pool->base.clock_sources[DCN31_CLK_SRC_PLL0] =
1966 dcn30_clock_source_create(ctx, ctx->dc_bios,
1967 CLOCK_SOURCE_COMBO_PHY_PLL0,
1968 &clk_src_regs[0], false);
1969 pool->base.clock_sources[DCN31_CLK_SRC_PLL1] =
1970 dcn30_clock_source_create(ctx, ctx->dc_bios,
1971 CLOCK_SOURCE_COMBO_PHY_PLL1,
1972 &clk_src_regs[1], false);
1973 pool->base.clock_sources[DCN31_CLK_SRC_PLL2] =
1974 dcn30_clock_source_create(ctx, ctx->dc_bios,
1975 CLOCK_SOURCE_COMBO_PHY_PLL2,
1976 &clk_src_regs[2], false);
1977 pool->base.clock_sources[DCN31_CLK_SRC_PLL3] =
1978 dcn30_clock_source_create(ctx, ctx->dc_bios,
1979 CLOCK_SOURCE_COMBO_PHY_PLL3,
1980 &clk_src_regs[3], false);
1981 pool->base.clock_sources[DCN31_CLK_SRC_PLL4] =
1982 dcn30_clock_source_create(ctx, ctx->dc_bios,
1983 CLOCK_SOURCE_COMBO_PHY_PLL4,
1984 &clk_src_regs[4], false);
1985
1986 pool->base.clk_src_count = DCN30_CLK_SRC_TOTAL;
1987
1988 /* todo: not reuse phy_pll registers */
1989 pool->base.dp_clock_source =
1990 dcn31_clock_source_create(ctx, ctx->dc_bios,
1991 CLOCK_SOURCE_ID_DP_DTO,
1992 &clk_src_regs[0], true);
1993
1994 for (i = 0; i < pool->base.clk_src_count; i++) {
1995 if (pool->base.clock_sources[i] == NULL) {
1996 dm_error("DC: failed to create clock sources!\n");
1997 BREAK_TO_DEBUGGER();
1998 goto create_fail;
1999 }
2000 }
2001
2002 pool->base.dccg = dccg314_create(ctx, &dccg_regs, &dccg_shift, &dccg_mask);
2003 if (pool->base.dccg == NULL) {
2004 dm_error("DC: failed to create dccg!\n");
2005 BREAK_TO_DEBUGGER();
2006 goto create_fail;
2007 }
2008
2009 init_data.ctx = dc->ctx;
2010 pool->base.irqs = dal_irq_service_dcn314_create(&init_data);
2011 if (!pool->base.irqs)
2012 goto create_fail;
2013
2014 /* HUBBUB */
2015 pool->base.hubbub = dcn31_hubbub_create(ctx);
2016 if (pool->base.hubbub == NULL) {
2017 BREAK_TO_DEBUGGER();
2018 dm_error("DC: failed to create hubbub!\n");
2019 goto create_fail;
2020 }
2021
2022 /* DIO */
2023 pool->base.dio = dcn314_dio_create(ctx);
2024 if (pool->base.dio == NULL) {
2025 BREAK_TO_DEBUGGER();
2026 dm_error("DC: failed to create dio!\n");
2027 goto create_fail;
2028 }
2029
2030 /* HUBPs, DPPs, OPPs and TGs */
2031 for (i = 0; i < pool->base.pipe_count; i++) {
2032 pool->base.hubps[i] = dcn31_hubp_create(ctx, i);
2033 if (pool->base.hubps[i] == NULL) {
2034 BREAK_TO_DEBUGGER();
2035 dm_error(
2036 "DC: failed to create hubps!\n");
2037 goto create_fail;
2038 }
2039
2040 pool->base.dpps[i] = dcn31_dpp_create(ctx, i);
2041 if (pool->base.dpps[i] == NULL) {
2042 BREAK_TO_DEBUGGER();
2043 dm_error(
2044 "DC: failed to create dpps!\n");
2045 goto create_fail;
2046 }
2047 }
2048
2049 for (i = 0; i < pool->base.res_cap->num_opp; i++) {
2050 pool->base.opps[i] = dcn31_opp_create(ctx, i);
2051 if (pool->base.opps[i] == NULL) {
2052 BREAK_TO_DEBUGGER();
2053 dm_error(
2054 "DC: failed to create output pixel processor!\n");
2055 goto create_fail;
2056 }
2057 }
2058
2059 for (i = 0; i < pool->base.res_cap->num_timing_generator; i++) {
2060 pool->base.timing_generators[i] = dcn31_timing_generator_create(
2061 ctx, i);
2062 if (pool->base.timing_generators[i] == NULL) {
2063 BREAK_TO_DEBUGGER();
2064 dm_error("DC: failed to create tg!\n");
2065 goto create_fail;
2066 }
2067 }
2068 pool->base.timing_generator_count = i;
2069
2070 /* PSR */
2071 pool->base.psr = dmub_psr_create(ctx);
2072 if (pool->base.psr == NULL) {
2073 dm_error("DC: failed to create psr obj!\n");
2074 BREAK_TO_DEBUGGER();
2075 goto create_fail;
2076 }
2077
2078 /* Replay */
2079 pool->base.replay = dmub_replay_create(ctx);
2080 if (pool->base.replay == NULL) {
2081 dm_error("DC: failed to create replay obj!\n");
2082 BREAK_TO_DEBUGGER();
2083 goto create_fail;
2084 }
2085
2086 /* ABM */
2087 for (i = 0; i < pool->base.res_cap->num_timing_generator; i++) {
2088 pool->base.multiple_abms[i] = dmub_abm_create(ctx,
2089 &abm_regs[i],
2090 &abm_shift,
2091 &abm_mask);
2092 if (pool->base.multiple_abms[i] == NULL) {
2093 dm_error("DC: failed to create abm for pipe %d!\n", i);
2094 BREAK_TO_DEBUGGER();
2095 goto create_fail;
2096 }
2097 }
2098
2099 /* MPC and DSC */
2100 pool->base.mpc = dcn31_mpc_create(ctx, pool->base.mpcc_count, pool->base.res_cap->num_mpc_3dlut);
2101 if (pool->base.mpc == NULL) {
2102 BREAK_TO_DEBUGGER();
2103 dm_error("DC: failed to create mpc!\n");
2104 goto create_fail;
2105 }
2106
2107 for (i = 0; i < pool->base.res_cap->num_dsc; i++) {
2108 pool->base.dscs[i] = dcn314_dsc_create(ctx, i);
2109 if (pool->base.dscs[i] == NULL) {
2110 BREAK_TO_DEBUGGER();
2111 dm_error("DC: failed to create display stream compressor %d!\n", i);
2112 goto create_fail;
2113 }
2114 }
2115
2116 /* DWB and MMHUBBUB */
2117 if (!dcn31_dwbc_create(ctx, &pool->base)) {
2118 BREAK_TO_DEBUGGER();
2119 dm_error("DC: failed to create dwbc!\n");
2120 goto create_fail;
2121 }
2122
2123 if (!dcn31_mmhubbub_create(ctx, &pool->base)) {
2124 BREAK_TO_DEBUGGER();
2125 dm_error("DC: failed to create mcif_wb!\n");
2126 goto create_fail;
2127 }
2128
2129 /* AUX and I2C */
2130 for (i = 0; i < pool->base.res_cap->num_ddc; i++) {
2131 pool->base.engines[i] = dcn31_aux_engine_create(ctx, i);
2132 if (pool->base.engines[i] == NULL) {
2133 BREAK_TO_DEBUGGER();
2134 dm_error(
2135 "DC:failed to create aux engine!!\n");
2136 goto create_fail;
2137 }
2138 pool->base.hw_i2cs[i] = dcn31_i2c_hw_create(ctx, i);
2139 if (pool->base.hw_i2cs[i] == NULL) {
2140 BREAK_TO_DEBUGGER();
2141 dm_error(
2142 "DC:failed to create hw i2c!!\n");
2143 goto create_fail;
2144 }
2145 pool->base.sw_i2cs[i] = NULL;
2146 }
2147
2148 /* DCN314 has 4 DPIA */
2149 pool->base.usb4_dpia_count = 4;
2150
2151 /* Audio, Stream Encoders including HPO and virtual, MPC 3D LUTs */
2152 if (!resource_construct(num_virtual_links, dc, &pool->base,
2153 &res_create_funcs))
2154 goto create_fail;
2155
2156 /* HW Sequencer and Plane caps */
2157 dcn314_hw_sequencer_construct(dc);
2158
2159 dc->caps.max_planes = pool->base.pipe_count;
2160
2161 for (i = 0; i < dc->caps.max_planes; ++i)
2162 dc->caps.planes[i] = plane_cap;
2163
2164 dc->caps.max_odm_combine_factor = 4;
2165
2166 dc->cap_funcs = cap_funcs;
2167
2168 dc->dcn_ip->max_num_dpp = dcn3_14_ip.max_num_dpp;
2169
2170 return true;
2171
2172 create_fail:
2173
2174 dcn314_resource_destruct(pool);
2175
2176 return false;
2177 }
2178
dcn314_create_resource_pool(const struct dc_init_data * init_data,struct dc * dc)2179 struct resource_pool *dcn314_create_resource_pool(
2180 const struct dc_init_data *init_data,
2181 struct dc *dc)
2182 {
2183 struct dcn314_resource_pool *pool =
2184 kzalloc_obj(struct dcn314_resource_pool);
2185
2186 if (!pool)
2187 return NULL;
2188
2189 if (dcn314_resource_construct(init_data->num_virtual_links, dc, pool))
2190 return &pool->base;
2191
2192 BREAK_TO_DEBUGGER();
2193 kfree(pool);
2194 return NULL;
2195 }
2196