1 /*
2  * Copyright 2020 Advanced Micro Devices, Inc.
3  *
4  * Permission is hereby granted, free of charge, to any person obtaining a
5  * copy of this software and associated documentation files (the "Software"),
6  * to deal in the Software without restriction, including without limitation
7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8  * and/or sell copies of the Software, and to permit persons to whom the
9  * Software is furnished to do so, subject to the following conditions:
10  *
11  * The above copyright notice and this permission notice shall be included in
12  * all copies or substantial portions of the Software.
13  *
14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20  * OTHER DEALINGS IN THE SOFTWARE.
21  *
22  * Authors: AMD
23  *
24  */
25 
26 
27 #include "dm_services.h"
28 #include "dm_helpers.h"
29 #include "core_types.h"
30 #include "resource.h"
31 #include "dcn30_hwseq.h"
32 #include "dccg.h"
33 #include "dce/dce_hwseq.h"
34 #include "dcn30/dcn30_mpc.h"
35 #include "dcn30/dcn30_dpp.h"
36 #include "dcn10/dcn10_cm_common.h"
37 #include "dcn30/dcn30_cm_common.h"
38 #include "reg_helper.h"
39 #include "abm.h"
40 #include "clk_mgr.h"
41 #include "hubp.h"
42 #include "dchubbub.h"
43 #include "timing_generator.h"
44 #include "opp.h"
45 #include "ipp.h"
46 #include "mpc.h"
47 #include "mcif_wb.h"
48 #include "dc_dmub_srv.h"
49 #include "link_hwss.h"
50 #include "dpcd_defs.h"
51 #include "dcn20/dcn20_hwseq.h"
52 #include "dcn30/dcn30_resource.h"
53 #include "link.h"
54 #include "dc_state_priv.h"
55 
56 
57 
58 #define DC_LOGGER_INIT(logger)
59 
60 #define CTX \
61 	hws->ctx
62 #define REG(reg)\
63 	hws->regs->reg
64 #define DC_LOGGER \
65 		dc->ctx->logger
66 
67 
68 #undef FN
69 #define FN(reg_name, field_name) \
70 	hws->shifts->field_name, hws->masks->field_name
71 
dcn30_set_blend_lut(struct pipe_ctx * pipe_ctx,const struct dc_plane_state * plane_state)72 bool dcn30_set_blend_lut(
73 	struct pipe_ctx *pipe_ctx, const struct dc_plane_state *plane_state)
74 {
75 	struct dpp *dpp_base = pipe_ctx->plane_res.dpp;
76 	bool result = true;
77 	struct pwl_params *blend_lut = NULL;
78 
79 	if (plane_state->blend_tf) {
80 		if (plane_state->blend_tf->type == TF_TYPE_HWPWL)
81 			blend_lut = &plane_state->blend_tf->pwl;
82 		else if (plane_state->blend_tf->type == TF_TYPE_DISTRIBUTED_POINTS) {
83 			cm3_helper_translate_curve_to_hw_format(
84 					plane_state->blend_tf, &dpp_base->regamma_params, false);
85 			blend_lut = &dpp_base->regamma_params;
86 		}
87 	}
88 	result = dpp_base->funcs->dpp_program_blnd_lut(dpp_base, blend_lut);
89 
90 	return result;
91 }
92 
dcn30_set_mpc_shaper_3dlut(struct pipe_ctx * pipe_ctx,const struct dc_stream_state * stream)93 static bool dcn30_set_mpc_shaper_3dlut(struct pipe_ctx *pipe_ctx,
94 				       const struct dc_stream_state *stream)
95 {
96 	struct dpp *dpp_base = pipe_ctx->plane_res.dpp;
97 	int mpcc_id = pipe_ctx->plane_res.hubp->inst;
98 	struct mpc *mpc = pipe_ctx->stream_res.opp->ctx->dc->res_pool->mpc;
99 	bool result = false;
100 	int acquired_rmu = 0;
101 	int mpcc_id_projected = 0;
102 
103 	const struct pwl_params *shaper_lut = NULL;
104 	//get the shaper lut params
105 	if (stream->func_shaper) {
106 		if (stream->func_shaper->type == TF_TYPE_HWPWL) {
107 			shaper_lut = &stream->func_shaper->pwl;
108 		} else if (stream->func_shaper->type == TF_TYPE_DISTRIBUTED_POINTS) {
109 			cm_helper_translate_curve_to_hw_format(stream->ctx, stream->func_shaper,
110 							       &dpp_base->shaper_params, true);
111 			shaper_lut = &dpp_base->shaper_params;
112 		}
113 	}
114 
115 	if (stream->lut3d_func &&
116 	    stream->lut3d_func->state.bits.initialized == 1 &&
117 	    stream->lut3d_func->state.bits.rmu_idx_valid == 1) {
118 		if (stream->lut3d_func->state.bits.rmu_mux_num == 0)
119 			mpcc_id_projected = stream->lut3d_func->state.bits.mpc_rmu0_mux;
120 		else if (stream->lut3d_func->state.bits.rmu_mux_num == 1)
121 			mpcc_id_projected = stream->lut3d_func->state.bits.mpc_rmu1_mux;
122 		else if (stream->lut3d_func->state.bits.rmu_mux_num == 2)
123 			mpcc_id_projected = stream->lut3d_func->state.bits.mpc_rmu2_mux;
124 		if (mpcc_id_projected != mpcc_id)
125 			BREAK_TO_DEBUGGER();
126 		/* find the reason why logical layer assigned a different
127 		 * mpcc_id into acquire_post_bldn_3dlut
128 		 */
129 		acquired_rmu = mpc->funcs->acquire_rmu(mpc, mpcc_id,
130 						       stream->lut3d_func->state.bits.rmu_mux_num);
131 		if (acquired_rmu != stream->lut3d_func->state.bits.rmu_mux_num)
132 			BREAK_TO_DEBUGGER();
133 
134 		result = mpc->funcs->program_3dlut(mpc, &stream->lut3d_func->lut_3d,
135 						   stream->lut3d_func->state.bits.rmu_mux_num);
136 		result = mpc->funcs->program_shaper(mpc, shaper_lut,
137 						    stream->lut3d_func->state.bits.rmu_mux_num);
138 	} else {
139 		// loop through the available mux and release the requested mpcc_id
140 		mpc->funcs->release_rmu(mpc, mpcc_id);
141 	}
142 
143 	return result;
144 }
145 
dcn30_set_input_transfer_func(struct dc * dc,struct pipe_ctx * pipe_ctx,const struct dc_plane_state * plane_state)146 bool dcn30_set_input_transfer_func(struct dc *dc,
147 				struct pipe_ctx *pipe_ctx,
148 				const struct dc_plane_state *plane_state)
149 {
150 	struct dce_hwseq *hws = dc->hwseq;
151 	struct dpp *dpp_base = pipe_ctx->plane_res.dpp;
152 	enum dc_transfer_func_predefined tf;
153 	bool result = true;
154 	struct pwl_params *params = NULL;
155 
156 	if (dpp_base == NULL || plane_state == NULL)
157 		return false;
158 
159 	tf = TRANSFER_FUNCTION_UNITY;
160 
161 	if (plane_state->in_transfer_func &&
162 		plane_state->in_transfer_func->type == TF_TYPE_PREDEFINED)
163 		tf = plane_state->in_transfer_func->tf;
164 
165 	dpp_base->funcs->dpp_set_pre_degam(dpp_base, tf);
166 
167 	if (plane_state->in_transfer_func) {
168 		if (plane_state->in_transfer_func->type == TF_TYPE_HWPWL)
169 			params = &plane_state->in_transfer_func->pwl;
170 		else if (plane_state->in_transfer_func->type == TF_TYPE_DISTRIBUTED_POINTS &&
171 			cm3_helper_translate_curve_to_hw_format(plane_state->in_transfer_func,
172 					&dpp_base->degamma_params, false))
173 			params = &dpp_base->degamma_params;
174 	}
175 
176 	result = dpp_base->funcs->dpp_program_gamcor_lut(dpp_base, params);
177 
178 	if (pipe_ctx->stream_res.opp && pipe_ctx->stream_res.opp->ctx) {
179 		if (dpp_base->funcs->dpp_program_blnd_lut)
180 			hws->funcs.set_blend_lut(pipe_ctx, plane_state);
181 		if (dpp_base->funcs->dpp_program_shaper_lut &&
182 				dpp_base->funcs->dpp_program_3dlut)
183 			hws->funcs.set_shaper_3dlut(pipe_ctx, plane_state);
184 	}
185 
186 	return result;
187 }
188 
dcn30_program_gamut_remap(struct pipe_ctx * pipe_ctx)189 void dcn30_program_gamut_remap(struct pipe_ctx *pipe_ctx)
190 {
191 	int i = 0;
192 	struct dpp_grph_csc_adjustment dpp_adjust;
193 	struct mpc_grph_gamut_adjustment mpc_adjust;
194 	int mpcc_id = pipe_ctx->plane_res.hubp->inst;
195 	struct mpc *mpc = pipe_ctx->stream_res.opp->ctx->dc->res_pool->mpc;
196 
197 	memset(&dpp_adjust, 0, sizeof(dpp_adjust));
198 	dpp_adjust.gamut_adjust_type = GRAPHICS_GAMUT_ADJUST_TYPE_BYPASS;
199 
200 	if (pipe_ctx->plane_state &&
201 	    pipe_ctx->plane_state->gamut_remap_matrix.enable_remap == true) {
202 		dpp_adjust.gamut_adjust_type = GRAPHICS_GAMUT_ADJUST_TYPE_SW;
203 		for (i = 0; i < CSC_TEMPERATURE_MATRIX_SIZE; i++)
204 			dpp_adjust.temperature_matrix[i] =
205 				pipe_ctx->plane_state->gamut_remap_matrix.matrix[i];
206 	}
207 
208 	pipe_ctx->plane_res.dpp->funcs->dpp_set_gamut_remap(pipe_ctx->plane_res.dpp,
209 							    &dpp_adjust);
210 
211 	memset(&mpc_adjust, 0, sizeof(mpc_adjust));
212 	mpc_adjust.gamut_adjust_type = GRAPHICS_GAMUT_ADJUST_TYPE_BYPASS;
213 
214 	if (pipe_ctx->top_pipe == NULL) {
215 		if (pipe_ctx->stream->gamut_remap_matrix.enable_remap == true) {
216 			mpc_adjust.gamut_adjust_type = GRAPHICS_GAMUT_ADJUST_TYPE_SW;
217 			for (i = 0; i < CSC_TEMPERATURE_MATRIX_SIZE; i++)
218 				mpc_adjust.temperature_matrix[i] =
219 					pipe_ctx->stream->gamut_remap_matrix.matrix[i];
220 		}
221 	}
222 
223 	mpc->funcs->set_gamut_remap(mpc, mpcc_id, &mpc_adjust);
224 }
225 
dcn30_set_output_transfer_func(struct dc * dc,struct pipe_ctx * pipe_ctx,const struct dc_stream_state * stream)226 bool dcn30_set_output_transfer_func(struct dc *dc,
227 				struct pipe_ctx *pipe_ctx,
228 				const struct dc_stream_state *stream)
229 {
230 	int mpcc_id = pipe_ctx->plane_res.hubp->inst;
231 	struct mpc *mpc = pipe_ctx->stream_res.opp->ctx->dc->res_pool->mpc;
232 	struct pwl_params *params = NULL;
233 	bool ret = false;
234 
235 	/* program OGAM or 3DLUT only for the top pipe*/
236 	if (pipe_ctx->top_pipe == NULL) {
237 		/*program rmu shaper and 3dlut in MPC*/
238 		ret = dcn30_set_mpc_shaper_3dlut(pipe_ctx, stream);
239 		if (ret == false && mpc->funcs->set_output_gamma && stream->out_transfer_func) {
240 			if (stream->out_transfer_func->type == TF_TYPE_HWPWL)
241 				params = &stream->out_transfer_func->pwl;
242 			else if (pipe_ctx->stream->out_transfer_func->type ==
243 					TF_TYPE_DISTRIBUTED_POINTS &&
244 					cm3_helper_translate_curve_to_hw_format(
245 					stream->out_transfer_func,
246 					&mpc->blender_params, false))
247 				params = &mpc->blender_params;
248 			 /* there are no ROM LUTs in OUTGAM */
249 			if (stream->out_transfer_func->type == TF_TYPE_PREDEFINED)
250 				BREAK_TO_DEBUGGER();
251 		}
252 	}
253 
254 	mpc->funcs->set_output_gamma(mpc, mpcc_id, params);
255 	return ret;
256 }
257 
dcn30_set_writeback(struct dc * dc,struct dc_writeback_info * wb_info,struct dc_state * context)258 static void dcn30_set_writeback(
259 		struct dc *dc,
260 		struct dc_writeback_info *wb_info,
261 		struct dc_state *context)
262 {
263 	struct mcif_wb *mcif_wb;
264 	struct mcif_buf_params *mcif_buf_params;
265 
266 	ASSERT(wb_info->dwb_pipe_inst < MAX_DWB_PIPES);
267 	ASSERT(wb_info->wb_enabled);
268 	ASSERT(wb_info->mpcc_inst >= 0);
269 	ASSERT(wb_info->mpcc_inst < dc->res_pool->mpcc_count);
270 	mcif_wb = dc->res_pool->mcif_wb[wb_info->dwb_pipe_inst];
271 	mcif_buf_params = &wb_info->mcif_buf_params;
272 
273 	/* set DWB MPC mux */
274 	dc->res_pool->mpc->funcs->set_dwb_mux(dc->res_pool->mpc,
275 			wb_info->dwb_pipe_inst, wb_info->mpcc_inst);
276 	/* set MCIF_WB buffer and arbitration configuration */
277 	mcif_wb->funcs->config_mcif_buf(mcif_wb, mcif_buf_params, wb_info->dwb_params.dest_height);
278 	mcif_wb->funcs->config_mcif_arb(mcif_wb, &context->bw_ctx.bw.dcn.bw_writeback.mcif_wb_arb[wb_info->dwb_pipe_inst]);
279 }
280 
dcn30_update_writeback(struct dc * dc,struct dc_writeback_info * wb_info,struct dc_state * context)281 void dcn30_update_writeback(
282 		struct dc *dc,
283 		struct dc_writeback_info *wb_info,
284 		struct dc_state *context)
285 {
286 	struct dwbc *dwb;
287 	dwb = dc->res_pool->dwbc[wb_info->dwb_pipe_inst];
288 	DC_LOG_DWB("%s dwb_pipe_inst = %d, mpcc_inst = %d",\
289 		__func__, wb_info->dwb_pipe_inst,\
290 		wb_info->mpcc_inst);
291 
292 	dcn30_set_writeback(dc, wb_info, context);
293 
294 	/* update DWB */
295 	dwb->funcs->update(dwb, &wb_info->dwb_params);
296 }
297 
dcn30_mmhubbub_warmup(struct dc * dc,unsigned int num_dwb,struct dc_writeback_info * wb_info)298 bool dcn30_mmhubbub_warmup(
299 	struct dc *dc,
300 	unsigned int num_dwb,
301 	struct dc_writeback_info *wb_info)
302 {
303 	struct dwbc *dwb;
304 	struct mcif_wb *mcif_wb;
305 	struct mcif_warmup_params warmup_params = {0};
306 	unsigned int  i, i_buf;
307 	/*make sure there is no active DWB eanbled */
308 	for (i = 0; i < num_dwb; i++) {
309 		dwb = dc->res_pool->dwbc[wb_info[i].dwb_pipe_inst];
310 		if (dwb->dwb_is_efc_transition || dwb->dwb_is_drc) {
311 			/*can not do warmup while any dwb enabled*/
312 			return false;
313 		}
314 	}
315 
316 	if (wb_info->mcif_warmup_params.p_vmid == 0)
317 		return false;
318 
319 	/*check whether this is new interface: warmup big buffer once*/
320 	if (wb_info->mcif_warmup_params.start_address.quad_part != 0 &&
321 		wb_info->mcif_warmup_params.region_size != 0) {
322 		/*mmhubbub is shared, so it does not matter which MCIF*/
323 		mcif_wb = dc->res_pool->mcif_wb[0];
324 		/*warmup a big chunk of VM buffer at once*/
325 		warmup_params.start_address.quad_part = wb_info->mcif_warmup_params.start_address.quad_part;
326 		warmup_params.address_increment =  wb_info->mcif_warmup_params.region_size;
327 		warmup_params.region_size = wb_info->mcif_warmup_params.region_size;
328 		warmup_params.p_vmid = wb_info->mcif_warmup_params.p_vmid;
329 
330 		if (warmup_params.address_increment == 0)
331 			warmup_params.address_increment = dc->dml.soc.vmm_page_size_bytes;
332 
333 		mcif_wb->funcs->warmup_mcif(mcif_wb, &warmup_params);
334 		return true;
335 	}
336 	/*following is the original: warmup each DWB's mcif buffer*/
337 	for (i = 0; i < num_dwb; i++) {
338 		dwb = dc->res_pool->dwbc[wb_info[i].dwb_pipe_inst];
339 		mcif_wb = dc->res_pool->mcif_wb[wb_info[i].dwb_pipe_inst];
340 		/*warmup is for VM mode only*/
341 		if (wb_info[i].mcif_buf_params.p_vmid == 0)
342 			return false;
343 
344 		/* Warmup MCIF_WB */
345 		for (i_buf = 0; i_buf < MCIF_BUF_COUNT; i_buf++) {
346 			warmup_params.start_address.quad_part = wb_info[i].mcif_buf_params.luma_address[i_buf];
347 			warmup_params.address_increment = dc->dml.soc.vmm_page_size_bytes;
348 			warmup_params.region_size = wb_info[i].mcif_buf_params.luma_pitch * wb_info[i].dwb_params.dest_height;
349 			warmup_params.p_vmid = wb_info[i].mcif_buf_params.p_vmid;
350 			mcif_wb->funcs->warmup_mcif(mcif_wb, &warmup_params);
351 		}
352 	}
353 	return true;
354 }
355 
dcn30_enable_writeback(struct dc * dc,struct dc_writeback_info * wb_info,struct dc_state * context)356 void dcn30_enable_writeback(
357 		struct dc *dc,
358 		struct dc_writeback_info *wb_info,
359 		struct dc_state *context)
360 {
361 	struct dwbc *dwb;
362 	struct mcif_wb *mcif_wb;
363 
364 	dwb = dc->res_pool->dwbc[wb_info->dwb_pipe_inst];
365 	mcif_wb = dc->res_pool->mcif_wb[wb_info->dwb_pipe_inst];
366 
367 	DC_LOG_DWB("%s dwb_pipe_inst = %d, mpcc_inst = %d",\
368 		__func__, wb_info->dwb_pipe_inst,\
369 		wb_info->mpcc_inst);
370 
371 	/* Warmup interface */
372 	dcn30_mmhubbub_warmup(dc, 1, wb_info);
373 
374 	/* Update writeback pipe */
375 	dcn30_set_writeback(dc, wb_info, context);
376 
377 	/* Enable MCIF_WB */
378 	mcif_wb->funcs->enable_mcif(mcif_wb);
379 	/* Enable DWB */
380 	dwb->funcs->enable(dwb, &wb_info->dwb_params);
381 }
382 
dcn30_disable_writeback(struct dc * dc,unsigned int dwb_pipe_inst)383 void dcn30_disable_writeback(
384 		struct dc *dc,
385 		unsigned int dwb_pipe_inst)
386 {
387 	struct dwbc *dwb;
388 	struct mcif_wb *mcif_wb;
389 
390 	ASSERT(dwb_pipe_inst < MAX_DWB_PIPES);
391 	dwb = dc->res_pool->dwbc[dwb_pipe_inst];
392 	mcif_wb = dc->res_pool->mcif_wb[dwb_pipe_inst];
393 	DC_LOG_DWB("%s dwb_pipe_inst = %d",\
394 		__func__, dwb_pipe_inst);
395 
396 	/* disable DWB */
397 	dwb->funcs->disable(dwb);
398 	/* disable MCIF */
399 	mcif_wb->funcs->disable_mcif(mcif_wb);
400 	/* disable MPC DWB mux */
401 	dc->res_pool->mpc->funcs->disable_dwb_mux(dc->res_pool->mpc, dwb_pipe_inst);
402 }
403 
dcn30_program_all_writeback_pipes_in_tree(struct dc * dc,const struct dc_stream_state * stream,struct dc_state * context)404 void dcn30_program_all_writeback_pipes_in_tree(
405 		struct dc *dc,
406 		const struct dc_stream_state *stream,
407 		struct dc_state *context)
408 {
409 	struct dc_writeback_info wb_info;
410 	struct dwbc *dwb;
411 	struct dc_stream_status *stream_status = NULL;
412 	int i_wb, i_pipe, i_stream;
413 	DC_LOG_DWB("%s", __func__);
414 
415 	ASSERT(stream);
416 	for (i_stream = 0; i_stream < context->stream_count; i_stream++) {
417 		if (context->streams[i_stream] == stream) {
418 			stream_status = &context->stream_status[i_stream];
419 			break;
420 		}
421 	}
422 	ASSERT(stream_status);
423 
424 	ASSERT(stream->num_wb_info <= dc->res_pool->res_cap->num_dwb);
425 	/* For each writeback pipe */
426 	for (i_wb = 0; i_wb < stream->num_wb_info; i_wb++) {
427 
428 		/* copy writeback info to local non-const so mpcc_inst can be set */
429 		wb_info = stream->writeback_info[i_wb];
430 		if (wb_info.wb_enabled) {
431 
432 			/* get the MPCC instance for writeback_source_plane */
433 			wb_info.mpcc_inst = -1;
434 			for (i_pipe = 0; i_pipe < dc->res_pool->pipe_count; i_pipe++) {
435 				struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[i_pipe];
436 
437 				if (!pipe_ctx->plane_state)
438 					continue;
439 
440 				if (pipe_ctx->plane_state == wb_info.writeback_source_plane) {
441 					wb_info.mpcc_inst = pipe_ctx->plane_res.mpcc_inst;
442 					break;
443 				}
444 			}
445 
446 			if (wb_info.mpcc_inst == -1) {
447 				/* Disable writeback pipe and disconnect from MPCC
448 				 * if source plane has been removed
449 				 */
450 				dc->hwss.disable_writeback(dc, wb_info.dwb_pipe_inst);
451 				continue;
452 			}
453 
454 			ASSERT(wb_info.dwb_pipe_inst < dc->res_pool->res_cap->num_dwb);
455 			dwb = dc->res_pool->dwbc[wb_info.dwb_pipe_inst];
456 			if (dwb->funcs->is_enabled(dwb)) {
457 				/* writeback pipe already enabled, only need to update */
458 				dc->hwss.update_writeback(dc, &wb_info, context);
459 			} else {
460 				/* Enable writeback pipe and connect to MPCC */
461 				dc->hwss.enable_writeback(dc, &wb_info, context);
462 			}
463 		} else {
464 			/* Disable writeback pipe and disconnect from MPCC */
465 			dc->hwss.disable_writeback(dc, wb_info.dwb_pipe_inst);
466 		}
467 	}
468 }
469 
dcn30_init_hw(struct dc * dc)470 void dcn30_init_hw(struct dc *dc)
471 {
472 	struct abm **abms = dc->res_pool->multiple_abms;
473 	struct dce_hwseq *hws = dc->hwseq;
474 	struct dc_bios *dcb = dc->ctx->dc_bios;
475 	struct resource_pool *res_pool = dc->res_pool;
476 	int i;
477 	int edp_num;
478 	uint32_t backlight = MAX_BACKLIGHT_LEVEL;
479 	uint32_t user_level = MAX_BACKLIGHT_LEVEL;
480 
481 	if (dc->clk_mgr && dc->clk_mgr->funcs->init_clocks)
482 		dc->clk_mgr->funcs->init_clocks(dc->clk_mgr);
483 
484 	// Initialize the dccg
485 	if (res_pool->dccg->funcs->dccg_init)
486 		res_pool->dccg->funcs->dccg_init(res_pool->dccg);
487 
488 	if (!dcb->funcs->is_accelerated_mode(dcb)) {
489 		hws->funcs.bios_golden_init(dc);
490 		hws->funcs.disable_vga(dc->hwseq);
491 	}
492 
493 	if (dc->debug.enable_mem_low_power.bits.dmcu) {
494 		// Force ERAM to shutdown if DMCU is not enabled
495 		if (dc->debug.disable_dmcu || dc->config.disable_dmcu) {
496 			REG_UPDATE(DMU_MEM_PWR_CNTL, DMCU_ERAM_MEM_PWR_FORCE, 3);
497 		}
498 	}
499 
500 	// Set default OPTC memory power states
501 	if (dc->debug.enable_mem_low_power.bits.optc) {
502 		// Shutdown when unassigned and light sleep in VBLANK
503 		REG_SET_2(ODM_MEM_PWR_CTRL3, 0, ODM_MEM_UNASSIGNED_PWR_MODE, 3, ODM_MEM_VBLANK_PWR_MODE, 1);
504 	}
505 
506 	if (dc->debug.enable_mem_low_power.bits.vga) {
507 		// Power down VGA memory
508 		REG_UPDATE(MMHUBBUB_MEM_PWR_CNTL, VGA_MEM_PWR_FORCE, 1);
509 	}
510 
511 	if (dc->ctx->dc_bios->fw_info_valid) {
512 		res_pool->ref_clocks.xtalin_clock_inKhz =
513 				dc->ctx->dc_bios->fw_info.pll_info.crystal_frequency;
514 
515 		if (res_pool->dccg && res_pool->hubbub) {
516 
517 			(res_pool->dccg->funcs->get_dccg_ref_freq)(res_pool->dccg,
518 					dc->ctx->dc_bios->fw_info.pll_info.crystal_frequency,
519 					&res_pool->ref_clocks.dccg_ref_clock_inKhz);
520 
521 			(res_pool->hubbub->funcs->get_dchub_ref_freq)(res_pool->hubbub,
522 					res_pool->ref_clocks.dccg_ref_clock_inKhz,
523 					&res_pool->ref_clocks.dchub_ref_clock_inKhz);
524 		} else {
525 			// Not all ASICs have DCCG sw component
526 			res_pool->ref_clocks.dccg_ref_clock_inKhz =
527 					res_pool->ref_clocks.xtalin_clock_inKhz;
528 			res_pool->ref_clocks.dchub_ref_clock_inKhz =
529 					res_pool->ref_clocks.xtalin_clock_inKhz;
530 		}
531 	} else
532 		ASSERT_CRITICAL(false);
533 
534 	for (i = 0; i < dc->link_count; i++) {
535 		/* Power up AND update implementation according to the
536 		 * required signal (which may be different from the
537 		 * default signal on connector).
538 		 */
539 		struct dc_link *link = dc->links[i];
540 
541 		link->link_enc->funcs->hw_init(link->link_enc);
542 
543 		/* Check for enabled DIG to identify enabled display */
544 		if (link->link_enc->funcs->is_dig_enabled &&
545 			link->link_enc->funcs->is_dig_enabled(link->link_enc)) {
546 			link->link_status.link_active = true;
547 			if (link->link_enc->funcs->fec_is_active &&
548 					link->link_enc->funcs->fec_is_active(link->link_enc))
549 				link->fec_state = dc_link_fec_enabled;
550 		}
551 	}
552 
553 	/* we want to turn off all dp displays before doing detection */
554 	dc->link_srv->blank_all_dp_displays(dc);
555 
556 	if (hws->funcs.enable_power_gating_plane)
557 		hws->funcs.enable_power_gating_plane(dc->hwseq, true);
558 
559 	/* If taking control over from VBIOS, we may want to optimize our first
560 	 * mode set, so we need to skip powering down pipes until we know which
561 	 * pipes we want to use.
562 	 * Otherwise, if taking control is not possible, we need to power
563 	 * everything down.
564 	 */
565 	if (dcb->funcs->is_accelerated_mode(dcb) || !dc->config.seamless_boot_edp_requested) {
566 		hws->funcs.init_pipes(dc, dc->current_state);
567 		if (dc->res_pool->hubbub->funcs->allow_self_refresh_control)
568 			dc->res_pool->hubbub->funcs->allow_self_refresh_control(dc->res_pool->hubbub,
569 					!dc->res_pool->hubbub->ctx->dc->debug.disable_stutter);
570 	}
571 
572 	/* In headless boot cases, DIG may be turned
573 	 * on which causes HW/SW discrepancies.
574 	 * To avoid this, power down hardware on boot
575 	 * if DIG is turned on and seamless boot not enabled
576 	 */
577 	if (!dc->config.seamless_boot_edp_requested) {
578 		struct dc_link *edp_links[MAX_NUM_EDP];
579 		struct dc_link *edp_link = NULL;
580 
581 		dc_get_edp_links(dc, edp_links, &edp_num);
582 		if (edp_num)
583 			edp_link = edp_links[0];
584 		if (edp_link && edp_link->link_enc->funcs->is_dig_enabled &&
585 				edp_link->link_enc->funcs->is_dig_enabled(edp_link->link_enc) &&
586 				dc->hwss.edp_backlight_control &&
587 				dc->hwss.power_down &&
588 				dc->hwss.edp_power_control) {
589 			dc->hwss.edp_backlight_control(edp_link, false);
590 			dc->hwss.power_down(dc);
591 			dc->hwss.edp_power_control(edp_link, false);
592 		} else {
593 			for (i = 0; i < dc->link_count; i++) {
594 				struct dc_link *link = dc->links[i];
595 
596 				if (link->link_enc->funcs->is_dig_enabled &&
597 						link->link_enc->funcs->is_dig_enabled(link->link_enc) &&
598 						dc->hwss.power_down) {
599 					dc->hwss.power_down(dc);
600 					break;
601 				}
602 
603 			}
604 		}
605 	}
606 
607 	for (i = 0; i < res_pool->audio_count; i++) {
608 		struct audio *audio = res_pool->audios[i];
609 
610 		audio->funcs->hw_init(audio);
611 	}
612 
613 	for (i = 0; i < dc->link_count; i++) {
614 		struct dc_link *link = dc->links[i];
615 
616 		if (link->panel_cntl) {
617 			backlight = link->panel_cntl->funcs->hw_init(link->panel_cntl);
618 			user_level = link->panel_cntl->stored_backlight_registers.USER_LEVEL;
619 		}
620 	}
621 
622 	for (i = 0; i < dc->res_pool->pipe_count; i++) {
623 		if (abms[i] != NULL)
624 			abms[i]->funcs->abm_init(abms[i], backlight, user_level);
625 	}
626 
627 	/* power AFMT HDMI memory TODO: may move to dis/en output save power*/
628 	REG_WRITE(DIO_MEM_PWR_CTRL, 0);
629 
630 	if (!dc->debug.disable_clock_gate) {
631 		/* enable all DCN clock gating */
632 		REG_WRITE(DCCG_GATE_DISABLE_CNTL, 0);
633 
634 		REG_WRITE(DCCG_GATE_DISABLE_CNTL2, 0);
635 
636 		REG_UPDATE(DCFCLK_CNTL, DCFCLK_GATE_DIS, 0);
637 	}
638 
639 	if (!dcb->funcs->is_accelerated_mode(dcb) && dc->res_pool->hubbub->funcs->init_watermarks)
640 		dc->res_pool->hubbub->funcs->init_watermarks(dc->res_pool->hubbub);
641 
642 	if (dc->clk_mgr->funcs->notify_wm_ranges)
643 		dc->clk_mgr->funcs->notify_wm_ranges(dc->clk_mgr);
644 
645 	//if softmax is enabled then hardmax will be set by a different call
646 	if (dc->clk_mgr->funcs->set_hard_max_memclk && !dc->clk_mgr->dc_mode_softmax_enabled)
647 		dc->clk_mgr->funcs->set_hard_max_memclk(dc->clk_mgr);
648 
649 	if (dc->res_pool->hubbub->funcs->force_pstate_change_control)
650 		dc->res_pool->hubbub->funcs->force_pstate_change_control(
651 				dc->res_pool->hubbub, false, false);
652 	if (dc->res_pool->hubbub->funcs->init_crb)
653 		dc->res_pool->hubbub->funcs->init_crb(dc->res_pool->hubbub);
654 
655 	// Get DMCUB capabilities
656 	dc_dmub_srv_query_caps_cmd(dc->ctx->dmub_srv);
657 	dc->caps.dmub_caps.psr = dc->ctx->dmub_srv->dmub->feature_caps.psr;
658 	dc->caps.dmub_caps.mclk_sw = dc->ctx->dmub_srv->dmub->feature_caps.fw_assisted_mclk_switch;
659 }
660 
dcn30_set_avmute(struct pipe_ctx * pipe_ctx,bool enable)661 void dcn30_set_avmute(struct pipe_ctx *pipe_ctx, bool enable)
662 {
663 	if (pipe_ctx == NULL)
664 		return;
665 
666 	if (dc_is_hdmi_signal(pipe_ctx->stream->signal) && pipe_ctx->stream_res.stream_enc != NULL)
667 		pipe_ctx->stream_res.stream_enc->funcs->set_avmute(
668 				pipe_ctx->stream_res.stream_enc,
669 				enable);
670 }
671 
dcn30_update_info_frame(struct pipe_ctx * pipe_ctx)672 void dcn30_update_info_frame(struct pipe_ctx *pipe_ctx)
673 {
674 	bool is_hdmi_tmds;
675 	bool is_dp;
676 
677 	ASSERT(pipe_ctx->stream);
678 
679 	if (pipe_ctx->stream_res.stream_enc == NULL)
680 		return;  /* this is not root pipe */
681 
682 	is_hdmi_tmds = dc_is_hdmi_tmds_signal(pipe_ctx->stream->signal);
683 	is_dp = dc_is_dp_signal(pipe_ctx->stream->signal);
684 
685 	if (!is_hdmi_tmds && !is_dp)
686 		return;
687 
688 	if (is_hdmi_tmds)
689 		pipe_ctx->stream_res.stream_enc->funcs->update_hdmi_info_packets(
690 			pipe_ctx->stream_res.stream_enc,
691 			&pipe_ctx->stream_res.encoder_info_frame);
692 	else {
693 		if (pipe_ctx->stream_res.stream_enc->funcs->update_dp_info_packets_sdp_line_num)
694 			pipe_ctx->stream_res.stream_enc->funcs->update_dp_info_packets_sdp_line_num(
695 				pipe_ctx->stream_res.stream_enc,
696 				&pipe_ctx->stream_res.encoder_info_frame);
697 
698 		pipe_ctx->stream_res.stream_enc->funcs->update_dp_info_packets(
699 			pipe_ctx->stream_res.stream_enc,
700 			&pipe_ctx->stream_res.encoder_info_frame);
701 	}
702 }
703 
dcn30_program_dmdata_engine(struct pipe_ctx * pipe_ctx)704 void dcn30_program_dmdata_engine(struct pipe_ctx *pipe_ctx)
705 {
706 	struct dc_stream_state    *stream     = pipe_ctx->stream;
707 	struct hubp               *hubp       = pipe_ctx->plane_res.hubp;
708 	bool                       enable     = false;
709 	struct stream_encoder     *stream_enc = pipe_ctx->stream_res.stream_enc;
710 	enum dynamic_metadata_mode mode       = dc_is_dp_signal(stream->signal)
711 							? dmdata_dp
712 							: dmdata_hdmi;
713 
714 	/* if using dynamic meta, don't set up generic infopackets */
715 	if (pipe_ctx->stream->dmdata_address.quad_part != 0) {
716 		pipe_ctx->stream_res.encoder_info_frame.hdrsmd.valid = false;
717 		enable = true;
718 	}
719 
720 	if (!hubp)
721 		return;
722 
723 	if (!stream_enc || !stream_enc->funcs->set_dynamic_metadata)
724 		return;
725 
726 	stream_enc->funcs->set_dynamic_metadata(stream_enc, enable,
727 							hubp->inst, mode);
728 }
729 
dcn30_apply_idle_power_optimizations(struct dc * dc,bool enable)730 bool dcn30_apply_idle_power_optimizations(struct dc *dc, bool enable)
731 {
732 	union dmub_rb_cmd cmd;
733 	uint32_t tmr_delay = 0, tmr_scale = 0;
734 	struct dc_cursor_attributes cursor_attr;
735 	bool cursor_cache_enable = false;
736 	struct dc_stream_state *stream = NULL;
737 	struct dc_plane_state *plane = NULL;
738 
739 	if (!dc->ctx->dmub_srv)
740 		return false;
741 
742 	if (enable) {
743 		if (dc->current_state) {
744 			int i;
745 
746 			/* First, check no-memory-requests case */
747 			for (i = 0; i < dc->current_state->stream_count; i++) {
748 				if (dc->current_state->stream_status[i].plane_count)
749 					/* Fail eligibility on a visible stream */
750 					break;
751 			}
752 
753 			if (i == dc->current_state->stream_count) {
754 				/* Enable no-memory-requests case */
755 				memset(&cmd, 0, sizeof(cmd));
756 				cmd.mall.header.type = DMUB_CMD__MALL;
757 				cmd.mall.header.sub_type = DMUB_CMD__MALL_ACTION_NO_DF_REQ;
758 				cmd.mall.header.payload_bytes = sizeof(cmd.mall) - sizeof(cmd.mall.header);
759 
760 				dc_wake_and_execute_dmub_cmd(dc->ctx, &cmd, DM_DMUB_WAIT_TYPE_NO_WAIT);
761 
762 				return true;
763 			}
764 
765 			stream = dc->current_state->streams[0];
766 			plane = (stream ? dc->current_state->stream_status[0].plane_states[0] : NULL);
767 
768 			if (stream && plane) {
769 				cursor_cache_enable = stream->cursor_position.enable &&
770 						plane->address.grph.cursor_cache_addr.quad_part;
771 				cursor_attr = stream->cursor_attributes;
772 			}
773 
774 			/*
775 			 * Second, check MALL eligibility
776 			 *
777 			 * single display only, single surface only, 8 and 16 bit formats only, no VM,
778 			 * do not use MALL for displays that support PSR as they use D0i3.2 in DMCUB FW
779 			 *
780 			 * TODO: When we implement multi-display, PSR displays will be allowed if there is
781 			 * a non-PSR display present, since in that case we can't do D0i3.2
782 			 */
783 			if (dc->current_state->stream_count == 1 &&
784 					stream->link->psr_settings.psr_version == DC_PSR_VERSION_UNSUPPORTED &&
785 					dc->current_state->stream_status[0].plane_count == 1 &&
786 					plane->format <= SURFACE_PIXEL_FORMAT_GRPH_ABGR16161616F &&
787 					plane->format >= SURFACE_PIXEL_FORMAT_GRPH_ARGB8888 &&
788 					plane->address.page_table_base.quad_part == 0 &&
789 					dc->hwss.does_plane_fit_in_mall &&
790 					dc->hwss.does_plane_fit_in_mall(dc, plane,
791 							cursor_cache_enable ? &cursor_attr : NULL)) {
792 				unsigned int v_total = stream->adjust.v_total_max ?
793 						stream->adjust.v_total_max : stream->timing.v_total;
794 				unsigned int refresh_hz = div_u64((unsigned long long) stream->timing.pix_clk_100hz *
795 						100LL, (v_total * stream->timing.h_total));
796 
797 				/*
798 				 * one frame time in microsec:
799 				 * Delay_Us = 1000000 / refresh
800 				 * dynamic_delay_us = 1000000 / refresh + 2 * stutter_period
801 				 *
802 				 * one frame time modified by 'additional timer percent' (p):
803 				 * Delay_Us_modified = dynamic_delay_us + dynamic_delay_us * p / 100
804 				 *                   = dynamic_delay_us * (1 + p / 100)
805 				 *                   = (1000000 / refresh + 2 * stutter_period) * (100 + p) / 100
806 				 *                   = (1000000 + 2 * stutter_period * refresh) * (100 + p) / (100 * refresh)
807 				 *
808 				 * formula for timer duration based on parameters, from regspec:
809 				 * dynamic_delay_us = 65.28 * (64 + MallFrameCacheTmrDly) * 2^MallFrameCacheTmrScale
810 				 *
811 				 * dynamic_delay_us / 65.28 = (64 + MallFrameCacheTmrDly) * 2^MallFrameCacheTmrScale
812 				 * (dynamic_delay_us / 65.28) / 2^MallFrameCacheTmrScale = 64 + MallFrameCacheTmrDly
813 				 * MallFrameCacheTmrDly = ((dynamic_delay_us / 65.28) / 2^MallFrameCacheTmrScale) - 64
814 				 *                      = (1000000 + 2 * stutter_period * refresh) * (100 + p) / (100 * refresh) / 65.28 / 2^MallFrameCacheTmrScale - 64
815 				 *                      = (1000000 + 2 * stutter_period * refresh) * (100 + p) / (refresh * 6528 * 2^MallFrameCacheTmrScale) - 64
816 				 *
817 				 * need to round up the result of the division before the subtraction
818 				 */
819 				unsigned int denom = refresh_hz * 6528;
820 				unsigned int stutter_period = dc->current_state->perf_params.stutter_period_us;
821 
822 				tmr_delay = div_u64(((1000000LL + 2 * stutter_period * refresh_hz) *
823 						(100LL + dc->debug.mall_additional_timer_percent) + denom - 1),
824 						denom) - 64LL;
825 
826 				/* In some cases the stutter period is really big (tiny modes) in these
827 				 * cases MALL cant be enabled, So skip these cases to avoid a ASSERT()
828 				 *
829 				 * We can check if stutter_period is more than 1/10th the frame time to
830 				 * consider if we can actually meet the range of hysteresis timer
831 				 */
832 				if (stutter_period > 100000/refresh_hz)
833 					return false;
834 
835 				/* scale should be increased until it fits into 6 bits */
836 				while (tmr_delay & ~0x3F) {
837 					tmr_scale++;
838 
839 					if (tmr_scale > 3) {
840 						/* Delay exceeds range of hysteresis timer */
841 						ASSERT(false);
842 						return false;
843 					}
844 
845 					denom *= 2;
846 					tmr_delay = div_u64(((1000000LL + 2 * stutter_period * refresh_hz) *
847 							(100LL + dc->debug.mall_additional_timer_percent) + denom - 1),
848 							denom) - 64LL;
849 				}
850 
851 				/* Copy HW cursor */
852 				if (cursor_cache_enable) {
853 					memset(&cmd, 0, sizeof(cmd));
854 					cmd.mall.header.type = DMUB_CMD__MALL;
855 					cmd.mall.header.sub_type = DMUB_CMD__MALL_ACTION_COPY_CURSOR;
856 					cmd.mall.header.payload_bytes =
857 							sizeof(cmd.mall) - sizeof(cmd.mall.header);
858 
859 					switch (cursor_attr.color_format) {
860 					case CURSOR_MODE_MONO:
861 						cmd.mall.cursor_bpp = 2;
862 						break;
863 					case CURSOR_MODE_COLOR_1BIT_AND:
864 					case CURSOR_MODE_COLOR_PRE_MULTIPLIED_ALPHA:
865 					case CURSOR_MODE_COLOR_UN_PRE_MULTIPLIED_ALPHA:
866 						cmd.mall.cursor_bpp = 32;
867 						break;
868 
869 					case CURSOR_MODE_COLOR_64BIT_FP_PRE_MULTIPLIED:
870 					case CURSOR_MODE_COLOR_64BIT_FP_UN_PRE_MULTIPLIED:
871 						cmd.mall.cursor_bpp = 64;
872 						break;
873 					}
874 
875 					cmd.mall.cursor_copy_src.quad_part = cursor_attr.address.quad_part;
876 					cmd.mall.cursor_copy_dst.quad_part =
877 							(plane->address.grph.cursor_cache_addr.quad_part + 2047) & ~2047;
878 					cmd.mall.cursor_width = cursor_attr.width;
879 					cmd.mall.cursor_height = cursor_attr.height;
880 					cmd.mall.cursor_pitch = cursor_attr.pitch;
881 
882 					dc_wake_and_execute_dmub_cmd(dc->ctx, &cmd, DM_DMUB_WAIT_TYPE_WAIT);
883 
884 					/* Use copied cursor, and it's okay to not switch back */
885 					cursor_attr.address.quad_part = cmd.mall.cursor_copy_dst.quad_part;
886 					dc_stream_set_cursor_attributes(stream, &cursor_attr);
887 				}
888 
889 				/* Enable MALL */
890 				memset(&cmd, 0, sizeof(cmd));
891 				cmd.mall.header.type = DMUB_CMD__MALL;
892 				cmd.mall.header.sub_type = DMUB_CMD__MALL_ACTION_ALLOW;
893 				cmd.mall.header.payload_bytes = sizeof(cmd.mall) - sizeof(cmd.mall.header);
894 				cmd.mall.tmr_delay = tmr_delay;
895 				cmd.mall.tmr_scale = tmr_scale;
896 				cmd.mall.debug_bits = dc->debug.mall_error_as_fatal;
897 
898 				dc_wake_and_execute_dmub_cmd(dc->ctx, &cmd, DM_DMUB_WAIT_TYPE_NO_WAIT);
899 
900 				return true;
901 			}
902 		}
903 
904 		/* No applicable optimizations */
905 		return false;
906 	}
907 
908 	/* Disable MALL */
909 	memset(&cmd, 0, sizeof(cmd));
910 	cmd.mall.header.type = DMUB_CMD__MALL;
911 	cmd.mall.header.sub_type = DMUB_CMD__MALL_ACTION_DISALLOW;
912 	cmd.mall.header.payload_bytes =
913 		sizeof(cmd.mall) - sizeof(cmd.mall.header);
914 
915 	dc_wake_and_execute_dmub_cmd(dc->ctx, &cmd, DM_DMUB_WAIT_TYPE_WAIT);
916 
917 	return true;
918 }
919 
dcn30_does_plane_fit_in_mall(struct dc * dc,struct dc_plane_state * plane,struct dc_cursor_attributes * cursor_attr)920 bool dcn30_does_plane_fit_in_mall(struct dc *dc, struct dc_plane_state *plane, struct dc_cursor_attributes *cursor_attr)
921 {
922 	// add meta size?
923 	unsigned int surface_size = plane->plane_size.surface_pitch * plane->plane_size.surface_size.height *
924 			(plane->format >= SURFACE_PIXEL_FORMAT_GRPH_ARGB16161616 ? 8 : 4);
925 	unsigned int mall_size = dc->caps.mall_size_total;
926 	unsigned int cursor_size = 0;
927 
928 	if (dc->debug.mall_size_override)
929 		mall_size = 1024 * 1024 * dc->debug.mall_size_override;
930 
931 	if (cursor_attr) {
932 		cursor_size = dc->caps.max_cursor_size * dc->caps.max_cursor_size;
933 
934 		switch (cursor_attr->color_format) {
935 		case CURSOR_MODE_MONO:
936 			cursor_size /= 2;
937 			break;
938 		case CURSOR_MODE_COLOR_1BIT_AND:
939 		case CURSOR_MODE_COLOR_PRE_MULTIPLIED_ALPHA:
940 		case CURSOR_MODE_COLOR_UN_PRE_MULTIPLIED_ALPHA:
941 			cursor_size *= 4;
942 			break;
943 
944 		case CURSOR_MODE_COLOR_64BIT_FP_PRE_MULTIPLIED:
945 		case CURSOR_MODE_COLOR_64BIT_FP_UN_PRE_MULTIPLIED:
946 			cursor_size *= 8;
947 			break;
948 		}
949 	}
950 
951 	return (surface_size + cursor_size) < mall_size;
952 }
953 
dcn30_hardware_release(struct dc * dc)954 void dcn30_hardware_release(struct dc *dc)
955 {
956 	bool subvp_in_use = false;
957 	uint32_t i;
958 
959 	dc_dmub_srv_p_state_delegate(dc, false, NULL);
960 	dc_dmub_setup_subvp_dmub_command(dc, dc->current_state, false);
961 
962 	/* SubVP treated the same way as FPO. If driver disable and
963 	 * we are using a SubVP config, disable and force on DCN side
964 	 * to prevent P-State hang on driver enable.
965 	 */
966 	for (i = 0; i < dc->res_pool->pipe_count; i++) {
967 		struct pipe_ctx *pipe = &dc->current_state->res_ctx.pipe_ctx[i];
968 
969 		if (!pipe->stream)
970 			continue;
971 
972 		if (dc_state_get_pipe_subvp_type(dc->current_state, pipe) == SUBVP_MAIN) {
973 			subvp_in_use = true;
974 			break;
975 		}
976 	}
977 	/* If pstate unsupported, or still supported
978 	 * by firmware, force it supported by dcn
979 	 */
980 	if (dc->current_state)
981 		if ((!dc->clk_mgr->clks.p_state_change_support || subvp_in_use ||
982 				dc->current_state->bw_ctx.bw.dcn.clk.fw_based_mclk_switching) &&
983 				dc->res_pool->hubbub->funcs->force_pstate_change_control)
984 			dc->res_pool->hubbub->funcs->force_pstate_change_control(
985 					dc->res_pool->hubbub, true, true);
986 }
987 
dcn30_set_disp_pattern_generator(const struct dc * dc,struct pipe_ctx * pipe_ctx,enum controller_dp_test_pattern test_pattern,enum controller_dp_color_space color_space,enum dc_color_depth color_depth,const struct tg_color * solid_color,int width,int height,int offset)988 void dcn30_set_disp_pattern_generator(const struct dc *dc,
989 		struct pipe_ctx *pipe_ctx,
990 		enum controller_dp_test_pattern test_pattern,
991 		enum controller_dp_color_space color_space,
992 		enum dc_color_depth color_depth,
993 		const struct tg_color *solid_color,
994 		int width, int height, int offset)
995 {
996 	pipe_ctx->stream_res.opp->funcs->opp_set_disp_pattern_generator(pipe_ctx->stream_res.opp, test_pattern,
997 			color_space, color_depth, solid_color, width, height, offset);
998 }
999 
dcn30_prepare_bandwidth(struct dc * dc,struct dc_state * context)1000 void dcn30_prepare_bandwidth(struct dc *dc,
1001 	struct dc_state *context)
1002 {
1003 	if (context->bw_ctx.bw.dcn.clk.fw_based_mclk_switching && !dc->clk_mgr->clks.fw_based_mclk_switching) {
1004 		dc->optimized_required = true;
1005 		context->bw_ctx.bw.dcn.clk.p_state_change_support = false;
1006 	}
1007 
1008 	if (dc->clk_mgr->dc_mode_softmax_enabled)
1009 		if (dc->clk_mgr->clks.dramclk_khz <= dc->clk_mgr->bw_params->dc_mode_softmax_memclk * 1000 &&
1010 				context->bw_ctx.bw.dcn.clk.dramclk_khz > dc->clk_mgr->bw_params->dc_mode_softmax_memclk * 1000)
1011 			dc->clk_mgr->funcs->set_max_memclk(dc->clk_mgr, dc->clk_mgr->bw_params->clk_table.entries[dc->clk_mgr->bw_params->clk_table.num_entries - 1].memclk_mhz);
1012 
1013 	dcn20_prepare_bandwidth(dc, context);
1014 
1015 	if (!dc->clk_mgr->clks.fw_based_mclk_switching)
1016 		dc_dmub_srv_p_state_delegate(dc, false, context);
1017 }
1018 
dcn30_set_static_screen_control(struct pipe_ctx ** pipe_ctx,int num_pipes,const struct dc_static_screen_params * params)1019 void dcn30_set_static_screen_control(struct pipe_ctx **pipe_ctx,
1020 		int num_pipes, const struct dc_static_screen_params *params)
1021 {
1022 	unsigned int i;
1023 	unsigned int triggers = 0;
1024 
1025 	if (params->triggers.surface_update)
1026 		triggers |= 0x100;
1027 	if (params->triggers.cursor_update)
1028 		triggers |= 0x8;
1029 	if (params->triggers.force_trigger)
1030 		triggers |= 0x1;
1031 
1032 	for (i = 0; i < num_pipes; i++)
1033 		pipe_ctx[i]->stream_res.tg->funcs->set_static_screen_control(pipe_ctx[i]->stream_res.tg,
1034 					triggers, params->num_frames);
1035 }
1036