1 /*
2 * Copyright 2020 Advanced Micro Devices, Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
21 *
22 * Authors: AMD
23 *
24 */
25
26 #include "dcn302/dcn302_init.h"
27 #include "dcn302_resource.h"
28 #include "dcn302/dcn302_dccg.h"
29 #include "irq/dcn302/irq_service_dcn302.h"
30
31 #include "dcn30/dcn30_dio_link_encoder.h"
32 #include "dcn30/dcn30_dio_stream_encoder.h"
33 #include "dcn30/dcn30_dwb.h"
34 #include "dcn30/dcn30_dpp.h"
35 #include "dcn30/dcn30_hubbub.h"
36 #include "dcn30/dcn30_hubp.h"
37 #include "dcn30/dcn30_mmhubbub.h"
38 #include "dcn30/dcn30_mpc.h"
39 #include "dcn30/dcn30_opp.h"
40 #include "dcn30/dcn30_optc.h"
41 #include "dcn30/dcn30_resource.h"
42
43 #include "dcn20/dcn20_dsc.h"
44 #include "dcn20/dcn20_resource.h"
45
46 #include "dml/dcn30/dcn30_fpu.h"
47
48 #include "dcn10/dcn10_resource.h"
49 #include "dio/dcn10/dcn10_dio.h"
50
51 #include "link_service.h"
52
53 #include "dce/dce_abm.h"
54 #include "dce/dce_audio.h"
55 #include "dce/dce_aux.h"
56 #include "dce/dce_clock_source.h"
57 #include "dce/dce_hwseq.h"
58 #include "dce/dce_i2c_hw.h"
59 #include "dce/dce_panel_cntl.h"
60 #include "dce/dmub_abm.h"
61 #include "dce/dmub_psr.h"
62 #include "clk_mgr.h"
63
64 #include "hw_sequencer_private.h"
65 #include "reg_helper.h"
66 #include "resource.h"
67 #include "vm_helper.h"
68
69 #include "dml/dcn302/dcn302_fpu.h"
70
71 #include "dimgrey_cavefish_ip_offset.h"
72 #include "dcn/dcn_3_0_2_offset.h"
73 #include "dcn/dcn_3_0_2_sh_mask.h"
74 #include "dpcs/dpcs_3_0_0_offset.h"
75 #include "dpcs/dpcs_3_0_0_sh_mask.h"
76 #include "nbio/nbio_7_4_offset.h"
77 #include "amdgpu_socbb.h"
78
79 #define DC_LOGGER \
80 dc->ctx->logger
81 #define DC_LOGGER_INIT(logger)
82
83 static const struct dc_debug_options debug_defaults_drv = {
84 .disable_dmcu = true,
85 .force_abm_enable = false,
86 .clock_trace = true,
87 .disable_pplib_clock_request = true,
88 .pipe_split_policy = MPC_SPLIT_DYNAMIC,
89 .force_single_disp_pipe_split = false,
90 .disable_dcc = DCC_ENABLE,
91 .vsr_support = true,
92 .performance_trace = false,
93 .max_downscale_src_width = 7680,/*upto 8K*/
94 .disable_pplib_wm_range = false,
95 .scl_reset_length10 = true,
96 .sanity_checks = false,
97 .underflow_assert_delay_us = 0xFFFFFFFF,
98 .dwb_fi_phase = -1, // -1 = disable,
99 .dmub_command_table = true,
100 .use_max_lb = true,
101 .exit_idle_opt_for_cursor_updates = true,
102 .using_dml2 = false,
103 };
104
105 static const struct dc_check_config config_defaults = {
106 .enable_legacy_fast_update = false,
107 };
108
109 static const struct dc_panel_config panel_config_defaults = {
110 .psr = {
111 .disable_psr = false,
112 .disallow_psrsu = false,
113 .disallow_replay = false,
114 },
115 };
116
117 enum dcn302_clk_src_array_id {
118 DCN302_CLK_SRC_PLL0,
119 DCN302_CLK_SRC_PLL1,
120 DCN302_CLK_SRC_PLL2,
121 DCN302_CLK_SRC_PLL3,
122 DCN302_CLK_SRC_PLL4,
123 DCN302_CLK_SRC_TOTAL
124 };
125
126 static const struct resource_caps res_cap_dcn302 = {
127 .num_timing_generator = 5,
128 .num_opp = 5,
129 .num_video_plane = 5,
130 .num_audio = 5,
131 .num_stream_encoder = 5,
132 .num_dwb = 1,
133 .num_ddc = 5,
134 .num_vmid = 16,
135 .num_mpc_3dlut = 2,
136 .num_dsc = 5,
137 };
138
139 static const struct dc_plane_cap plane_cap = {
140 .type = DC_PLANE_TYPE_DCN_UNIVERSAL,
141 .per_pixel_alpha = true,
142 .pixel_format_support = {
143 .argb8888 = true,
144 .nv12 = true,
145 .fp16 = true,
146 .p010 = true,
147 .ayuv = false,
148 },
149 .max_upscale_factor = {
150 .argb8888 = 16000,
151 .nv12 = 16000,
152 .fp16 = 16000
153 },
154 /* 6:1 downscaling ratio: 1000/6 = 166.666 */
155 .max_downscale_factor = {
156 .argb8888 = 167,
157 .nv12 = 167,
158 .fp16 = 167
159 },
160 16,
161 16
162 };
163
164 /* NBIO */
165 #define NBIO_BASE_INNER(seg) \
166 NBIO_BASE__INST0_SEG ## seg
167
168 #define NBIO_BASE(seg) \
169 NBIO_BASE_INNER(seg)
170
171 #define NBIO_SR(reg_name)\
172 .reg_name = NBIO_BASE(mm ## reg_name ## _BASE_IDX) + \
173 mm ## reg_name
174
175 /* DCN */
176 #define BASE_INNER(seg) DCN_BASE__INST0_SEG ## seg
177
178 #define BASE(seg) BASE_INNER(seg)
179
180 #define SR(reg_name)\
181 .reg_name = BASE(mm ## reg_name ## _BASE_IDX) + mm ## reg_name
182
183 #define SF(reg_name, field_name, post_fix)\
184 .field_name = reg_name ## __ ## field_name ## post_fix
185
186 #define SRI(reg_name, block, id)\
187 .reg_name = BASE(mm ## block ## id ## _ ## reg_name ## _BASE_IDX) + mm ## block ## id ## _ ## reg_name
188
189 #define SRI2(reg_name, block, id)\
190 .reg_name = BASE(mm ## reg_name ## _BASE_IDX) + mm ## reg_name
191
192 #define SRII(reg_name, block, id)\
193 .reg_name[id] = BASE(mm ## block ## id ## _ ## reg_name ## _BASE_IDX) + \
194 mm ## block ## id ## _ ## reg_name
195
196 #define DCCG_SRII(reg_name, block, id)\
197 .block ## _ ## reg_name[id] = BASE(mm ## block ## id ## _ ## reg_name ## _BASE_IDX) + \
198 mm ## block ## id ## _ ## reg_name
199
200 #define VUPDATE_SRII(reg_name, block, id)\
201 .reg_name[id] = BASE(mm ## reg_name ## _ ## block ## id ## _BASE_IDX) + \
202 mm ## reg_name ## _ ## block ## id
203
204 #define SRII_DWB(reg_name, temp_name, block, id)\
205 .reg_name[id] = BASE(mm ## block ## id ## _ ## temp_name ## _BASE_IDX) + \
206 mm ## block ## id ## _ ## temp_name
207
208 #define SF_DWB2(reg_name, block, id, field_name, post_fix) \
209 .field_name = reg_name ## __ ## field_name ## post_fix
210
211 #define SRII_MPC_RMU(reg_name, block, id)\
212 .RMU##_##reg_name[id] = BASE(mm ## block ## id ## _ ## reg_name ## _BASE_IDX) + \
213 mm ## block ## id ## _ ## reg_name
214
215 static const struct dcn_hubbub_registers hubbub_reg = {
216 HUBBUB_REG_LIST_DCN30(0)
217 };
218
219 static const struct dcn_hubbub_shift hubbub_shift = {
220 HUBBUB_MASK_SH_LIST_DCN30(__SHIFT)
221 };
222
223 static const struct dcn_hubbub_mask hubbub_mask = {
224 HUBBUB_MASK_SH_LIST_DCN30(_MASK)
225 };
226
227 #define vmid_regs(id)\
228 [id] = { DCN20_VMID_REG_LIST(id) }
229
230 static const struct dcn_vmid_registers vmid_regs[] = {
231 vmid_regs(0),
232 vmid_regs(1),
233 vmid_regs(2),
234 vmid_regs(3),
235 vmid_regs(4),
236 vmid_regs(5),
237 vmid_regs(6),
238 vmid_regs(7),
239 vmid_regs(8),
240 vmid_regs(9),
241 vmid_regs(10),
242 vmid_regs(11),
243 vmid_regs(12),
244 vmid_regs(13),
245 vmid_regs(14),
246 vmid_regs(15)
247 };
248
249 static const struct dcn20_vmid_shift vmid_shifts = {
250 DCN20_VMID_MASK_SH_LIST(__SHIFT)
251 };
252
253 static const struct dcn20_vmid_mask vmid_masks = {
254 DCN20_VMID_MASK_SH_LIST(_MASK)
255 };
256
257 static const struct dcn_dio_registers dio_regs = {
258 DIO_REG_LIST_DCN10()
259 };
260
261 #define DIO_MASK_SH_LIST(mask_sh)\
262 HWS_SF(, DIO_MEM_PWR_CTRL, I2C_LIGHT_SLEEP_FORCE, mask_sh)
263
264 static const struct dcn_dio_shift dio_shift = {
265 DIO_MASK_SH_LIST(__SHIFT)
266 };
267
268 static const struct dcn_dio_mask dio_mask = {
269 DIO_MASK_SH_LIST(_MASK)
270 };
271
dcn302_dio_create(struct dc_context * ctx)272 static struct dio *dcn302_dio_create(struct dc_context *ctx)
273 {
274 struct dcn10_dio *dio10 = kzalloc_obj(struct dcn10_dio);
275
276 if (!dio10)
277 return NULL;
278
279 dcn10_dio_construct(dio10, ctx, &dio_regs, &dio_shift, &dio_mask);
280
281 return &dio10->base;
282 }
283
dcn302_hubbub_create(struct dc_context * ctx)284 static struct hubbub *dcn302_hubbub_create(struct dc_context *ctx)
285 {
286 int i;
287
288 struct dcn20_hubbub *hubbub3 = kzalloc_obj(struct dcn20_hubbub);
289
290 if (!hubbub3)
291 return NULL;
292
293 hubbub3_construct(hubbub3, ctx, &hubbub_reg, &hubbub_shift, &hubbub_mask);
294
295 for (i = 0; i < res_cap_dcn302.num_vmid; i++) {
296 struct dcn20_vmid *vmid = &hubbub3->vmid[i];
297
298 vmid->ctx = ctx;
299
300 vmid->regs = &vmid_regs[i];
301 vmid->shifts = &vmid_shifts;
302 vmid->masks = &vmid_masks;
303 }
304
305 return &hubbub3->base;
306 }
307
308 #define vpg_regs(id)\
309 [id] = { VPG_DCN3_REG_LIST(id) }
310
311 static const struct dcn30_vpg_registers vpg_regs[] = {
312 vpg_regs(0),
313 vpg_regs(1),
314 vpg_regs(2),
315 vpg_regs(3),
316 vpg_regs(4),
317 vpg_regs(5)
318 };
319
320 static const struct dcn30_vpg_shift vpg_shift = {
321 DCN3_VPG_MASK_SH_LIST(__SHIFT)
322 };
323
324 static const struct dcn30_vpg_mask vpg_mask = {
325 DCN3_VPG_MASK_SH_LIST(_MASK)
326 };
327
dcn302_vpg_create(struct dc_context * ctx,uint32_t inst)328 static struct vpg *dcn302_vpg_create(struct dc_context *ctx, uint32_t inst)
329 {
330 struct dcn30_vpg *vpg3 = kzalloc_obj(struct dcn30_vpg);
331
332 if (!vpg3)
333 return NULL;
334
335 vpg3_construct(vpg3, ctx, inst, &vpg_regs[inst], &vpg_shift, &vpg_mask);
336
337 return &vpg3->base;
338 }
339
340 #define afmt_regs(id)\
341 [id] = { AFMT_DCN3_REG_LIST(id) }
342
343 static const struct dcn30_afmt_registers afmt_regs[] = {
344 afmt_regs(0),
345 afmt_regs(1),
346 afmt_regs(2),
347 afmt_regs(3),
348 afmt_regs(4),
349 afmt_regs(5)
350 };
351
352 static const struct dcn30_afmt_shift afmt_shift = {
353 DCN3_AFMT_MASK_SH_LIST(__SHIFT)
354 };
355
356 static const struct dcn30_afmt_mask afmt_mask = {
357 DCN3_AFMT_MASK_SH_LIST(_MASK)
358 };
359
dcn302_afmt_create(struct dc_context * ctx,uint32_t inst)360 static struct afmt *dcn302_afmt_create(struct dc_context *ctx, uint32_t inst)
361 {
362 struct dcn30_afmt *afmt3 = kzalloc_obj(struct dcn30_afmt);
363
364 if (!afmt3)
365 return NULL;
366
367 afmt3_construct(afmt3, ctx, inst, &afmt_regs[inst], &afmt_shift, &afmt_mask);
368
369 return &afmt3->base;
370 }
371
372 #define audio_regs(id)\
373 [id] = { AUD_COMMON_REG_LIST(id) }
374
375 static const struct dce_audio_registers audio_regs[] = {
376 audio_regs(0),
377 audio_regs(1),
378 audio_regs(2),
379 audio_regs(3),
380 audio_regs(4),
381 audio_regs(5),
382 audio_regs(6)
383 };
384
385 #define DCE120_AUD_COMMON_MASK_SH_LIST(mask_sh)\
386 SF(AZF0ENDPOINT0_AZALIA_F0_CODEC_ENDPOINT_INDEX, AZALIA_ENDPOINT_REG_INDEX, mask_sh),\
387 SF(AZF0ENDPOINT0_AZALIA_F0_CODEC_ENDPOINT_DATA, AZALIA_ENDPOINT_REG_DATA, mask_sh),\
388 AUD_COMMON_MASK_SH_LIST_BASE(mask_sh)
389
390 static const struct dce_audio_shift audio_shift = {
391 DCE120_AUD_COMMON_MASK_SH_LIST(__SHIFT)
392 };
393
394 static const struct dce_audio_mask audio_mask = {
395 DCE120_AUD_COMMON_MASK_SH_LIST(_MASK)
396 };
397
dcn302_create_audio(struct dc_context * ctx,unsigned int inst)398 static struct audio *dcn302_create_audio(struct dc_context *ctx, unsigned int inst)
399 {
400 return dce_audio_create(ctx, inst, &audio_regs[inst], &audio_shift, &audio_mask);
401 }
402
403 #define stream_enc_regs(id)\
404 [id] = { SE_DCN3_REG_LIST(id) }
405
406 static const struct dcn10_stream_enc_registers stream_enc_regs[] = {
407 stream_enc_regs(0),
408 stream_enc_regs(1),
409 stream_enc_regs(2),
410 stream_enc_regs(3),
411 stream_enc_regs(4)
412 };
413
414 static const struct dcn10_stream_encoder_shift se_shift = {
415 SE_COMMON_MASK_SH_LIST_DCN30(__SHIFT)
416 };
417
418 static const struct dcn10_stream_encoder_mask se_mask = {
419 SE_COMMON_MASK_SH_LIST_DCN30(_MASK)
420 };
421
dcn302_stream_encoder_create(enum engine_id eng_id,struct dc_context * ctx)422 static struct stream_encoder *dcn302_stream_encoder_create(enum engine_id eng_id, struct dc_context *ctx)
423 {
424 struct dcn10_stream_encoder *enc1;
425 struct vpg *vpg;
426 struct afmt *afmt;
427 int vpg_inst;
428 int afmt_inst;
429
430 /* Mapping of VPG, AFMT, DME register blocks to DIO block instance */
431 if (eng_id <= ENGINE_ID_DIGE) {
432 vpg_inst = eng_id;
433 afmt_inst = eng_id;
434 } else
435 return NULL;
436
437 enc1 = kzalloc_obj(struct dcn10_stream_encoder);
438 vpg = dcn302_vpg_create(ctx, vpg_inst);
439 afmt = dcn302_afmt_create(ctx, afmt_inst);
440
441 if (!enc1 || !vpg || !afmt) {
442 kfree(enc1);
443 kfree(vpg);
444 kfree(afmt);
445 return NULL;
446 }
447
448 dcn30_dio_stream_encoder_construct(enc1, ctx, ctx->dc_bios, eng_id, vpg, afmt, &stream_enc_regs[eng_id],
449 &se_shift, &se_mask);
450
451 return &enc1->base;
452 }
453
454 #define clk_src_regs(index, pllid)\
455 [index] = { CS_COMMON_REG_LIST_DCN3_02(index, pllid) }
456
457 static const struct dce110_clk_src_regs clk_src_regs[] = {
458 clk_src_regs(0, A),
459 clk_src_regs(1, B),
460 clk_src_regs(2, C),
461 clk_src_regs(3, D),
462 clk_src_regs(4, E)
463 };
464
465 static const struct dce110_clk_src_shift cs_shift = {
466 CS_COMMON_MASK_SH_LIST_DCN2_0(__SHIFT)
467 };
468
469 static const struct dce110_clk_src_mask cs_mask = {
470 CS_COMMON_MASK_SH_LIST_DCN2_0(_MASK)
471 };
472
dcn302_clock_source_create(struct dc_context * ctx,struct dc_bios * bios,enum clock_source_id id,const struct dce110_clk_src_regs * regs,bool dp_clk_src)473 static struct clock_source *dcn302_clock_source_create(struct dc_context *ctx, struct dc_bios *bios,
474 enum clock_source_id id, const struct dce110_clk_src_regs *regs, bool dp_clk_src)
475 {
476 struct dce110_clk_src *clk_src = kzalloc_obj(struct dce110_clk_src);
477
478 if (!clk_src)
479 return NULL;
480
481 if (dcn3_clk_src_construct(clk_src, ctx, bios, id, regs, &cs_shift, &cs_mask)) {
482 clk_src->base.dp_clk_src = dp_clk_src;
483 return &clk_src->base;
484 }
485
486 kfree(clk_src);
487 BREAK_TO_DEBUGGER();
488 return NULL;
489 }
490
491 static const struct dce_hwseq_registers hwseq_reg = {
492 HWSEQ_DCN302_REG_LIST()
493 };
494
495 static const struct dce_hwseq_shift hwseq_shift = {
496 HWSEQ_DCN302_MASK_SH_LIST(__SHIFT)
497 };
498
499 static const struct dce_hwseq_mask hwseq_mask = {
500 HWSEQ_DCN302_MASK_SH_LIST(_MASK)
501 };
502
dcn302_hwseq_create(struct dc_context * ctx)503 static struct dce_hwseq *dcn302_hwseq_create(struct dc_context *ctx)
504 {
505 struct dce_hwseq *hws = kzalloc_obj(struct dce_hwseq);
506
507 if (hws) {
508 hws->ctx = ctx;
509 hws->regs = &hwseq_reg;
510 hws->shifts = &hwseq_shift;
511 hws->masks = &hwseq_mask;
512 }
513 return hws;
514 }
515
516 #define hubp_regs(id)\
517 [id] = { HUBP_REG_LIST_DCN30(id) }
518
519 static const struct dcn_hubp2_registers hubp_regs[] = {
520 hubp_regs(0),
521 hubp_regs(1),
522 hubp_regs(2),
523 hubp_regs(3),
524 hubp_regs(4)
525 };
526
527 static const struct dcn_hubp2_shift hubp_shift = {
528 HUBP_MASK_SH_LIST_DCN30(__SHIFT)
529 };
530
531 static const struct dcn_hubp2_mask hubp_mask = {
532 HUBP_MASK_SH_LIST_DCN30(_MASK)
533 };
534
dcn302_hubp_create(struct dc_context * ctx,uint32_t inst)535 static struct hubp *dcn302_hubp_create(struct dc_context *ctx, uint32_t inst)
536 {
537 struct dcn20_hubp *hubp2 = kzalloc_obj(struct dcn20_hubp);
538
539 if (!hubp2)
540 return NULL;
541
542 if (hubp3_construct(hubp2, ctx, inst, &hubp_regs[inst], &hubp_shift, &hubp_mask))
543 return &hubp2->base;
544
545 BREAK_TO_DEBUGGER();
546 kfree(hubp2);
547 return NULL;
548 }
549
550 #define dpp_regs(id)\
551 [id] = { DPP_REG_LIST_DCN30(id) }
552
553 static const struct dcn3_dpp_registers dpp_regs[] = {
554 dpp_regs(0),
555 dpp_regs(1),
556 dpp_regs(2),
557 dpp_regs(3),
558 dpp_regs(4)
559 };
560
561 static const struct dcn3_dpp_shift tf_shift = {
562 DPP_REG_LIST_SH_MASK_DCN30(__SHIFT)
563 };
564
565 static const struct dcn3_dpp_mask tf_mask = {
566 DPP_REG_LIST_SH_MASK_DCN30(_MASK)
567 };
568
dcn302_dpp_create(struct dc_context * ctx,uint32_t inst)569 static struct dpp *dcn302_dpp_create(struct dc_context *ctx, uint32_t inst)
570 {
571 struct dcn3_dpp *dpp = kzalloc_obj(struct dcn3_dpp);
572
573 if (!dpp)
574 return NULL;
575
576 if (dpp3_construct(dpp, ctx, inst, &dpp_regs[inst], &tf_shift, &tf_mask))
577 return &dpp->base;
578
579 BREAK_TO_DEBUGGER();
580 kfree(dpp);
581 return NULL;
582 }
583
584 #define opp_regs(id)\
585 [id] = { OPP_REG_LIST_DCN30(id) }
586
587 static const struct dcn20_opp_registers opp_regs[] = {
588 opp_regs(0),
589 opp_regs(1),
590 opp_regs(2),
591 opp_regs(3),
592 opp_regs(4)
593 };
594
595 static const struct dcn20_opp_shift opp_shift = {
596 OPP_MASK_SH_LIST_DCN20(__SHIFT)
597 };
598
599 static const struct dcn20_opp_mask opp_mask = {
600 OPP_MASK_SH_LIST_DCN20(_MASK)
601 };
602
dcn302_opp_create(struct dc_context * ctx,uint32_t inst)603 static struct output_pixel_processor *dcn302_opp_create(struct dc_context *ctx, uint32_t inst)
604 {
605 struct dcn20_opp *opp = kzalloc_obj(struct dcn20_opp);
606
607 if (!opp) {
608 BREAK_TO_DEBUGGER();
609 return NULL;
610 }
611
612 dcn20_opp_construct(opp, ctx, inst, &opp_regs[inst], &opp_shift, &opp_mask);
613 return &opp->base;
614 }
615
616 #define optc_regs(id)\
617 [id] = { OPTC_COMMON_REG_LIST_DCN3_0(id) }
618
619 static const struct dcn_optc_registers optc_regs[] = {
620 optc_regs(0),
621 optc_regs(1),
622 optc_regs(2),
623 optc_regs(3),
624 optc_regs(4)
625 };
626
627 static const struct dcn_optc_shift optc_shift = {
628 OPTC_COMMON_MASK_SH_LIST_DCN30(__SHIFT)
629 };
630
631 static const struct dcn_optc_mask optc_mask = {
632 OPTC_COMMON_MASK_SH_LIST_DCN30(_MASK)
633 };
634
dcn302_timing_generator_create(struct dc_context * ctx,uint32_t instance)635 static struct timing_generator *dcn302_timing_generator_create(struct dc_context *ctx, uint32_t instance)
636 {
637 struct optc *tgn10 = kzalloc_obj(struct optc);
638
639 if (!tgn10)
640 return NULL;
641
642 tgn10->base.inst = instance;
643 tgn10->base.ctx = ctx;
644
645 tgn10->tg_regs = &optc_regs[instance];
646 tgn10->tg_shift = &optc_shift;
647 tgn10->tg_mask = &optc_mask;
648
649 dcn30_timing_generator_init(tgn10);
650
651 return &tgn10->base;
652 }
653
654 static const struct dcn30_mpc_registers mpc_regs = {
655 MPC_REG_LIST_DCN3_0(0),
656 MPC_REG_LIST_DCN3_0(1),
657 MPC_REG_LIST_DCN3_0(2),
658 MPC_REG_LIST_DCN3_0(3),
659 MPC_REG_LIST_DCN3_0(4),
660 MPC_OUT_MUX_REG_LIST_DCN3_0(0),
661 MPC_OUT_MUX_REG_LIST_DCN3_0(1),
662 MPC_OUT_MUX_REG_LIST_DCN3_0(2),
663 MPC_OUT_MUX_REG_LIST_DCN3_0(3),
664 MPC_OUT_MUX_REG_LIST_DCN3_0(4),
665 MPC_RMU_GLOBAL_REG_LIST_DCN3AG,
666 MPC_RMU_REG_LIST_DCN3AG(0),
667 MPC_RMU_REG_LIST_DCN3AG(1),
668 MPC_RMU_REG_LIST_DCN3AG(2),
669 MPC_DWB_MUX_REG_LIST_DCN3_0(0),
670 };
671
672 static const struct dcn30_mpc_shift mpc_shift = {
673 MPC_COMMON_MASK_SH_LIST_DCN30(__SHIFT)
674 };
675
676 static const struct dcn30_mpc_mask mpc_mask = {
677 MPC_COMMON_MASK_SH_LIST_DCN30(_MASK)
678 };
679
dcn302_mpc_create(struct dc_context * ctx,int num_mpcc,int num_rmu)680 static struct mpc *dcn302_mpc_create(struct dc_context *ctx, int num_mpcc, int num_rmu)
681 {
682 struct dcn30_mpc *mpc30 = kzalloc_obj(struct dcn30_mpc);
683
684 if (!mpc30)
685 return NULL;
686
687 dcn30_mpc_construct(mpc30, ctx, &mpc_regs, &mpc_shift, &mpc_mask, num_mpcc, num_rmu);
688
689 return &mpc30->base;
690 }
691
692 #define dsc_regsDCN20(id)\
693 [id] = { DSC_REG_LIST_DCN20(id) }
694
695 static const struct dcn20_dsc_registers dsc_regs[] = {
696 dsc_regsDCN20(0),
697 dsc_regsDCN20(1),
698 dsc_regsDCN20(2),
699 dsc_regsDCN20(3),
700 dsc_regsDCN20(4)
701 };
702
703 static const struct dcn20_dsc_shift dsc_shift = {
704 DSC_REG_LIST_SH_MASK_DCN20(__SHIFT)
705 };
706
707 static const struct dcn20_dsc_mask dsc_mask = {
708 DSC_REG_LIST_SH_MASK_DCN20(_MASK)
709 };
710
dcn302_dsc_create(struct dc_context * ctx,uint32_t inst)711 static struct display_stream_compressor *dcn302_dsc_create(struct dc_context *ctx, uint32_t inst)
712 {
713 struct dcn20_dsc *dsc = kzalloc_obj(struct dcn20_dsc);
714
715 if (!dsc) {
716 BREAK_TO_DEBUGGER();
717 return NULL;
718 }
719
720 dsc2_construct(dsc, ctx, inst, &dsc_regs[inst], &dsc_shift, &dsc_mask);
721 return &dsc->base;
722 }
723
724 #define dwbc_regs_dcn3(id)\
725 [id] = { DWBC_COMMON_REG_LIST_DCN30(id) }
726
727 static const struct dcn30_dwbc_registers dwbc30_regs[] = {
728 dwbc_regs_dcn3(0)
729 };
730
731 static const struct dcn30_dwbc_shift dwbc30_shift = {
732 DWBC_COMMON_MASK_SH_LIST_DCN30(__SHIFT)
733 };
734
735 static const struct dcn30_dwbc_mask dwbc30_mask = {
736 DWBC_COMMON_MASK_SH_LIST_DCN30(_MASK)
737 };
738
dcn302_dwbc_create(struct dc_context * ctx,struct resource_pool * pool)739 static bool dcn302_dwbc_create(struct dc_context *ctx, struct resource_pool *pool)
740 {
741 int i;
742 uint32_t pipe_count = pool->res_cap->num_dwb;
743
744 for (i = 0; i < pipe_count; i++) {
745 struct dcn30_dwbc *dwbc30 = kzalloc_obj(struct dcn30_dwbc);
746
747 if (!dwbc30) {
748 dm_error("DC: failed to create dwbc30!\n");
749 return false;
750 }
751
752 dcn30_dwbc_construct(dwbc30, ctx, &dwbc30_regs[i], &dwbc30_shift, &dwbc30_mask, i);
753
754 pool->dwbc[i] = &dwbc30->base;
755 }
756 return true;
757 }
758
759 #define mcif_wb_regs_dcn3(id)\
760 [id] = { MCIF_WB_COMMON_REG_LIST_DCN30(id) }
761
762 static const struct dcn30_mmhubbub_registers mcif_wb30_regs[] = {
763 mcif_wb_regs_dcn3(0)
764 };
765
766 static const struct dcn30_mmhubbub_shift mcif_wb30_shift = {
767 MCIF_WB_COMMON_MASK_SH_LIST_DCN30(__SHIFT)
768 };
769
770 static const struct dcn30_mmhubbub_mask mcif_wb30_mask = {
771 MCIF_WB_COMMON_MASK_SH_LIST_DCN30(_MASK)
772 };
773
dcn302_mmhubbub_create(struct dc_context * ctx,struct resource_pool * pool)774 static bool dcn302_mmhubbub_create(struct dc_context *ctx, struct resource_pool *pool)
775 {
776 int i;
777 uint32_t pipe_count = pool->res_cap->num_dwb;
778
779 for (i = 0; i < pipe_count; i++) {
780 struct dcn30_mmhubbub *mcif_wb30 = kzalloc_obj(struct dcn30_mmhubbub);
781
782 if (!mcif_wb30) {
783 dm_error("DC: failed to create mcif_wb30!\n");
784 return false;
785 }
786
787 dcn30_mmhubbub_construct(mcif_wb30, ctx, &mcif_wb30_regs[i], &mcif_wb30_shift, &mcif_wb30_mask, i);
788
789 pool->mcif_wb[i] = &mcif_wb30->base;
790 }
791 return true;
792 }
793
794 #define aux_engine_regs(id)\
795 [id] = {\
796 AUX_COMMON_REG_LIST0(id), \
797 .AUXN_IMPCAL = 0, \
798 .AUXP_IMPCAL = 0, \
799 .AUX_RESET_MASK = DP_AUX0_AUX_CONTROL__AUX_RESET_MASK, \
800 }
801
802 static const struct dce110_aux_registers aux_engine_regs[] = {
803 aux_engine_regs(0),
804 aux_engine_regs(1),
805 aux_engine_regs(2),
806 aux_engine_regs(3),
807 aux_engine_regs(4)
808 };
809
810 static const struct dce110_aux_registers_shift aux_shift = {
811 DCN_AUX_MASK_SH_LIST(__SHIFT)
812 };
813
814 static const struct dce110_aux_registers_mask aux_mask = {
815 DCN_AUX_MASK_SH_LIST(_MASK)
816 };
817
dcn302_aux_engine_create(struct dc_context * ctx,uint32_t inst)818 static struct dce_aux *dcn302_aux_engine_create(struct dc_context *ctx, uint32_t inst)
819 {
820 struct aux_engine_dce110 *aux_engine = kzalloc_obj(struct aux_engine_dce110);
821
822 if (!aux_engine)
823 return NULL;
824
825 dce110_aux_engine_construct(aux_engine, ctx, inst, SW_AUX_TIMEOUT_PERIOD_MULTIPLIER * AUX_TIMEOUT_PERIOD,
826 &aux_engine_regs[inst], &aux_mask, &aux_shift, ctx->dc->caps.extended_aux_timeout_support);
827
828 return &aux_engine->base;
829 }
830
831 #define i2c_inst_regs(id) { I2C_HW_ENGINE_COMMON_REG_LIST(id) }
832
833 static const struct dce_i2c_registers i2c_hw_regs[] = {
834 i2c_inst_regs(1),
835 i2c_inst_regs(2),
836 i2c_inst_regs(3),
837 i2c_inst_regs(4),
838 i2c_inst_regs(5)
839 };
840
841 static const struct dce_i2c_shift i2c_shifts = {
842 I2C_COMMON_MASK_SH_LIST_DCN2(__SHIFT)
843 };
844
845 static const struct dce_i2c_mask i2c_masks = {
846 I2C_COMMON_MASK_SH_LIST_DCN2(_MASK)
847 };
848
dcn302_i2c_hw_create(struct dc_context * ctx,uint32_t inst)849 static struct dce_i2c_hw *dcn302_i2c_hw_create(struct dc_context *ctx, uint32_t inst)
850 {
851 struct dce_i2c_hw *dce_i2c_hw = kzalloc_obj(struct dce_i2c_hw);
852
853 if (!dce_i2c_hw)
854 return NULL;
855
856 dcn2_i2c_hw_construct(dce_i2c_hw, ctx, inst, &i2c_hw_regs[inst], &i2c_shifts, &i2c_masks);
857
858 return dce_i2c_hw;
859 }
860
861 static const struct encoder_feature_support link_enc_feature = {
862 .max_hdmi_deep_color = COLOR_DEPTH_121212,
863 .max_hdmi_pixel_clock = 600000,
864 .hdmi_ycbcr420_supported = true,
865 .dp_ycbcr420_supported = true,
866 .fec_supported = true,
867 .flags.bits.IS_HBR2_CAPABLE = true,
868 .flags.bits.IS_HBR3_CAPABLE = true,
869 .flags.bits.IS_TPS3_CAPABLE = true,
870 .flags.bits.IS_TPS4_CAPABLE = true
871 };
872
873 #define link_regs(id, phyid)\
874 [id] = {\
875 LE_DCN3_REG_LIST(id), \
876 UNIPHY_DCN2_REG_LIST(phyid), \
877 DPCS_DCN2_REG_LIST(id), \
878 SRI(DP_DPHY_INTERNAL_CTRL, DP, id) \
879 }
880
881 static const struct dcn10_link_enc_registers link_enc_regs[] = {
882 link_regs(0, A),
883 link_regs(1, B),
884 link_regs(2, C),
885 link_regs(3, D),
886 link_regs(4, E)
887 };
888
889 static const struct dcn10_link_enc_shift le_shift = {
890 LINK_ENCODER_MASK_SH_LIST_DCN30(__SHIFT),
891 DPCS_DCN2_MASK_SH_LIST(__SHIFT)
892 };
893
894 static const struct dcn10_link_enc_mask le_mask = {
895 LINK_ENCODER_MASK_SH_LIST_DCN30(_MASK),
896 DPCS_DCN2_MASK_SH_LIST(_MASK)
897 };
898
899 #define aux_regs(id)\
900 [id] = { DCN2_AUX_REG_LIST(id) }
901
902 static const struct dcn10_link_enc_aux_registers link_enc_aux_regs[] = {
903 aux_regs(0),
904 aux_regs(1),
905 aux_regs(2),
906 aux_regs(3),
907 aux_regs(4)
908 };
909
910 #define hpd_regs(id)\
911 [id] = { HPD_REG_LIST(id) }
912
913 static const struct dcn10_link_enc_hpd_registers link_enc_hpd_regs[] = {
914 hpd_regs(0),
915 hpd_regs(1),
916 hpd_regs(2),
917 hpd_regs(3),
918 hpd_regs(4)
919 };
920
dcn302_link_encoder_create(struct dc_context * ctx,const struct encoder_init_data * enc_init_data)921 static struct link_encoder *dcn302_link_encoder_create(
922 struct dc_context *ctx,
923 const struct encoder_init_data *enc_init_data)
924 {
925 struct dcn20_link_encoder *enc20 = kzalloc_obj(struct dcn20_link_encoder);
926
927 if (!enc20 || enc_init_data->hpd_source >= ARRAY_SIZE(link_enc_hpd_regs))
928 return NULL;
929
930 dcn30_link_encoder_construct(enc20, enc_init_data, &link_enc_feature,
931 &link_enc_regs[enc_init_data->transmitter], &link_enc_aux_regs[enc_init_data->channel - 1],
932 &link_enc_hpd_regs[enc_init_data->hpd_source], &le_shift, &le_mask);
933
934 return &enc20->enc10.base;
935 }
936
937 static const struct dce_panel_cntl_registers panel_cntl_regs[] = {
938 { DCN_PANEL_CNTL_REG_LIST() }
939 };
940
941 static const struct dce_panel_cntl_shift panel_cntl_shift = {
942 DCE_PANEL_CNTL_MASK_SH_LIST(__SHIFT)
943 };
944
945 static const struct dce_panel_cntl_mask panel_cntl_mask = {
946 DCE_PANEL_CNTL_MASK_SH_LIST(_MASK)
947 };
948
dcn302_panel_cntl_create(const struct panel_cntl_init_data * init_data)949 static struct panel_cntl *dcn302_panel_cntl_create(const struct panel_cntl_init_data *init_data)
950 {
951 struct dce_panel_cntl *panel_cntl = kzalloc_obj(struct dce_panel_cntl);
952
953 if (!panel_cntl)
954 return NULL;
955
956 dce_panel_cntl_construct(panel_cntl, init_data, &panel_cntl_regs[init_data->inst],
957 &panel_cntl_shift, &panel_cntl_mask);
958
959 return &panel_cntl->base;
960 }
961
read_dce_straps(struct dc_context * ctx,struct resource_straps * straps)962 static void read_dce_straps(struct dc_context *ctx, struct resource_straps *straps)
963 {
964 generic_reg_get(ctx, mmDC_PINSTRAPS + BASE(mmDC_PINSTRAPS_BASE_IDX),
965 FN(DC_PINSTRAPS, DC_PINSTRAPS_AUDIO), &straps->dc_pinstraps_audio);
966 }
967
968 static const struct resource_create_funcs res_create_funcs = {
969 .read_dce_straps = read_dce_straps,
970 .create_audio = dcn302_create_audio,
971 .create_stream_encoder = dcn302_stream_encoder_create,
972 .create_hwseq = dcn302_hwseq_create,
973 };
974
is_soc_bounding_box_valid(struct dc * dc)975 static bool is_soc_bounding_box_valid(struct dc *dc)
976 {
977 uint32_t hw_internal_rev = dc->ctx->asic_id.hw_internal_rev;
978
979 if (ASICREV_IS_DIMGREY_CAVEFISH_P(hw_internal_rev))
980 return true;
981
982 return false;
983 }
984
init_soc_bounding_box(struct dc * dc,struct resource_pool * pool)985 static bool init_soc_bounding_box(struct dc *dc, struct resource_pool *pool)
986 {
987 struct _vcs_dpi_soc_bounding_box_st *loaded_bb = &dcn3_02_soc;
988 struct _vcs_dpi_ip_params_st *loaded_ip = &dcn3_02_ip;
989
990 DC_LOGGER_INIT(dc->ctx->logger);
991
992 if (!is_soc_bounding_box_valid(dc)) {
993 DC_LOG_ERROR("%s: not valid soc bounding box\n", __func__);
994 return false;
995 }
996
997 loaded_ip->max_num_otg = pool->pipe_count;
998 loaded_ip->max_num_dpp = pool->pipe_count;
999 loaded_ip->clamp_min_dcfclk = dc->config.clamp_min_dcfclk;
1000 DC_FP_START();
1001 dcn20_patch_bounding_box(dc, loaded_bb);
1002 DC_FP_END();
1003
1004 if (dc->ctx->dc_bios->funcs->get_soc_bb_info) {
1005 struct bp_soc_bb_info bb_info = { 0 };
1006
1007 if (dc->ctx->dc_bios->funcs->get_soc_bb_info(
1008 dc->ctx->dc_bios, &bb_info) == BP_RESULT_OK) {
1009
1010 DC_FP_START();
1011 dcn302_fpu_init_soc_bounding_box(bb_info);
1012 DC_FP_END();
1013 }
1014 }
1015
1016 return true;
1017 }
1018
dcn302_resource_destruct(struct resource_pool * pool)1019 static void dcn302_resource_destruct(struct resource_pool *pool)
1020 {
1021 unsigned int i;
1022
1023 for (i = 0; i < pool->stream_enc_count; i++) {
1024 if (pool->stream_enc[i] != NULL) {
1025 if (pool->stream_enc[i]->vpg != NULL) {
1026 kfree(DCN30_VPG_FROM_VPG(pool->stream_enc[i]->vpg));
1027 pool->stream_enc[i]->vpg = NULL;
1028 }
1029 if (pool->stream_enc[i]->afmt != NULL) {
1030 kfree(DCN30_AFMT_FROM_AFMT(pool->stream_enc[i]->afmt));
1031 pool->stream_enc[i]->afmt = NULL;
1032 }
1033 kfree(DCN10STRENC_FROM_STRENC(pool->stream_enc[i]));
1034 pool->stream_enc[i] = NULL;
1035 }
1036 }
1037
1038 for (i = 0; i < pool->res_cap->num_dsc; i++) {
1039 if (pool->dscs[i] != NULL)
1040 dcn20_dsc_destroy(&pool->dscs[i]);
1041 }
1042
1043 if (pool->mpc != NULL) {
1044 kfree(TO_DCN20_MPC(pool->mpc));
1045 pool->mpc = NULL;
1046 }
1047
1048 if (pool->hubbub != NULL) {
1049 kfree(pool->hubbub);
1050 pool->hubbub = NULL;
1051 }
1052
1053 if (pool->dio != NULL) {
1054 kfree(TO_DCN10_DIO(pool->dio));
1055 pool->dio = NULL;
1056 }
1057
1058 for (i = 0; i < pool->pipe_count; i++) {
1059 if (pool->dpps[i] != NULL) {
1060 kfree(TO_DCN20_DPP(pool->dpps[i]));
1061 pool->dpps[i] = NULL;
1062 }
1063
1064 if (pool->hubps[i] != NULL) {
1065 kfree(TO_DCN20_HUBP(pool->hubps[i]));
1066 pool->hubps[i] = NULL;
1067 }
1068
1069 if (pool->irqs != NULL)
1070 dal_irq_service_destroy(&pool->irqs);
1071 }
1072
1073 for (i = 0; i < pool->res_cap->num_ddc; i++) {
1074 if (pool->engines[i] != NULL)
1075 dce110_engine_destroy(&pool->engines[i]);
1076 if (pool->hw_i2cs[i] != NULL) {
1077 kfree(pool->hw_i2cs[i]);
1078 pool->hw_i2cs[i] = NULL;
1079 }
1080 if (pool->sw_i2cs[i] != NULL) {
1081 kfree(pool->sw_i2cs[i]);
1082 pool->sw_i2cs[i] = NULL;
1083 }
1084 }
1085
1086 for (i = 0; i < pool->res_cap->num_opp; i++) {
1087 if (pool->opps[i] != NULL)
1088 pool->opps[i]->funcs->opp_destroy(&pool->opps[i]);
1089 }
1090
1091 for (i = 0; i < pool->res_cap->num_timing_generator; i++) {
1092 if (pool->timing_generators[i] != NULL) {
1093 kfree(DCN10TG_FROM_TG(pool->timing_generators[i]));
1094 pool->timing_generators[i] = NULL;
1095 }
1096 }
1097
1098 for (i = 0; i < pool->res_cap->num_dwb; i++) {
1099 if (pool->dwbc[i] != NULL) {
1100 kfree(TO_DCN30_DWBC(pool->dwbc[i]));
1101 pool->dwbc[i] = NULL;
1102 }
1103 if (pool->mcif_wb[i] != NULL) {
1104 kfree(TO_DCN30_MMHUBBUB(pool->mcif_wb[i]));
1105 pool->mcif_wb[i] = NULL;
1106 }
1107 }
1108
1109 for (i = 0; i < pool->audio_count; i++) {
1110 if (pool->audios[i])
1111 dce_aud_destroy(&pool->audios[i]);
1112 }
1113
1114 for (i = 0; i < pool->clk_src_count; i++) {
1115 if (pool->clock_sources[i] != NULL)
1116 dcn20_clock_source_destroy(&pool->clock_sources[i]);
1117 }
1118
1119 if (pool->dp_clock_source != NULL)
1120 dcn20_clock_source_destroy(&pool->dp_clock_source);
1121
1122 for (i = 0; i < pool->res_cap->num_mpc_3dlut; i++) {
1123 if (pool->mpc_lut[i] != NULL) {
1124 dc_3dlut_func_release(pool->mpc_lut[i]);
1125 pool->mpc_lut[i] = NULL;
1126 }
1127 if (pool->mpc_shaper[i] != NULL) {
1128 dc_transfer_func_release(pool->mpc_shaper[i]);
1129 pool->mpc_shaper[i] = NULL;
1130 }
1131 }
1132
1133 for (i = 0; i < pool->pipe_count; i++) {
1134 if (pool->multiple_abms[i] != NULL)
1135 dce_abm_destroy(&pool->multiple_abms[i]);
1136 }
1137
1138 if (pool->psr != NULL)
1139 dmub_psr_destroy(&pool->psr);
1140
1141 if (pool->dccg != NULL)
1142 dcn_dccg_destroy(&pool->dccg);
1143
1144 if (pool->oem_device != NULL) {
1145 struct dc *dc = pool->oem_device->ctx->dc;
1146
1147 dc->link_srv->destroy_ddc_service(&pool->oem_device);
1148 }
1149 }
1150
dcn302_destroy_resource_pool(struct resource_pool ** pool)1151 static void dcn302_destroy_resource_pool(struct resource_pool **pool)
1152 {
1153 dcn302_resource_destruct(*pool);
1154 kfree(*pool);
1155 *pool = NULL;
1156 }
1157
dcn302_update_bw_bounding_box(struct dc * dc,struct clk_bw_params * bw_params)1158 void dcn302_update_bw_bounding_box(struct dc *dc, struct clk_bw_params *bw_params)
1159 {
1160 DC_FP_START();
1161 dcn302_fpu_update_bw_bounding_box(dc, bw_params);
1162 DC_FP_END();
1163 }
1164
dcn302_get_panel_config_defaults(struct dc_panel_config * panel_config)1165 static void dcn302_get_panel_config_defaults(struct dc_panel_config *panel_config)
1166 {
1167 *panel_config = panel_config_defaults;
1168 }
1169
1170 static struct resource_funcs dcn302_res_pool_funcs = {
1171 .destroy = dcn302_destroy_resource_pool,
1172 .link_enc_create = dcn302_link_encoder_create,
1173 .panel_cntl_create = dcn302_panel_cntl_create,
1174 .validate_bandwidth = dcn30_validate_bandwidth,
1175 .calculate_wm_and_dlg = dcn30_calculate_wm_and_dlg,
1176 .update_soc_for_wm_a = dcn30_update_soc_for_wm_a,
1177 .populate_dml_pipes = dcn30_populate_dml_pipes_from_context,
1178 .acquire_free_pipe_as_secondary_dpp_pipe = dcn20_acquire_free_pipe_for_layer,
1179 .release_pipe = dcn20_release_pipe,
1180 .add_stream_to_ctx = dcn30_add_stream_to_ctx,
1181 .add_dsc_to_stream_resource = dcn20_add_dsc_to_stream_resource,
1182 .remove_stream_from_ctx = dcn20_remove_stream_from_ctx,
1183 .populate_dml_writeback_from_context = dcn30_populate_dml_writeback_from_context,
1184 .set_mcif_arb_params = dcn30_set_mcif_arb_params,
1185 .find_first_free_match_stream_enc_for_link = dcn10_find_first_free_match_stream_enc_for_link,
1186 .acquire_post_bldn_3dlut = dcn30_acquire_post_bldn_3dlut,
1187 .release_post_bldn_3dlut = dcn30_release_post_bldn_3dlut,
1188 .update_bw_bounding_box = dcn302_update_bw_bounding_box,
1189 .patch_unknown_plane_state = dcn20_patch_unknown_plane_state,
1190 .get_panel_config_defaults = dcn302_get_panel_config_defaults,
1191 .get_vstartup_for_pipe = dcn10_get_vstartup_for_pipe
1192 };
1193
1194 static struct dc_cap_funcs cap_funcs = {
1195 .get_dcc_compression_cap = dcn20_get_dcc_compression_cap
1196 };
1197
1198 static const struct bios_registers bios_regs = {
1199 NBIO_SR(BIOS_SCRATCH_3),
1200 NBIO_SR(BIOS_SCRATCH_6)
1201 };
1202
1203 static const struct dccg_registers dccg_regs = {
1204 DCCG_REG_LIST_DCN3_02()
1205 };
1206
1207 static const struct dccg_shift dccg_shift = {
1208 DCCG_MASK_SH_LIST_DCN3_02(__SHIFT)
1209 };
1210
1211 static const struct dccg_mask dccg_mask = {
1212 DCCG_MASK_SH_LIST_DCN3_02(_MASK)
1213 };
1214
1215 #define abm_regs(id)\
1216 [id] = { ABM_DCN302_REG_LIST(id) }
1217
1218 static const struct dce_abm_registers abm_regs[] = {
1219 abm_regs(0),
1220 abm_regs(1),
1221 abm_regs(2),
1222 abm_regs(3),
1223 abm_regs(4)
1224 };
1225
1226 static const struct dce_abm_shift abm_shift = {
1227 ABM_MASK_SH_LIST_DCN30(__SHIFT)
1228 };
1229
1230 static const struct dce_abm_mask abm_mask = {
1231 ABM_MASK_SH_LIST_DCN30(_MASK)
1232 };
1233
dcn302_resource_construct(uint8_t num_virtual_links,struct dc * dc,struct resource_pool * pool)1234 static bool dcn302_resource_construct(
1235 uint8_t num_virtual_links,
1236 struct dc *dc,
1237 struct resource_pool *pool)
1238 {
1239 int i;
1240 struct dc_context *ctx = dc->ctx;
1241 struct irq_service_init_data init_data;
1242 struct ddc_service_init_data ddc_init_data = {0};
1243
1244 ctx->dc_bios->regs = &bios_regs;
1245
1246 pool->res_cap = &res_cap_dcn302;
1247
1248 pool->funcs = &dcn302_res_pool_funcs;
1249
1250 /*************************************************
1251 * Resource + asic cap harcoding *
1252 *************************************************/
1253 pool->underlay_pipe_index = NO_UNDERLAY_PIPE;
1254 pool->pipe_count = pool->res_cap->num_timing_generator;
1255 pool->mpcc_count = pool->res_cap->num_timing_generator;
1256 dc->caps.max_downscale_ratio = 600;
1257 dc->caps.i2c_speed_in_khz = 100;
1258 dc->caps.i2c_speed_in_khz_hdcp = 5; /*1.4 w/a applied by derfault*/
1259 dc->caps.max_cursor_size = 256;
1260 dc->caps.min_horizontal_blanking_period = 80;
1261 dc->caps.dmdata_alloc_size = 2048;
1262 dc->caps.mall_size_per_mem_channel = 4;
1263 /* total size = mall per channel * num channels * 1024 * 1024 */
1264 dc->caps.mall_size_total = dc->caps.mall_size_per_mem_channel * dc->ctx->dc_bios->vram_info.num_chans * 1048576;
1265 dc->caps.cursor_cache_size = dc->caps.max_cursor_size * dc->caps.max_cursor_size * 8;
1266 dc->caps.max_slave_planes = 2;
1267 dc->caps.max_slave_yuv_planes = 2;
1268 dc->caps.max_slave_rgb_planes = 2;
1269 dc->caps.post_blend_color_processing = true;
1270 dc->caps.force_dp_tps4_for_cp2520 = true;
1271 dc->caps.extended_aux_timeout_support = true;
1272 dc->caps.dmcub_support = true;
1273 dc->caps.max_v_total = (1 << 15) - 1;
1274 dc->caps.vtotal_limited_by_fp2 = true;
1275
1276 /* Color pipeline capabilities */
1277 dc->caps.color.dpp.dcn_arch = 1;
1278 dc->caps.color.dpp.input_lut_shared = 0;
1279 dc->caps.color.dpp.icsc = 1;
1280 dc->caps.color.dpp.dgam_ram = 0; // must use gamma_corr
1281 dc->caps.color.dpp.dgam_rom_caps.srgb = 1;
1282 dc->caps.color.dpp.dgam_rom_caps.bt2020 = 1;
1283 dc->caps.color.dpp.dgam_rom_caps.gamma2_2 = 1;
1284 dc->caps.color.dpp.dgam_rom_caps.pq = 1;
1285 dc->caps.color.dpp.dgam_rom_caps.hlg = 1;
1286 dc->caps.color.dpp.post_csc = 1;
1287 dc->caps.color.dpp.gamma_corr = 1;
1288 dc->caps.color.dpp.dgam_rom_for_yuv = 0;
1289
1290 dc->caps.color.dpp.hw_3d_lut = 1;
1291 dc->caps.color.dpp.ogam_ram = 1;
1292 // no OGAM ROM on DCN3
1293 dc->caps.color.dpp.ogam_rom_caps.srgb = 0;
1294 dc->caps.color.dpp.ogam_rom_caps.bt2020 = 0;
1295 dc->caps.color.dpp.ogam_rom_caps.gamma2_2 = 0;
1296 dc->caps.color.dpp.ogam_rom_caps.pq = 0;
1297 dc->caps.color.dpp.ogam_rom_caps.hlg = 0;
1298 dc->caps.color.dpp.ocsc = 0;
1299
1300 dc->caps.color.mpc.gamut_remap = 1;
1301 dc->caps.color.mpc.num_3dluts = pool->res_cap->num_mpc_3dlut; //3
1302 dc->caps.color.mpc.ogam_ram = 1;
1303 dc->caps.color.mpc.ogam_rom_caps.srgb = 0;
1304 dc->caps.color.mpc.ogam_rom_caps.bt2020 = 0;
1305 dc->caps.color.mpc.ogam_rom_caps.gamma2_2 = 0;
1306 dc->caps.color.mpc.ogam_rom_caps.pq = 0;
1307 dc->caps.color.mpc.ogam_rom_caps.hlg = 0;
1308 dc->caps.color.mpc.ocsc = 1;
1309
1310 dc->caps.dp_hdmi21_pcon_support = true;
1311
1312 /* read VBIOS LTTPR caps */
1313 if (ctx->dc_bios->funcs->get_lttpr_caps) {
1314 enum bp_result bp_query_result;
1315 uint8_t is_vbios_lttpr_enable = 0;
1316
1317 bp_query_result = ctx->dc_bios->funcs->get_lttpr_caps(ctx->dc_bios, &is_vbios_lttpr_enable);
1318 dc->caps.vbios_lttpr_enable = (bp_query_result == BP_RESULT_OK) && !!is_vbios_lttpr_enable;
1319 }
1320
1321 if (ctx->dc_bios->funcs->get_lttpr_interop) {
1322 enum bp_result bp_query_result;
1323 uint8_t is_vbios_interop_enabled = 0;
1324
1325 bp_query_result = ctx->dc_bios->funcs->get_lttpr_interop(ctx->dc_bios,
1326 &is_vbios_interop_enabled);
1327 dc->caps.vbios_lttpr_aware = (bp_query_result == BP_RESULT_OK) && !!is_vbios_interop_enabled;
1328 }
1329 dc->check_config = config_defaults;
1330
1331 if (dc->ctx->dce_environment == DCE_ENV_PRODUCTION_DRV)
1332 dc->debug = debug_defaults_drv;
1333
1334 // Init the vm_helper
1335 if (dc->vm_helper)
1336 vm_helper_init(dc->vm_helper, 16);
1337
1338 /*************************************************
1339 * Create resources *
1340 *************************************************/
1341
1342 /* Clock Sources for Pixel Clock*/
1343 pool->clock_sources[DCN302_CLK_SRC_PLL0] =
1344 dcn302_clock_source_create(ctx, ctx->dc_bios,
1345 CLOCK_SOURCE_COMBO_PHY_PLL0,
1346 &clk_src_regs[0], false);
1347 pool->clock_sources[DCN302_CLK_SRC_PLL1] =
1348 dcn302_clock_source_create(ctx, ctx->dc_bios,
1349 CLOCK_SOURCE_COMBO_PHY_PLL1,
1350 &clk_src_regs[1], false);
1351 pool->clock_sources[DCN302_CLK_SRC_PLL2] =
1352 dcn302_clock_source_create(ctx, ctx->dc_bios,
1353 CLOCK_SOURCE_COMBO_PHY_PLL2,
1354 &clk_src_regs[2], false);
1355 pool->clock_sources[DCN302_CLK_SRC_PLL3] =
1356 dcn302_clock_source_create(ctx, ctx->dc_bios,
1357 CLOCK_SOURCE_COMBO_PHY_PLL3,
1358 &clk_src_regs[3], false);
1359 pool->clock_sources[DCN302_CLK_SRC_PLL4] =
1360 dcn302_clock_source_create(ctx, ctx->dc_bios,
1361 CLOCK_SOURCE_COMBO_PHY_PLL4,
1362 &clk_src_regs[4], false);
1363
1364 pool->clk_src_count = DCN302_CLK_SRC_TOTAL;
1365
1366 /* todo: not reuse phy_pll registers */
1367 pool->dp_clock_source =
1368 dcn302_clock_source_create(ctx, ctx->dc_bios,
1369 CLOCK_SOURCE_ID_DP_DTO,
1370 &clk_src_regs[0], true);
1371
1372 for (i = 0; i < pool->clk_src_count; i++) {
1373 if (pool->clock_sources[i] == NULL) {
1374 dm_error("DC: failed to create clock sources!\n");
1375 BREAK_TO_DEBUGGER();
1376 goto create_fail;
1377 }
1378 }
1379
1380 /* DCCG */
1381 pool->dccg = dccg30_create(ctx, &dccg_regs, &dccg_shift, &dccg_mask);
1382 if (pool->dccg == NULL) {
1383 dm_error("DC: failed to create dccg!\n");
1384 BREAK_TO_DEBUGGER();
1385 goto create_fail;
1386 }
1387
1388 /* PP Lib and SMU interfaces */
1389 init_soc_bounding_box(dc, pool);
1390
1391 /* DML */
1392 dml_init_instance(&dc->dml, &dcn3_02_soc, &dcn3_02_ip, DML_PROJECT_DCN30);
1393
1394 /* IRQ */
1395 init_data.ctx = dc->ctx;
1396 pool->irqs = dal_irq_service_dcn302_create(&init_data);
1397 if (!pool->irqs)
1398 goto create_fail;
1399
1400 /* HUBBUB */
1401 pool->hubbub = dcn302_hubbub_create(ctx);
1402 if (pool->hubbub == NULL) {
1403 BREAK_TO_DEBUGGER();
1404 dm_error("DC: failed to create hubbub!\n");
1405 goto create_fail;
1406 }
1407
1408 /* DIO */
1409 pool->dio = dcn302_dio_create(ctx);
1410 if (pool->dio == NULL) {
1411 BREAK_TO_DEBUGGER();
1412 dm_error("DC: failed to create dio!\n");
1413 goto create_fail;
1414 }
1415
1416 /* HUBPs, DPPs, OPPs and TGs */
1417 for (i = 0; i < pool->pipe_count; i++) {
1418 pool->hubps[i] = dcn302_hubp_create(ctx, i);
1419 if (pool->hubps[i] == NULL) {
1420 BREAK_TO_DEBUGGER();
1421 dm_error("DC: failed to create hubps!\n");
1422 goto create_fail;
1423 }
1424
1425 pool->dpps[i] = dcn302_dpp_create(ctx, i);
1426 if (pool->dpps[i] == NULL) {
1427 BREAK_TO_DEBUGGER();
1428 dm_error("DC: failed to create dpps!\n");
1429 goto create_fail;
1430 }
1431 }
1432
1433 for (i = 0; i < pool->res_cap->num_opp; i++) {
1434 pool->opps[i] = dcn302_opp_create(ctx, i);
1435 if (pool->opps[i] == NULL) {
1436 BREAK_TO_DEBUGGER();
1437 dm_error("DC: failed to create output pixel processor!\n");
1438 goto create_fail;
1439 }
1440 }
1441
1442 for (i = 0; i < pool->res_cap->num_timing_generator; i++) {
1443 pool->timing_generators[i] = dcn302_timing_generator_create(ctx, i);
1444 if (pool->timing_generators[i] == NULL) {
1445 BREAK_TO_DEBUGGER();
1446 dm_error("DC: failed to create tg!\n");
1447 goto create_fail;
1448 }
1449 }
1450 pool->timing_generator_count = i;
1451
1452 /* PSR */
1453 pool->psr = dmub_psr_create(ctx);
1454 if (pool->psr == NULL) {
1455 dm_error("DC: failed to create psr!\n");
1456 BREAK_TO_DEBUGGER();
1457 goto create_fail;
1458 }
1459
1460 /* ABMs */
1461 for (i = 0; i < pool->res_cap->num_timing_generator; i++) {
1462 pool->multiple_abms[i] = dmub_abm_create(ctx, &abm_regs[i], &abm_shift, &abm_mask);
1463 if (pool->multiple_abms[i] == NULL) {
1464 dm_error("DC: failed to create abm for pipe %d!\n", i);
1465 BREAK_TO_DEBUGGER();
1466 goto create_fail;
1467 }
1468 }
1469
1470 /* MPC and DSC */
1471 pool->mpc = dcn302_mpc_create(ctx, pool->mpcc_count, pool->res_cap->num_mpc_3dlut);
1472 if (pool->mpc == NULL) {
1473 BREAK_TO_DEBUGGER();
1474 dm_error("DC: failed to create mpc!\n");
1475 goto create_fail;
1476 }
1477
1478 for (i = 0; i < pool->res_cap->num_dsc; i++) {
1479 pool->dscs[i] = dcn302_dsc_create(ctx, i);
1480 if (pool->dscs[i] == NULL) {
1481 BREAK_TO_DEBUGGER();
1482 dm_error("DC: failed to create display stream compressor %d!\n", i);
1483 goto create_fail;
1484 }
1485 }
1486
1487 /* DWB and MMHUBBUB */
1488 if (!dcn302_dwbc_create(ctx, pool)) {
1489 BREAK_TO_DEBUGGER();
1490 dm_error("DC: failed to create dwbc!\n");
1491 goto create_fail;
1492 }
1493
1494 if (!dcn302_mmhubbub_create(ctx, pool)) {
1495 BREAK_TO_DEBUGGER();
1496 dm_error("DC: failed to create mcif_wb!\n");
1497 goto create_fail;
1498 }
1499
1500 /* AUX and I2C */
1501 for (i = 0; i < pool->res_cap->num_ddc; i++) {
1502 pool->engines[i] = dcn302_aux_engine_create(ctx, i);
1503 if (pool->engines[i] == NULL) {
1504 BREAK_TO_DEBUGGER();
1505 dm_error("DC:failed to create aux engine!!\n");
1506 goto create_fail;
1507 }
1508 pool->hw_i2cs[i] = dcn302_i2c_hw_create(ctx, i);
1509 if (pool->hw_i2cs[i] == NULL) {
1510 BREAK_TO_DEBUGGER();
1511 dm_error("DC:failed to create hw i2c!!\n");
1512 goto create_fail;
1513 }
1514 pool->sw_i2cs[i] = NULL;
1515 }
1516
1517 /* Audio, Stream Encoders including HPO and virtual, MPC 3D LUTs */
1518 if (!resource_construct(num_virtual_links, dc, pool,
1519 &res_create_funcs))
1520 goto create_fail;
1521
1522 /* HW Sequencer and Plane caps */
1523 dcn302_hw_sequencer_construct(dc);
1524
1525 dc->caps.max_planes = pool->pipe_count;
1526
1527 for (i = 0; i < dc->caps.max_planes; ++i)
1528 dc->caps.planes[i] = plane_cap;
1529
1530 dc->caps.max_odm_combine_factor = 4;
1531
1532 dc->cap_funcs = cap_funcs;
1533
1534 if (dc->ctx->dc_bios->fw_info.oem_i2c_present) {
1535 ddc_init_data.ctx = dc->ctx;
1536 ddc_init_data.link = NULL;
1537 ddc_init_data.id.id = dc->ctx->dc_bios->fw_info.oem_i2c_obj_id;
1538 ddc_init_data.id.enum_id = 0;
1539 ddc_init_data.id.type = OBJECT_TYPE_GENERIC;
1540 pool->oem_device = dc->link_srv->create_ddc_service(&ddc_init_data);
1541 } else {
1542 pool->oem_device = NULL;
1543 }
1544
1545 return true;
1546
1547 create_fail:
1548
1549 dcn302_resource_destruct(pool);
1550
1551 return false;
1552 }
1553
dcn302_create_resource_pool(const struct dc_init_data * init_data,struct dc * dc)1554 struct resource_pool *dcn302_create_resource_pool(const struct dc_init_data *init_data, struct dc *dc)
1555 {
1556 struct resource_pool *pool = kzalloc_obj(struct resource_pool);
1557
1558 if (!pool)
1559 return NULL;
1560
1561 if (dcn302_resource_construct(init_data->num_virtual_links, dc, pool))
1562 return pool;
1563
1564 BREAK_TO_DEBUGGER();
1565 kfree(pool);
1566 return NULL;
1567 }
1568