1 /*
2 * Copyright 2016 Advanced Micro Devices, Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
21 *
22 * Authors: AMD
23 *
24 */
25
26 #include "dm_services.h"
27 #include "dm_helpers.h"
28 #include "core_types.h"
29 #include "resource.h"
30 #include "dce/dce_hwseq.h"
31 #include "dce110/dce110_hwseq.h"
32 #include "dcn21_hwseq.h"
33 #include "vmid.h"
34 #include "reg_helper.h"
35 #include "hw/clk_mgr.h"
36 #include "hw/dccg.h"
37 #include "dc_dmub_srv.h"
38 #include "abm.h"
39 #include "link_service.h"
40
41 #define DC_LOGGER_INIT(logger)
42
43 #define CTX \
44 hws->ctx
45 #define REG(reg)\
46 hws->regs->reg
47
48 #undef FN
49 #define FN(reg_name, field_name) \
50 hws->shifts->field_name, hws->masks->field_name
51
52 /* Temporary read settings, future will get values from kmd directly */
mmhub_update_page_table_config(struct dcn_hubbub_phys_addr_config * config,struct dce_hwseq * hws)53 static void mmhub_update_page_table_config(struct dcn_hubbub_phys_addr_config *config,
54 struct dce_hwseq *hws)
55 {
56 uint32_t page_table_base_hi;
57 uint32_t page_table_base_lo;
58
59 REG_GET(VM_CONTEXT0_PAGE_TABLE_BASE_ADDR_HI32,
60 PAGE_DIRECTORY_ENTRY_HI32, &page_table_base_hi);
61 REG_GET(VM_CONTEXT0_PAGE_TABLE_BASE_ADDR_LO32,
62 PAGE_DIRECTORY_ENTRY_LO32, &page_table_base_lo);
63
64 config->gart_config.page_table_base_addr = ((uint64_t)page_table_base_hi << 32) | page_table_base_lo;
65
66 }
67
dcn21_init_sys_ctx(struct dce_hwseq * hws,struct dc * dc,struct dc_phy_addr_space_config * pa_config)68 int dcn21_init_sys_ctx(struct dce_hwseq *hws, struct dc *dc, struct dc_phy_addr_space_config *pa_config)
69 {
70 struct dcn_hubbub_phys_addr_config config = {0};
71
72 config.system_aperture.fb_top = pa_config->system_aperture.fb_top;
73 config.system_aperture.fb_offset = pa_config->system_aperture.fb_offset;
74 config.system_aperture.fb_base = pa_config->system_aperture.fb_base;
75 config.system_aperture.agp_top = pa_config->system_aperture.agp_top;
76 config.system_aperture.agp_bot = pa_config->system_aperture.agp_bot;
77 config.system_aperture.agp_base = pa_config->system_aperture.agp_base;
78 config.gart_config.page_table_start_addr = pa_config->gart_config.page_table_start_addr;
79 config.gart_config.page_table_end_addr = pa_config->gart_config.page_table_end_addr;
80 config.gart_config.page_table_base_addr = pa_config->gart_config.page_table_base_addr;
81
82 mmhub_update_page_table_config(&config, hws);
83
84 return dc->res_pool->hubbub->funcs->init_dchub_sys_ctx(dc->res_pool->hubbub, &config);
85 }
86
87 // work around for Renoir s0i3, if register is programmed, bypass golden init.
88
dcn21_s0i3_golden_init_wa(struct dc * dc)89 bool dcn21_s0i3_golden_init_wa(struct dc *dc)
90 {
91 if (dc->res_pool->dccg && dc->res_pool->dccg->funcs && dc->res_pool->dccg->funcs->is_s0i3_golden_init_wa_done)
92 return !dc->res_pool->dccg->funcs->is_s0i3_golden_init_wa_done(dc->res_pool->dccg);
93
94 return false;
95 }
96
dcn21_exit_optimized_pwr_state(const struct dc * dc,struct dc_state * context)97 void dcn21_exit_optimized_pwr_state(
98 const struct dc *dc,
99 struct dc_state *context)
100 {
101 dc->clk_mgr->funcs->update_clocks(
102 dc->clk_mgr,
103 context,
104 false);
105 }
106
dcn21_optimize_pwr_state(const struct dc * dc,struct dc_state * context)107 void dcn21_optimize_pwr_state(
108 const struct dc *dc,
109 struct dc_state *context)
110 {
111 dc->clk_mgr->funcs->update_clocks(
112 dc->clk_mgr,
113 context,
114 true);
115 }
116
117 /* If user hotplug a HDMI monitor while in monitor off,
118 * OS will do a mode set (with output timing) but keep output off.
119 * In this case DAL will ask vbios to power up the pll in the PHY.
120 * If user unplug the monitor (while we are on monitor off) or
121 * system attempt to enter modern standby (which we will disable PLL),
122 * PHY will hang on the next mode set attempt.
123 * if enable PLL follow by disable PLL (without executing lane enable/disable),
124 * RDPCS_PHY_DP_MPLLB_STATE remains 1,
125 * which indicate that PLL disable attempt actually didn't go through.
126 * As a workaround, insert PHY lane enable/disable before PLL disable.
127 */
dcn21_PLAT_58856_wa(struct dc_state * context,struct pipe_ctx * pipe_ctx)128 void dcn21_PLAT_58856_wa(struct dc_state *context, struct pipe_ctx *pipe_ctx)
129 {
130 if (!pipe_ctx->stream->dpms_off)
131 return;
132
133 pipe_ctx->stream->dpms_off = false;
134 pipe_ctx->stream->ctx->dc->link_srv->set_dpms_on(context, pipe_ctx);
135 pipe_ctx->stream->ctx->dc->link_srv->set_dpms_off(pipe_ctx);
136 pipe_ctx->stream->dpms_off = true;
137 }
138
dcn21_dmub_abm_set_pipe(struct abm * abm,uint32_t otg_inst,uint32_t option,uint32_t panel_inst,uint32_t pwrseq_inst)139 bool dcn21_dmub_abm_set_pipe(struct abm *abm, uint32_t otg_inst,
140 uint32_t option, uint32_t panel_inst, uint32_t pwrseq_inst)
141 {
142 union dmub_rb_cmd cmd;
143 struct dc_context *dc = abm->ctx;
144 uint8_t ramping_boundary = 0xFF;
145
146 memset(&cmd, 0, sizeof(cmd));
147 cmd.abm_set_pipe.header.type = DMUB_CMD__ABM;
148 cmd.abm_set_pipe.header.sub_type = DMUB_CMD__ABM_SET_PIPE;
149 cmd.abm_set_pipe.abm_set_pipe_data.otg_inst = otg_inst;
150 cmd.abm_set_pipe.abm_set_pipe_data.pwrseq_inst = pwrseq_inst;
151 cmd.abm_set_pipe.abm_set_pipe_data.set_pipe_option = option;
152 cmd.abm_set_pipe.abm_set_pipe_data.panel_inst = panel_inst;
153 cmd.abm_set_pipe.abm_set_pipe_data.ramping_boundary = ramping_boundary;
154 cmd.abm_set_pipe.header.payload_bytes = sizeof(struct dmub_cmd_abm_set_pipe_data);
155
156 dc_wake_and_execute_dmub_cmd(dc, &cmd, DM_DMUB_WAIT_TYPE_WAIT);
157
158 return true;
159 }
160
dmub_abm_set_backlight(struct dc_context * dc,uint32_t backlight_pwm_u16_16,uint32_t frame_ramp,uint32_t panel_inst)161 static void dmub_abm_set_backlight(struct dc_context *dc, uint32_t backlight_pwm_u16_16,
162 uint32_t frame_ramp, uint32_t panel_inst)
163 {
164 union dmub_rb_cmd cmd;
165
166 memset(&cmd, 0, sizeof(cmd));
167 cmd.abm_set_backlight.header.type = DMUB_CMD__ABM;
168 cmd.abm_set_backlight.header.sub_type = DMUB_CMD__ABM_SET_BACKLIGHT;
169 cmd.abm_set_backlight.abm_set_backlight_data.frame_ramp = frame_ramp;
170 cmd.abm_set_backlight.abm_set_backlight_data.backlight_user_level = backlight_pwm_u16_16;
171 cmd.abm_set_backlight.abm_set_backlight_data.version = DMUB_CMD_ABM_CONTROL_VERSION_1;
172 cmd.abm_set_backlight.abm_set_backlight_data.panel_mask = (0x01 << panel_inst);
173 cmd.abm_set_backlight.header.payload_bytes = sizeof(struct dmub_cmd_abm_set_backlight_data);
174
175 dc_wake_and_execute_dmub_cmd(dc, &cmd, DM_DMUB_WAIT_TYPE_WAIT);
176 }
177
dcn21_set_abm_immediate_disable(struct pipe_ctx * pipe_ctx)178 void dcn21_set_abm_immediate_disable(struct pipe_ctx *pipe_ctx)
179 {
180 struct abm *abm = pipe_ctx->stream_res.abm;
181 uint32_t otg_inst = pipe_ctx->stream_res.tg->inst;
182 struct panel_cntl *panel_cntl = pipe_ctx->stream->link->panel_cntl;
183 struct dmcu *dmcu = pipe_ctx->stream->ctx->dc->res_pool->dmcu;
184
185 // make a short term w/a for an issue that backlight ramping unexpectedly paused in the middle,
186 // will decouple backlight from ABM and redefine DMUB interface, then this w/a could be removed
187 if (pipe_ctx->stream->abm_level == 0 || pipe_ctx->stream->abm_level == ABM_LEVEL_IMMEDIATE_DISABLE) {
188 return;
189 }
190
191 if (dmcu) {
192 dce110_set_abm_immediate_disable(pipe_ctx);
193 return;
194 }
195
196 if (abm && panel_cntl) {
197 if (abm->funcs && abm->funcs->set_pipe_ex) {
198 abm->funcs->set_pipe_ex(abm, otg_inst, SET_ABM_PIPE_IMMEDIATELY_DISABLE,
199 panel_cntl->inst, panel_cntl->pwrseq_inst);
200 } else {
201 dcn21_dmub_abm_set_pipe(abm,
202 otg_inst,
203 SET_ABM_PIPE_IMMEDIATELY_DISABLE,
204 panel_cntl->inst,
205 panel_cntl->pwrseq_inst);
206 }
207 panel_cntl->funcs->store_backlight_level(panel_cntl);
208 }
209 }
210
dcn21_set_pipe(struct pipe_ctx * pipe_ctx)211 void dcn21_set_pipe(struct pipe_ctx *pipe_ctx)
212 {
213 struct abm *abm = pipe_ctx->stream_res.abm;
214 struct timing_generator *tg = pipe_ctx->stream_res.tg;
215 struct panel_cntl *panel_cntl = pipe_ctx->stream->link->panel_cntl;
216 struct dmcu *dmcu = pipe_ctx->stream->ctx->dc->res_pool->dmcu;
217 uint32_t otg_inst;
218
219 if (!abm || !tg || !panel_cntl)
220 return;
221
222 otg_inst = tg->inst;
223
224 if (dmcu) {
225 dce110_set_pipe(pipe_ctx);
226 return;
227 }
228
229 if (abm->funcs && abm->funcs->set_pipe_ex) {
230 abm->funcs->set_pipe_ex(abm,
231 otg_inst,
232 SET_ABM_PIPE_NORMAL,
233 panel_cntl->inst,
234 panel_cntl->pwrseq_inst);
235 } else {
236 dcn21_dmub_abm_set_pipe(abm, otg_inst,
237 SET_ABM_PIPE_NORMAL,
238 panel_cntl->inst,
239 panel_cntl->pwrseq_inst);
240 }
241 }
242
dcn21_set_backlight_level(struct pipe_ctx * pipe_ctx,struct set_backlight_level_params * backlight_level_params)243 bool dcn21_set_backlight_level(struct pipe_ctx *pipe_ctx,
244 struct set_backlight_level_params *backlight_level_params)
245 {
246 struct dc_context *dc = pipe_ctx->stream->ctx;
247 struct abm *abm = pipe_ctx->stream_res.abm;
248 struct timing_generator *tg = pipe_ctx->stream_res.tg;
249 struct panel_cntl *panel_cntl = pipe_ctx->stream->link->panel_cntl;
250 uint32_t otg_inst;
251 uint32_t backlight_pwm_u16_16 = backlight_level_params->backlight_pwm_u16_16;
252 uint32_t frame_ramp = backlight_level_params->frame_ramp;
253
254 if (!abm || !tg || !panel_cntl)
255 return false;
256
257 otg_inst = tg->inst;
258
259 if (dc->dc->res_pool->dmcu) {
260 dce110_set_backlight_level(pipe_ctx, backlight_level_params);
261 return true;
262 }
263
264 if (abm->funcs && abm->funcs->set_pipe_ex) {
265 abm->funcs->set_pipe_ex(abm,
266 otg_inst,
267 SET_ABM_PIPE_NORMAL,
268 panel_cntl->inst,
269 panel_cntl->pwrseq_inst);
270 } else {
271 dcn21_dmub_abm_set_pipe(abm,
272 otg_inst,
273 SET_ABM_PIPE_NORMAL,
274 panel_cntl->inst,
275 panel_cntl->pwrseq_inst);
276 }
277
278 if (abm->funcs && abm->funcs->set_backlight_level_pwm)
279 abm->funcs->set_backlight_level_pwm(abm, backlight_pwm_u16_16,
280 frame_ramp, 0, panel_cntl->inst);
281 else
282 dmub_abm_set_backlight(dc, backlight_pwm_u16_16, frame_ramp, panel_cntl->inst);
283
284 return true;
285 }
286
dcn21_is_abm_supported(struct dc * dc,struct dc_state * context,struct dc_stream_state * stream)287 bool dcn21_is_abm_supported(struct dc *dc,
288 struct dc_state *context, struct dc_stream_state *stream)
289 {
290 int i;
291
292 for (i = 0; i < dc->res_pool->pipe_count; i++) {
293 struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[i];
294
295 if (pipe_ctx->stream == stream &&
296 (pipe_ctx->prev_odm_pipe == NULL && pipe_ctx->next_odm_pipe == NULL))
297 return true;
298 }
299 return false;
300 }
301
302