1 /*
2 * Copyright 2018 Advanced Micro Devices, Inc.
3 * Copyright 2019 Raptor Engineering, LLC
4 *
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the "Software"),
7 * to deal in the Software without restriction, including without limitation
8 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
9 * and/or sell copies of the Software, and to permit persons to whom the
10 * Software is furnished to do so, subject to the following conditions:
11 *
12 * The above copyright notice and this permission notice shall be included in
13 * all copies or substantial portions of the Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
19 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
20 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
21 * OTHER DEALINGS IN THE SOFTWARE.
22 *
23 * Authors: AMD
24 *
25 */
26
27 #include <linux/slab.h>
28
29 #include "dm_services.h"
30 #include "dc.h"
31
32 #include "dcn21/dcn21_init.h"
33
34 #include "resource.h"
35 #include "include/irq_service_interface.h"
36 #include "dcn20/dcn20_resource.h"
37 #include "dcn21/dcn21_resource.h"
38
39 #include "dml/dcn20/dcn20_fpu.h"
40
41 #include "clk_mgr.h"
42 #include "dcn10/dcn10_hubp.h"
43 #include "dcn10/dcn10_ipp.h"
44 #include "dcn20/dcn20_hubbub.h"
45 #include "dcn20/dcn20_mpc.h"
46 #include "dcn20/dcn20_hubp.h"
47 #include "dcn21/dcn21_hubp.h"
48 #include "irq/dcn21/irq_service_dcn21.h"
49 #include "dcn20/dcn20_dpp.h"
50 #include "dcn20/dcn20_optc.h"
51 #include "dcn21/dcn21_hwseq.h"
52 #include "dce110/dce110_hwseq.h"
53 #include "dcn20/dcn20_opp.h"
54 #include "dcn20/dcn20_dsc.h"
55 #include "dcn21/dcn21_link_encoder.h"
56 #include "dcn20/dcn20_stream_encoder.h"
57 #include "dce/dce_clock_source.h"
58 #include "dce/dce_audio.h"
59 #include "dce/dce_hwseq.h"
60 #include "dio/virtual/virtual_stream_encoder.h"
61 #include "dml/display_mode_vba.h"
62 #include "dcn20/dcn20_dccg.h"
63 #include "dcn21/dcn21_dccg.h"
64 #include "dcn21/dcn21_hubbub.h"
65 #include "dcn10/dcn10_resource.h"
66 #include "dce/dce_panel_cntl.h"
67
68 #include "dcn20/dcn20_dwb.h"
69 #include "dcn20/dcn20_mmhubbub.h"
70 #include "dpcs/dpcs_2_1_0_offset.h"
71 #include "dpcs/dpcs_2_1_0_sh_mask.h"
72
73 #include "renoir_ip_offset.h"
74 #include "dcn/dcn_2_1_0_offset.h"
75 #include "dcn/dcn_2_1_0_sh_mask.h"
76
77 #include "nbio/nbio_7_0_offset.h"
78
79 #include "mmhub/mmhub_2_0_0_offset.h"
80 #include "mmhub/mmhub_2_0_0_sh_mask.h"
81
82 #include "reg_helper.h"
83 #include "dce/dce_abm.h"
84 #include "dce/dce_dmcu.h"
85 #include "dce/dce_aux.h"
86 #include "dce/dce_i2c.h"
87 #include "dio/dcn10/dcn10_dio.h"
88 #include "dcn21_resource.h"
89 #include "vm_helper.h"
90 #include "dcn20/dcn20_vmid.h"
91 #include "dce/dmub_psr.h"
92 #include "dce/dmub_abm.h"
93
94 /* begin *********************
95 * macros to expend register list macro defined in HW object header file */
96
97 /* DCN */
98 #define BASE_INNER(seg) DMU_BASE__INST0_SEG ## seg
99
100 #define BASE(seg) BASE_INNER(seg)
101
102 #define SR(reg_name)\
103 .reg_name = BASE(mm ## reg_name ## _BASE_IDX) + \
104 mm ## reg_name
105
106 #define SRI(reg_name, block, id)\
107 .reg_name = BASE(mm ## block ## id ## _ ## reg_name ## _BASE_IDX) + \
108 mm ## block ## id ## _ ## reg_name
109
110 #define SRIR(var_name, reg_name, block, id)\
111 .var_name = BASE(mm ## block ## id ## _ ## reg_name ## _BASE_IDX) + \
112 mm ## block ## id ## _ ## reg_name
113
114 #define SRII(reg_name, block, id)\
115 .reg_name[id] = BASE(mm ## block ## id ## _ ## reg_name ## _BASE_IDX) + \
116 mm ## block ## id ## _ ## reg_name
117
118 #define DCCG_SRII(reg_name, block, id)\
119 .block ## _ ## reg_name[id] = BASE(mm ## block ## id ## _ ## reg_name ## _BASE_IDX) + \
120 mm ## block ## id ## _ ## reg_name
121
122 #define VUPDATE_SRII(reg_name, block, id)\
123 .reg_name[id] = BASE(mm ## reg_name ## _ ## block ## id ## _BASE_IDX) + \
124 mm ## reg_name ## _ ## block ## id
125
126 /* NBIO */
127 #define NBIO_BASE_INNER(seg) \
128 NBIF0_BASE__INST0_SEG ## seg
129
130 #define NBIO_BASE(seg) \
131 NBIO_BASE_INNER(seg)
132
133 #define NBIO_SR(reg_name)\
134 .reg_name = NBIO_BASE(mm ## reg_name ## _BASE_IDX) + \
135 mm ## reg_name
136
137 /* MMHUB */
138 #define MMHUB_BASE_INNER(seg) \
139 MMHUB_BASE__INST0_SEG ## seg
140
141 #define MMHUB_BASE(seg) \
142 MMHUB_BASE_INNER(seg)
143
144 #define MMHUB_SR(reg_name)\
145 .reg_name = MMHUB_BASE(mmMM ## reg_name ## _BASE_IDX) + \
146 mmMM ## reg_name
147
148 #define clk_src_regs(index, pllid)\
149 [index] = {\
150 CS_COMMON_REG_LIST_DCN2_1(index, pllid),\
151 }
152
153 static const struct dce110_clk_src_regs clk_src_regs[] = {
154 clk_src_regs(0, A),
155 clk_src_regs(1, B),
156 clk_src_regs(2, C),
157 clk_src_regs(3, D),
158 clk_src_regs(4, E),
159 };
160
161 static const struct dce110_clk_src_shift cs_shift = {
162 CS_COMMON_MASK_SH_LIST_DCN2_0(__SHIFT)
163 };
164
165 static const struct dce110_clk_src_mask cs_mask = {
166 CS_COMMON_MASK_SH_LIST_DCN2_0(_MASK)
167 };
168
169 static const struct bios_registers bios_regs = {
170 NBIO_SR(BIOS_SCRATCH_3),
171 NBIO_SR(BIOS_SCRATCH_6)
172 };
173
174 static const struct dce_dmcu_registers dmcu_regs = {
175 DMCU_DCN20_REG_LIST()
176 };
177
178 static const struct dce_dmcu_shift dmcu_shift = {
179 DMCU_MASK_SH_LIST_DCN10(__SHIFT)
180 };
181
182 static const struct dce_dmcu_mask dmcu_mask = {
183 DMCU_MASK_SH_LIST_DCN10(_MASK)
184 };
185
186 static const struct dce_abm_registers abm_regs = {
187 ABM_DCN20_REG_LIST()
188 };
189
190 static const struct dce_abm_shift abm_shift = {
191 ABM_MASK_SH_LIST_DCN20(__SHIFT)
192 };
193
194 static const struct dce_abm_mask abm_mask = {
195 ABM_MASK_SH_LIST_DCN20(_MASK)
196 };
197
198 #define audio_regs(id)\
199 [id] = {\
200 AUD_COMMON_REG_LIST(id)\
201 }
202
203 static const struct dce_audio_registers audio_regs[] = {
204 audio_regs(0),
205 audio_regs(1),
206 audio_regs(2),
207 audio_regs(3),
208 audio_regs(4),
209 audio_regs(5),
210 };
211
212 #define DCE120_AUD_COMMON_MASK_SH_LIST(mask_sh)\
213 SF(AZF0ENDPOINT0_AZALIA_F0_CODEC_ENDPOINT_INDEX, AZALIA_ENDPOINT_REG_INDEX, mask_sh),\
214 SF(AZF0ENDPOINT0_AZALIA_F0_CODEC_ENDPOINT_DATA, AZALIA_ENDPOINT_REG_DATA, mask_sh),\
215 AUD_COMMON_MASK_SH_LIST_BASE(mask_sh)
216
217 static const struct dce_audio_shift audio_shift = {
218 DCE120_AUD_COMMON_MASK_SH_LIST(__SHIFT)
219 };
220
221 static const struct dce_audio_mask audio_mask = {
222 DCE120_AUD_COMMON_MASK_SH_LIST(_MASK)
223 };
224
225 static const struct dccg_registers dccg_regs = {
226 DCCG_COMMON_REG_LIST_DCN_BASE()
227 };
228
229 static const struct dccg_shift dccg_shift = {
230 DCCG_MASK_SH_LIST_DCN2_1(__SHIFT)
231 };
232
233 static const struct dccg_mask dccg_mask = {
234 DCCG_MASK_SH_LIST_DCN2_1(_MASK)
235 };
236
237 #define opp_regs(id)\
238 [id] = {\
239 OPP_REG_LIST_DCN20(id),\
240 }
241
242 static const struct dcn20_opp_registers opp_regs[] = {
243 opp_regs(0),
244 opp_regs(1),
245 opp_regs(2),
246 opp_regs(3),
247 opp_regs(4),
248 opp_regs(5),
249 };
250
251 static const struct dcn20_opp_shift opp_shift = {
252 OPP_MASK_SH_LIST_DCN20(__SHIFT)
253 };
254
255 static const struct dcn20_opp_mask opp_mask = {
256 OPP_MASK_SH_LIST_DCN20(_MASK)
257 };
258
259 #define tg_regs(id)\
260 [id] = {TG_COMMON_REG_LIST_DCN2_0(id)}
261
262 static const struct dcn_optc_registers tg_regs[] = {
263 tg_regs(0),
264 tg_regs(1),
265 tg_regs(2),
266 tg_regs(3)
267 };
268
269 static const struct dcn_optc_shift tg_shift = {
270 TG_COMMON_MASK_SH_LIST_DCN2_0(__SHIFT)
271 };
272
273 static const struct dcn_optc_mask tg_mask = {
274 TG_COMMON_MASK_SH_LIST_DCN2_0(_MASK)
275 };
276
277 static const struct dcn20_mpc_registers mpc_regs = {
278 MPC_REG_LIST_DCN2_0(0),
279 MPC_REG_LIST_DCN2_0(1),
280 MPC_REG_LIST_DCN2_0(2),
281 MPC_REG_LIST_DCN2_0(3),
282 MPC_REG_LIST_DCN2_0(4),
283 MPC_REG_LIST_DCN2_0(5),
284 MPC_OUT_MUX_REG_LIST_DCN2_0(0),
285 MPC_OUT_MUX_REG_LIST_DCN2_0(1),
286 MPC_OUT_MUX_REG_LIST_DCN2_0(2),
287 MPC_OUT_MUX_REG_LIST_DCN2_0(3),
288 MPC_DBG_REG_LIST_DCN2_0()
289 };
290
291 static const struct dcn20_mpc_shift mpc_shift = {
292 MPC_COMMON_MASK_SH_LIST_DCN2_0(__SHIFT),
293 MPC_DEBUG_REG_LIST_SH_DCN20
294 };
295
296 static const struct dcn20_mpc_mask mpc_mask = {
297 MPC_COMMON_MASK_SH_LIST_DCN2_0(_MASK),
298 MPC_DEBUG_REG_LIST_MASK_DCN20
299 };
300
301 #define hubp_regs(id)\
302 [id] = {\
303 HUBP_REG_LIST_DCN21(id)\
304 }
305
306 static const struct dcn_hubp2_registers hubp_regs[] = {
307 hubp_regs(0),
308 hubp_regs(1),
309 hubp_regs(2),
310 hubp_regs(3)
311 };
312
313 static const struct dcn_hubp2_shift hubp_shift = {
314 HUBP_MASK_SH_LIST_DCN21(__SHIFT)
315 };
316
317 static const struct dcn_hubp2_mask hubp_mask = {
318 HUBP_MASK_SH_LIST_DCN21(_MASK)
319 };
320
321 static const struct dcn_hubbub_registers hubbub_reg = {
322 HUBBUB_REG_LIST_DCN21()
323 };
324
325 static const struct dcn_hubbub_shift hubbub_shift = {
326 HUBBUB_MASK_SH_LIST_DCN21(__SHIFT)
327 };
328
329 static const struct dcn_hubbub_mask hubbub_mask = {
330 HUBBUB_MASK_SH_LIST_DCN21(_MASK)
331 };
332
333 static const struct dcn_dio_registers dio_regs = {
334 DIO_REG_LIST_DCN10()
335 };
336
337 static const struct dcn_dio_shift dio_shift = { 0 };
338
339 static const struct dcn_dio_mask dio_mask = { 0 };
340
dcn21_dio_create(struct dc_context * ctx)341 static struct dio *dcn21_dio_create(struct dc_context *ctx)
342 {
343 struct dcn10_dio *dio10 = kzalloc_obj(struct dcn10_dio);
344
345 if (!dio10)
346 return NULL;
347
348 dcn10_dio_construct(dio10, ctx, &dio_regs, &dio_shift, &dio_mask);
349
350 return &dio10->base;
351 }
352
353 #define vmid_regs(id)\
354 [id] = {\
355 DCN20_VMID_REG_LIST(id)\
356 }
357
358 static const struct dcn_vmid_registers vmid_regs[] = {
359 vmid_regs(0),
360 vmid_regs(1),
361 vmid_regs(2),
362 vmid_regs(3),
363 vmid_regs(4),
364 vmid_regs(5),
365 vmid_regs(6),
366 vmid_regs(7),
367 vmid_regs(8),
368 vmid_regs(9),
369 vmid_regs(10),
370 vmid_regs(11),
371 vmid_regs(12),
372 vmid_regs(13),
373 vmid_regs(14),
374 vmid_regs(15)
375 };
376
377 static const struct dcn20_vmid_shift vmid_shifts = {
378 DCN20_VMID_MASK_SH_LIST(__SHIFT)
379 };
380
381 static const struct dcn20_vmid_mask vmid_masks = {
382 DCN20_VMID_MASK_SH_LIST(_MASK)
383 };
384
385 #define dsc_regsDCN20(id)\
386 [id] = {\
387 DSC_REG_LIST_DCN20(id)\
388 }
389
390 static const struct dcn20_dsc_registers dsc_regs[] = {
391 dsc_regsDCN20(0),
392 dsc_regsDCN20(1),
393 dsc_regsDCN20(2),
394 dsc_regsDCN20(3),
395 dsc_regsDCN20(4),
396 dsc_regsDCN20(5)
397 };
398
399 static const struct dcn20_dsc_shift dsc_shift = {
400 DSC_REG_LIST_SH_MASK_DCN20(__SHIFT)
401 };
402
403 static const struct dcn20_dsc_mask dsc_mask = {
404 DSC_REG_LIST_SH_MASK_DCN20(_MASK)
405 };
406
407 #define ipp_regs(id)\
408 [id] = {\
409 IPP_REG_LIST_DCN20(id),\
410 }
411
412 static const struct dcn10_ipp_registers ipp_regs[] = {
413 ipp_regs(0),
414 ipp_regs(1),
415 ipp_regs(2),
416 ipp_regs(3),
417 };
418
419 static const struct dcn10_ipp_shift ipp_shift = {
420 IPP_MASK_SH_LIST_DCN20(__SHIFT)
421 };
422
423 static const struct dcn10_ipp_mask ipp_mask = {
424 IPP_MASK_SH_LIST_DCN20(_MASK),
425 };
426
427 #define opp_regs(id)\
428 [id] = {\
429 OPP_REG_LIST_DCN20(id),\
430 }
431
432
433 #define aux_engine_regs(id)\
434 [id] = {\
435 AUX_COMMON_REG_LIST0(id), \
436 .AUXN_IMPCAL = 0, \
437 .AUXP_IMPCAL = 0, \
438 .AUX_RESET_MASK = DP_AUX0_AUX_CONTROL__AUX_RESET_MASK, \
439 }
440
441 static const struct dce110_aux_registers aux_engine_regs[] = {
442 aux_engine_regs(0),
443 aux_engine_regs(1),
444 aux_engine_regs(2),
445 aux_engine_regs(3),
446 aux_engine_regs(4),
447 };
448
449 #define tf_regs(id)\
450 [id] = {\
451 TF_REG_LIST_DCN20(id),\
452 TF_REG_LIST_DCN20_COMMON_APPEND(id),\
453 }
454
455 static const struct dcn2_dpp_registers tf_regs[] = {
456 tf_regs(0),
457 tf_regs(1),
458 tf_regs(2),
459 tf_regs(3),
460 };
461
462 static const struct dcn2_dpp_shift tf_shift = {
463 TF_REG_LIST_SH_MASK_DCN20(__SHIFT),
464 TF_DEBUG_REG_LIST_SH_DCN20
465 };
466
467 static const struct dcn2_dpp_mask tf_mask = {
468 TF_REG_LIST_SH_MASK_DCN20(_MASK),
469 TF_DEBUG_REG_LIST_MASK_DCN20
470 };
471
472 #define stream_enc_regs(id)\
473 [id] = {\
474 SE_DCN2_REG_LIST(id)\
475 }
476
477 static const struct dcn10_stream_enc_registers stream_enc_regs[] = {
478 stream_enc_regs(0),
479 stream_enc_regs(1),
480 stream_enc_regs(2),
481 stream_enc_regs(3),
482 stream_enc_regs(4),
483 };
484
485 static const struct dce110_aux_registers_shift aux_shift = {
486 DCN_AUX_MASK_SH_LIST(__SHIFT)
487 };
488
489 static const struct dce110_aux_registers_mask aux_mask = {
490 DCN_AUX_MASK_SH_LIST(_MASK)
491 };
492
493 static const struct dcn10_stream_encoder_shift se_shift = {
494 SE_COMMON_MASK_SH_LIST_DCN20(__SHIFT)
495 };
496
497 static const struct dcn10_stream_encoder_mask se_mask = {
498 SE_COMMON_MASK_SH_LIST_DCN20(_MASK)
499 };
500
501 static void dcn21_pp_smu_destroy(struct pp_smu_funcs **pp_smu);
502
dcn21_ipp_create(struct dc_context * ctx,uint32_t inst)503 static struct input_pixel_processor *dcn21_ipp_create(
504 struct dc_context *ctx, uint32_t inst)
505 {
506 struct dcn10_ipp *ipp =
507 kzalloc_obj(struct dcn10_ipp);
508
509 if (!ipp) {
510 BREAK_TO_DEBUGGER();
511 return NULL;
512 }
513
514 dcn20_ipp_construct(ipp, ctx, inst,
515 &ipp_regs[inst], &ipp_shift, &ipp_mask);
516 return &ipp->base;
517 }
518
dcn21_dpp_create(struct dc_context * ctx,uint32_t inst)519 static struct dpp *dcn21_dpp_create(
520 struct dc_context *ctx,
521 uint32_t inst)
522 {
523 struct dcn20_dpp *dpp =
524 kzalloc_obj(struct dcn20_dpp);
525
526 if (!dpp)
527 return NULL;
528
529 if (dpp2_construct(dpp, ctx, inst,
530 &tf_regs[inst], &tf_shift, &tf_mask))
531 return &dpp->base;
532
533 BREAK_TO_DEBUGGER();
534 kfree(dpp);
535 return NULL;
536 }
537
dcn21_aux_engine_create(struct dc_context * ctx,uint32_t inst)538 static struct dce_aux *dcn21_aux_engine_create(
539 struct dc_context *ctx,
540 uint32_t inst)
541 {
542 struct aux_engine_dce110 *aux_engine =
543 kzalloc_obj(struct aux_engine_dce110);
544
545 if (!aux_engine)
546 return NULL;
547
548 dce110_aux_engine_construct(aux_engine, ctx, inst,
549 SW_AUX_TIMEOUT_PERIOD_MULTIPLIER * AUX_TIMEOUT_PERIOD,
550 &aux_engine_regs[inst],
551 &aux_mask,
552 &aux_shift,
553 ctx->dc->caps.extended_aux_timeout_support);
554
555 return &aux_engine->base;
556 }
557
558 #define i2c_inst_regs(id) { I2C_HW_ENGINE_COMMON_REG_LIST(id) }
559
560 static const struct dce_i2c_registers i2c_hw_regs[] = {
561 i2c_inst_regs(1),
562 i2c_inst_regs(2),
563 i2c_inst_regs(3),
564 i2c_inst_regs(4),
565 i2c_inst_regs(5),
566 };
567
568 static const struct dce_i2c_shift i2c_shifts = {
569 I2C_COMMON_MASK_SH_LIST_DCN2(__SHIFT)
570 };
571
572 static const struct dce_i2c_mask i2c_masks = {
573 I2C_COMMON_MASK_SH_LIST_DCN2(_MASK)
574 };
575
dcn21_i2c_hw_create(struct dc_context * ctx,uint32_t inst)576 static struct dce_i2c_hw *dcn21_i2c_hw_create(struct dc_context *ctx,
577 uint32_t inst)
578 {
579 struct dce_i2c_hw *dce_i2c_hw =
580 kzalloc_obj(struct dce_i2c_hw);
581
582 if (!dce_i2c_hw)
583 return NULL;
584
585 dcn2_i2c_hw_construct(dce_i2c_hw, ctx, inst,
586 &i2c_hw_regs[inst], &i2c_shifts, &i2c_masks);
587
588 return dce_i2c_hw;
589 }
590
591 static const struct resource_caps res_cap_rn = {
592 .num_timing_generator = 4,
593 .num_opp = 4,
594 .num_video_plane = 4,
595 .num_audio = 4, // 4 audio endpoints. 4 audio streams
596 .num_stream_encoder = 5,
597 .num_pll = 5, // maybe 3 because the last two used for USB-c
598 .num_dwb = 1,
599 .num_ddc = 5,
600 .num_vmid = 16,
601 .num_dsc = 3,
602 };
603
604 static const struct dc_plane_cap plane_cap = {
605 .type = DC_PLANE_TYPE_DCN_UNIVERSAL,
606 .per_pixel_alpha = true,
607
608 .pixel_format_support = {
609 .argb8888 = true,
610 .nv12 = true,
611 .fp16 = true,
612 .p010 = true
613 },
614
615 .max_upscale_factor = {
616 .argb8888 = 16000,
617 .nv12 = 16000,
618 .fp16 = 16000
619 },
620
621 .max_downscale_factor = {
622 .argb8888 = 250,
623 .nv12 = 250,
624 .fp16 = 250
625 },
626 64,
627 64
628 };
629
630 static const struct dc_debug_options debug_defaults_drv = {
631 .disable_dmcu = false,
632 .force_abm_enable = false,
633 .clock_trace = true,
634 .disable_pplib_clock_request = true,
635 .min_disp_clk_khz = 100000,
636 .pipe_split_policy = MPC_SPLIT_DYNAMIC,
637 .force_single_disp_pipe_split = false,
638 .disable_dcc = DCC_ENABLE,
639 .vsr_support = true,
640 .performance_trace = false,
641 .max_downscale_src_width = 4096,
642 .disable_pplib_wm_range = false,
643 .scl_reset_length10 = true,
644 .sanity_checks = true,
645 .disable_48mhz_pwrdwn = false,
646 .usbc_combo_phy_reset_wa = true,
647 .dmub_command_table = true,
648 .use_max_lb = true,
649 .using_dml2 = false,
650 };
651
652 static const struct dc_check_config config_defaults = {
653 .enable_legacy_fast_update = true,
654 };
655
656 static const struct dc_panel_config panel_config_defaults = {
657 .psr = {
658 .disable_psr = false,
659 .disallow_psrsu = false,
660 .disallow_replay = false,
661 },
662 .ilr = {
663 .optimize_edp_link_rate = true,
664 },
665 };
666
667 enum dcn20_clk_src_array_id {
668 DCN20_CLK_SRC_PLL0,
669 DCN20_CLK_SRC_PLL1,
670 DCN20_CLK_SRC_PLL2,
671 DCN20_CLK_SRC_PLL3,
672 DCN20_CLK_SRC_PLL4,
673 DCN20_CLK_SRC_TOTAL_DCN21
674 };
675
dcn21_resource_destruct(struct dcn21_resource_pool * pool)676 static void dcn21_resource_destruct(struct dcn21_resource_pool *pool)
677 {
678 unsigned int i;
679
680 for (i = 0; i < pool->base.stream_enc_count; i++) {
681 if (pool->base.stream_enc[i] != NULL) {
682 kfree(DCN10STRENC_FROM_STRENC(pool->base.stream_enc[i]));
683 pool->base.stream_enc[i] = NULL;
684 }
685 }
686
687 for (i = 0; i < pool->base.res_cap->num_dsc; i++) {
688 if (pool->base.dscs[i] != NULL)
689 dcn20_dsc_destroy(&pool->base.dscs[i]);
690 }
691
692 if (pool->base.mpc != NULL) {
693 kfree(TO_DCN20_MPC(pool->base.mpc));
694 pool->base.mpc = NULL;
695 }
696 if (pool->base.hubbub != NULL) {
697 kfree(pool->base.hubbub);
698 pool->base.hubbub = NULL;
699 }
700
701 if (pool->base.dio != NULL) {
702 kfree(TO_DCN10_DIO(pool->base.dio));
703 pool->base.dio = NULL;
704 }
705
706 for (i = 0; i < pool->base.pipe_count; i++) {
707 if (pool->base.dpps[i] != NULL)
708 dcn20_dpp_destroy(&pool->base.dpps[i]);
709
710 if (pool->base.ipps[i] != NULL)
711 pool->base.ipps[i]->funcs->ipp_destroy(&pool->base.ipps[i]);
712
713 if (pool->base.hubps[i] != NULL) {
714 kfree(TO_DCN20_HUBP(pool->base.hubps[i]));
715 pool->base.hubps[i] = NULL;
716 }
717
718 if (pool->base.irqs != NULL)
719 dal_irq_service_destroy(&pool->base.irqs);
720 }
721
722 for (i = 0; i < pool->base.res_cap->num_ddc; i++) {
723 if (pool->base.engines[i] != NULL)
724 dce110_engine_destroy(&pool->base.engines[i]);
725 if (pool->base.hw_i2cs[i] != NULL) {
726 kfree(pool->base.hw_i2cs[i]);
727 pool->base.hw_i2cs[i] = NULL;
728 }
729 if (pool->base.sw_i2cs[i] != NULL) {
730 kfree(pool->base.sw_i2cs[i]);
731 pool->base.sw_i2cs[i] = NULL;
732 }
733 }
734
735 for (i = 0; i < pool->base.res_cap->num_opp; i++) {
736 if (pool->base.opps[i] != NULL)
737 pool->base.opps[i]->funcs->opp_destroy(&pool->base.opps[i]);
738 }
739
740 for (i = 0; i < pool->base.res_cap->num_timing_generator; i++) {
741 if (pool->base.timing_generators[i] != NULL) {
742 kfree(DCN10TG_FROM_TG(pool->base.timing_generators[i]));
743 pool->base.timing_generators[i] = NULL;
744 }
745 }
746
747 for (i = 0; i < pool->base.res_cap->num_dwb; i++) {
748 if (pool->base.dwbc[i] != NULL) {
749 kfree(TO_DCN20_DWBC(pool->base.dwbc[i]));
750 pool->base.dwbc[i] = NULL;
751 }
752 if (pool->base.mcif_wb[i] != NULL) {
753 kfree(TO_DCN20_MMHUBBUB(pool->base.mcif_wb[i]));
754 pool->base.mcif_wb[i] = NULL;
755 }
756 }
757
758 for (i = 0; i < pool->base.audio_count; i++) {
759 if (pool->base.audios[i])
760 dce_aud_destroy(&pool->base.audios[i]);
761 }
762
763 for (i = 0; i < pool->base.clk_src_count; i++) {
764 if (pool->base.clock_sources[i] != NULL) {
765 dcn20_clock_source_destroy(&pool->base.clock_sources[i]);
766 pool->base.clock_sources[i] = NULL;
767 }
768 }
769
770 if (pool->base.dp_clock_source != NULL) {
771 dcn20_clock_source_destroy(&pool->base.dp_clock_source);
772 pool->base.dp_clock_source = NULL;
773 }
774
775 if (pool->base.abm != NULL) {
776 if (pool->base.abm->ctx->dc->config.disable_dmcu)
777 dmub_abm_destroy(&pool->base.abm);
778 else
779 dce_abm_destroy(&pool->base.abm);
780 }
781
782 if (pool->base.dmcu != NULL)
783 dce_dmcu_destroy(&pool->base.dmcu);
784
785 if (pool->base.psr != NULL)
786 dmub_psr_destroy(&pool->base.psr);
787
788 if (pool->base.dccg != NULL)
789 dcn_dccg_destroy(&pool->base.dccg);
790
791 if (pool->base.pp_smu != NULL)
792 dcn21_pp_smu_destroy(&pool->base.pp_smu);
793 }
794
dcn21_fast_validate_bw(struct dc * dc,struct dc_state * context,display_e2e_pipe_params_st * pipes,int * pipe_cnt_out,int * pipe_split_from,int * vlevel_out,enum dc_validate_mode validate_mode)795 bool dcn21_fast_validate_bw(struct dc *dc,
796 struct dc_state *context,
797 display_e2e_pipe_params_st *pipes,
798 int *pipe_cnt_out,
799 int *pipe_split_from,
800 int *vlevel_out,
801 enum dc_validate_mode validate_mode)
802 {
803 bool out = false;
804 int split[MAX_PIPES] = { 0 };
805 bool merge[MAX_PIPES] = { false };
806 int pipe_cnt, i, pipe_idx, vlevel;
807
808 ASSERT(pipes);
809 if (!pipes)
810 return false;
811
812 dcn20_merge_pipes_for_validate(dc, context);
813
814 pipe_cnt = dc->res_pool->funcs->populate_dml_pipes(dc, context, pipes, validate_mode);
815
816 *pipe_cnt_out = pipe_cnt;
817
818 if (!pipe_cnt) {
819 out = true;
820 goto validate_out;
821 }
822 /*
823 * DML favors voltage over p-state, but we're more interested in
824 * supporting p-state over voltage. We can't support p-state in
825 * prefetch mode > 0 so try capping the prefetch mode to start.
826 */
827 context->bw_ctx.dml.soc.allow_dram_self_refresh_or_dram_clock_change_in_vblank =
828 dm_allow_self_refresh_and_mclk_switch;
829 vlevel = dml_get_voltage_level(&context->bw_ctx.dml, pipes, pipe_cnt);
830
831 if (vlevel > context->bw_ctx.dml.soc.num_states) {
832 /*
833 * If mode is unsupported or there's still no p-state support then
834 * fall back to favoring voltage.
835 *
836 * We don't actually support prefetch mode 2, so require that we
837 * at least support prefetch mode 1.
838 */
839 context->bw_ctx.dml.soc.allow_dram_self_refresh_or_dram_clock_change_in_vblank =
840 dm_allow_self_refresh;
841 vlevel = dml_get_voltage_level(&context->bw_ctx.dml, pipes, pipe_cnt);
842 if (vlevel > context->bw_ctx.dml.soc.num_states)
843 goto validate_fail;
844 }
845
846 vlevel = dcn20_validate_apply_pipe_split_flags(dc, context, vlevel, split, merge);
847
848 for (i = 0, pipe_idx = 0; i < dc->res_pool->pipe_count; i++) {
849 struct pipe_ctx *pipe = &context->res_ctx.pipe_ctx[i];
850 struct pipe_ctx *mpo_pipe = pipe->bottom_pipe;
851 struct vba_vars_st *vba = &context->bw_ctx.dml.vba;
852
853 if (!pipe->stream)
854 continue;
855
856 /* We only support full screen mpo with ODM */
857 if (vba->ODMCombineEnabled[vba->pipe_plane[pipe_idx]] != dm_odm_combine_mode_disabled
858 && pipe->plane_state && mpo_pipe
859 && memcmp(&mpo_pipe->plane_state->clip_rect,
860 &pipe->stream->src,
861 sizeof(struct rect)) != 0) {
862 ASSERT(mpo_pipe->plane_state != pipe->plane_state);
863 goto validate_fail;
864 }
865 pipe_idx++;
866 }
867
868 /*initialize pipe_just_split_from to invalid idx*/
869 for (i = 0; i < MAX_PIPES; i++)
870 pipe_split_from[i] = -1;
871
872 for (i = 0, pipe_idx = -1; i < dc->res_pool->pipe_count; i++) {
873 struct pipe_ctx *pipe = &context->res_ctx.pipe_ctx[i];
874 struct pipe_ctx *hsplit_pipe = pipe->bottom_pipe;
875
876 if (!pipe->stream || pipe_split_from[i] >= 0)
877 continue;
878
879 pipe_idx++;
880
881 if (!pipe->top_pipe && !pipe->plane_state && context->bw_ctx.dml.vba.ODMCombineEnabled[pipe_idx]) {
882 hsplit_pipe = dcn20_find_secondary_pipe(dc, &context->res_ctx, dc->res_pool, pipe);
883 ASSERT(hsplit_pipe);
884 if (!dcn20_split_stream_for_odm(
885 dc, &context->res_ctx,
886 pipe, hsplit_pipe))
887 goto validate_fail;
888 pipe_split_from[hsplit_pipe->pipe_idx] = pipe_idx;
889 dcn20_build_mapped_resource(dc, context, pipe->stream);
890 }
891
892 if (!pipe->plane_state)
893 continue;
894 /* Skip 2nd half of already split pipe */
895 if (pipe->top_pipe && pipe->plane_state == pipe->top_pipe->plane_state)
896 continue;
897
898 if (split[i] == 2) {
899 if (!hsplit_pipe || hsplit_pipe->plane_state != pipe->plane_state) {
900 /* pipe not split previously needs split */
901 hsplit_pipe = dcn20_find_secondary_pipe(dc, &context->res_ctx, dc->res_pool, pipe);
902 ASSERT(hsplit_pipe);
903 if (!hsplit_pipe) {
904 DC_FP_START();
905 dcn20_fpu_adjust_dppclk(&context->bw_ctx.dml.vba, vlevel, context->bw_ctx.dml.vba.maxMpcComb, pipe_idx, true);
906 DC_FP_END();
907 continue;
908 }
909 if (context->bw_ctx.dml.vba.ODMCombineEnabled[pipe_idx]) {
910 if (!dcn20_split_stream_for_odm(
911 dc, &context->res_ctx,
912 pipe, hsplit_pipe))
913 goto validate_fail;
914 dcn20_build_mapped_resource(dc, context, pipe->stream);
915 } else {
916 dcn20_split_stream_for_mpc(
917 &context->res_ctx, dc->res_pool,
918 pipe, hsplit_pipe);
919 resource_build_scaling_params(pipe);
920 resource_build_scaling_params(hsplit_pipe);
921 }
922 pipe_split_from[hsplit_pipe->pipe_idx] = pipe_idx;
923 }
924 } else if (hsplit_pipe && hsplit_pipe->plane_state == pipe->plane_state) {
925 /* merge should already have been done */
926 ASSERT(0);
927 }
928 }
929 /* Actual dsc count per stream dsc validation*/
930 if (!dcn20_validate_dsc(dc, context)) {
931 context->bw_ctx.dml.vba.ValidationStatus[context->bw_ctx.dml.vba.soc.num_states] =
932 DML_FAIL_DSC_VALIDATION_FAILURE;
933 goto validate_fail;
934 }
935
936 *vlevel_out = vlevel;
937
938 out = true;
939 goto validate_out;
940
941 validate_fail:
942 out = false;
943
944 validate_out:
945 return out;
946 }
947
948 /*
949 * Some of the functions further below use the FPU, so we need to wrap this
950 * with DC_FP_START()/DC_FP_END(). Use the same approach as for
951 * dcn20_validate_bandwidth in dcn20_resource.c.
952 */
dcn21_validate_bandwidth(struct dc * dc,struct dc_state * context,enum dc_validate_mode validate_mode)953 static enum dc_status dcn21_validate_bandwidth(struct dc *dc, struct dc_state *context,
954 enum dc_validate_mode validate_mode)
955 {
956 bool voltage_supported;
957 display_e2e_pipe_params_st *pipes;
958
959 pipes = kzalloc_objs(display_e2e_pipe_params_st,
960 dc->res_pool->pipe_count);
961 if (!pipes)
962 return DC_FAIL_BANDWIDTH_VALIDATE;
963
964 DC_FP_START();
965 voltage_supported = dcn21_validate_bandwidth_fp(dc, context, validate_mode, pipes);
966 DC_FP_END();
967
968 kfree(pipes);
969 return voltage_supported ? DC_OK : DC_NOT_SUPPORTED;
970 }
971
dcn21_destroy_resource_pool(struct resource_pool ** pool)972 static void dcn21_destroy_resource_pool(struct resource_pool **pool)
973 {
974 struct dcn21_resource_pool *dcn21_pool = TO_DCN21_RES_POOL(*pool);
975
976 dcn21_resource_destruct(dcn21_pool);
977 kfree(dcn21_pool);
978 *pool = NULL;
979 }
980
dcn21_clock_source_create(struct dc_context * ctx,struct dc_bios * bios,enum clock_source_id id,const struct dce110_clk_src_regs * regs,bool dp_clk_src)981 static struct clock_source *dcn21_clock_source_create(
982 struct dc_context *ctx,
983 struct dc_bios *bios,
984 enum clock_source_id id,
985 const struct dce110_clk_src_regs *regs,
986 bool dp_clk_src)
987 {
988 struct dce110_clk_src *clk_src =
989 kzalloc_obj(struct dce110_clk_src);
990
991 if (!clk_src)
992 return NULL;
993
994 if (dcn20_clk_src_construct(clk_src, ctx, bios, id,
995 regs, &cs_shift, &cs_mask)) {
996 clk_src->base.dp_clk_src = dp_clk_src;
997 return &clk_src->base;
998 }
999
1000 kfree(clk_src);
1001 BREAK_TO_DEBUGGER();
1002 return NULL;
1003 }
1004
dcn21_hubp_create(struct dc_context * ctx,uint32_t inst)1005 static struct hubp *dcn21_hubp_create(
1006 struct dc_context *ctx,
1007 uint32_t inst)
1008 {
1009 struct dcn21_hubp *hubp21 =
1010 kzalloc_obj(struct dcn21_hubp);
1011
1012 if (!hubp21)
1013 return NULL;
1014
1015 if (hubp21_construct(hubp21, ctx, inst,
1016 &hubp_regs[inst], &hubp_shift, &hubp_mask))
1017 return &hubp21->base;
1018
1019 BREAK_TO_DEBUGGER();
1020 kfree(hubp21);
1021 return NULL;
1022 }
1023
dcn21_hubbub_create(struct dc_context * ctx)1024 static struct hubbub *dcn21_hubbub_create(struct dc_context *ctx)
1025 {
1026 int i;
1027
1028 struct dcn20_hubbub *hubbub = kzalloc_obj(struct dcn20_hubbub);
1029
1030 if (!hubbub)
1031 return NULL;
1032
1033 hubbub21_construct(hubbub, ctx,
1034 &hubbub_reg,
1035 &hubbub_shift,
1036 &hubbub_mask);
1037
1038 for (i = 0; i < res_cap_rn.num_vmid; i++) {
1039 struct dcn20_vmid *vmid = &hubbub->vmid[i];
1040
1041 vmid->ctx = ctx;
1042
1043 vmid->regs = &vmid_regs[i];
1044 vmid->shifts = &vmid_shifts;
1045 vmid->masks = &vmid_masks;
1046 }
1047 hubbub->num_vmid = res_cap_rn.num_vmid;
1048
1049 return &hubbub->base;
1050 }
1051
dcn21_opp_create(struct dc_context * ctx,uint32_t inst)1052 static struct output_pixel_processor *dcn21_opp_create(struct dc_context *ctx,
1053 uint32_t inst)
1054 {
1055 struct dcn20_opp *opp =
1056 kzalloc_obj(struct dcn20_opp);
1057
1058 if (!opp) {
1059 BREAK_TO_DEBUGGER();
1060 return NULL;
1061 }
1062
1063 dcn20_opp_construct(opp, ctx, inst,
1064 &opp_regs[inst], &opp_shift, &opp_mask);
1065 return &opp->base;
1066 }
1067
dcn21_timing_generator_create(struct dc_context * ctx,uint32_t instance)1068 static struct timing_generator *dcn21_timing_generator_create(struct dc_context *ctx,
1069 uint32_t instance)
1070 {
1071 struct optc *tgn10 =
1072 kzalloc_obj(struct optc);
1073
1074 if (!tgn10)
1075 return NULL;
1076
1077 tgn10->base.inst = instance;
1078 tgn10->base.ctx = ctx;
1079
1080 tgn10->tg_regs = &tg_regs[instance];
1081 tgn10->tg_shift = &tg_shift;
1082 tgn10->tg_mask = &tg_mask;
1083
1084 dcn20_timing_generator_init(tgn10);
1085
1086 return &tgn10->base;
1087 }
1088
dcn21_mpc_create(struct dc_context * ctx)1089 static struct mpc *dcn21_mpc_create(struct dc_context *ctx)
1090 {
1091 struct dcn20_mpc *mpc20 = kzalloc_obj(struct dcn20_mpc);
1092
1093 if (!mpc20)
1094 return NULL;
1095
1096 dcn20_mpc_construct(mpc20, ctx,
1097 &mpc_regs,
1098 &mpc_shift,
1099 &mpc_mask,
1100 6);
1101
1102 return &mpc20->base;
1103 }
1104
read_dce_straps(struct dc_context * ctx,struct resource_straps * straps)1105 static void read_dce_straps(
1106 struct dc_context *ctx,
1107 struct resource_straps *straps)
1108 {
1109 generic_reg_get(ctx, mmDC_PINSTRAPS + BASE(mmDC_PINSTRAPS_BASE_IDX),
1110 FN(DC_PINSTRAPS, DC_PINSTRAPS_AUDIO), &straps->dc_pinstraps_audio);
1111
1112 }
1113
1114
dcn21_dsc_create(struct dc_context * ctx,uint32_t inst)1115 static struct display_stream_compressor *dcn21_dsc_create(struct dc_context *ctx,
1116 uint32_t inst)
1117 {
1118 struct dcn20_dsc *dsc =
1119 kzalloc_obj(struct dcn20_dsc);
1120
1121 if (!dsc) {
1122 BREAK_TO_DEBUGGER();
1123 return NULL;
1124 }
1125
1126 dsc2_construct(dsc, ctx, inst, &dsc_regs[inst], &dsc_shift, &dsc_mask);
1127 return &dsc->base;
1128 }
1129
dcn21_pp_smu_create(struct dc_context * ctx)1130 static struct pp_smu_funcs *dcn21_pp_smu_create(struct dc_context *ctx)
1131 {
1132 struct pp_smu_funcs *pp_smu = kzalloc_obj(*pp_smu);
1133
1134 if (!pp_smu)
1135 return pp_smu;
1136
1137 dm_pp_get_funcs(ctx, pp_smu);
1138
1139 if (pp_smu->ctx.ver != PP_SMU_VER_RN)
1140 pp_smu = memset(pp_smu, 0, sizeof(struct pp_smu_funcs));
1141
1142
1143 return pp_smu;
1144 }
1145
dcn21_pp_smu_destroy(struct pp_smu_funcs ** pp_smu)1146 static void dcn21_pp_smu_destroy(struct pp_smu_funcs **pp_smu)
1147 {
1148 if (pp_smu && *pp_smu) {
1149 kfree(*pp_smu);
1150 *pp_smu = NULL;
1151 }
1152 }
1153
dcn21_create_audio(struct dc_context * ctx,unsigned int inst)1154 static struct audio *dcn21_create_audio(
1155 struct dc_context *ctx, unsigned int inst)
1156 {
1157 return dce_audio_create(ctx, inst,
1158 &audio_regs[inst], &audio_shift, &audio_mask);
1159 }
1160
1161 static struct dc_cap_funcs cap_funcs = {
1162 .get_dcc_compression_cap = dcn20_get_dcc_compression_cap
1163 };
1164
dcn21_stream_encoder_create(enum engine_id eng_id,struct dc_context * ctx)1165 static struct stream_encoder *dcn21_stream_encoder_create(enum engine_id eng_id,
1166 struct dc_context *ctx)
1167 {
1168 struct dcn10_stream_encoder *enc1 =
1169 kzalloc_obj(struct dcn10_stream_encoder);
1170
1171 if (!enc1)
1172 return NULL;
1173
1174 dcn20_stream_encoder_construct(enc1, ctx, ctx->dc_bios, eng_id,
1175 &stream_enc_regs[eng_id],
1176 &se_shift, &se_mask);
1177
1178 return &enc1->base;
1179 }
1180
1181 static const struct dce_hwseq_registers hwseq_reg = {
1182 HWSEQ_DCN21_REG_LIST()
1183 };
1184
1185 static const struct dce_hwseq_shift hwseq_shift = {
1186 HWSEQ_DCN21_MASK_SH_LIST(__SHIFT)
1187 };
1188
1189 static const struct dce_hwseq_mask hwseq_mask = {
1190 HWSEQ_DCN21_MASK_SH_LIST(_MASK)
1191 };
1192
dcn21_hwseq_create(struct dc_context * ctx)1193 static struct dce_hwseq *dcn21_hwseq_create(
1194 struct dc_context *ctx)
1195 {
1196 struct dce_hwseq *hws = kzalloc_obj(struct dce_hwseq);
1197
1198 if (hws) {
1199 hws->ctx = ctx;
1200 hws->regs = &hwseq_reg;
1201 hws->shifts = &hwseq_shift;
1202 hws->masks = &hwseq_mask;
1203 hws->wa.DEGVIDCN21 = true;
1204 hws->wa.disallow_self_refresh_during_multi_plane_transition = true;
1205 }
1206 return hws;
1207 }
1208
1209 static const struct resource_create_funcs res_create_funcs = {
1210 .read_dce_straps = read_dce_straps,
1211 .create_audio = dcn21_create_audio,
1212 .create_stream_encoder = dcn21_stream_encoder_create,
1213 .create_hwseq = dcn21_hwseq_create,
1214 };
1215
1216 static const struct encoder_feature_support link_enc_feature = {
1217 .max_hdmi_deep_color = COLOR_DEPTH_121212,
1218 .max_hdmi_pixel_clock = 600000,
1219 .hdmi_ycbcr420_supported = true,
1220 .dp_ycbcr420_supported = true,
1221 .fec_supported = true,
1222 .flags.bits.IS_HBR2_CAPABLE = true,
1223 .flags.bits.IS_HBR3_CAPABLE = true,
1224 .flags.bits.IS_TPS3_CAPABLE = true,
1225 .flags.bits.IS_TPS4_CAPABLE = true
1226 };
1227
1228
1229 #define link_regs(id, phyid)\
1230 [id] = {\
1231 LE_DCN2_REG_LIST(id), \
1232 UNIPHY_DCN2_REG_LIST(phyid), \
1233 DPCS_DCN21_REG_LIST(id), \
1234 SRI(DP_DPHY_INTERNAL_CTRL, DP, id) \
1235 }
1236
1237 static const struct dcn10_link_enc_registers link_enc_regs[] = {
1238 link_regs(0, A),
1239 link_regs(1, B),
1240 link_regs(2, C),
1241 link_regs(3, D),
1242 link_regs(4, E),
1243 };
1244
1245 static const struct dce_panel_cntl_registers panel_cntl_regs[] = {
1246 { DCN_PANEL_CNTL_REG_LIST() }
1247 };
1248
1249 static const struct dce_panel_cntl_shift panel_cntl_shift = {
1250 DCE_PANEL_CNTL_MASK_SH_LIST(__SHIFT)
1251 };
1252
1253 static const struct dce_panel_cntl_mask panel_cntl_mask = {
1254 DCE_PANEL_CNTL_MASK_SH_LIST(_MASK)
1255 };
1256
1257 #define aux_regs(id)\
1258 [id] = {\
1259 DCN2_AUX_REG_LIST(id)\
1260 }
1261
1262 static const struct dcn10_link_enc_aux_registers link_enc_aux_regs[] = {
1263 aux_regs(0),
1264 aux_regs(1),
1265 aux_regs(2),
1266 aux_regs(3),
1267 aux_regs(4)
1268 };
1269
1270 #define hpd_regs(id)\
1271 [id] = {\
1272 HPD_REG_LIST(id)\
1273 }
1274
1275 static const struct dcn10_link_enc_hpd_registers link_enc_hpd_regs[] = {
1276 hpd_regs(0),
1277 hpd_regs(1),
1278 hpd_regs(2),
1279 hpd_regs(3),
1280 hpd_regs(4)
1281 };
1282
1283 static const struct dcn10_link_enc_shift le_shift = {
1284 LINK_ENCODER_MASK_SH_LIST_DCN20(__SHIFT),\
1285 DPCS_DCN21_MASK_SH_LIST(__SHIFT)
1286 };
1287
1288 static const struct dcn10_link_enc_mask le_mask = {
1289 LINK_ENCODER_MASK_SH_LIST_DCN20(_MASK),\
1290 DPCS_DCN21_MASK_SH_LIST(_MASK)
1291 };
1292
map_transmitter_id_to_phy_instance(enum transmitter transmitter)1293 static int map_transmitter_id_to_phy_instance(
1294 enum transmitter transmitter)
1295 {
1296 switch (transmitter) {
1297 case TRANSMITTER_UNIPHY_A:
1298 return 0;
1299 break;
1300 case TRANSMITTER_UNIPHY_B:
1301 return 1;
1302 break;
1303 case TRANSMITTER_UNIPHY_C:
1304 return 2;
1305 break;
1306 case TRANSMITTER_UNIPHY_D:
1307 return 3;
1308 break;
1309 case TRANSMITTER_UNIPHY_E:
1310 return 4;
1311 break;
1312 default:
1313 ASSERT(0);
1314 return 0;
1315 }
1316 }
1317
dcn21_link_encoder_create(struct dc_context * ctx,const struct encoder_init_data * enc_init_data)1318 static struct link_encoder *dcn21_link_encoder_create(
1319 struct dc_context *ctx,
1320 const struct encoder_init_data *enc_init_data)
1321 {
1322 struct dcn21_link_encoder *enc21 =
1323 kzalloc_obj(struct dcn21_link_encoder);
1324 int link_regs_id;
1325
1326 if (!enc21 || enc_init_data->hpd_source >= ARRAY_SIZE(link_enc_hpd_regs))
1327 return NULL;
1328
1329 link_regs_id =
1330 map_transmitter_id_to_phy_instance(enc_init_data->transmitter);
1331
1332 dcn21_link_encoder_construct(enc21,
1333 enc_init_data,
1334 &link_enc_feature,
1335 &link_enc_regs[link_regs_id],
1336 &link_enc_aux_regs[enc_init_data->channel - 1],
1337 &link_enc_hpd_regs[enc_init_data->hpd_source],
1338 &le_shift,
1339 &le_mask);
1340
1341 return &enc21->enc10.base;
1342 }
1343
dcn21_panel_cntl_create(const struct panel_cntl_init_data * init_data)1344 static struct panel_cntl *dcn21_panel_cntl_create(const struct panel_cntl_init_data *init_data)
1345 {
1346 struct dce_panel_cntl *panel_cntl =
1347 kzalloc_obj(struct dce_panel_cntl);
1348
1349 if (!panel_cntl)
1350 return NULL;
1351
1352 dce_panel_cntl_construct(panel_cntl,
1353 init_data,
1354 &panel_cntl_regs[init_data->inst],
1355 &panel_cntl_shift,
1356 &panel_cntl_mask);
1357
1358 return &panel_cntl->base;
1359 }
1360
dcn21_get_panel_config_defaults(struct dc_panel_config * panel_config)1361 static void dcn21_get_panel_config_defaults(struct dc_panel_config *panel_config)
1362 {
1363 *panel_config = panel_config_defaults;
1364 }
1365
1366 #define CTX ctx
1367
1368 #define REG(reg_name) \
1369 (DCN_BASE.instance[0].segment[mm ## reg_name ## _BASE_IDX] + mm ## reg_name)
1370
read_pipe_fuses(struct dc_context * ctx)1371 static uint32_t read_pipe_fuses(struct dc_context *ctx)
1372 {
1373 uint32_t value = REG_READ(CC_DC_PIPE_DIS);
1374 /* RV1 support max 4 pipes */
1375 value = value & 0xf;
1376 return value;
1377 }
1378
dcn21_patch_unknown_plane_state(struct dc_plane_state * plane_state)1379 static enum dc_status dcn21_patch_unknown_plane_state(struct dc_plane_state *plane_state)
1380 {
1381 if (plane_state->ctx->dc->debug.disable_dcc == DCC_ENABLE) {
1382 plane_state->dcc.enable = 1;
1383 /* align to our worst case block width */
1384 plane_state->dcc.meta_pitch = ((plane_state->src_rect.width + 1023) / 1024) * 1024;
1385 }
1386
1387 return dcn20_patch_unknown_plane_state(plane_state);
1388 }
1389
1390 static const struct resource_funcs dcn21_res_pool_funcs = {
1391 .destroy = dcn21_destroy_resource_pool,
1392 .link_enc_create = dcn21_link_encoder_create,
1393 .panel_cntl_create = dcn21_panel_cntl_create,
1394 .validate_bandwidth = dcn21_validate_bandwidth,
1395 .populate_dml_pipes = dcn21_populate_dml_pipes_from_context,
1396 .add_stream_to_ctx = dcn20_add_stream_to_ctx,
1397 .add_dsc_to_stream_resource = dcn20_add_dsc_to_stream_resource,
1398 .remove_stream_from_ctx = dcn20_remove_stream_from_ctx,
1399 .acquire_free_pipe_as_secondary_dpp_pipe = dcn20_acquire_free_pipe_for_layer,
1400 .release_pipe = dcn20_release_pipe,
1401 .populate_dml_writeback_from_context = dcn20_populate_dml_writeback_from_context,
1402 .patch_unknown_plane_state = dcn21_patch_unknown_plane_state,
1403 .set_mcif_arb_params = dcn20_set_mcif_arb_params,
1404 .find_first_free_match_stream_enc_for_link = dcn10_find_first_free_match_stream_enc_for_link,
1405 .update_bw_bounding_box = dcn21_update_bw_bounding_box,
1406 .get_panel_config_defaults = dcn21_get_panel_config_defaults,
1407 .get_vstartup_for_pipe = dcn10_get_vstartup_for_pipe
1408 };
1409
dcn21_resource_construct(uint8_t num_virtual_links,struct dc * dc,struct dcn21_resource_pool * pool)1410 static bool dcn21_resource_construct(
1411 uint8_t num_virtual_links,
1412 struct dc *dc,
1413 struct dcn21_resource_pool *pool)
1414 {
1415 int i, j;
1416 struct dc_context *ctx = dc->ctx;
1417 struct irq_service_init_data init_data;
1418 uint32_t pipe_fuses = read_pipe_fuses(ctx);
1419 uint32_t num_pipes = 0;
1420
1421 ctx->dc_bios->regs = &bios_regs;
1422
1423 pool->base.res_cap = &res_cap_rn;
1424
1425 pool->base.funcs = &dcn21_res_pool_funcs;
1426
1427 /*************************************************
1428 * Resource + asic cap harcoding *
1429 *************************************************/
1430 pool->base.underlay_pipe_index = NO_UNDERLAY_PIPE;
1431
1432 /* max pipe num for ASIC before check pipe fuses */
1433 pool->base.pipe_count = pool->base.res_cap->num_timing_generator;
1434
1435 dc->caps.max_downscale_ratio = 200;
1436 dc->caps.i2c_speed_in_khz = 100;
1437 dc->caps.i2c_speed_in_khz_hdcp = 5; /*1.4 w/a applied by default*/
1438 dc->caps.max_cursor_size = 256;
1439 dc->caps.min_horizontal_blanking_period = 80;
1440 dc->caps.dmdata_alloc_size = 2048;
1441
1442 dc->caps.max_slave_planes = 3;
1443 dc->caps.max_slave_yuv_planes = 3;
1444 dc->caps.max_slave_rgb_planes = 3;
1445 dc->caps.post_blend_color_processing = true;
1446 dc->caps.force_dp_tps4_for_cp2520 = true;
1447 dc->caps.extended_aux_timeout_support = true;
1448 dc->caps.dmcub_support = true;
1449 dc->caps.is_apu = true;
1450
1451 /* Color pipeline capabilities */
1452 dc->caps.color.dpp.dcn_arch = 1;
1453 dc->caps.color.dpp.input_lut_shared = 0;
1454 dc->caps.color.dpp.icsc = 1;
1455 dc->caps.color.dpp.dgam_ram = 1;
1456 dc->caps.color.dpp.dgam_rom_caps.srgb = 1;
1457 dc->caps.color.dpp.dgam_rom_caps.bt2020 = 1;
1458 dc->caps.color.dpp.dgam_rom_caps.gamma2_2 = 0;
1459 dc->caps.color.dpp.dgam_rom_caps.pq = 0;
1460 dc->caps.color.dpp.dgam_rom_caps.hlg = 0;
1461 dc->caps.color.dpp.post_csc = 0;
1462 dc->caps.color.dpp.gamma_corr = 0;
1463 dc->caps.color.dpp.dgam_rom_for_yuv = 1;
1464
1465 dc->caps.color.dpp.hw_3d_lut = 1;
1466 dc->caps.color.dpp.ogam_ram = 1;
1467 // no OGAM ROM on DCN2
1468 dc->caps.color.dpp.ogam_rom_caps.srgb = 0;
1469 dc->caps.color.dpp.ogam_rom_caps.bt2020 = 0;
1470 dc->caps.color.dpp.ogam_rom_caps.gamma2_2 = 0;
1471 dc->caps.color.dpp.ogam_rom_caps.pq = 0;
1472 dc->caps.color.dpp.ogam_rom_caps.hlg = 0;
1473 dc->caps.color.dpp.ocsc = 0;
1474
1475 dc->caps.color.mpc.gamut_remap = 0;
1476 dc->caps.color.mpc.num_3dluts = 0;
1477 dc->caps.color.mpc.shared_3d_lut = 0;
1478 dc->caps.color.mpc.ogam_ram = 1;
1479 dc->caps.color.mpc.ogam_rom_caps.srgb = 0;
1480 dc->caps.color.mpc.ogam_rom_caps.bt2020 = 0;
1481 dc->caps.color.mpc.ogam_rom_caps.gamma2_2 = 0;
1482 dc->caps.color.mpc.ogam_rom_caps.pq = 0;
1483 dc->caps.color.mpc.ogam_rom_caps.hlg = 0;
1484 dc->caps.color.mpc.ocsc = 1;
1485
1486 dc->caps.dp_hdmi21_pcon_support = true;
1487 dc->check_config = config_defaults;
1488
1489 if (dc->ctx->dce_environment == DCE_ENV_PRODUCTION_DRV)
1490 dc->debug = debug_defaults_drv;
1491
1492 // Init the vm_helper
1493 if (dc->vm_helper)
1494 vm_helper_init(dc->vm_helper, 16);
1495
1496 /*************************************************
1497 * Create resources *
1498 *************************************************/
1499
1500 pool->base.clock_sources[DCN20_CLK_SRC_PLL0] =
1501 dcn21_clock_source_create(ctx, ctx->dc_bios,
1502 CLOCK_SOURCE_COMBO_PHY_PLL0,
1503 &clk_src_regs[0], false);
1504 pool->base.clock_sources[DCN20_CLK_SRC_PLL1] =
1505 dcn21_clock_source_create(ctx, ctx->dc_bios,
1506 CLOCK_SOURCE_COMBO_PHY_PLL1,
1507 &clk_src_regs[1], false);
1508 pool->base.clock_sources[DCN20_CLK_SRC_PLL2] =
1509 dcn21_clock_source_create(ctx, ctx->dc_bios,
1510 CLOCK_SOURCE_COMBO_PHY_PLL2,
1511 &clk_src_regs[2], false);
1512 pool->base.clock_sources[DCN20_CLK_SRC_PLL3] =
1513 dcn21_clock_source_create(ctx, ctx->dc_bios,
1514 CLOCK_SOURCE_COMBO_PHY_PLL3,
1515 &clk_src_regs[3], false);
1516 pool->base.clock_sources[DCN20_CLK_SRC_PLL4] =
1517 dcn21_clock_source_create(ctx, ctx->dc_bios,
1518 CLOCK_SOURCE_COMBO_PHY_PLL4,
1519 &clk_src_regs[4], false);
1520
1521 pool->base.clk_src_count = DCN20_CLK_SRC_TOTAL_DCN21;
1522
1523 /* todo: not reuse phy_pll registers */
1524 pool->base.dp_clock_source =
1525 dcn21_clock_source_create(ctx, ctx->dc_bios,
1526 CLOCK_SOURCE_ID_DP_DTO,
1527 &clk_src_regs[0], true);
1528
1529 for (i = 0; i < pool->base.clk_src_count; i++) {
1530 if (pool->base.clock_sources[i] == NULL) {
1531 dm_error("DC: failed to create clock sources!\n");
1532 BREAK_TO_DEBUGGER();
1533 goto create_fail;
1534 }
1535 }
1536
1537 pool->base.dccg = dccg21_create(ctx, &dccg_regs, &dccg_shift, &dccg_mask);
1538 if (pool->base.dccg == NULL) {
1539 dm_error("DC: failed to create dccg!\n");
1540 BREAK_TO_DEBUGGER();
1541 goto create_fail;
1542 }
1543
1544 if (!dc->config.disable_dmcu) {
1545 pool->base.dmcu = dcn21_dmcu_create(ctx,
1546 &dmcu_regs,
1547 &dmcu_shift,
1548 &dmcu_mask);
1549 if (pool->base.dmcu == NULL) {
1550 dm_error("DC: failed to create dmcu!\n");
1551 BREAK_TO_DEBUGGER();
1552 goto create_fail;
1553 }
1554
1555 dc->debug.dmub_command_table = false;
1556 }
1557
1558 if (dc->config.disable_dmcu) {
1559 pool->base.psr = dmub_psr_create(ctx);
1560
1561 if (pool->base.psr == NULL) {
1562 dm_error("DC: failed to create psr obj!\n");
1563 BREAK_TO_DEBUGGER();
1564 goto create_fail;
1565 }
1566 }
1567
1568 if (dc->config.disable_dmcu)
1569 pool->base.abm = dmub_abm_create(ctx,
1570 &abm_regs,
1571 &abm_shift,
1572 &abm_mask);
1573 else
1574 pool->base.abm = dce_abm_create(ctx,
1575 &abm_regs,
1576 &abm_shift,
1577 &abm_mask);
1578
1579 pool->base.pp_smu = dcn21_pp_smu_create(ctx);
1580
1581 num_pipes = dcn2_1_ip.max_num_dpp;
1582
1583 for (i = 0; i < dcn2_1_ip.max_num_dpp; i++)
1584 if (pipe_fuses & 1 << i)
1585 num_pipes--;
1586 dcn2_1_ip.max_num_dpp = num_pipes;
1587 dcn2_1_ip.max_num_otg = num_pipes;
1588
1589 dml_init_instance(&dc->dml, &dcn2_1_soc, &dcn2_1_ip, DML_PROJECT_DCN21);
1590
1591 init_data.ctx = dc->ctx;
1592 pool->base.irqs = dal_irq_service_dcn21_create(&init_data);
1593 if (!pool->base.irqs)
1594 goto create_fail;
1595
1596 j = 0;
1597 /* mem input -> ipp -> dpp -> opp -> TG */
1598 for (i = 0; i < pool->base.pipe_count; i++) {
1599 /* if pipe is disabled, skip instance of HW pipe,
1600 * i.e, skip ASIC register instance
1601 */
1602 if ((pipe_fuses & (1 << i)) != 0)
1603 continue;
1604
1605 pool->base.hubps[j] = dcn21_hubp_create(ctx, i);
1606 if (pool->base.hubps[j] == NULL) {
1607 BREAK_TO_DEBUGGER();
1608 dm_error(
1609 "DC: failed to create memory input!\n");
1610 goto create_fail;
1611 }
1612
1613 pool->base.ipps[j] = dcn21_ipp_create(ctx, i);
1614 if (pool->base.ipps[j] == NULL) {
1615 BREAK_TO_DEBUGGER();
1616 dm_error(
1617 "DC: failed to create input pixel processor!\n");
1618 goto create_fail;
1619 }
1620
1621 pool->base.dpps[j] = dcn21_dpp_create(ctx, i);
1622 if (pool->base.dpps[j] == NULL) {
1623 BREAK_TO_DEBUGGER();
1624 dm_error(
1625 "DC: failed to create dpps!\n");
1626 goto create_fail;
1627 }
1628
1629 pool->base.opps[j] = dcn21_opp_create(ctx, i);
1630 if (pool->base.opps[j] == NULL) {
1631 BREAK_TO_DEBUGGER();
1632 dm_error(
1633 "DC: failed to create output pixel processor!\n");
1634 goto create_fail;
1635 }
1636
1637 pool->base.timing_generators[j] = dcn21_timing_generator_create(
1638 ctx, i);
1639 if (pool->base.timing_generators[j] == NULL) {
1640 BREAK_TO_DEBUGGER();
1641 dm_error("DC: failed to create tg!\n");
1642 goto create_fail;
1643 }
1644 j++;
1645 }
1646
1647 for (i = 0; i < pool->base.res_cap->num_ddc; i++) {
1648 pool->base.engines[i] = dcn21_aux_engine_create(ctx, i);
1649 if (pool->base.engines[i] == NULL) {
1650 BREAK_TO_DEBUGGER();
1651 dm_error(
1652 "DC:failed to create aux engine!!\n");
1653 goto create_fail;
1654 }
1655 pool->base.hw_i2cs[i] = dcn21_i2c_hw_create(ctx, i);
1656 if (pool->base.hw_i2cs[i] == NULL) {
1657 BREAK_TO_DEBUGGER();
1658 dm_error(
1659 "DC:failed to create hw i2c!!\n");
1660 goto create_fail;
1661 }
1662 pool->base.sw_i2cs[i] = NULL;
1663 }
1664
1665 pool->base.timing_generator_count = j;
1666 pool->base.pipe_count = j;
1667 pool->base.mpcc_count = j;
1668
1669 pool->base.mpc = dcn21_mpc_create(ctx);
1670 if (pool->base.mpc == NULL) {
1671 BREAK_TO_DEBUGGER();
1672 dm_error("DC: failed to create mpc!\n");
1673 goto create_fail;
1674 }
1675
1676 pool->base.hubbub = dcn21_hubbub_create(ctx);
1677 if (pool->base.hubbub == NULL) {
1678 BREAK_TO_DEBUGGER();
1679 dm_error("DC: failed to create hubbub!\n");
1680 goto create_fail;
1681 }
1682
1683 /* DIO */
1684 pool->base.dio = dcn21_dio_create(ctx);
1685 if (pool->base.dio == NULL) {
1686 BREAK_TO_DEBUGGER();
1687 dm_error("DC: failed to create dio!\n");
1688 goto create_fail;
1689 }
1690
1691 for (i = 0; i < pool->base.res_cap->num_dsc; i++) {
1692 pool->base.dscs[i] = dcn21_dsc_create(ctx, i);
1693 if (pool->base.dscs[i] == NULL) {
1694 BREAK_TO_DEBUGGER();
1695 dm_error("DC: failed to create display stream compressor %d!\n", i);
1696 goto create_fail;
1697 }
1698 }
1699
1700 if (!dcn20_dwbc_create(ctx, &pool->base)) {
1701 BREAK_TO_DEBUGGER();
1702 dm_error("DC: failed to create dwbc!\n");
1703 goto create_fail;
1704 }
1705 if (!dcn20_mmhubbub_create(ctx, &pool->base)) {
1706 BREAK_TO_DEBUGGER();
1707 dm_error("DC: failed to create mcif_wb!\n");
1708 goto create_fail;
1709 }
1710
1711 if (!resource_construct(num_virtual_links, dc, &pool->base,
1712 &res_create_funcs))
1713 goto create_fail;
1714
1715 dcn21_hw_sequencer_construct(dc);
1716
1717 dc->caps.max_planes = pool->base.pipe_count;
1718
1719 for (i = 0; i < dc->caps.max_planes; ++i)
1720 dc->caps.planes[i] = plane_cap;
1721
1722 dc->caps.max_odm_combine_factor = 2;
1723
1724 dc->cap_funcs = cap_funcs;
1725
1726 return true;
1727
1728 create_fail:
1729
1730 dcn21_resource_destruct(pool);
1731
1732 return false;
1733 }
1734
dcn21_create_resource_pool(const struct dc_init_data * init_data,struct dc * dc)1735 struct resource_pool *dcn21_create_resource_pool(
1736 const struct dc_init_data *init_data,
1737 struct dc *dc)
1738 {
1739 struct dcn21_resource_pool *pool =
1740 kzalloc_obj(struct dcn21_resource_pool);
1741
1742 if (!pool)
1743 return NULL;
1744
1745 if (dcn21_resource_construct(init_data->num_virtual_links, dc, pool))
1746 return &pool->base;
1747
1748 BREAK_TO_DEBUGGER();
1749 kfree(pool);
1750 return NULL;
1751 }
1752