1 /*
2 * Copyright 2016 Advanced Micro Devices, Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
21 *
22 * Authors: AMD
23 *
24 */
25
26 #include "dm_services.h"
27 #include "dc.h"
28
29 #include "dcn201/dcn201_init.h"
30 #include "dml/dcn20/dcn20_fpu.h"
31 #include "resource.h"
32 #include "include/irq_service_interface.h"
33 #include "dcn201_resource.h"
34
35 #include "dcn20/dcn20_resource.h"
36
37 #include "dcn10/dcn10_hubp.h"
38 #include "dcn10/dcn10_ipp.h"
39 #include "dcn201/dcn201_mpc.h"
40 #include "dcn201/dcn201_hubp.h"
41 #include "irq/dcn201/irq_service_dcn201.h"
42 #include "dcn201/dcn201_dpp.h"
43 #include "dcn201/dcn201_hubbub.h"
44 #include "dcn201/dcn201_dccg.h"
45 #include "dcn201/dcn201_optc.h"
46 #include "dcn201/dcn201_hwseq.h"
47 #include "dce110/dce110_hwseq.h"
48 #include "dcn201/dcn201_opp.h"
49 #include "dcn201/dcn201_link_encoder.h"
50 #include "dcn20/dcn20_stream_encoder.h"
51 #include "dce/dce_clock_source.h"
52 #include "dce/dce_audio.h"
53 #include "dce/dce_hwseq.h"
54 #include "dio/virtual/virtual_stream_encoder.h"
55 #include "dce110/dce110_resource.h"
56 #include "dce/dce_aux.h"
57 #include "dce/dce_i2c.h"
58 #include "dcn10/dcn10_resource.h"
59 #include "dio/dcn10/dcn10_dio.h"
60
61 #include "cyan_skillfish_ip_offset.h"
62
63 #include "dcn/dcn_2_0_1_offset.h"
64 #include "dcn/dcn_2_0_1_sh_mask.h"
65 #include "dpcs/dpcs_2_0_3_offset.h"
66 #include "dpcs/dpcs_2_0_3_sh_mask.h"
67
68 #include "mmhub/mmhub_2_0_0_offset.h"
69 #include "mmhub/mmhub_2_0_0_sh_mask.h"
70 #include "nbio/nbio_7_4_offset.h"
71
72 #include "reg_helper.h"
73
74 #define MIN_DISP_CLK_KHZ 100000
75 #define MIN_DPP_CLK_KHZ 100000
76
77 static struct _vcs_dpi_ip_params_st dcn201_ip = {
78 .gpuvm_enable = 0,
79 .hostvm_enable = 0,
80 .gpuvm_max_page_table_levels = 4,
81 .hostvm_max_page_table_levels = 4,
82 .hostvm_cached_page_table_levels = 0,
83 .pte_group_size_bytes = 2048,
84 .rob_buffer_size_kbytes = 168,
85 .det_buffer_size_kbytes = 164,
86 .dpte_buffer_size_in_pte_reqs_luma = 84,
87 .pde_proc_buffer_size_64k_reqs = 48,
88 .dpp_output_buffer_pixels = 2560,
89 .opp_output_buffer_lines = 1,
90 .pixel_chunk_size_kbytes = 8,
91 .pte_chunk_size_kbytes = 2,
92 .meta_chunk_size_kbytes = 2,
93 .writeback_chunk_size_kbytes = 2,
94 .line_buffer_size_bits = 789504,
95 .is_line_buffer_bpp_fixed = 0,
96 .line_buffer_fixed_bpp = 0,
97 .dcc_supported = true,
98 .max_line_buffer_lines = 12,
99 .writeback_luma_buffer_size_kbytes = 12,
100 .writeback_chroma_buffer_size_kbytes = 8,
101 .writeback_chroma_line_buffer_width_pixels = 4,
102 .writeback_max_hscl_ratio = 1,
103 .writeback_max_vscl_ratio = 1,
104 .writeback_min_hscl_ratio = 1,
105 .writeback_min_vscl_ratio = 1,
106 .writeback_max_hscl_taps = 12,
107 .writeback_max_vscl_taps = 12,
108 .writeback_line_buffer_luma_buffer_size = 0,
109 .writeback_line_buffer_chroma_buffer_size = 9600,
110 .cursor_buffer_size = 8,
111 .cursor_chunk_size = 2,
112 .max_num_otg = 2,
113 .max_num_dpp = 4,
114 .max_num_wb = 0,
115 .max_dchub_pscl_bw_pix_per_clk = 4,
116 .max_pscl_lb_bw_pix_per_clk = 2,
117 .max_lb_vscl_bw_pix_per_clk = 4,
118 .max_vscl_hscl_bw_pix_per_clk = 4,
119 .max_hscl_ratio = 8,
120 .max_vscl_ratio = 8,
121 .hscl_mults = 4,
122 .vscl_mults = 4,
123 .max_hscl_taps = 8,
124 .max_vscl_taps = 8,
125 .dispclk_ramp_margin_percent = 1,
126 .underscan_factor = 1.10,
127 .min_vblank_lines = 30,
128 .dppclk_delay_subtotal = 77,
129 .dppclk_delay_scl_lb_only = 16,
130 .dppclk_delay_scl = 50,
131 .dppclk_delay_cnvc_formatter = 8,
132 .dppclk_delay_cnvc_cursor = 6,
133 .dispclk_delay_subtotal = 87,
134 .dcfclk_cstate_latency = 10,
135 .max_inter_dcn_tile_repeaters = 8,
136 .number_of_cursors = 1,
137 };
138
139 static struct _vcs_dpi_soc_bounding_box_st dcn201_soc = {
140 .clock_limits = {
141 {
142 .state = 0,
143 .dscclk_mhz = 400.0,
144 .dcfclk_mhz = 1000.0,
145 .fabricclk_mhz = 200.0,
146 .dispclk_mhz = 300.0,
147 .dppclk_mhz = 300.0,
148 .phyclk_mhz = 810.0,
149 .socclk_mhz = 1254.0,
150 .dram_speed_mts = 2000.0,
151 },
152 {
153 .state = 1,
154 .dscclk_mhz = 400.0,
155 .dcfclk_mhz = 1000.0,
156 .fabricclk_mhz = 250.0,
157 .dispclk_mhz = 1200.0,
158 .dppclk_mhz = 1200.0,
159 .phyclk_mhz = 810.0,
160 .socclk_mhz = 1254.0,
161 .dram_speed_mts = 3600.0,
162 },
163 {
164 .state = 2,
165 .dscclk_mhz = 400.0,
166 .dcfclk_mhz = 1000.0,
167 .fabricclk_mhz = 750.0,
168 .dispclk_mhz = 1200.0,
169 .dppclk_mhz = 1200.0,
170 .phyclk_mhz = 810.0,
171 .socclk_mhz = 1254.0,
172 .dram_speed_mts = 6800.0,
173 },
174 {
175 .state = 3,
176 .dscclk_mhz = 400.0,
177 .dcfclk_mhz = 1000.0,
178 .fabricclk_mhz = 250.0,
179 .dispclk_mhz = 1200.0,
180 .dppclk_mhz = 1200.0,
181 .phyclk_mhz = 810.0,
182 .socclk_mhz = 1254.0,
183 .dram_speed_mts = 14000.0,
184 },
185 /* state4 is not an actual state, just defines unsupported for dml*/
186 {
187 .state = 4,
188 .dscclk_mhz = 400.0,
189 .dcfclk_mhz = 1000.0,
190 .fabricclk_mhz = 750.0,
191 .dispclk_mhz = 1200.0,
192 .dppclk_mhz = 1200.0,
193 .phyclk_mhz = 810.0,
194 .socclk_mhz = 1254.0,
195 .dram_speed_mts = 14000.0,
196 }
197 },
198 .num_states = 4,
199 .sr_exit_time_us = 9.0,
200 .sr_enter_plus_exit_time_us = 11.0,
201 .urgent_latency_us = 4.0,
202 .urgent_latency_pixel_data_only_us = 4.0,
203 .urgent_latency_pixel_mixed_with_vm_data_us = 4.0,
204 .urgent_latency_vm_data_only_us = 4.0,
205 .urgent_out_of_order_return_per_channel_pixel_only_bytes = 256,
206 .urgent_out_of_order_return_per_channel_pixel_and_vm_bytes = 256,
207 .urgent_out_of_order_return_per_channel_vm_only_bytes = 256,
208 .pct_ideal_dram_sdp_bw_after_urgent_pixel_only = 80.0,
209 .pct_ideal_dram_sdp_bw_after_urgent_pixel_and_vm = 80.0,
210 .pct_ideal_dram_sdp_bw_after_urgent_vm_only = 80.0,
211 .max_avg_sdp_bw_use_normal_percent = 80.0,
212 .max_avg_dram_bw_use_normal_percent = 69.0,
213 .writeback_latency_us = 12.0,
214 .ideal_dram_bw_after_urgent_percent = 80.0,
215 .max_request_size_bytes = 256,
216 .dram_channel_width_bytes = 2,
217 .fabric_datapath_to_dcn_data_return_bytes = 64,
218 .dcn_downspread_percent = 0.3,
219 .downspread_percent = 0.3,
220 .dram_page_open_time_ns = 50.0,
221 .dram_rw_turnaround_time_ns = 17.5,
222 .dram_return_buffer_per_channel_bytes = 8192,
223 .round_trip_ping_latency_dcfclk_cycles = 128,
224 .urgent_out_of_order_return_per_channel_bytes = 256,
225 .channel_interleave_bytes = 256,
226 .num_banks = 8,
227 .num_chans = 16,
228 .vmm_page_size_bytes = 4096,
229 .dram_clock_change_latency_us = 250.0,
230 .writeback_dram_clock_change_latency_us = 23.0,
231 .return_bus_width_bytes = 64,
232 .dispclk_dppclk_vco_speed_mhz = 3000,
233 .use_urgent_burst_bw = 0,
234 };
235
236 enum dcn20_clk_src_array_id {
237 DCN20_CLK_SRC_PLL0,
238 DCN20_CLK_SRC_PLL1,
239 DCN20_CLK_SRC_TOTAL_DCN201
240 };
241
242 /* begin *********************
243 * macros to expend register list macro defined in HW object header file */
244
245 /* DCN */
246
247 #undef BASE_INNER
248 #define BASE_INNER(seg) DMU_BASE__INST0_SEG ## seg
249
250 #define BASE(seg) BASE_INNER(seg)
251
252 #define SR(reg_name)\
253 .reg_name = BASE(mm ## reg_name ## _BASE_IDX) + \
254 mm ## reg_name
255
256 #define SRI(reg_name, block, id)\
257 .reg_name = BASE(mm ## block ## id ## _ ## reg_name ## _BASE_IDX) + \
258 mm ## block ## id ## _ ## reg_name
259
260 #define SRIR(var_name, reg_name, block, id)\
261 .var_name = BASE(mm ## block ## id ## _ ## reg_name ## _BASE_IDX) + \
262 mm ## block ## id ## _ ## reg_name
263
264 #define SRII(reg_name, block, id)\
265 .reg_name[id] = BASE(mm ## block ## id ## _ ## reg_name ## _BASE_IDX) + \
266 mm ## block ## id ## _ ## reg_name
267
268 #define SRI_IX(reg_name, block, id)\
269 .reg_name = ix ## block ## id ## _ ## reg_name
270
271 #define DCCG_SRII(reg_name, block, id)\
272 .block ## _ ## reg_name[id] = BASE(mm ## block ## id ## _ ## reg_name ## _BASE_IDX) + \
273 mm ## block ## id ## _ ## reg_name
274
275 #define VUPDATE_SRII(reg_name, block, id)\
276 .reg_name[id] = BASE(mm ## reg_name ## _ ## block ## id ## _BASE_IDX) + \
277 mm ## reg_name ## _ ## block ## id
278
279 /* NBIO */
280 #define NBIO_BASE_INNER(seg) \
281 NBIO_BASE__INST0_SEG ## seg
282
283 #define NBIO_BASE(seg) \
284 NBIO_BASE_INNER(seg)
285
286 #define NBIO_SR(reg_name)\
287 .reg_name = NBIO_BASE(mm ## reg_name ## _BASE_IDX) + \
288 mm ## reg_name
289
290 /* MMHUB */
291 #define MMHUB_BASE_INNER(seg) \
292 MMHUB_BASE__INST0_SEG ## seg
293
294 #define MMHUB_BASE(seg) \
295 MMHUB_BASE_INNER(seg)
296
297 #define MMHUB_SR(reg_name)\
298 .reg_name = MMHUB_BASE(mmMM ## reg_name ## _BASE_IDX) + \
299 mmMM ## reg_name
300
301 static const struct bios_registers bios_regs = {
302 NBIO_SR(BIOS_SCRATCH_3),
303 NBIO_SR(BIOS_SCRATCH_6)
304 };
305
306 #define clk_src_regs(index, pllid)\
307 [index] = {\
308 CS_COMMON_REG_LIST_DCN201(index, pllid),\
309 }
310
311 static const struct dce110_clk_src_regs clk_src_regs[] = {
312 clk_src_regs(0, A),
313 clk_src_regs(1, B)
314 };
315
316 static const struct dce110_clk_src_shift cs_shift = {
317 CS_COMMON_MASK_SH_LIST_DCN2_0(__SHIFT)
318 };
319
320 static const struct dce110_clk_src_mask cs_mask = {
321 CS_COMMON_MASK_SH_LIST_DCN2_0(_MASK)
322 };
323
324 #define audio_regs(id)\
325 [id] = {\
326 AUD_COMMON_REG_LIST(id)\
327 }
328
329 static const struct dce_audio_registers audio_regs[] = {
330 audio_regs(0),
331 audio_regs(1),
332 };
333
334 #define DCE120_AUD_COMMON_MASK_SH_LIST(mask_sh)\
335 SF(AZF0ENDPOINT0_AZALIA_F0_CODEC_ENDPOINT_INDEX, AZALIA_ENDPOINT_REG_INDEX, mask_sh),\
336 SF(AZF0ENDPOINT0_AZALIA_F0_CODEC_ENDPOINT_DATA, AZALIA_ENDPOINT_REG_DATA, mask_sh),\
337 AUD_COMMON_MASK_SH_LIST_BASE(mask_sh)
338
339 static const struct dce_audio_shift audio_shift = {
340 DCE120_AUD_COMMON_MASK_SH_LIST(__SHIFT)
341 };
342
343 static const struct dce_audio_mask audio_mask = {
344 DCE120_AUD_COMMON_MASK_SH_LIST(_MASK)
345 };
346
347 #define stream_enc_regs(id)\
348 [id] = {\
349 SE_DCN2_REG_LIST(id)\
350 }
351
352 static const struct dcn10_stream_enc_registers stream_enc_regs[] = {
353 stream_enc_regs(0),
354 stream_enc_regs(1)
355 };
356
357 static const struct dcn10_stream_encoder_shift se_shift = {
358 SE_COMMON_MASK_SH_LIST_DCN20(__SHIFT)
359 };
360
361 static const struct dcn10_stream_encoder_mask se_mask = {
362 SE_COMMON_MASK_SH_LIST_DCN20(_MASK)
363 };
364
365 static const struct dce110_aux_registers_shift aux_shift = {
366 DCN_AUX_MASK_SH_LIST(__SHIFT)
367 };
368
369 static const struct dce110_aux_registers_mask aux_mask = {
370 DCN_AUX_MASK_SH_LIST(_MASK)
371 };
372
373 #define aux_regs(id)\
374 [id] = {\
375 DCN2_AUX_REG_LIST(id)\
376 }
377
378 static const struct dcn10_link_enc_aux_registers link_enc_aux_regs[] = {
379 aux_regs(0),
380 aux_regs(1),
381 };
382
383 #define hpd_regs(id)\
384 [id] = {\
385 HPD_REG_LIST(id)\
386 }
387
388 static const struct dcn10_link_enc_hpd_registers link_enc_hpd_regs[] = {
389 hpd_regs(0),
390 hpd_regs(1),
391 };
392
393 #define link_regs(id, phyid)\
394 [id] = {\
395 LE_DCN_COMMON_REG_LIST(id), \
396 UNIPHY_DCN2_REG_LIST(phyid) \
397 }
398
399 static const struct dcn10_link_enc_registers link_enc_regs[] = {
400 link_regs(0, A),
401 link_regs(1, B),
402 };
403
404 #define LINK_ENCODER_MASK_SH_LIST_DCN201(mask_sh)\
405 LINK_ENCODER_MASK_SH_LIST_DCN20(mask_sh)
406
407 static const struct dcn10_link_enc_shift le_shift = {
408 LINK_ENCODER_MASK_SH_LIST_DCN201(__SHIFT)
409 };
410
411 static const struct dcn10_link_enc_mask le_mask = {
412 LINK_ENCODER_MASK_SH_LIST_DCN201(_MASK)
413 };
414
415 #define ipp_regs(id)\
416 [id] = {\
417 IPP_REG_LIST_DCN201(id),\
418 }
419
420 static const struct dcn10_ipp_registers ipp_regs[] = {
421 ipp_regs(0),
422 ipp_regs(1),
423 ipp_regs(2),
424 ipp_regs(3),
425 };
426
427 static const struct dcn10_ipp_shift ipp_shift = {
428 IPP_MASK_SH_LIST_DCN201(__SHIFT)
429 };
430
431 static const struct dcn10_ipp_mask ipp_mask = {
432 IPP_MASK_SH_LIST_DCN201(_MASK)
433 };
434
435 #define opp_regs(id)\
436 [id] = {\
437 OPP_REG_LIST_DCN201(id),\
438 }
439
440 static const struct dcn201_opp_registers opp_regs[] = {
441 opp_regs(0),
442 opp_regs(1),
443 };
444
445 static const struct dcn201_opp_shift opp_shift = {
446 OPP_MASK_SH_LIST_DCN201(__SHIFT)
447 };
448
449 static const struct dcn201_opp_mask opp_mask = {
450 OPP_MASK_SH_LIST_DCN201(_MASK)
451 };
452
453 #define aux_engine_regs(id)\
454 [id] = {\
455 AUX_COMMON_REG_LIST0(id), \
456 .AUX_RESET_MASK = 0 \
457 }
458
459 static const struct dce110_aux_registers aux_engine_regs[] = {
460 aux_engine_regs(0),
461 aux_engine_regs(1)
462 };
463
464 #define tf_regs(id)\
465 [id] = {\
466 TF_REG_LIST_DCN201(id),\
467 }
468
469 static const struct dcn201_dpp_registers tf_regs[] = {
470 tf_regs(0),
471 tf_regs(1),
472 tf_regs(2),
473 tf_regs(3),
474 };
475
476 static const struct dcn201_dpp_shift tf_shift = {
477 TF_REG_LIST_SH_MASK_DCN201(__SHIFT)
478 };
479
480 static const struct dcn201_dpp_mask tf_mask = {
481 TF_REG_LIST_SH_MASK_DCN201(_MASK)
482 };
483
484 static const struct dcn201_mpc_registers mpc_regs = {
485 MPC_REG_LIST_DCN201(0),
486 MPC_REG_LIST_DCN201(1),
487 MPC_REG_LIST_DCN201(2),
488 MPC_REG_LIST_DCN201(3),
489 MPC_REG_LIST_DCN201(4),
490 MPC_OUT_MUX_REG_LIST_DCN201(0),
491 MPC_OUT_MUX_REG_LIST_DCN201(1),
492 };
493
494 static const struct dcn201_mpc_shift mpc_shift = {
495 MPC_COMMON_MASK_SH_LIST_DCN201(__SHIFT)
496 };
497
498 static const struct dcn201_mpc_mask mpc_mask = {
499 MPC_COMMON_MASK_SH_LIST_DCN201(_MASK)
500 };
501
502 #define tg_regs_dcn201(id)\
503 [id] = {TG_COMMON_REG_LIST_DCN201(id)}
504
505 static const struct dcn_optc_registers tg_regs[] = {
506 tg_regs_dcn201(0),
507 tg_regs_dcn201(1)
508 };
509
510 static const struct dcn_optc_shift tg_shift = {
511 TG_COMMON_MASK_SH_LIST_DCN201(__SHIFT)
512 };
513
514 static const struct dcn_optc_mask tg_mask = {
515 TG_COMMON_MASK_SH_LIST_DCN201(_MASK)
516 };
517
518 #define hubp_regsDCN201(id)\
519 [id] = {\
520 HUBP_REG_LIST_DCN201(id)\
521 }
522
523 static const struct dcn201_hubp_registers hubp_regs[] = {
524 hubp_regsDCN201(0),
525 hubp_regsDCN201(1),
526 hubp_regsDCN201(2),
527 hubp_regsDCN201(3)
528 };
529
530 static const struct dcn201_hubp_shift hubp_shift = {
531 HUBP_MASK_SH_LIST_DCN201(__SHIFT)
532 };
533
534 static const struct dcn201_hubp_mask hubp_mask = {
535 HUBP_MASK_SH_LIST_DCN201(_MASK)
536 };
537
538 static const struct dcn_hubbub_registers hubbub_reg = {
539 HUBBUB_REG_LIST_DCN201(0)
540 };
541
542 static const struct dcn_hubbub_shift hubbub_shift = {
543 HUBBUB_MASK_SH_LIST_DCN201(__SHIFT)
544 };
545
546 static const struct dcn_hubbub_mask hubbub_mask = {
547 HUBBUB_MASK_SH_LIST_DCN201(_MASK)
548 };
549
550
551 static const struct dccg_registers dccg_regs = {
552 DCCG_COMMON_REG_LIST_DCN_BASE()
553 };
554
555 static const struct dccg_shift dccg_shift = {
556 DCCG_COMMON_MASK_SH_LIST_DCN_COMMON_BASE(__SHIFT)
557 };
558
559 static const struct dccg_mask dccg_mask = {
560 DCCG_COMMON_MASK_SH_LIST_DCN_COMMON_BASE(_MASK)
561 };
562
563 static const struct resource_caps res_cap_dnc201 = {
564 .num_timing_generator = 2,
565 .num_opp = 2,
566 .num_video_plane = 4,
567 .num_audio = 2,
568 .num_stream_encoder = 2,
569 .num_pll = 2,
570 .num_dwb = 0,
571 .num_dsc = 0,
572 .num_ddc = 2,
573 };
574
575 static const struct dc_plane_cap plane_cap = {
576 .type = DC_PLANE_TYPE_DCN_UNIVERSAL,
577 .per_pixel_alpha = true,
578
579 .pixel_format_support = {
580 .argb8888 = true,
581 .nv12 = false,
582 .fp16 = true,
583 .p010 = false,
584 },
585
586 .max_upscale_factor = {
587 .argb8888 = 16000,
588 .nv12 = 16000,
589 .fp16 = 1
590 },
591
592 .max_downscale_factor = {
593 .argb8888 = 250,
594 .nv12 = 250,
595 .fp16 = 250
596 },
597 64,
598 64
599 };
600
601 static const struct dc_debug_options debug_defaults_drv = {
602 .disable_dmcu = true,
603 .force_abm_enable = false,
604 .clock_trace = true,
605 .disable_pplib_clock_request = true,
606 .pipe_split_policy = MPC_SPLIT_DYNAMIC,
607 .force_single_disp_pipe_split = false,
608 .disable_dcc = DCC_ENABLE,
609 .vsr_support = true,
610 .performance_trace = false,
611 .az_endpoint_mute_only = true,
612 .max_downscale_src_width = 3840,
613 .disable_pplib_wm_range = true,
614 .scl_reset_length10 = true,
615 .sanity_checks = false,
616 .underflow_assert_delay_us = 0xFFFFFFFF,
617 .enable_tri_buf = true,
618 .using_dml2 = false,
619 };
620
621 static const struct dc_check_config config_defaults = {
622 .enable_legacy_fast_update = true,
623 };
624
dcn201_dpp_destroy(struct dpp ** dpp)625 static void dcn201_dpp_destroy(struct dpp **dpp)
626 {
627 kfree(TO_DCN201_DPP(*dpp));
628 *dpp = NULL;
629 }
630
dcn201_dpp_create(struct dc_context * ctx,uint32_t inst)631 static struct dpp *dcn201_dpp_create(
632 struct dc_context *ctx,
633 uint32_t inst)
634 {
635 struct dcn201_dpp *dpp =
636 kzalloc_obj(struct dcn201_dpp);
637
638 if (!dpp)
639 return NULL;
640
641 if (dpp201_construct(dpp, ctx, inst,
642 &tf_regs[inst], &tf_shift, &tf_mask))
643 return &dpp->base;
644
645 kfree(dpp);
646 return NULL;
647 }
648
dcn201_ipp_create(struct dc_context * ctx,uint32_t inst)649 static struct input_pixel_processor *dcn201_ipp_create(
650 struct dc_context *ctx, uint32_t inst)
651 {
652 struct dcn10_ipp *ipp =
653 kzalloc_obj(struct dcn10_ipp);
654
655 if (!ipp) {
656 return NULL;
657 }
658
659 dcn20_ipp_construct(ipp, ctx, inst,
660 &ipp_regs[inst], &ipp_shift, &ipp_mask);
661 return &ipp->base;
662 }
663
664
dcn201_opp_create(struct dc_context * ctx,uint32_t inst)665 static struct output_pixel_processor *dcn201_opp_create(
666 struct dc_context *ctx, uint32_t inst)
667 {
668 struct dcn201_opp *opp =
669 kzalloc_obj(struct dcn201_opp);
670
671 if (!opp) {
672 return NULL;
673 }
674
675 dcn201_opp_construct(opp, ctx, inst,
676 &opp_regs[inst], &opp_shift, &opp_mask);
677 return &opp->base;
678 }
679
dcn201_aux_engine_create(struct dc_context * ctx,uint32_t inst)680 static struct dce_aux *dcn201_aux_engine_create(struct dc_context *ctx,
681 uint32_t inst)
682 {
683 struct aux_engine_dce110 *aux_engine =
684 kzalloc_obj(struct aux_engine_dce110);
685
686 if (!aux_engine)
687 return NULL;
688
689 dce110_aux_engine_construct(aux_engine, ctx, inst,
690 SW_AUX_TIMEOUT_PERIOD_MULTIPLIER * AUX_TIMEOUT_PERIOD,
691 &aux_engine_regs[inst],
692 &aux_mask,
693 &aux_shift,
694 ctx->dc->caps.extended_aux_timeout_support);
695
696 return &aux_engine->base;
697 }
698 #define i2c_inst_regs(id) { I2C_HW_ENGINE_COMMON_REG_LIST(id) }
699
700 static const struct dce_i2c_registers i2c_hw_regs[] = {
701 i2c_inst_regs(1),
702 i2c_inst_regs(2),
703 };
704
705 static const struct dce_i2c_shift i2c_shifts = {
706 I2C_COMMON_MASK_SH_LIST_DCN2(__SHIFT)
707 };
708
709 static const struct dce_i2c_mask i2c_masks = {
710 I2C_COMMON_MASK_SH_LIST_DCN2(_MASK)
711 };
712
dcn201_i2c_hw_create(struct dc_context * ctx,uint32_t inst)713 static struct dce_i2c_hw *dcn201_i2c_hw_create(struct dc_context *ctx,
714 uint32_t inst)
715 {
716 struct dce_i2c_hw *dce_i2c_hw =
717 kzalloc_obj(struct dce_i2c_hw);
718
719 if (!dce_i2c_hw)
720 return NULL;
721
722 dcn2_i2c_hw_construct(dce_i2c_hw, ctx, inst,
723 &i2c_hw_regs[inst], &i2c_shifts, &i2c_masks);
724
725 return dce_i2c_hw;
726 }
727
dcn201_mpc_create(struct dc_context * ctx,uint32_t num_mpcc)728 static struct mpc *dcn201_mpc_create(struct dc_context *ctx, uint32_t num_mpcc)
729 {
730 struct dcn201_mpc *mpc201 = kzalloc_obj(struct dcn201_mpc);
731
732 if (!mpc201)
733 return NULL;
734
735 dcn201_mpc_construct(mpc201, ctx,
736 &mpc_regs,
737 &mpc_shift,
738 &mpc_mask,
739 num_mpcc);
740
741 return &mpc201->base;
742 }
743
dcn201_hubbub_create(struct dc_context * ctx)744 static struct hubbub *dcn201_hubbub_create(struct dc_context *ctx)
745 {
746 struct dcn20_hubbub *hubbub = kzalloc_obj(struct dcn20_hubbub);
747
748 if (!hubbub)
749 return NULL;
750
751 hubbub201_construct(hubbub, ctx,
752 &hubbub_reg,
753 &hubbub_shift,
754 &hubbub_mask);
755
756 return &hubbub->base;
757 }
758
759 static const struct dcn_dio_registers dio_regs = {
760 DIO_REG_LIST_DCN10()
761 };
762
763 #define DIO_MASK_SH_LIST(mask_sh)\
764 HWS_SF(, DIO_MEM_PWR_CTRL, I2C_LIGHT_SLEEP_FORCE, mask_sh)
765
766 static const struct dcn_dio_shift dio_shift = {
767 DIO_MASK_SH_LIST(__SHIFT)
768 };
769
770 static const struct dcn_dio_mask dio_mask = {
771 DIO_MASK_SH_LIST(_MASK)
772 };
773
dcn201_dio_create(struct dc_context * ctx)774 static struct dio *dcn201_dio_create(struct dc_context *ctx)
775 {
776 struct dcn10_dio *dio10 = kzalloc_obj(struct dcn10_dio);
777
778 if (!dio10)
779 return NULL;
780
781 dcn10_dio_construct(dio10, ctx, &dio_regs, &dio_shift, &dio_mask);
782
783 return &dio10->base;
784 }
785
dcn201_timing_generator_create(struct dc_context * ctx,uint32_t instance)786 static struct timing_generator *dcn201_timing_generator_create(
787 struct dc_context *ctx,
788 uint32_t instance)
789 {
790 struct optc *tgn10 =
791 kzalloc_obj(struct optc);
792
793 if (!tgn10)
794 return NULL;
795
796 tgn10->base.inst = instance;
797 tgn10->base.ctx = ctx;
798
799 tgn10->tg_regs = &tg_regs[instance];
800 tgn10->tg_shift = &tg_shift;
801 tgn10->tg_mask = &tg_mask;
802
803 dcn201_timing_generator_init(tgn10);
804
805 return &tgn10->base;
806 }
807
808 static const struct encoder_feature_support link_enc_feature = {
809 .max_hdmi_deep_color = COLOR_DEPTH_121212,
810 .max_hdmi_pixel_clock = 600000,
811 .hdmi_ycbcr420_supported = true,
812 .dp_ycbcr420_supported = true,
813 .fec_supported = true,
814 .flags.bits.IS_HBR2_CAPABLE = true,
815 .flags.bits.IS_HBR3_CAPABLE = true,
816 .flags.bits.IS_TPS3_CAPABLE = true,
817 .flags.bits.IS_TPS4_CAPABLE = true
818 };
819
dcn201_link_encoder_create(struct dc_context * ctx,const struct encoder_init_data * enc_init_data)820 static struct link_encoder *dcn201_link_encoder_create(
821 struct dc_context *ctx,
822 const struct encoder_init_data *enc_init_data)
823 {
824 struct dcn20_link_encoder *enc20 =
825 kzalloc_obj(struct dcn20_link_encoder);
826 struct dcn10_link_encoder *enc10;
827
828 if (!enc20 || enc_init_data->hpd_source >= ARRAY_SIZE(link_enc_hpd_regs))
829 return NULL;
830
831 enc10 = &enc20->enc10;
832
833 dcn201_link_encoder_construct(enc20,
834 enc_init_data,
835 &link_enc_feature,
836 &link_enc_regs[enc_init_data->transmitter],
837 &link_enc_aux_regs[enc_init_data->channel - 1],
838 &link_enc_hpd_regs[enc_init_data->hpd_source],
839 &le_shift,
840 &le_mask);
841
842 return &enc10->base;
843 }
844
dcn201_clock_source_create(struct dc_context * ctx,struct dc_bios * bios,enum clock_source_id id,const struct dce110_clk_src_regs * regs,bool dp_clk_src)845 static struct clock_source *dcn201_clock_source_create(
846 struct dc_context *ctx,
847 struct dc_bios *bios,
848 enum clock_source_id id,
849 const struct dce110_clk_src_regs *regs,
850 bool dp_clk_src)
851 {
852 struct dce110_clk_src *clk_src =
853 kzalloc_obj(struct dce110_clk_src);
854
855 if (!clk_src)
856 return NULL;
857
858 if (dce112_clk_src_construct(clk_src, ctx, bios, id,
859 regs, &cs_shift, &cs_mask)) {
860 clk_src->base.dp_clk_src = dp_clk_src;
861 return &clk_src->base;
862 }
863 kfree(clk_src);
864 return NULL;
865 }
866
read_dce_straps(struct dc_context * ctx,struct resource_straps * straps)867 static void read_dce_straps(
868 struct dc_context *ctx,
869 struct resource_straps *straps)
870 {
871 generic_reg_get(ctx, mmDC_PINSTRAPS + BASE(mmDC_PINSTRAPS_BASE_IDX),
872
873 FN(DC_PINSTRAPS, DC_PINSTRAPS_AUDIO), &straps->dc_pinstraps_audio);
874 }
875
dcn201_create_audio(struct dc_context * ctx,unsigned int inst)876 static struct audio *dcn201_create_audio(
877 struct dc_context *ctx, unsigned int inst)
878 {
879 return dce_audio_create(ctx, inst,
880 &audio_regs[inst], &audio_shift, &audio_mask);
881 }
882
dcn201_stream_encoder_create(enum engine_id eng_id,struct dc_context * ctx)883 static struct stream_encoder *dcn201_stream_encoder_create(
884 enum engine_id eng_id,
885 struct dc_context *ctx)
886 {
887 struct dcn10_stream_encoder *enc1 =
888 kzalloc_obj(struct dcn10_stream_encoder);
889
890 if (!enc1)
891 return NULL;
892
893 dcn20_stream_encoder_construct(enc1, ctx, ctx->dc_bios, eng_id,
894 &stream_enc_regs[eng_id],
895 &se_shift, &se_mask);
896
897 return &enc1->base;
898 }
899
900 static const struct dce_hwseq_registers hwseq_reg = {
901 HWSEQ_DCN201_REG_LIST()
902 };
903
904 static const struct dce_hwseq_shift hwseq_shift = {
905 HWSEQ_DCN201_MASK_SH_LIST(__SHIFT)
906 };
907
908 static const struct dce_hwseq_mask hwseq_mask = {
909 HWSEQ_DCN201_MASK_SH_LIST(_MASK)
910 };
911
dcn201_hwseq_create(struct dc_context * ctx)912 static struct dce_hwseq *dcn201_hwseq_create(
913 struct dc_context *ctx)
914 {
915 struct dce_hwseq *hws = kzalloc_obj(struct dce_hwseq);
916
917 if (hws) {
918 hws->ctx = ctx;
919 hws->regs = &hwseq_reg;
920 hws->shifts = &hwseq_shift;
921 hws->masks = &hwseq_mask;
922 }
923 return hws;
924 }
925
926 static const struct resource_create_funcs res_create_funcs = {
927 .read_dce_straps = read_dce_straps,
928 .create_audio = dcn201_create_audio,
929 .create_stream_encoder = dcn201_stream_encoder_create,
930 .create_hwseq = dcn201_hwseq_create,
931 };
932
dcn201_clock_source_destroy(struct clock_source ** clk_src)933 static void dcn201_clock_source_destroy(struct clock_source **clk_src)
934 {
935 kfree(TO_DCE110_CLK_SRC(*clk_src));
936 *clk_src = NULL;
937 }
938
dcn201_resource_destruct(struct dcn201_resource_pool * pool)939 static void dcn201_resource_destruct(struct dcn201_resource_pool *pool)
940 {
941 unsigned int i;
942
943 for (i = 0; i < pool->base.stream_enc_count; i++) {
944 if (pool->base.stream_enc[i] != NULL) {
945 kfree(DCN10STRENC_FROM_STRENC(pool->base.stream_enc[i]));
946 pool->base.stream_enc[i] = NULL;
947 }
948 }
949
950
951 if (pool->base.mpc != NULL) {
952 kfree(TO_DCN201_MPC(pool->base.mpc));
953 pool->base.mpc = NULL;
954 }
955
956 if (pool->base.hubbub != NULL) {
957 kfree(pool->base.hubbub);
958 pool->base.hubbub = NULL;
959 }
960
961 if (pool->base.dio != NULL) {
962 kfree(TO_DCN10_DIO(pool->base.dio));
963 pool->base.dio = NULL;
964 }
965
966 for (i = 0; i < pool->base.pipe_count; i++) {
967 if (pool->base.dpps[i] != NULL)
968 dcn201_dpp_destroy(&pool->base.dpps[i]);
969
970 if (pool->base.ipps[i] != NULL)
971 pool->base.ipps[i]->funcs->ipp_destroy(&pool->base.ipps[i]);
972
973 if (pool->base.hubps[i] != NULL) {
974 kfree(TO_DCN10_HUBP(pool->base.hubps[i]));
975 pool->base.hubps[i] = NULL;
976 }
977
978 if (pool->base.irqs != NULL) {
979 dal_irq_service_destroy(&pool->base.irqs);
980 }
981 }
982
983 for (i = 0; i < pool->base.res_cap->num_opp; i++) {
984 if (pool->base.opps[i] != NULL)
985 pool->base.opps[i]->funcs->opp_destroy(&pool->base.opps[i]);
986 }
987
988 for (i = 0; i < pool->base.res_cap->num_timing_generator; i++) {
989 if (pool->base.timing_generators[i] != NULL) {
990 kfree(DCN10TG_FROM_TG(pool->base.timing_generators[i]));
991 pool->base.timing_generators[i] = NULL;
992 }
993 }
994 for (i = 0; i < pool->base.audio_count; i++) {
995 if (pool->base.audios[i])
996 dce_aud_destroy(&pool->base.audios[i]);
997 }
998
999 for (i = 0; i < pool->base.clk_src_count; i++) {
1000 if (pool->base.clock_sources[i] != NULL) {
1001 dcn201_clock_source_destroy(&pool->base.clock_sources[i]);
1002 pool->base.clock_sources[i] = NULL;
1003 }
1004 }
1005
1006 if (pool->base.dp_clock_source != NULL) {
1007 dcn201_clock_source_destroy(&pool->base.dp_clock_source);
1008 pool->base.dp_clock_source = NULL;
1009 }
1010
1011 if (pool->base.dccg != NULL)
1012 dcn_dccg_destroy(&pool->base.dccg);
1013 }
1014
dcn201_hubp_create(struct dc_context * ctx,uint32_t inst)1015 static struct hubp *dcn201_hubp_create(
1016 struct dc_context *ctx,
1017 uint32_t inst)
1018 {
1019 struct dcn201_hubp *hubp201 =
1020 kzalloc_obj(struct dcn201_hubp);
1021
1022 if (!hubp201)
1023 return NULL;
1024
1025 if (dcn201_hubp_construct(hubp201, ctx, inst,
1026 &hubp_regs[inst], &hubp_shift, &hubp_mask))
1027 return &hubp201->base;
1028
1029 kfree(hubp201);
1030 return NULL;
1031 }
1032
dcn201_acquire_free_pipe_for_layer(const struct dc_state * cur_ctx,struct dc_state * new_ctx,const struct resource_pool * pool,const struct pipe_ctx * opp_head_pipe)1033 static struct pipe_ctx *dcn201_acquire_free_pipe_for_layer(
1034 const struct dc_state *cur_ctx,
1035 struct dc_state *new_ctx,
1036 const struct resource_pool *pool,
1037 const struct pipe_ctx *opp_head_pipe)
1038 {
1039 struct resource_context *res_ctx = &new_ctx->res_ctx;
1040 struct pipe_ctx *head_pipe = resource_get_otg_master_for_stream(res_ctx, opp_head_pipe->stream);
1041 struct pipe_ctx *idle_pipe = resource_find_free_secondary_pipe_legacy(res_ctx, pool, head_pipe);
1042
1043 if (!head_pipe) {
1044 ASSERT(0);
1045 return NULL;
1046 }
1047
1048 if (!idle_pipe)
1049 return NULL;
1050
1051 idle_pipe->stream = head_pipe->stream;
1052 idle_pipe->stream_res.tg = head_pipe->stream_res.tg;
1053 idle_pipe->stream_res.opp = head_pipe->stream_res.opp;
1054
1055 idle_pipe->plane_res.hubp = pool->hubps[idle_pipe->pipe_idx];
1056 idle_pipe->plane_res.ipp = pool->ipps[idle_pipe->pipe_idx];
1057 idle_pipe->plane_res.dpp = pool->dpps[idle_pipe->pipe_idx];
1058 idle_pipe->plane_res.mpcc_inst = pool->dpps[idle_pipe->pipe_idx]->inst;
1059
1060 return idle_pipe;
1061 }
1062
dcn201_get_dcc_compression_cap(const struct dc * dc,const struct dc_dcc_surface_param * input,struct dc_surface_dcc_cap * output)1063 static bool dcn201_get_dcc_compression_cap(const struct dc *dc,
1064 const struct dc_dcc_surface_param *input,
1065 struct dc_surface_dcc_cap *output)
1066 {
1067 return dc->res_pool->hubbub->funcs->get_dcc_compression_cap(
1068 dc->res_pool->hubbub,
1069 input,
1070 output);
1071 }
1072
dcn201_populate_dml_writeback_from_context(struct dc * dc,struct resource_context * res_ctx,display_e2e_pipe_params_st * pipes)1073 static void dcn201_populate_dml_writeback_from_context(struct dc *dc,
1074 struct resource_context *res_ctx,
1075 display_e2e_pipe_params_st *pipes)
1076 {
1077 DC_FP_START();
1078 dcn201_populate_dml_writeback_from_context_fpu(dc, res_ctx, pipes);
1079 DC_FP_END();
1080 }
1081
dcn201_destroy_resource_pool(struct resource_pool ** pool)1082 static void dcn201_destroy_resource_pool(struct resource_pool **pool)
1083 {
1084 struct dcn201_resource_pool *dcn201_pool = TO_DCN201_RES_POOL(*pool);
1085
1086 dcn201_resource_destruct(dcn201_pool);
1087 kfree(dcn201_pool);
1088 *pool = NULL;
1089 }
1090
dcn201_link_init(struct dc_link * link)1091 static void dcn201_link_init(struct dc_link *link)
1092 {
1093 if (link->ctx->dc_bios->integrated_info)
1094 link->dp_ss_off = !link->ctx->dc_bios->integrated_info->dp_ss_control;
1095 }
1096
1097 static struct dc_cap_funcs cap_funcs = {
1098 .get_dcc_compression_cap = dcn201_get_dcc_compression_cap,
1099 };
1100
1101 static struct resource_funcs dcn201_res_pool_funcs = {
1102 .link_init = dcn201_link_init,
1103 .destroy = dcn201_destroy_resource_pool,
1104 .link_enc_create = dcn201_link_encoder_create,
1105 .panel_cntl_create = NULL,
1106 .validate_bandwidth = dcn20_validate_bandwidth,
1107 .populate_dml_pipes = dcn20_populate_dml_pipes_from_context,
1108 .add_stream_to_ctx = dcn20_add_stream_to_ctx,
1109 .add_dsc_to_stream_resource = NULL,
1110 .remove_stream_from_ctx = dcn20_remove_stream_from_ctx,
1111 .acquire_free_pipe_as_secondary_dpp_pipe = dcn201_acquire_free_pipe_for_layer,
1112 .release_pipe = dcn20_release_pipe,
1113 .populate_dml_writeback_from_context = dcn201_populate_dml_writeback_from_context,
1114 .patch_unknown_plane_state = dcn20_patch_unknown_plane_state,
1115 .set_mcif_arb_params = dcn20_set_mcif_arb_params,
1116 .find_first_free_match_stream_enc_for_link = dcn10_find_first_free_match_stream_enc_for_link,
1117 .get_vstartup_for_pipe = dcn10_get_vstartup_for_pipe
1118 };
1119
dcn201_resource_construct(uint8_t num_virtual_links,struct dc * dc,struct dcn201_resource_pool * pool)1120 static bool dcn201_resource_construct(
1121 uint8_t num_virtual_links,
1122 struct dc *dc,
1123 struct dcn201_resource_pool *pool)
1124 {
1125 int i;
1126 struct dc_context *ctx = dc->ctx;
1127
1128 ctx->dc_bios->regs = &bios_regs;
1129
1130 pool->base.res_cap = &res_cap_dnc201;
1131 pool->base.funcs = &dcn201_res_pool_funcs;
1132
1133 /*************************************************
1134 * Resource + asic cap harcoding *
1135 *************************************************/
1136 pool->base.underlay_pipe_index = NO_UNDERLAY_PIPE;
1137
1138 pool->base.pipe_count = 4;
1139 pool->base.mpcc_count = 5;
1140 dc->caps.max_downscale_ratio = 200;
1141 dc->caps.i2c_speed_in_khz = 100;
1142 dc->caps.i2c_speed_in_khz_hdcp = 5; /*1.5 w/a applied by default*/
1143 dc->caps.max_cursor_size = 256;
1144 dc->caps.min_horizontal_blanking_period = 80;
1145 dc->caps.dmdata_alloc_size = 2048;
1146
1147 dc->caps.max_slave_planes = 1;
1148 dc->caps.max_slave_yuv_planes = 1;
1149 dc->caps.max_slave_rgb_planes = 1;
1150 dc->caps.post_blend_color_processing = true;
1151 dc->caps.force_dp_tps4_for_cp2520 = true;
1152 dc->caps.extended_aux_timeout_support = true;
1153
1154 /* Color pipeline capabilities */
1155 dc->caps.color.dpp.dcn_arch = 1;
1156 dc->caps.color.dpp.input_lut_shared = 0;
1157 dc->caps.color.dpp.icsc = 1;
1158 dc->caps.color.dpp.dgam_ram = 1;
1159 dc->caps.color.dpp.dgam_rom_caps.srgb = 1;
1160 dc->caps.color.dpp.dgam_rom_caps.bt2020 = 1;
1161 dc->caps.color.dpp.dgam_rom_caps.gamma2_2 = 0;
1162 dc->caps.color.dpp.dgam_rom_caps.pq = 0;
1163 dc->caps.color.dpp.dgam_rom_caps.hlg = 0;
1164 dc->caps.color.dpp.post_csc = 0;
1165 dc->caps.color.dpp.gamma_corr = 0;
1166 dc->caps.color.dpp.dgam_rom_for_yuv = 1;
1167
1168 dc->caps.color.dpp.hw_3d_lut = 1;
1169 dc->caps.color.dpp.ogam_ram = 1;
1170 // no OGAM ROM on DCN2
1171 dc->caps.color.dpp.ogam_rom_caps.srgb = 0;
1172 dc->caps.color.dpp.ogam_rom_caps.bt2020 = 0;
1173 dc->caps.color.dpp.ogam_rom_caps.gamma2_2 = 0;
1174 dc->caps.color.dpp.ogam_rom_caps.pq = 0;
1175 dc->caps.color.dpp.ogam_rom_caps.hlg = 0;
1176 dc->caps.color.dpp.ocsc = 0;
1177
1178 dc->caps.color.mpc.gamut_remap = 0;
1179 dc->caps.color.mpc.num_3dluts = 0;
1180 dc->caps.color.mpc.shared_3d_lut = 0;
1181 dc->caps.color.mpc.ogam_ram = 1;
1182 dc->caps.color.mpc.ogam_rom_caps.srgb = 0;
1183 dc->caps.color.mpc.ogam_rom_caps.bt2020 = 0;
1184 dc->caps.color.mpc.ogam_rom_caps.gamma2_2 = 0;
1185 dc->caps.color.mpc.ogam_rom_caps.pq = 0;
1186 dc->caps.color.mpc.ogam_rom_caps.hlg = 0;
1187 dc->caps.color.mpc.ocsc = 1;
1188
1189 dc->debug = debug_defaults_drv;
1190 dc->check_config = config_defaults;
1191
1192 /*a0 only, remove later*/
1193 dc->work_arounds.no_connect_phy_config = true;
1194 dc->work_arounds.dedcn20_305_wa = true;
1195 /*************************************************
1196 * Create resources *
1197 *************************************************/
1198
1199 pool->base.clock_sources[DCN20_CLK_SRC_PLL0] =
1200 dcn201_clock_source_create(ctx, ctx->dc_bios,
1201 CLOCK_SOURCE_COMBO_PHY_PLL0,
1202 &clk_src_regs[0], false);
1203 pool->base.clock_sources[DCN20_CLK_SRC_PLL1] =
1204 dcn201_clock_source_create(ctx, ctx->dc_bios,
1205 CLOCK_SOURCE_COMBO_PHY_PLL1,
1206 &clk_src_regs[1], false);
1207
1208 pool->base.clk_src_count = DCN20_CLK_SRC_TOTAL_DCN201;
1209
1210 /* todo: not reuse phy_pll registers */
1211 pool->base.dp_clock_source =
1212 dcn201_clock_source_create(ctx, ctx->dc_bios,
1213 CLOCK_SOURCE_ID_DP_DTO,
1214 &clk_src_regs[0], true);
1215
1216 for (i = 0; i < pool->base.clk_src_count; i++) {
1217 if (pool->base.clock_sources[i] == NULL) {
1218 dm_error("DC: failed to create clock sources!\n");
1219 goto create_fail;
1220 }
1221 }
1222
1223 pool->base.dccg = dccg201_create(ctx, &dccg_regs, &dccg_shift, &dccg_mask);
1224 if (pool->base.dccg == NULL) {
1225 dm_error("DC: failed to create dccg!\n");
1226 goto create_fail;
1227 }
1228
1229 dcn201_ip.max_num_otg = pool->base.res_cap->num_timing_generator;
1230 dcn201_ip.max_num_dpp = pool->base.pipe_count;
1231 dml_init_instance(&dc->dml, &dcn201_soc, &dcn201_ip, DML_PROJECT_DCN201);
1232 {
1233 struct irq_service_init_data init_data;
1234 init_data.ctx = dc->ctx;
1235 pool->base.irqs = dal_irq_service_dcn201_create(&init_data);
1236 if (!pool->base.irqs)
1237 goto create_fail;
1238 }
1239
1240 /* mem input -> ipp -> dpp -> opp -> TG */
1241 for (i = 0; i < pool->base.pipe_count; i++) {
1242 pool->base.hubps[i] = dcn201_hubp_create(ctx, i);
1243 if (pool->base.hubps[i] == NULL) {
1244 dm_error(
1245 "DC: failed to create memory input!\n");
1246 goto create_fail;
1247 }
1248
1249 pool->base.ipps[i] = dcn201_ipp_create(ctx, i);
1250 if (pool->base.ipps[i] == NULL) {
1251 dm_error(
1252 "DC: failed to create input pixel processor!\n");
1253 goto create_fail;
1254 }
1255
1256 pool->base.dpps[i] = dcn201_dpp_create(ctx, i);
1257 if (pool->base.dpps[i] == NULL) {
1258 dm_error(
1259 "DC: failed to create dpps!\n");
1260 goto create_fail;
1261 }
1262 }
1263
1264 for (i = 0; i < pool->base.res_cap->num_opp; i++) {
1265 pool->base.opps[i] = dcn201_opp_create(ctx, i);
1266 if (pool->base.opps[i] == NULL) {
1267 dm_error(
1268 "DC: failed to create output pixel processor!\n");
1269 goto create_fail;
1270 }
1271 }
1272
1273 for (i = 0; i < pool->base.res_cap->num_ddc; i++) {
1274 pool->base.engines[i] = dcn201_aux_engine_create(ctx, i);
1275 if (pool->base.engines[i] == NULL) {
1276 dm_error(
1277 "DC:failed to create aux engine!!\n");
1278 goto create_fail;
1279 }
1280 pool->base.hw_i2cs[i] = dcn201_i2c_hw_create(ctx, i);
1281 if (pool->base.hw_i2cs[i] == NULL) {
1282 dm_error(
1283 "DC:failed to create hw i2c!!\n");
1284 goto create_fail;
1285 }
1286 pool->base.sw_i2cs[i] = NULL;
1287 }
1288
1289 for (i = 0; i < pool->base.res_cap->num_timing_generator; i++) {
1290 pool->base.timing_generators[i] = dcn201_timing_generator_create(
1291 ctx, i);
1292 if (pool->base.timing_generators[i] == NULL) {
1293 dm_error("DC: failed to create tg!\n");
1294 goto create_fail;
1295 }
1296 }
1297
1298 pool->base.timing_generator_count = i;
1299
1300 pool->base.mpc = dcn201_mpc_create(ctx, pool->base.mpcc_count);
1301 if (pool->base.mpc == NULL) {
1302 dm_error("DC: failed to create mpc!\n");
1303 goto create_fail;
1304 }
1305
1306 pool->base.hubbub = dcn201_hubbub_create(ctx);
1307 if (pool->base.hubbub == NULL) {
1308 dm_error("DC: failed to create hubbub!\n");
1309 goto create_fail;
1310 }
1311
1312 /* DIO */
1313 pool->base.dio = dcn201_dio_create(ctx);
1314 if (pool->base.dio == NULL) {
1315 BREAK_TO_DEBUGGER();
1316 dm_error("DC: failed to create dio!\n");
1317 goto create_fail;
1318 }
1319
1320 if (!resource_construct(num_virtual_links, dc, &pool->base,
1321 &res_create_funcs))
1322 goto create_fail;
1323
1324 dcn201_hw_sequencer_construct(dc);
1325
1326 dc->caps.max_planes = pool->base.pipe_count;
1327
1328 for (i = 0; i < dc->caps.max_planes; ++i)
1329 dc->caps.planes[i] = plane_cap;
1330
1331 dc->caps.max_odm_combine_factor = 2;
1332
1333 dc->cap_funcs = cap_funcs;
1334
1335 return true;
1336
1337 create_fail:
1338
1339 dcn201_resource_destruct(pool);
1340
1341 return false;
1342 }
1343
dcn201_create_resource_pool(const struct dc_init_data * init_data,struct dc * dc)1344 struct resource_pool *dcn201_create_resource_pool(
1345 const struct dc_init_data *init_data,
1346 struct dc *dc)
1347 {
1348 struct dcn201_resource_pool *pool =
1349 kzalloc_obj(struct dcn201_resource_pool);
1350
1351 if (!pool)
1352 return NULL;
1353
1354 if (dcn201_resource_construct(init_data->num_virtual_links, dc, pool))
1355 return &pool->base;
1356
1357 kfree(pool);
1358 return NULL;
1359 }
1360