1 /*
2  * Copyright 2015 Advanced Micro Devices, Inc.
3  *
4  * Permission is hereby granted, free of charge, to any person obtaining a
5  * copy of this software and associated documentation files (the "Software"),
6  * to deal in the Software without restriction, including without limitation
7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8  * and/or sell copies of the Software, and to permit persons to whom the
9  * Software is furnished to do so, subject to the following conditions:
10  *
11  * The above copyright notice and this permission notice shall be included in
12  * all copies or substantial portions of the Software.
13  *
14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20  * OTHER DEALINGS IN THE SOFTWARE.
21  *
22  * Authors: AMD
23  *
24  */
25 
26 #include "dm_services.h"
27 #include "dc.h"
28 #include "core_types.h"
29 #include "dce120_hwseq.h"
30 #include "dce/dce_hwseq.h"
31 
32 #include "dce100/dce100_hwseq.h"
33 #include "dce110/dce110_hwseq.h"
34 
35 #include "dce/dce_12_0_offset.h"
36 #include "dce/dce_12_0_sh_mask.h"
37 #include "soc15_hw_ip.h"
38 #include "vega10_ip_offset.h"
39 #include "reg_helper.h"
40 
41 #define CTX \
42 	hws->ctx
43 #define REG(reg)\
44 	hws->regs->reg
45 
46 #undef FN
47 #define FN(reg_name, field_name) \
48 	hws->shifts->field_name, hws->masks->field_name
49 
50 struct dce120_hw_seq_reg_offsets {
51 	uint32_t crtc;
52 };
53 
54 #if 0
55 static const struct dce120_hw_seq_reg_offsets reg_offsets[] = {
56 {
57 	.crtc = (mmCRTC0_CRTC_GSL_CONTROL - mmCRTC0_CRTC_GSL_CONTROL),
58 },
59 {
60 	.crtc = (mmCRTC1_CRTC_GSL_CONTROL - mmCRTC0_CRTC_GSL_CONTROL),
61 },
62 {
63 	.crtc = (mmCRTC2_CRTC_GSL_CONTROL - mmCRTC0_CRTC_GSL_CONTROL),
64 },
65 {
66 	.crtc = (mmCRTC3_CRTC_GSL_CONTROL - mmCRTC0_CRTC_GSL_CONTROL),
67 },
68 {
69 	.crtc = (mmCRTC4_CRTC_GSL_CONTROL - mmCRTC0_CRTC_GSL_CONTROL),
70 },
71 {
72 	.crtc = (mmCRTC5_CRTC_GSL_CONTROL - mmCRTC0_CRTC_GSL_CONTROL),
73 }
74 };
75 
76 #define HW_REG_CRTC(reg, id)\
77 	(reg + reg_offsets[id].crtc)
78 
79 #define CNTL_ID(controller_id)\
80 	controller_id
81 /*******************************************************************************
82  * Private definitions
83  ******************************************************************************/
84 static void dce120_init_pte(struct dc_context *ctx, uint8_t controller_id)
85 {
86 	uint32_t addr;
87 	uint32_t value = 0;
88 	uint32_t chunk_int = 0;
89 	uint32_t chunk_mul = 0;
90 /*
91 	addr = mmDCP0_DVMM_PTE_CONTROL + controller_id *
92 			(mmDCP1_DVMM_PTE_CONTROL- mmDCP0_DVMM_PTE_CONTROL);
93 
94 	value = dm_read_reg(ctx, addr);
95 
96 	set_reg_field_value(
97 			value, 0, DCP, controller_id,
98 			DVMM_PTE_CONTROL,
99 			DVMM_USE_SINGLE_PTE);
100 
101 	set_reg_field_value_soc15(
102 			value, 1, DCP, controller_id,
103 			DVMM_PTE_CONTROL,
104 			DVMM_PTE_BUFFER_MODE0);
105 
106 	set_reg_field_value_soc15(
107 			value, 1, DCP, controller_id,
108 			DVMM_PTE_CONTROL,
109 			DVMM_PTE_BUFFER_MODE1);
110 
111 	dm_write_reg(ctx, addr, value);*/
112 
113 	addr = mmDVMM_PTE_REQ;
114 	value = dm_read_reg(ctx, addr);
115 
116 	chunk_int = get_reg_field_value(
117 		value,
118 		DVMM_PTE_REQ,
119 		HFLIP_PTEREQ_PER_CHUNK_INT);
120 
121 	chunk_mul = get_reg_field_value(
122 		value,
123 		DVMM_PTE_REQ,
124 		HFLIP_PTEREQ_PER_CHUNK_MULTIPLIER);
125 
126 	if (chunk_int != 0x4 || chunk_mul != 0x4) {
127 
128 		set_reg_field_value(
129 			value,
130 			255,
131 			DVMM_PTE_REQ,
132 			MAX_PTEREQ_TO_ISSUE);
133 
134 		set_reg_field_value(
135 			value,
136 			4,
137 			DVMM_PTE_REQ,
138 			HFLIP_PTEREQ_PER_CHUNK_INT);
139 
140 		set_reg_field_value(
141 			value,
142 			4,
143 			DVMM_PTE_REQ,
144 			HFLIP_PTEREQ_PER_CHUNK_MULTIPLIER);
145 
146 		dm_write_reg(ctx, addr, value);
147 	}
148 }
149 #endif
150 
dce120_enable_display_power_gating(struct dc * dc,uint8_t controller_id,struct dc_bios * dcb,enum pipe_gating_control power_gating)151 static bool dce120_enable_display_power_gating(
152 	struct dc *dc,
153 	uint8_t controller_id,
154 	struct dc_bios *dcb,
155 	enum pipe_gating_control power_gating)
156 {
157 	/* disable for bringup */
158 #if 0
159 	enum bp_result bp_result = BP_RESULT_OK;
160 	enum bp_pipe_control_action cntl;
161 	struct dc_context *ctx = dc->ctx;
162 
163 	if (power_gating == PIPE_GATING_CONTROL_INIT)
164 		cntl = ASIC_PIPE_INIT;
165 	else if (power_gating == PIPE_GATING_CONTROL_ENABLE)
166 		cntl = ASIC_PIPE_ENABLE;
167 	else
168 		cntl = ASIC_PIPE_DISABLE;
169 
170 	if (power_gating != PIPE_GATING_CONTROL_INIT || controller_id == 0) {
171 
172 		bp_result = dcb->funcs->enable_disp_power_gating(
173 						dcb, controller_id + 1, cntl);
174 
175 		/* Revert MASTER_UPDATE_MODE to 0 because bios sets it 2
176 		 * by default when command table is called
177 		 */
178 		dm_write_reg(ctx,
179 			HW_REG_CRTC(mmCRTC0_CRTC_MASTER_UPDATE_MODE, controller_id),
180 			0);
181 	}
182 
183 	if (power_gating != PIPE_GATING_CONTROL_ENABLE)
184 		dce120_init_pte(ctx, controller_id);
185 
186 	if (bp_result == BP_RESULT_OK)
187 		return true;
188 	else
189 		return false;
190 #endif
191 	return false;
192 }
193 
dce120_update_dchub(struct dce_hwseq * hws,struct dchub_init_data * dh_data)194 static void dce120_update_dchub(
195 	struct dce_hwseq *hws,
196 	struct dchub_init_data *dh_data)
197 {
198 	/* TODO: port code from dal2 */
199 	switch (dh_data->fb_mode) {
200 	case FRAME_BUFFER_MODE_ZFB_ONLY:
201 		/*For ZFB case need to put DCHUB FB BASE and TOP upside down to indicate ZFB mode*/
202 		REG_UPDATE_2(DCHUB_FB_LOCATION,
203 				FB_TOP, 0,
204 				FB_BASE, 0x0FFFF);
205 
206 		REG_UPDATE(DCHUB_AGP_BASE,
207 				AGP_BASE, dh_data->zfb_phys_addr_base >> 22);
208 
209 		REG_UPDATE(DCHUB_AGP_BOT,
210 				AGP_BOT, dh_data->zfb_mc_base_addr >> 22);
211 
212 		REG_UPDATE(DCHUB_AGP_TOP,
213 				AGP_TOP, (dh_data->zfb_mc_base_addr + dh_data->zfb_size_in_byte - 1) >> 22);
214 		break;
215 	case FRAME_BUFFER_MODE_MIXED_ZFB_AND_LOCAL:
216 		/*Should not touch FB LOCATION (done by VBIOS on AsicInit table)*/
217 		REG_UPDATE(DCHUB_AGP_BASE,
218 				AGP_BASE, dh_data->zfb_phys_addr_base >> 22);
219 
220 		REG_UPDATE(DCHUB_AGP_BOT,
221 				AGP_BOT, dh_data->zfb_mc_base_addr >> 22);
222 
223 		REG_UPDATE(DCHUB_AGP_TOP,
224 				AGP_TOP, (dh_data->zfb_mc_base_addr + dh_data->zfb_size_in_byte - 1) >> 22);
225 		break;
226 	case FRAME_BUFFER_MODE_LOCAL_ONLY:
227 		/*Should not touch FB LOCATION (done by VBIOS on AsicInit table)*/
228 		REG_UPDATE(DCHUB_AGP_BASE,
229 				AGP_BASE, 0);
230 
231 		REG_UPDATE(DCHUB_AGP_BOT,
232 				AGP_BOT, 0x03FFFF);
233 
234 		REG_UPDATE(DCHUB_AGP_TOP,
235 				AGP_TOP, 0);
236 		break;
237 	default:
238 		break;
239 	}
240 
241 	dh_data->dchub_initialzied = true;
242 	dh_data->dchub_info_valid = false;
243 }
244 
245 /**
246  * dce121_xgmi_enabled() - Check if xGMI is enabled
247  * @hws: DCE hardware sequencer object
248  *
249  * Return true if xGMI is enabled. False otherwise.
250  */
dce121_xgmi_enabled(struct dce_hwseq * hws)251 bool dce121_xgmi_enabled(struct dce_hwseq *hws)
252 {
253 	uint32_t pf_max_region;
254 
255 	REG_GET(MC_VM_XGMI_LFB_CNTL, PF_MAX_REGION, &pf_max_region);
256 	/* PF_MAX_REGION == 0 means xgmi is disabled */
257 	return !!pf_max_region;
258 }
259 
dce120_hw_sequencer_construct(struct dc * dc)260 void dce120_hw_sequencer_construct(struct dc *dc)
261 {
262 	/* All registers used by dce11.2 match those in dce11 in offset and
263 	 * structure
264 	 */
265 	dce110_hw_sequencer_construct(dc);
266 	dc->hwseq->funcs.enable_display_power_gating = dce120_enable_display_power_gating;
267 	dc->hwss.update_dchub = dce120_update_dchub;
268 	dc->hwss.clear_surface_dcc_and_tiling = dce100_reset_surface_dcc_and_tiling;
269 }
270 
271