1 /*
2 * Copyright 2012-15 Advanced Micro Devices, Inc.cls
3 *
4  *
5  * Permission is hereby granted, free of charge, to any person obtaining a
6  * copy of this software and associated documentation files (the "Software"),
7  * to deal in the Software without restriction, including without limitation
8  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
9  * and/or sell copies of the Software, and to permit persons to whom the
10  * Software is furnished to do so, subject to the following conditions:
11  *
12  * The above copyright notice and this permission notice shall be included in
13  * all copies or substantial portions of the Software.
14  *
15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
18  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
19  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
20  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
21  * OTHER DEALINGS IN THE SOFTWARE.
22  *
23  * Authors: AMD
24  *
25  */
26 
27 #include "dm_services.h"
28 
29 
30 #include "stream_encoder.h"
31 #include "resource.h"
32 #include "include/irq_service_interface.h"
33 #include "dce120_resource.h"
34 
35 #include "dce112/dce112_resource.h"
36 
37 #include "dce110/dce110_resource.h"
38 #include "virtual/virtual_stream_encoder.h"
39 #include "dce120/dce120_timing_generator.h"
40 #include "irq/dce120/irq_service_dce120.h"
41 #include "dce/dce_opp.h"
42 #include "dce/dce_clock_source.h"
43 #include "dce/dce_ipp.h"
44 #include "dce/dce_mem_input.h"
45 #include "dce/dce_panel_cntl.h"
46 
47 #include "dce110/dce110_hwseq.h"
48 #include "dce120/dce120_hwseq.h"
49 #include "dce/dce_transform.h"
50 #include "clk_mgr.h"
51 #include "dce/dce_audio.h"
52 #include "dce/dce_link_encoder.h"
53 #include "dce/dce_stream_encoder.h"
54 #include "dce/dce_hwseq.h"
55 #include "dce/dce_abm.h"
56 #include "dce/dce_dmcu.h"
57 #include "dce/dce_aux.h"
58 #include "dce/dce_i2c.h"
59 
60 #include "dce/dce_12_0_offset.h"
61 #include "dce/dce_12_0_sh_mask.h"
62 #include "soc15_hw_ip.h"
63 #include "vega10_ip_offset.h"
64 #include "nbio/nbio_6_1_offset.h"
65 #include "mmhub/mmhub_1_0_offset.h"
66 #include "mmhub/mmhub_1_0_sh_mask.h"
67 #include "reg_helper.h"
68 
69 #include "dce100/dce100_resource.h"
70 #include "link.h"
71 
72 #ifndef mmDP0_DP_DPHY_INTERNAL_CTRL
73 	#define mmDP0_DP_DPHY_INTERNAL_CTRL		0x210f
74 	#define mmDP0_DP_DPHY_INTERNAL_CTRL_BASE_IDX	2
75 	#define mmDP1_DP_DPHY_INTERNAL_CTRL		0x220f
76 	#define mmDP1_DP_DPHY_INTERNAL_CTRL_BASE_IDX	2
77 	#define mmDP2_DP_DPHY_INTERNAL_CTRL		0x230f
78 	#define mmDP2_DP_DPHY_INTERNAL_CTRL_BASE_IDX	2
79 	#define mmDP3_DP_DPHY_INTERNAL_CTRL		0x240f
80 	#define mmDP3_DP_DPHY_INTERNAL_CTRL_BASE_IDX	2
81 	#define mmDP4_DP_DPHY_INTERNAL_CTRL		0x250f
82 	#define mmDP4_DP_DPHY_INTERNAL_CTRL_BASE_IDX	2
83 	#define mmDP5_DP_DPHY_INTERNAL_CTRL		0x260f
84 	#define mmDP5_DP_DPHY_INTERNAL_CTRL_BASE_IDX	2
85 	#define mmDP6_DP_DPHY_INTERNAL_CTRL		0x270f
86 	#define mmDP6_DP_DPHY_INTERNAL_CTRL_BASE_IDX	2
87 #endif
88 
89 enum dce120_clk_src_array_id {
90 	DCE120_CLK_SRC_PLL0,
91 	DCE120_CLK_SRC_PLL1,
92 	DCE120_CLK_SRC_PLL2,
93 	DCE120_CLK_SRC_PLL3,
94 	DCE120_CLK_SRC_PLL4,
95 	DCE120_CLK_SRC_PLL5,
96 
97 	DCE120_CLK_SRC_TOTAL
98 };
99 
100 static const struct dce110_timing_generator_offsets dce120_tg_offsets[] = {
101 	{
102 		.crtc = (mmCRTC0_CRTC_CONTROL - mmCRTC0_CRTC_CONTROL),
103 	},
104 	{
105 		.crtc = (mmCRTC1_CRTC_CONTROL - mmCRTC0_CRTC_CONTROL),
106 	},
107 	{
108 		.crtc = (mmCRTC2_CRTC_CONTROL - mmCRTC0_CRTC_CONTROL),
109 	},
110 	{
111 		.crtc = (mmCRTC3_CRTC_CONTROL - mmCRTC0_CRTC_CONTROL),
112 	},
113 	{
114 		.crtc = (mmCRTC4_CRTC_CONTROL - mmCRTC0_CRTC_CONTROL),
115 	},
116 	{
117 		.crtc = (mmCRTC5_CRTC_CONTROL - mmCRTC0_CRTC_CONTROL),
118 	}
119 };
120 
121 /* begin *********************
122  * macros to expend register list macro defined in HW object header file */
123 
124 #define BASE_INNER(seg) \
125 	DCE_BASE__INST0_SEG ## seg
126 
127 #define NBIO_BASE_INNER(seg) \
128 	NBIF_BASE__INST0_SEG ## seg
129 
130 #define NBIO_BASE(seg) \
131 	NBIO_BASE_INNER(seg)
132 
133 /* compile time expand base address. */
134 #define BASE(seg) \
135 	BASE_INNER(seg)
136 
137 #define SR(reg_name)\
138 		.reg_name = BASE(mm ## reg_name ## _BASE_IDX) +  \
139 					mm ## reg_name
140 
141 #define SRI(reg_name, block, id)\
142 	.reg_name = BASE(mm ## block ## id ## _ ## reg_name ## _BASE_IDX) + \
143 					mm ## block ## id ## _ ## reg_name
144 
145 /* MMHUB */
146 #define MMHUB_BASE_INNER(seg) \
147 	MMHUB_BASE__INST0_SEG ## seg
148 
149 #define MMHUB_BASE(seg) \
150 	MMHUB_BASE_INNER(seg)
151 
152 #define MMHUB_SR(reg_name)\
153 		.reg_name = MMHUB_BASE(mm ## reg_name ## _BASE_IDX) +  \
154 					mm ## reg_name
155 
156 /* macros to expend register list macro defined in HW object header file
157  * end *********************/
158 
159 
160 static const struct dce_dmcu_registers dmcu_regs = {
161 		DMCU_DCE110_COMMON_REG_LIST()
162 };
163 
164 static const struct dce_dmcu_shift dmcu_shift = {
165 		DMCU_MASK_SH_LIST_DCE110(__SHIFT)
166 };
167 
168 static const struct dce_dmcu_mask dmcu_mask = {
169 		DMCU_MASK_SH_LIST_DCE110(_MASK)
170 };
171 
172 static const struct dce_abm_registers abm_regs = {
173 		ABM_DCE110_COMMON_REG_LIST()
174 };
175 
176 static const struct dce_abm_shift abm_shift = {
177 		ABM_MASK_SH_LIST_DCE110(__SHIFT)
178 };
179 
180 static const struct dce_abm_mask abm_mask = {
181 		ABM_MASK_SH_LIST_DCE110(_MASK)
182 };
183 
184 #define ipp_regs(id)\
185 [id] = {\
186 		IPP_DCE110_REG_LIST_DCE_BASE(id)\
187 }
188 
189 static const struct dce_ipp_registers ipp_regs[] = {
190 		ipp_regs(0),
191 		ipp_regs(1),
192 		ipp_regs(2),
193 		ipp_regs(3),
194 		ipp_regs(4),
195 		ipp_regs(5)
196 };
197 
198 static const struct dce_ipp_shift ipp_shift = {
199 		IPP_DCE120_MASK_SH_LIST_SOC_BASE(__SHIFT)
200 };
201 
202 static const struct dce_ipp_mask ipp_mask = {
203 		IPP_DCE120_MASK_SH_LIST_SOC_BASE(_MASK)
204 };
205 
206 #define transform_regs(id)\
207 [id] = {\
208 		XFM_COMMON_REG_LIST_DCE110(id)\
209 }
210 
211 static const struct dce_transform_registers xfm_regs[] = {
212 		transform_regs(0),
213 		transform_regs(1),
214 		transform_regs(2),
215 		transform_regs(3),
216 		transform_regs(4),
217 		transform_regs(5)
218 };
219 
220 static const struct dce_transform_shift xfm_shift = {
221 		XFM_COMMON_MASK_SH_LIST_SOC_BASE(__SHIFT)
222 };
223 
224 static const struct dce_transform_mask xfm_mask = {
225 		XFM_COMMON_MASK_SH_LIST_SOC_BASE(_MASK)
226 };
227 
228 #define aux_regs(id)\
229 [id] = {\
230 	AUX_REG_LIST(id)\
231 }
232 
233 static const struct dce110_link_enc_aux_registers link_enc_aux_regs[] = {
234 		aux_regs(0),
235 		aux_regs(1),
236 		aux_regs(2),
237 		aux_regs(3),
238 		aux_regs(4),
239 		aux_regs(5)
240 };
241 
242 #define hpd_regs(id)\
243 [id] = {\
244 	HPD_REG_LIST(id)\
245 }
246 
247 static const struct dce110_link_enc_hpd_registers link_enc_hpd_regs[] = {
248 		hpd_regs(0),
249 		hpd_regs(1),
250 		hpd_regs(2),
251 		hpd_regs(3),
252 		hpd_regs(4),
253 		hpd_regs(5)
254 };
255 
256 #define link_regs(id)\
257 [id] = {\
258 	LE_DCE120_REG_LIST(id), \
259 	SRI(DP_DPHY_INTERNAL_CTRL, DP, id) \
260 }
261 
262 static const struct dce110_link_enc_registers link_enc_regs[] = {
263 	link_regs(0),
264 	link_regs(1),
265 	link_regs(2),
266 	link_regs(3),
267 	link_regs(4),
268 	link_regs(5),
269 	link_regs(6),
270 };
271 
272 
273 #define stream_enc_regs(id)\
274 [id] = {\
275 	SE_COMMON_REG_LIST(id),\
276 	.TMDS_CNTL = 0,\
277 }
278 
279 static const struct dce110_stream_enc_registers stream_enc_regs[] = {
280 	stream_enc_regs(0),
281 	stream_enc_regs(1),
282 	stream_enc_regs(2),
283 	stream_enc_regs(3),
284 	stream_enc_regs(4),
285 	stream_enc_regs(5)
286 };
287 
288 static const struct dce_stream_encoder_shift se_shift = {
289 		SE_COMMON_MASK_SH_LIST_DCE120(__SHIFT)
290 };
291 
292 static const struct dce_stream_encoder_mask se_mask = {
293 		SE_COMMON_MASK_SH_LIST_DCE120(_MASK)
294 };
295 
296 static const struct dce_panel_cntl_registers panel_cntl_regs[] = {
297 	{ DCE_PANEL_CNTL_REG_LIST() }
298 };
299 
300 static const struct dce_panel_cntl_shift panel_cntl_shift = {
301 	DCE_PANEL_CNTL_MASK_SH_LIST(__SHIFT)
302 };
303 
304 static const struct dce_panel_cntl_mask panel_cntl_mask = {
305 	DCE_PANEL_CNTL_MASK_SH_LIST(_MASK)
306 };
307 
308 static const struct dce110_aux_registers_shift aux_shift = {
309 	DCE12_AUX_MASK_SH_LIST(__SHIFT)
310 };
311 
312 static const struct dce110_aux_registers_mask aux_mask = {
313 	DCE12_AUX_MASK_SH_LIST(_MASK)
314 };
315 
316 #define opp_regs(id)\
317 [id] = {\
318 	OPP_DCE_120_REG_LIST(id),\
319 }
320 
321 static const struct dce_opp_registers opp_regs[] = {
322 	opp_regs(0),
323 	opp_regs(1),
324 	opp_regs(2),
325 	opp_regs(3),
326 	opp_regs(4),
327 	opp_regs(5)
328 };
329 
330 static const struct dce_opp_shift opp_shift = {
331 	OPP_COMMON_MASK_SH_LIST_DCE_120(__SHIFT)
332 };
333 
334 static const struct dce_opp_mask opp_mask = {
335 	OPP_COMMON_MASK_SH_LIST_DCE_120(_MASK)
336 };
337  #define aux_engine_regs(id)\
338 [id] = {\
339 	AUX_COMMON_REG_LIST(id), \
340 	.AUX_RESET_MASK = 0 \
341 }
342 
343 static const struct dce110_aux_registers aux_engine_regs[] = {
344 		aux_engine_regs(0),
345 		aux_engine_regs(1),
346 		aux_engine_regs(2),
347 		aux_engine_regs(3),
348 		aux_engine_regs(4),
349 		aux_engine_regs(5)
350 };
351 
352 #define audio_regs(id)\
353 [id] = {\
354 	AUD_COMMON_REG_LIST(id)\
355 }
356 
357 static const struct dce_audio_registers audio_regs[] = {
358 	audio_regs(0),
359 	audio_regs(1),
360 	audio_regs(2),
361 	audio_regs(3),
362 	audio_regs(4),
363 	audio_regs(5),
364 	audio_regs(6),
365 };
366 
367 #define DCE120_AUD_COMMON_MASK_SH_LIST(mask_sh)\
368 		SF(AZF0ENDPOINT0_AZALIA_F0_CODEC_ENDPOINT_INDEX, AZALIA_ENDPOINT_REG_INDEX, mask_sh),\
369 		SF(AZF0ENDPOINT0_AZALIA_F0_CODEC_ENDPOINT_DATA, AZALIA_ENDPOINT_REG_DATA, mask_sh),\
370 		AUD_COMMON_MASK_SH_LIST_BASE(mask_sh)
371 
372 static const struct dce_audio_shift audio_shift = {
373 		DCE120_AUD_COMMON_MASK_SH_LIST(__SHIFT)
374 };
375 
376 static const struct dce_audio_mask audio_mask = {
377 		DCE120_AUD_COMMON_MASK_SH_LIST(_MASK)
378 };
379 
map_transmitter_id_to_phy_instance(enum transmitter transmitter)380 static int map_transmitter_id_to_phy_instance(
381 	enum transmitter transmitter)
382 {
383 	switch (transmitter) {
384 	case TRANSMITTER_UNIPHY_A:
385 		return 0;
386 	case TRANSMITTER_UNIPHY_B:
387 		return 1;
388 	case TRANSMITTER_UNIPHY_C:
389 		return 2;
390 	case TRANSMITTER_UNIPHY_D:
391 		return 3;
392 	case TRANSMITTER_UNIPHY_E:
393 		return 4;
394 	case TRANSMITTER_UNIPHY_F:
395 		return 5;
396 	case TRANSMITTER_UNIPHY_G:
397 		return 6;
398 	default:
399 		ASSERT(0);
400 		return 0;
401 	}
402 }
403 
404 #define clk_src_regs(index, id)\
405 [index] = {\
406 	CS_COMMON_REG_LIST_DCE_112(id),\
407 }
408 
409 static const struct dce110_clk_src_regs clk_src_regs[] = {
410 	clk_src_regs(0, A),
411 	clk_src_regs(1, B),
412 	clk_src_regs(2, C),
413 	clk_src_regs(3, D),
414 	clk_src_regs(4, E),
415 	clk_src_regs(5, F)
416 };
417 
418 static const struct dce110_clk_src_shift cs_shift = {
419 		CS_COMMON_MASK_SH_LIST_DCE_112(__SHIFT)
420 };
421 
422 static const struct dce110_clk_src_mask cs_mask = {
423 		CS_COMMON_MASK_SH_LIST_DCE_112(_MASK)
424 };
425 
dce120_opp_create(struct dc_context * ctx,uint32_t inst)426 static struct output_pixel_processor *dce120_opp_create(
427 	struct dc_context *ctx,
428 	uint32_t inst)
429 {
430 	struct dce110_opp *opp =
431 		kzalloc(sizeof(struct dce110_opp), GFP_KERNEL);
432 
433 	if (!opp)
434 		return NULL;
435 
436 	dce110_opp_construct(opp,
437 			     ctx, inst, &opp_regs[inst], &opp_shift, &opp_mask);
438 	return &opp->base;
439 }
dce120_aux_engine_create(struct dc_context * ctx,uint32_t inst)440 static struct dce_aux *dce120_aux_engine_create(
441 	struct dc_context *ctx,
442 	uint32_t inst)
443 {
444 	struct aux_engine_dce110 *aux_engine =
445 		kzalloc(sizeof(struct aux_engine_dce110), GFP_KERNEL);
446 
447 	if (!aux_engine)
448 		return NULL;
449 
450 	dce110_aux_engine_construct(aux_engine, ctx, inst,
451 				    SW_AUX_TIMEOUT_PERIOD_MULTIPLIER * AUX_TIMEOUT_PERIOD,
452 				    &aux_engine_regs[inst],
453 					&aux_mask,
454 					&aux_shift,
455 					ctx->dc->caps.extended_aux_timeout_support);
456 
457 	return &aux_engine->base;
458 }
459 #define i2c_inst_regs(id) { I2C_HW_ENGINE_COMMON_REG_LIST(id) }
460 
461 static const struct dce_i2c_registers i2c_hw_regs[] = {
462 		i2c_inst_regs(1),
463 		i2c_inst_regs(2),
464 		i2c_inst_regs(3),
465 		i2c_inst_regs(4),
466 		i2c_inst_regs(5),
467 		i2c_inst_regs(6),
468 };
469 
470 static const struct dce_i2c_shift i2c_shifts = {
471 		I2C_COMMON_MASK_SH_LIST_DCE110(__SHIFT)
472 };
473 
474 static const struct dce_i2c_mask i2c_masks = {
475 		I2C_COMMON_MASK_SH_LIST_DCE110(_MASK)
476 };
477 
dce120_i2c_hw_create(struct dc_context * ctx,uint32_t inst)478 static struct dce_i2c_hw *dce120_i2c_hw_create(
479 	struct dc_context *ctx,
480 	uint32_t inst)
481 {
482 	struct dce_i2c_hw *dce_i2c_hw =
483 		kzalloc(sizeof(struct dce_i2c_hw), GFP_KERNEL);
484 
485 	if (!dce_i2c_hw)
486 		return NULL;
487 
488 	dce112_i2c_hw_construct(dce_i2c_hw, ctx, inst,
489 				    &i2c_hw_regs[inst], &i2c_shifts, &i2c_masks);
490 
491 	return dce_i2c_hw;
492 }
493 static const struct bios_registers bios_regs = {
494 	.BIOS_SCRATCH_3 = mmBIOS_SCRATCH_3 + NBIO_BASE(mmBIOS_SCRATCH_3_BASE_IDX),
495 	.BIOS_SCRATCH_6 = mmBIOS_SCRATCH_6 + NBIO_BASE(mmBIOS_SCRATCH_6_BASE_IDX)
496 };
497 
498 static const struct resource_caps res_cap = {
499 		.num_timing_generator = 6,
500 		.num_audio = 7,
501 		.num_stream_encoder = 6,
502 		.num_pll = 6,
503 		.num_ddc = 6,
504 };
505 
506 static const struct dc_plane_cap plane_cap = {
507 	.type = DC_PLANE_TYPE_DCE_RGB,
508 
509 	.pixel_format_support = {
510 			.argb8888 = true,
511 			.nv12 = false,
512 			.fp16 = true
513 	},
514 
515 	.max_upscale_factor = {
516 			.argb8888 = 16000,
517 			.nv12 = 1,
518 			.fp16 = 1
519 	},
520 
521 	.max_downscale_factor = {
522 			.argb8888 = 250,
523 			.nv12 = 1,
524 			.fp16 = 1
525 	}
526 };
527 
528 static const struct dc_debug_options debug_defaults = {
529 		.disable_clock_gate = true,
530 		.enable_legacy_fast_update = true,
531 };
532 
dce120_clock_source_create(struct dc_context * ctx,struct dc_bios * bios,enum clock_source_id id,const struct dce110_clk_src_regs * regs,bool dp_clk_src)533 static struct clock_source *dce120_clock_source_create(
534 	struct dc_context *ctx,
535 	struct dc_bios *bios,
536 	enum clock_source_id id,
537 	const struct dce110_clk_src_regs *regs,
538 	bool dp_clk_src)
539 {
540 	struct dce110_clk_src *clk_src =
541 		kzalloc(sizeof(*clk_src), GFP_KERNEL);
542 
543 	if (!clk_src)
544 		return NULL;
545 
546 	if (dce112_clk_src_construct(clk_src, ctx, bios, id,
547 				     regs, &cs_shift, &cs_mask)) {
548 		clk_src->base.dp_clk_src = dp_clk_src;
549 		return &clk_src->base;
550 	}
551 
552 	kfree(clk_src);
553 	BREAK_TO_DEBUGGER();
554 	return NULL;
555 }
556 
dce120_clock_source_destroy(struct clock_source ** clk_src)557 static void dce120_clock_source_destroy(struct clock_source **clk_src)
558 {
559 	kfree(TO_DCE110_CLK_SRC(*clk_src));
560 	*clk_src = NULL;
561 }
562 
563 
dce120_hw_sequencer_create(struct dc * dc)564 static bool dce120_hw_sequencer_create(struct dc *dc)
565 {
566 	/* All registers used by dce11.2 match those in dce11 in offset and
567 	 * structure
568 	 */
569 	dce120_hw_sequencer_construct(dc);
570 
571 	/*TODO	Move to separate file and Override what is needed */
572 
573 	return true;
574 }
575 
dce120_timing_generator_create(struct dc_context * ctx,uint32_t instance,const struct dce110_timing_generator_offsets * offsets)576 static struct timing_generator *dce120_timing_generator_create(
577 		struct dc_context *ctx,
578 		uint32_t instance,
579 		const struct dce110_timing_generator_offsets *offsets)
580 {
581 	struct dce110_timing_generator *tg110 =
582 		kzalloc(sizeof(struct dce110_timing_generator), GFP_KERNEL);
583 
584 	if (!tg110)
585 		return NULL;
586 
587 	dce120_timing_generator_construct(tg110, ctx, instance, offsets);
588 	return &tg110->base;
589 }
590 
dce120_transform_destroy(struct transform ** xfm)591 static void dce120_transform_destroy(struct transform **xfm)
592 {
593 	kfree(TO_DCE_TRANSFORM(*xfm));
594 	*xfm = NULL;
595 }
596 
dce120_resource_destruct(struct dce110_resource_pool * pool)597 static void dce120_resource_destruct(struct dce110_resource_pool *pool)
598 {
599 	unsigned int i;
600 
601 	for (i = 0; i < pool->base.pipe_count; i++) {
602 		if (pool->base.opps[i] != NULL)
603 			dce110_opp_destroy(&pool->base.opps[i]);
604 
605 		if (pool->base.transforms[i] != NULL)
606 			dce120_transform_destroy(&pool->base.transforms[i]);
607 
608 		if (pool->base.ipps[i] != NULL)
609 			dce_ipp_destroy(&pool->base.ipps[i]);
610 
611 		if (pool->base.mis[i] != NULL) {
612 			kfree(TO_DCE_MEM_INPUT(pool->base.mis[i]));
613 			pool->base.mis[i] = NULL;
614 		}
615 
616 		if (pool->base.irqs != NULL) {
617 			dal_irq_service_destroy(&pool->base.irqs);
618 		}
619 
620 		if (pool->base.timing_generators[i] != NULL) {
621 			kfree(DCE110TG_FROM_TG(pool->base.timing_generators[i]));
622 			pool->base.timing_generators[i] = NULL;
623 		}
624 	}
625 
626 	for (i = 0; i < pool->base.res_cap->num_ddc; i++) {
627 		if (pool->base.engines[i] != NULL)
628 			dce110_engine_destroy(&pool->base.engines[i]);
629 		if (pool->base.hw_i2cs[i] != NULL) {
630 			kfree(pool->base.hw_i2cs[i]);
631 			pool->base.hw_i2cs[i] = NULL;
632 		}
633 		if (pool->base.sw_i2cs[i] != NULL) {
634 			kfree(pool->base.sw_i2cs[i]);
635 			pool->base.sw_i2cs[i] = NULL;
636 		}
637 	}
638 
639 	for (i = 0; i < pool->base.audio_count; i++) {
640 		if (pool->base.audios[i])
641 			dce_aud_destroy(&pool->base.audios[i]);
642 	}
643 
644 	for (i = 0; i < pool->base.stream_enc_count; i++) {
645 		if (pool->base.stream_enc[i] != NULL)
646 			kfree(DCE110STRENC_FROM_STRENC(pool->base.stream_enc[i]));
647 	}
648 
649 	for (i = 0; i < pool->base.clk_src_count; i++) {
650 		if (pool->base.clock_sources[i] != NULL)
651 			dce120_clock_source_destroy(
652 				&pool->base.clock_sources[i]);
653 	}
654 
655 	if (pool->base.dp_clock_source != NULL)
656 		dce120_clock_source_destroy(&pool->base.dp_clock_source);
657 
658 	if (pool->base.abm != NULL)
659 		dce_abm_destroy(&pool->base.abm);
660 
661 	if (pool->base.dmcu != NULL)
662 		dce_dmcu_destroy(&pool->base.dmcu);
663 
664 	if (pool->base.oem_device != NULL) {
665 		struct dc *dc = pool->base.oem_device->ctx->dc;
666 
667 		dc->link_srv->destroy_ddc_service(&pool->base.oem_device);
668 	}
669 }
670 
read_dce_straps(struct dc_context * ctx,struct resource_straps * straps)671 static void read_dce_straps(
672 	struct dc_context *ctx,
673 	struct resource_straps *straps)
674 {
675 	uint32_t reg_val = dm_read_reg_soc15(ctx, mmCC_DC_MISC_STRAPS, 0);
676 
677 	straps->audio_stream_number = get_reg_field_value(reg_val,
678 							  CC_DC_MISC_STRAPS,
679 							  AUDIO_STREAM_NUMBER);
680 	straps->hdmi_disable = get_reg_field_value(reg_val,
681 						   CC_DC_MISC_STRAPS,
682 						   HDMI_DISABLE);
683 
684 	reg_val = dm_read_reg_soc15(ctx, mmDC_PINSTRAPS, 0);
685 	straps->dc_pinstraps_audio = get_reg_field_value(reg_val,
686 							 DC_PINSTRAPS,
687 							 DC_PINSTRAPS_AUDIO);
688 }
689 
create_audio(struct dc_context * ctx,unsigned int inst)690 static struct audio *create_audio(
691 		struct dc_context *ctx, unsigned int inst)
692 {
693 	return dce_audio_create(ctx, inst,
694 			&audio_regs[inst], &audio_shift, &audio_mask);
695 }
696 
697 static const struct encoder_feature_support link_enc_feature = {
698 		.max_hdmi_deep_color = COLOR_DEPTH_121212,
699 		.max_hdmi_pixel_clock = 600000,
700 		.hdmi_ycbcr420_supported = true,
701 		.dp_ycbcr420_supported = false,
702 		.flags.bits.IS_HBR2_CAPABLE = true,
703 		.flags.bits.IS_HBR3_CAPABLE = true,
704 		.flags.bits.IS_TPS3_CAPABLE = true,
705 		.flags.bits.IS_TPS4_CAPABLE = true,
706 };
707 
dce120_link_encoder_create(struct dc_context * ctx,const struct encoder_init_data * enc_init_data)708 static struct link_encoder *dce120_link_encoder_create(
709 	struct dc_context *ctx,
710 	const struct encoder_init_data *enc_init_data)
711 {
712 	struct dce110_link_encoder *enc110 =
713 		kzalloc(sizeof(struct dce110_link_encoder), GFP_KERNEL);
714 	int link_regs_id;
715 
716 	if (!enc110 || enc_init_data->hpd_source >= ARRAY_SIZE(link_enc_hpd_regs))
717 		return NULL;
718 
719 	link_regs_id =
720 		map_transmitter_id_to_phy_instance(enc_init_data->transmitter);
721 
722 	dce110_link_encoder_construct(enc110,
723 				      enc_init_data,
724 				      &link_enc_feature,
725 				      &link_enc_regs[link_regs_id],
726 				      &link_enc_aux_regs[enc_init_data->channel - 1],
727 				      &link_enc_hpd_regs[enc_init_data->hpd_source]);
728 
729 	return &enc110->base;
730 }
731 
dce120_panel_cntl_create(const struct panel_cntl_init_data * init_data)732 static struct panel_cntl *dce120_panel_cntl_create(const struct panel_cntl_init_data *init_data)
733 {
734 	struct dce_panel_cntl *panel_cntl =
735 		kzalloc(sizeof(struct dce_panel_cntl), GFP_KERNEL);
736 
737 	if (!panel_cntl)
738 		return NULL;
739 
740 	dce_panel_cntl_construct(panel_cntl,
741 			init_data,
742 			&panel_cntl_regs[init_data->inst],
743 			&panel_cntl_shift,
744 			&panel_cntl_mask);
745 
746 	return &panel_cntl->base;
747 }
748 
dce120_ipp_create(struct dc_context * ctx,uint32_t inst)749 static struct input_pixel_processor *dce120_ipp_create(
750 	struct dc_context *ctx, uint32_t inst)
751 {
752 	struct dce_ipp *ipp = kzalloc(sizeof(struct dce_ipp), GFP_KERNEL);
753 
754 	if (!ipp) {
755 		BREAK_TO_DEBUGGER();
756 		return NULL;
757 	}
758 
759 	dce_ipp_construct(ipp, ctx, inst,
760 			&ipp_regs[inst], &ipp_shift, &ipp_mask);
761 	return &ipp->base;
762 }
763 
dce120_stream_encoder_create(enum engine_id eng_id,struct dc_context * ctx)764 static struct stream_encoder *dce120_stream_encoder_create(
765 	enum engine_id eng_id,
766 	struct dc_context *ctx)
767 {
768 	struct dce110_stream_encoder *enc110 =
769 		kzalloc(sizeof(struct dce110_stream_encoder), GFP_KERNEL);
770 
771 	if (!enc110)
772 		return NULL;
773 
774 	dce110_stream_encoder_construct(enc110, ctx, ctx->dc_bios, eng_id,
775 					&stream_enc_regs[eng_id],
776 					&se_shift, &se_mask);
777 	return &enc110->base;
778 }
779 
780 #define SRII(reg_name, block, id)\
781 	.reg_name[id] = BASE(mm ## block ## id ## _ ## reg_name ## _BASE_IDX) + \
782 					mm ## block ## id ## _ ## reg_name
783 
784 static const struct dce_hwseq_registers hwseq_reg = {
785 		HWSEQ_DCE120_REG_LIST()
786 };
787 
788 static const struct dce_hwseq_shift hwseq_shift = {
789 		HWSEQ_DCE12_MASK_SH_LIST(__SHIFT)
790 };
791 
792 static const struct dce_hwseq_mask hwseq_mask = {
793 		HWSEQ_DCE12_MASK_SH_LIST(_MASK)
794 };
795 
796 /* HWSEQ regs for VG20 */
797 static const struct dce_hwseq_registers dce121_hwseq_reg = {
798 		HWSEQ_VG20_REG_LIST()
799 };
800 
801 static const struct dce_hwseq_shift dce121_hwseq_shift = {
802 		HWSEQ_VG20_MASK_SH_LIST(__SHIFT)
803 };
804 
805 static const struct dce_hwseq_mask dce121_hwseq_mask = {
806 		HWSEQ_VG20_MASK_SH_LIST(_MASK)
807 };
808 
dce120_hwseq_create(struct dc_context * ctx)809 static struct dce_hwseq *dce120_hwseq_create(
810 	struct dc_context *ctx)
811 {
812 	struct dce_hwseq *hws = kzalloc(sizeof(struct dce_hwseq), GFP_KERNEL);
813 
814 	if (hws) {
815 		hws->ctx = ctx;
816 		hws->regs = &hwseq_reg;
817 		hws->shifts = &hwseq_shift;
818 		hws->masks = &hwseq_mask;
819 	}
820 	return hws;
821 }
822 
dce121_hwseq_create(struct dc_context * ctx)823 static struct dce_hwseq *dce121_hwseq_create(
824 	struct dc_context *ctx)
825 {
826 	struct dce_hwseq *hws = kzalloc(sizeof(struct dce_hwseq), GFP_KERNEL);
827 
828 	if (hws) {
829 		hws->ctx = ctx;
830 		hws->regs = &dce121_hwseq_reg;
831 		hws->shifts = &dce121_hwseq_shift;
832 		hws->masks = &dce121_hwseq_mask;
833 	}
834 	return hws;
835 }
836 
837 static const struct resource_create_funcs res_create_funcs = {
838 	.read_dce_straps = read_dce_straps,
839 	.create_audio = create_audio,
840 	.create_stream_encoder = dce120_stream_encoder_create,
841 	.create_hwseq = dce120_hwseq_create,
842 };
843 
844 static const struct resource_create_funcs dce121_res_create_funcs = {
845 	.read_dce_straps = read_dce_straps,
846 	.create_audio = create_audio,
847 	.create_stream_encoder = dce120_stream_encoder_create,
848 	.create_hwseq = dce121_hwseq_create,
849 };
850 
851 
852 #define mi_inst_regs(id) { MI_DCE12_REG_LIST(id) }
853 static const struct dce_mem_input_registers mi_regs[] = {
854 		mi_inst_regs(0),
855 		mi_inst_regs(1),
856 		mi_inst_regs(2),
857 		mi_inst_regs(3),
858 		mi_inst_regs(4),
859 		mi_inst_regs(5),
860 };
861 
862 static const struct dce_mem_input_shift mi_shifts = {
863 		MI_DCE12_MASK_SH_LIST(__SHIFT)
864 };
865 
866 static const struct dce_mem_input_mask mi_masks = {
867 		MI_DCE12_MASK_SH_LIST(_MASK)
868 };
869 
dce120_mem_input_create(struct dc_context * ctx,uint32_t inst)870 static struct mem_input *dce120_mem_input_create(
871 	struct dc_context *ctx,
872 	uint32_t inst)
873 {
874 	struct dce_mem_input *dce_mi = kzalloc(sizeof(struct dce_mem_input),
875 					       GFP_KERNEL);
876 
877 	if (!dce_mi) {
878 		BREAK_TO_DEBUGGER();
879 		return NULL;
880 	}
881 
882 	dce120_mem_input_construct(dce_mi, ctx, inst, &mi_regs[inst], &mi_shifts, &mi_masks);
883 	return &dce_mi->base;
884 }
885 
dce120_transform_create(struct dc_context * ctx,uint32_t inst)886 static struct transform *dce120_transform_create(
887 	struct dc_context *ctx,
888 	uint32_t inst)
889 {
890 	struct dce_transform *transform =
891 		kzalloc(sizeof(struct dce_transform), GFP_KERNEL);
892 
893 	if (!transform)
894 		return NULL;
895 
896 	dce_transform_construct(transform, ctx, inst,
897 				&xfm_regs[inst], &xfm_shift, &xfm_mask);
898 	transform->lb_memory_size = 0x1404; /*5124*/
899 	return &transform->base;
900 }
901 
dce120_destroy_resource_pool(struct resource_pool ** pool)902 static void dce120_destroy_resource_pool(struct resource_pool **pool)
903 {
904 	struct dce110_resource_pool *dce110_pool = TO_DCE110_RES_POOL(*pool);
905 
906 	dce120_resource_destruct(dce110_pool);
907 	kfree(dce110_pool);
908 	*pool = NULL;
909 }
910 
911 static const struct resource_funcs dce120_res_pool_funcs = {
912 	.destroy = dce120_destroy_resource_pool,
913 	.link_enc_create = dce120_link_encoder_create,
914 	.panel_cntl_create = dce120_panel_cntl_create,
915 	.validate_bandwidth = dce112_validate_bandwidth,
916 	.validate_plane = dce100_validate_plane,
917 	.add_stream_to_ctx = dce112_add_stream_to_ctx,
918 	.find_first_free_match_stream_enc_for_link = dce110_find_first_free_match_stream_enc_for_link
919 };
920 
bw_calcs_data_update_from_pplib(struct dc * dc)921 static void bw_calcs_data_update_from_pplib(struct dc *dc)
922 {
923 	struct dm_pp_clock_levels_with_latency eng_clks = {0};
924 	struct dm_pp_clock_levels_with_latency mem_clks = {0};
925 	struct dm_pp_wm_sets_with_clock_ranges clk_ranges = {0};
926 	int i;
927 	unsigned int clk;
928 	unsigned int latency;
929 	/*original logic in dal3*/
930 	int memory_type_multiplier = MEMORY_TYPE_MULTIPLIER_CZ;
931 
932 	/*do system clock*/
933 	if (!dm_pp_get_clock_levels_by_type_with_latency(
934 				dc->ctx,
935 				DM_PP_CLOCK_TYPE_ENGINE_CLK,
936 				&eng_clks) || eng_clks.num_levels == 0) {
937 
938 		eng_clks.num_levels = 8;
939 		clk = 300000;
940 
941 		for (i = 0; i < eng_clks.num_levels; i++) {
942 			eng_clks.data[i].clocks_in_khz = clk;
943 			clk += 100000;
944 		}
945 	}
946 
947 	/* convert all the clock fro kHz to fix point mHz  TODO: wloop data */
948 	dc->bw_vbios->high_sclk = bw_frc_to_fixed(
949 		eng_clks.data[eng_clks.num_levels-1].clocks_in_khz, 1000);
950 	dc->bw_vbios->mid1_sclk  = bw_frc_to_fixed(
951 		eng_clks.data[eng_clks.num_levels/8].clocks_in_khz, 1000);
952 	dc->bw_vbios->mid2_sclk  = bw_frc_to_fixed(
953 		eng_clks.data[eng_clks.num_levels*2/8].clocks_in_khz, 1000);
954 	dc->bw_vbios->mid3_sclk  = bw_frc_to_fixed(
955 		eng_clks.data[eng_clks.num_levels*3/8].clocks_in_khz, 1000);
956 	dc->bw_vbios->mid4_sclk  = bw_frc_to_fixed(
957 		eng_clks.data[eng_clks.num_levels*4/8].clocks_in_khz, 1000);
958 	dc->bw_vbios->mid5_sclk  = bw_frc_to_fixed(
959 		eng_clks.data[eng_clks.num_levels*5/8].clocks_in_khz, 1000);
960 	dc->bw_vbios->mid6_sclk  = bw_frc_to_fixed(
961 		eng_clks.data[eng_clks.num_levels*6/8].clocks_in_khz, 1000);
962 	dc->bw_vbios->low_sclk  = bw_frc_to_fixed(
963 			eng_clks.data[0].clocks_in_khz, 1000);
964 
965 	/*do memory clock*/
966 	if (!dm_pp_get_clock_levels_by_type_with_latency(
967 			dc->ctx,
968 			DM_PP_CLOCK_TYPE_MEMORY_CLK,
969 			&mem_clks) || mem_clks.num_levels == 0) {
970 
971 		mem_clks.num_levels = 3;
972 		clk = 250000;
973 		latency = 45;
974 
975 		for (i = 0; i < eng_clks.num_levels; i++) {
976 			mem_clks.data[i].clocks_in_khz = clk;
977 			mem_clks.data[i].latency_in_us = latency;
978 			clk += 500000;
979 			latency -= 5;
980 		}
981 
982 	}
983 
984 	/* we don't need to call PPLIB for validation clock since they
985 	 * also give us the highest sclk and highest mclk (UMA clock).
986 	 * ALSO always convert UMA clock (from PPLIB)  to YCLK (HW formula):
987 	 * YCLK = UMACLK*m_memoryTypeMultiplier
988 	 */
989 	if (dc->bw_vbios->memory_type == bw_def_hbm)
990 		memory_type_multiplier = MEMORY_TYPE_HBM;
991 
992 	dc->bw_vbios->low_yclk = bw_frc_to_fixed(
993 		mem_clks.data[0].clocks_in_khz * memory_type_multiplier, 1000);
994 	dc->bw_vbios->mid_yclk = bw_frc_to_fixed(
995 		mem_clks.data[mem_clks.num_levels>>1].clocks_in_khz * memory_type_multiplier,
996 		1000);
997 	dc->bw_vbios->high_yclk = bw_frc_to_fixed(
998 		mem_clks.data[mem_clks.num_levels-1].clocks_in_khz * memory_type_multiplier,
999 		1000);
1000 
1001 	/* Now notify PPLib/SMU about which Watermarks sets they should select
1002 	 * depending on DPM state they are in. And update BW MGR GFX Engine and
1003 	 * Memory clock member variables for Watermarks calculations for each
1004 	 * Watermark Set
1005 	 */
1006 	clk_ranges.num_wm_sets = 4;
1007 	clk_ranges.wm_clk_ranges[0].wm_set_id = WM_SET_A;
1008 	clk_ranges.wm_clk_ranges[0].wm_min_eng_clk_in_khz =
1009 			eng_clks.data[0].clocks_in_khz;
1010 	clk_ranges.wm_clk_ranges[0].wm_max_eng_clk_in_khz =
1011 			eng_clks.data[eng_clks.num_levels*3/8].clocks_in_khz - 1;
1012 	clk_ranges.wm_clk_ranges[0].wm_min_mem_clk_in_khz =
1013 			mem_clks.data[0].clocks_in_khz;
1014 	clk_ranges.wm_clk_ranges[0].wm_max_mem_clk_in_khz =
1015 			mem_clks.data[mem_clks.num_levels>>1].clocks_in_khz - 1;
1016 
1017 	clk_ranges.wm_clk_ranges[1].wm_set_id = WM_SET_B;
1018 	clk_ranges.wm_clk_ranges[1].wm_min_eng_clk_in_khz =
1019 			eng_clks.data[eng_clks.num_levels*3/8].clocks_in_khz;
1020 	/* 5 GHz instead of data[7].clockInKHz to cover Overdrive */
1021 	clk_ranges.wm_clk_ranges[1].wm_max_eng_clk_in_khz = 5000000;
1022 	clk_ranges.wm_clk_ranges[1].wm_min_mem_clk_in_khz =
1023 			mem_clks.data[0].clocks_in_khz;
1024 	clk_ranges.wm_clk_ranges[1].wm_max_mem_clk_in_khz =
1025 			mem_clks.data[mem_clks.num_levels>>1].clocks_in_khz - 1;
1026 
1027 	clk_ranges.wm_clk_ranges[2].wm_set_id = WM_SET_C;
1028 	clk_ranges.wm_clk_ranges[2].wm_min_eng_clk_in_khz =
1029 			eng_clks.data[0].clocks_in_khz;
1030 	clk_ranges.wm_clk_ranges[2].wm_max_eng_clk_in_khz =
1031 			eng_clks.data[eng_clks.num_levels*3/8].clocks_in_khz - 1;
1032 	clk_ranges.wm_clk_ranges[2].wm_min_mem_clk_in_khz =
1033 			mem_clks.data[mem_clks.num_levels>>1].clocks_in_khz;
1034 	/* 5 GHz instead of data[2].clockInKHz to cover Overdrive */
1035 	clk_ranges.wm_clk_ranges[2].wm_max_mem_clk_in_khz = 5000000;
1036 
1037 	clk_ranges.wm_clk_ranges[3].wm_set_id = WM_SET_D;
1038 	clk_ranges.wm_clk_ranges[3].wm_min_eng_clk_in_khz =
1039 			eng_clks.data[eng_clks.num_levels*3/8].clocks_in_khz;
1040 	/* 5 GHz instead of data[7].clockInKHz to cover Overdrive */
1041 	clk_ranges.wm_clk_ranges[3].wm_max_eng_clk_in_khz = 5000000;
1042 	clk_ranges.wm_clk_ranges[3].wm_min_mem_clk_in_khz =
1043 			mem_clks.data[mem_clks.num_levels>>1].clocks_in_khz;
1044 	/* 5 GHz instead of data[2].clockInKHz to cover Overdrive */
1045 	clk_ranges.wm_clk_ranges[3].wm_max_mem_clk_in_khz = 5000000;
1046 
1047 	/* Notify PP Lib/SMU which Watermarks to use for which clock ranges */
1048 	dm_pp_notify_wm_clock_changes(dc->ctx, &clk_ranges);
1049 }
1050 
read_pipe_fuses(struct dc_context * ctx)1051 static uint32_t read_pipe_fuses(struct dc_context *ctx)
1052 {
1053 	uint32_t value = dm_read_reg_soc15(ctx, mmCC_DC_PIPE_DIS, 0);
1054 	/* VG20 support max 6 pipes */
1055 	value = value & 0x3f;
1056 	return value;
1057 }
1058 
dce120_resource_construct(uint8_t num_virtual_links,struct dc * dc,struct dce110_resource_pool * pool)1059 static bool dce120_resource_construct(
1060 	uint8_t num_virtual_links,
1061 	struct dc *dc,
1062 	struct dce110_resource_pool *pool)
1063 {
1064 	struct ddc_service_init_data ddc_init_data = {0};
1065 	unsigned int i;
1066 	int j;
1067 	struct dc_context *ctx = dc->ctx;
1068 	struct irq_service_init_data irq_init_data;
1069 	static const struct resource_create_funcs *res_funcs;
1070 	bool is_vg20 = ASICREV_IS_VEGA20_P(ctx->asic_id.hw_internal_rev);
1071 	uint32_t pipe_fuses = 0;
1072 
1073 	ctx->dc_bios->regs = &bios_regs;
1074 
1075 	pool->base.res_cap = &res_cap;
1076 	pool->base.funcs = &dce120_res_pool_funcs;
1077 
1078 	/* TODO: Fill more data from GreenlandAsicCapability.cpp */
1079 	pool->base.pipe_count = res_cap.num_timing_generator;
1080 	pool->base.timing_generator_count = pool->base.res_cap->num_timing_generator;
1081 	pool->base.underlay_pipe_index = NO_UNDERLAY_PIPE;
1082 
1083 	dc->caps.max_downscale_ratio = 200;
1084 	dc->caps.i2c_speed_in_khz = 100;
1085 	dc->caps.i2c_speed_in_khz_hdcp = 100; /*1.4 w/a not applied by default*/
1086 	dc->caps.max_cursor_size = 128;
1087 	dc->caps.min_horizontal_blanking_period = 80;
1088 	dc->caps.dual_link_dvi = true;
1089 	dc->caps.psp_setup_panel_mode = true;
1090 	dc->caps.extended_aux_timeout_support = false;
1091 	dc->debug = debug_defaults;
1092 
1093 	/*************************************************
1094 	 *  Create resources                             *
1095 	 *************************************************/
1096 
1097 	pool->base.clock_sources[DCE120_CLK_SRC_PLL0] =
1098 			dce120_clock_source_create(ctx, ctx->dc_bios,
1099 				CLOCK_SOURCE_COMBO_PHY_PLL0,
1100 				&clk_src_regs[0], false);
1101 	pool->base.clock_sources[DCE120_CLK_SRC_PLL1] =
1102 			dce120_clock_source_create(ctx, ctx->dc_bios,
1103 				CLOCK_SOURCE_COMBO_PHY_PLL1,
1104 				&clk_src_regs[1], false);
1105 	pool->base.clock_sources[DCE120_CLK_SRC_PLL2] =
1106 			dce120_clock_source_create(ctx, ctx->dc_bios,
1107 				CLOCK_SOURCE_COMBO_PHY_PLL2,
1108 				&clk_src_regs[2], false);
1109 	pool->base.clock_sources[DCE120_CLK_SRC_PLL3] =
1110 			dce120_clock_source_create(ctx, ctx->dc_bios,
1111 				CLOCK_SOURCE_COMBO_PHY_PLL3,
1112 				&clk_src_regs[3], false);
1113 	pool->base.clock_sources[DCE120_CLK_SRC_PLL4] =
1114 			dce120_clock_source_create(ctx, ctx->dc_bios,
1115 				CLOCK_SOURCE_COMBO_PHY_PLL4,
1116 				&clk_src_regs[4], false);
1117 	pool->base.clock_sources[DCE120_CLK_SRC_PLL5] =
1118 			dce120_clock_source_create(ctx, ctx->dc_bios,
1119 				CLOCK_SOURCE_COMBO_PHY_PLL5,
1120 				&clk_src_regs[5], false);
1121 	pool->base.clk_src_count = DCE120_CLK_SRC_TOTAL;
1122 
1123 	pool->base.dp_clock_source =
1124 			dce120_clock_source_create(ctx, ctx->dc_bios,
1125 				CLOCK_SOURCE_ID_DP_DTO,
1126 				&clk_src_regs[0], true);
1127 
1128 	for (i = 0; i < pool->base.clk_src_count; i++) {
1129 		if (pool->base.clock_sources[i] == NULL) {
1130 			dm_error("DC: failed to create clock sources!\n");
1131 			BREAK_TO_DEBUGGER();
1132 			goto clk_src_create_fail;
1133 		}
1134 	}
1135 
1136 	pool->base.dmcu = dce_dmcu_create(ctx,
1137 			&dmcu_regs,
1138 			&dmcu_shift,
1139 			&dmcu_mask);
1140 	if (pool->base.dmcu == NULL) {
1141 		dm_error("DC: failed to create dmcu!\n");
1142 		BREAK_TO_DEBUGGER();
1143 		goto res_create_fail;
1144 	}
1145 
1146 	pool->base.abm = dce_abm_create(ctx,
1147 			&abm_regs,
1148 			&abm_shift,
1149 			&abm_mask);
1150 	if (pool->base.abm == NULL) {
1151 		dm_error("DC: failed to create abm!\n");
1152 		BREAK_TO_DEBUGGER();
1153 		goto res_create_fail;
1154 	}
1155 
1156 
1157 	irq_init_data.ctx = dc->ctx;
1158 	pool->base.irqs = dal_irq_service_dce120_create(&irq_init_data);
1159 	if (!pool->base.irqs)
1160 		goto irqs_create_fail;
1161 
1162 	/* VG20: Pipe harvesting enabled, retrieve valid pipe fuses */
1163 	if (is_vg20)
1164 		pipe_fuses = read_pipe_fuses(ctx);
1165 
1166 	/* index to valid pipe resource */
1167 	j = 0;
1168 	for (i = 0; i < pool->base.pipe_count; i++) {
1169 		if (is_vg20) {
1170 			if ((pipe_fuses & (1 << i)) != 0) {
1171 				dm_error("DC: skip invalid pipe %d!\n", i);
1172 				continue;
1173 			}
1174 		}
1175 
1176 		pool->base.timing_generators[j] =
1177 				dce120_timing_generator_create(
1178 					ctx,
1179 					i,
1180 					&dce120_tg_offsets[i]);
1181 		if (pool->base.timing_generators[j] == NULL) {
1182 			BREAK_TO_DEBUGGER();
1183 			dm_error("DC: failed to create tg!\n");
1184 			goto controller_create_fail;
1185 		}
1186 
1187 		pool->base.mis[j] = dce120_mem_input_create(ctx, i);
1188 
1189 		if (pool->base.mis[j] == NULL) {
1190 			BREAK_TO_DEBUGGER();
1191 			dm_error(
1192 				"DC: failed to create memory input!\n");
1193 			goto controller_create_fail;
1194 		}
1195 
1196 		pool->base.ipps[j] = dce120_ipp_create(ctx, i);
1197 		if (pool->base.ipps[i] == NULL) {
1198 			BREAK_TO_DEBUGGER();
1199 			dm_error(
1200 				"DC: failed to create input pixel processor!\n");
1201 			goto controller_create_fail;
1202 		}
1203 
1204 		pool->base.transforms[j] = dce120_transform_create(ctx, i);
1205 		if (pool->base.transforms[i] == NULL) {
1206 			BREAK_TO_DEBUGGER();
1207 			dm_error(
1208 				"DC: failed to create transform!\n");
1209 			goto res_create_fail;
1210 		}
1211 
1212 		pool->base.opps[j] = dce120_opp_create(
1213 			ctx,
1214 			i);
1215 		if (pool->base.opps[j] == NULL) {
1216 			BREAK_TO_DEBUGGER();
1217 			dm_error(
1218 				"DC: failed to create output pixel processor!\n");
1219 		}
1220 
1221 		/* check next valid pipe */
1222 		j++;
1223 	}
1224 
1225 	for (i = 0; i < pool->base.res_cap->num_ddc; i++) {
1226 		pool->base.engines[i] = dce120_aux_engine_create(ctx, i);
1227 		if (pool->base.engines[i] == NULL) {
1228 			BREAK_TO_DEBUGGER();
1229 			dm_error(
1230 				"DC:failed to create aux engine!!\n");
1231 			goto res_create_fail;
1232 		}
1233 		pool->base.hw_i2cs[i] = dce120_i2c_hw_create(ctx, i);
1234 		if (pool->base.hw_i2cs[i] == NULL) {
1235 			BREAK_TO_DEBUGGER();
1236 			dm_error(
1237 				"DC:failed to create i2c engine!!\n");
1238 			goto res_create_fail;
1239 		}
1240 		pool->base.sw_i2cs[i] = NULL;
1241 	}
1242 
1243 	/* valid pipe num */
1244 	pool->base.pipe_count = j;
1245 	pool->base.timing_generator_count = j;
1246 
1247 	if (is_vg20)
1248 		res_funcs = &dce121_res_create_funcs;
1249 	else
1250 		res_funcs = &res_create_funcs;
1251 
1252 	if (!resource_construct(num_virtual_links, dc, &pool->base, res_funcs))
1253 		goto res_create_fail;
1254 
1255 	/* Create hardware sequencer */
1256 	if (!dce120_hw_sequencer_create(dc))
1257 		goto controller_create_fail;
1258 
1259 	dc->caps.max_planes =  pool->base.pipe_count;
1260 
1261 	for (i = 0; i < dc->caps.max_planes; ++i)
1262 		dc->caps.planes[i] = plane_cap;
1263 
1264 	bw_calcs_init(dc->bw_dceip, dc->bw_vbios, dc->ctx->asic_id);
1265 
1266 	bw_calcs_data_update_from_pplib(dc);
1267 
1268 	if (dc->ctx->dc_bios->fw_info.oem_i2c_present) {
1269 		ddc_init_data.ctx = dc->ctx;
1270 		ddc_init_data.link = NULL;
1271 		ddc_init_data.id.id = dc->ctx->dc_bios->fw_info.oem_i2c_obj_id;
1272 		ddc_init_data.id.enum_id = 0;
1273 		ddc_init_data.id.type = OBJECT_TYPE_GENERIC;
1274 		pool->base.oem_device = dc->link_srv->create_ddc_service(&ddc_init_data);
1275 	}
1276 
1277 	return true;
1278 
1279 irqs_create_fail:
1280 controller_create_fail:
1281 clk_src_create_fail:
1282 res_create_fail:
1283 
1284 	dce120_resource_destruct(pool);
1285 
1286 	return false;
1287 }
1288 
dce120_create_resource_pool(uint8_t num_virtual_links,struct dc * dc)1289 struct resource_pool *dce120_create_resource_pool(
1290 	uint8_t num_virtual_links,
1291 	struct dc *dc)
1292 {
1293 	struct dce110_resource_pool *pool =
1294 		kzalloc(sizeof(struct dce110_resource_pool), GFP_KERNEL);
1295 
1296 	if (!pool)
1297 		return NULL;
1298 
1299 	if (dce120_resource_construct(num_virtual_links, dc, pool))
1300 		return &pool->base;
1301 
1302 	kfree(pool);
1303 	BREAK_TO_DEBUGGER();
1304 	return NULL;
1305 }
1306