1 /*
2 * Copyright 2012-16 Advanced Micro Devices, Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
21 *
22 * Authors: AMD
23 *
24 */
25
26 #include "core_types.h"
27 #include "clk_mgr_internal.h"
28
29 #include "dce/dce_11_2_d.h"
30 #include "dce/dce_11_2_sh_mask.h"
31 #include "dce100/dce_clk_mgr.h"
32 #include "dce110/dce110_clk_mgr.h"
33 #include "dce112_clk_mgr.h"
34 #include "dal_asic_id.h"
35
36 /* set register offset */
37 #define SR(reg_name)\
38 .reg_name = mm ## reg_name
39
40 /* set register offset with instance */
41 #define SRI(reg_name, block, id)\
42 .reg_name = mm ## block ## id ## _ ## reg_name
43
44 static const struct clk_mgr_registers disp_clk_regs = {
45 CLK_COMMON_REG_LIST_DCE_BASE()
46 };
47
48 static const struct clk_mgr_shift disp_clk_shift = {
49 CLK_COMMON_MASK_SH_LIST_DCE_COMMON_BASE(__SHIFT)
50 };
51
52 static const struct clk_mgr_mask disp_clk_mask = {
53 CLK_COMMON_MASK_SH_LIST_DCE_COMMON_BASE(_MASK)
54 };
55
56 static const struct state_dependent_clocks dce112_max_clks_by_state[] = {
57 /*ClocksStateInvalid - should not be used*/
58 { .display_clk_khz = 0, .pixel_clk_khz = 0 },
59 /*ClocksStateUltraLow - currently by HW design team not supposed to be used*/
60 { .display_clk_khz = 389189, .pixel_clk_khz = 346672 },
61 /*ClocksStateLow*/
62 { .display_clk_khz = 459000, .pixel_clk_khz = 400000 },
63 /*ClocksStateNominal*/
64 { .display_clk_khz = 667000, .pixel_clk_khz = 600000 },
65 /*ClocksStatePerformance*/
66 { .display_clk_khz = 1132000, .pixel_clk_khz = 600000 } };
67
68
69 //TODO: remove use the two broken down functions
dce112_set_clock(struct clk_mgr * clk_mgr_base,int requested_clk_khz)70 int dce112_set_clock(struct clk_mgr *clk_mgr_base, int requested_clk_khz)
71 {
72 struct clk_mgr_internal *clk_mgr_dce = TO_CLK_MGR_INTERNAL(clk_mgr_base);
73 struct bp_set_dce_clock_parameters dce_clk_params;
74 struct dc_bios *bp = clk_mgr_base->ctx->dc_bios;
75 struct dc *dc = clk_mgr_base->ctx->dc;
76 struct dmcu *dmcu = dc->res_pool->dmcu;
77 int actual_clock = requested_clk_khz;
78 /* Prepare to program display clock*/
79 memset(&dce_clk_params, 0, sizeof(dce_clk_params));
80
81 /* Make sure requested clock isn't lower than minimum threshold*/
82 requested_clk_khz = max(requested_clk_khz,
83 clk_mgr_dce->base.dentist_vco_freq_khz / 62);
84
85 dce_clk_params.target_clock_frequency = requested_clk_khz;
86 dce_clk_params.pll_id = CLOCK_SOURCE_ID_DFS;
87 dce_clk_params.clock_type = DCECLOCK_TYPE_DISPLAY_CLOCK;
88
89 bp->funcs->set_dce_clock(bp, &dce_clk_params);
90 actual_clock = dce_clk_params.target_clock_frequency;
91
92 /*
93 * from power down, we need mark the clock state as ClocksStateNominal
94 * from HWReset, so when resume we will call pplib voltage regulator.
95 */
96 if (requested_clk_khz == 0)
97 clk_mgr_dce->cur_min_clks_state = DM_PP_CLOCKS_STATE_NOMINAL;
98
99 /*Program DP ref Clock*/
100 /*VBIOS will determine DPREFCLK frequency, so we don't set it*/
101 dce_clk_params.target_clock_frequency = 0;
102 dce_clk_params.clock_type = DCECLOCK_TYPE_DPREFCLK;
103 if (!ASICREV_IS_VEGA20_P(clk_mgr_base->ctx->asic_id.hw_internal_rev))
104 dce_clk_params.flags.USE_GENLOCK_AS_SOURCE_FOR_DPREFCLK =
105 (dce_clk_params.pll_id ==
106 CLOCK_SOURCE_COMBO_DISPLAY_PLL0);
107 else
108 dce_clk_params.flags.USE_GENLOCK_AS_SOURCE_FOR_DPREFCLK = false;
109
110 bp->funcs->set_dce_clock(bp, &dce_clk_params);
111
112 if (!IS_FPGA_MAXIMUS_DC(dc->ctx->dce_environment)) {
113 if (dmcu && dmcu->funcs->is_dmcu_initialized(dmcu)) {
114 if (clk_mgr_dce->dfs_bypass_disp_clk != actual_clock)
115 dmcu->funcs->set_psr_wait_loop(dmcu,
116 actual_clock / 1000 / 7);
117 }
118 }
119
120 clk_mgr_dce->dfs_bypass_disp_clk = actual_clock;
121 return actual_clock;
122 }
123
dce112_set_dispclk(struct clk_mgr_internal * clk_mgr,int requested_clk_khz)124 int dce112_set_dispclk(struct clk_mgr_internal *clk_mgr, int requested_clk_khz)
125 {
126 struct bp_set_dce_clock_parameters dce_clk_params;
127 struct dc_bios *bp = clk_mgr->base.ctx->dc_bios;
128 struct dc *dc = clk_mgr->base.ctx->dc;
129 struct dmcu *dmcu = dc->res_pool->dmcu;
130 int actual_clock = requested_clk_khz;
131 /* Prepare to program display clock*/
132 memset(&dce_clk_params, 0, sizeof(dce_clk_params));
133
134 /* Make sure requested clock isn't lower than minimum threshold*/
135 if (requested_clk_khz > 0)
136 requested_clk_khz = max(requested_clk_khz,
137 clk_mgr->base.dentist_vco_freq_khz / 62);
138
139 dce_clk_params.target_clock_frequency = requested_clk_khz;
140 dce_clk_params.pll_id = CLOCK_SOURCE_ID_DFS;
141 dce_clk_params.clock_type = DCECLOCK_TYPE_DISPLAY_CLOCK;
142
143 bp->funcs->set_dce_clock(bp, &dce_clk_params);
144 actual_clock = dce_clk_params.target_clock_frequency;
145
146 /*
147 * from power down, we need mark the clock state as ClocksStateNominal
148 * from HWReset, so when resume we will call pplib voltage regulator.
149 */
150 if (requested_clk_khz == 0)
151 clk_mgr->cur_min_clks_state = DM_PP_CLOCKS_STATE_NOMINAL;
152
153
154 if (!IS_FPGA_MAXIMUS_DC(dc->ctx->dce_environment)) {
155 if (dmcu && dmcu->funcs->is_dmcu_initialized(dmcu)) {
156 if (clk_mgr->dfs_bypass_disp_clk != actual_clock)
157 dmcu->funcs->set_psr_wait_loop(dmcu,
158 actual_clock / 1000 / 7);
159 }
160 }
161
162 clk_mgr->dfs_bypass_disp_clk = actual_clock;
163 return actual_clock;
164
165 }
166
dce112_set_dprefclk(struct clk_mgr_internal * clk_mgr)167 int dce112_set_dprefclk(struct clk_mgr_internal *clk_mgr)
168 {
169 struct bp_set_dce_clock_parameters dce_clk_params;
170 struct dc_bios *bp = clk_mgr->base.ctx->dc_bios;
171
172 memset(&dce_clk_params, 0, sizeof(dce_clk_params));
173
174 /*Program DP ref Clock*/
175 /*VBIOS will determine DPREFCLK frequency, so we don't set it*/
176 dce_clk_params.target_clock_frequency = 0;
177 dce_clk_params.pll_id = CLOCK_SOURCE_ID_DFS;
178 dce_clk_params.clock_type = DCECLOCK_TYPE_DPREFCLK;
179 if (!ASICREV_IS_VEGA20_P(clk_mgr->base.ctx->asic_id.hw_internal_rev))
180 dce_clk_params.flags.USE_GENLOCK_AS_SOURCE_FOR_DPREFCLK =
181 (dce_clk_params.pll_id ==
182 CLOCK_SOURCE_COMBO_DISPLAY_PLL0);
183 else
184 dce_clk_params.flags.USE_GENLOCK_AS_SOURCE_FOR_DPREFCLK = false;
185
186 bp->funcs->set_dce_clock(bp, &dce_clk_params);
187
188 /* Returns the dp_refclk that was set */
189 return dce_clk_params.target_clock_frequency;
190 }
191
dce112_update_clocks(struct clk_mgr * clk_mgr_base,struct dc_state * context,bool safe_to_lower)192 static void dce112_update_clocks(struct clk_mgr *clk_mgr_base,
193 struct dc_state *context,
194 bool safe_to_lower)
195 {
196 struct clk_mgr_internal *clk_mgr_dce = TO_CLK_MGR_INTERNAL(clk_mgr_base);
197 struct dm_pp_power_level_change_request level_change_req;
198 int patched_disp_clk = context->bw_ctx.bw.dce.dispclk_khz;
199
200 /*TODO: W/A for dal3 linux, investigate why this works */
201 if (!clk_mgr_dce->dfs_bypass_active)
202 patched_disp_clk = patched_disp_clk * 115 / 100;
203
204 level_change_req.power_level = dce_get_required_clocks_state(clk_mgr_base, context);
205 /* get max clock state from PPLIB */
206 if ((level_change_req.power_level < clk_mgr_dce->cur_min_clks_state && safe_to_lower)
207 || level_change_req.power_level > clk_mgr_dce->cur_min_clks_state) {
208 if (dm_pp_apply_power_level_change_request(clk_mgr_base->ctx, &level_change_req))
209 clk_mgr_dce->cur_min_clks_state = level_change_req.power_level;
210 }
211
212 if (should_set_clock(safe_to_lower, patched_disp_clk, clk_mgr_base->clks.dispclk_khz)) {
213 patched_disp_clk = dce112_set_clock(clk_mgr_base, patched_disp_clk);
214 clk_mgr_base->clks.dispclk_khz = patched_disp_clk;
215 }
216 dce11_pplib_apply_display_requirements(clk_mgr_base->ctx->dc, context);
217 }
218
219 static struct clk_mgr_funcs dce112_funcs = {
220 .get_dp_ref_clk_frequency = dce_get_dp_ref_freq_khz,
221 .update_clocks = dce112_update_clocks
222 };
223
dce112_clk_mgr_construct(struct dc_context * ctx,struct clk_mgr_internal * clk_mgr)224 void dce112_clk_mgr_construct(
225 struct dc_context *ctx,
226 struct clk_mgr_internal *clk_mgr)
227 {
228 dce_clk_mgr_construct(ctx, clk_mgr);
229
230 memcpy(clk_mgr->max_clks_by_state,
231 dce112_max_clks_by_state,
232 sizeof(dce112_max_clks_by_state));
233
234 clk_mgr->regs = &disp_clk_regs;
235 clk_mgr->clk_mgr_shift = &disp_clk_shift;
236 clk_mgr->clk_mgr_mask = &disp_clk_mask;
237 clk_mgr->base.funcs = &dce112_funcs;
238 }
239