1 /*
2 * Copyright 2021 Advanced Micro Devices, Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
21 *
22 * Authors: AMD
23 *
24 */
25
26 #include "reg_helper.h"
27 #include "core_types.h"
28 #include "dcn32_dccg.h"
29 #include "dcn20/dcn20_dccg.h"
30
31 #define TO_DCN_DCCG(dccg)\
32 container_of(dccg, struct dcn_dccg, base)
33
34 #define REG(reg) \
35 (dccg_dcn->regs->reg)
36
37 #undef FN
38 #define FN(reg_name, field_name) \
39 dccg_dcn->dccg_shift->field_name, dccg_dcn->dccg_mask->field_name
40
41 #define CTX \
42 dccg_dcn->base.ctx
43 #define DC_LOGGER \
44 dccg->ctx->logger
45
dccg32_trigger_dio_fifo_resync(struct dccg * dccg)46 static void dccg32_trigger_dio_fifo_resync(
47 struct dccg *dccg)
48 {
49 struct dcn_dccg *dccg_dcn = TO_DCN_DCCG(dccg);
50 uint32_t dispclk_rdivider_value = 0;
51
52 REG_GET(DENTIST_DISPCLK_CNTL, DENTIST_DISPCLK_RDIVIDER, &dispclk_rdivider_value);
53
54 /* Not valid for the WDIVIDER to be set to 0 */
55 if (dispclk_rdivider_value != 0)
56 REG_UPDATE(DENTIST_DISPCLK_CNTL, DENTIST_DISPCLK_WDIVIDER, dispclk_rdivider_value);
57 }
58
dccg32_get_pixel_rate_div(struct dccg * dccg,uint32_t otg_inst,uint32_t * k1,uint32_t * k2)59 static void dccg32_get_pixel_rate_div(
60 struct dccg *dccg,
61 uint32_t otg_inst,
62 uint32_t *k1,
63 uint32_t *k2)
64 {
65 struct dcn_dccg *dccg_dcn = TO_DCN_DCCG(dccg);
66 uint32_t val_k1 = PIXEL_RATE_DIV_NA, val_k2 = PIXEL_RATE_DIV_NA;
67
68 *k1 = PIXEL_RATE_DIV_NA;
69 *k2 = PIXEL_RATE_DIV_NA;
70
71 switch (otg_inst) {
72 case 0:
73 REG_GET_2(OTG_PIXEL_RATE_DIV,
74 OTG0_PIXEL_RATE_DIVK1, &val_k1,
75 OTG0_PIXEL_RATE_DIVK2, &val_k2);
76 break;
77 case 1:
78 REG_GET_2(OTG_PIXEL_RATE_DIV,
79 OTG1_PIXEL_RATE_DIVK1, &val_k1,
80 OTG1_PIXEL_RATE_DIVK2, &val_k2);
81 break;
82 case 2:
83 REG_GET_2(OTG_PIXEL_RATE_DIV,
84 OTG2_PIXEL_RATE_DIVK1, &val_k1,
85 OTG2_PIXEL_RATE_DIVK2, &val_k2);
86 break;
87 case 3:
88 REG_GET_2(OTG_PIXEL_RATE_DIV,
89 OTG3_PIXEL_RATE_DIVK1, &val_k1,
90 OTG3_PIXEL_RATE_DIVK2, &val_k2);
91 break;
92 default:
93 BREAK_TO_DEBUGGER();
94 return;
95 }
96
97 *k1 = val_k1;
98 *k2 = val_k2;
99 }
100
dccg32_set_pixel_rate_div(struct dccg * dccg,uint32_t otg_inst,enum pixel_rate_div k1,enum pixel_rate_div k2)101 static void dccg32_set_pixel_rate_div(
102 struct dccg *dccg,
103 uint32_t otg_inst,
104 enum pixel_rate_div k1,
105 enum pixel_rate_div k2)
106 {
107 struct dcn_dccg *dccg_dcn = TO_DCN_DCCG(dccg);
108 uint32_t cur_k1 = PIXEL_RATE_DIV_NA;
109 uint32_t cur_k2 = PIXEL_RATE_DIV_NA;
110
111 // Don't program 0xF into the register field. Not valid since
112 // K1 / K2 field is only 1 / 2 bits wide
113 if (k1 == PIXEL_RATE_DIV_NA || k2 == PIXEL_RATE_DIV_NA) {
114 BREAK_TO_DEBUGGER();
115 return;
116 }
117
118 dccg32_get_pixel_rate_div(dccg, otg_inst, &cur_k1, &cur_k2);
119 if (k1 == cur_k1 && k2 == cur_k2)
120 return;
121
122 switch (otg_inst) {
123 case 0:
124 REG_UPDATE_2(OTG_PIXEL_RATE_DIV,
125 OTG0_PIXEL_RATE_DIVK1, k1,
126 OTG0_PIXEL_RATE_DIVK2, k2);
127 break;
128 case 1:
129 REG_UPDATE_2(OTG_PIXEL_RATE_DIV,
130 OTG1_PIXEL_RATE_DIVK1, k1,
131 OTG1_PIXEL_RATE_DIVK2, k2);
132 break;
133 case 2:
134 REG_UPDATE_2(OTG_PIXEL_RATE_DIV,
135 OTG2_PIXEL_RATE_DIVK1, k1,
136 OTG2_PIXEL_RATE_DIVK2, k2);
137 break;
138 case 3:
139 REG_UPDATE_2(OTG_PIXEL_RATE_DIV,
140 OTG3_PIXEL_RATE_DIVK1, k1,
141 OTG3_PIXEL_RATE_DIVK2, k2);
142 break;
143 default:
144 BREAK_TO_DEBUGGER();
145 return;
146 }
147 }
148
dccg32_set_dtbclk_p_src(struct dccg * dccg,enum streamclk_source src,uint32_t otg_inst)149 static void dccg32_set_dtbclk_p_src(
150 struct dccg *dccg,
151 enum streamclk_source src,
152 uint32_t otg_inst)
153 {
154 struct dcn_dccg *dccg_dcn = TO_DCN_DCCG(dccg);
155
156 uint32_t p_src_sel = 0; /* selects dprefclk */
157 if (src == DTBCLK0)
158 p_src_sel = 2; /* selects dtbclk0 */
159
160 switch (otg_inst) {
161 case 0:
162 if (src == REFCLK)
163 REG_UPDATE(DTBCLK_P_CNTL,
164 DTBCLK_P0_EN, 0);
165 else
166 REG_UPDATE_2(DTBCLK_P_CNTL,
167 DTBCLK_P0_SRC_SEL, p_src_sel,
168 DTBCLK_P0_EN, 1);
169 break;
170 case 1:
171 if (src == REFCLK)
172 REG_UPDATE(DTBCLK_P_CNTL,
173 DTBCLK_P1_EN, 0);
174 else
175 REG_UPDATE_2(DTBCLK_P_CNTL,
176 DTBCLK_P1_SRC_SEL, p_src_sel,
177 DTBCLK_P1_EN, 1);
178 break;
179 case 2:
180 if (src == REFCLK)
181 REG_UPDATE(DTBCLK_P_CNTL,
182 DTBCLK_P2_EN, 0);
183 else
184 REG_UPDATE_2(DTBCLK_P_CNTL,
185 DTBCLK_P2_SRC_SEL, p_src_sel,
186 DTBCLK_P2_EN, 1);
187 break;
188 case 3:
189 if (src == REFCLK)
190 REG_UPDATE(DTBCLK_P_CNTL,
191 DTBCLK_P3_EN, 0);
192 else
193 REG_UPDATE_2(DTBCLK_P_CNTL,
194 DTBCLK_P3_SRC_SEL, p_src_sel,
195 DTBCLK_P3_EN, 1);
196 break;
197 default:
198 BREAK_TO_DEBUGGER();
199 return;
200 }
201
202 }
203
204 /* Controls the generation of pixel valid for OTG in (OTG -> HPO case) */
dccg32_set_dtbclk_dto(struct dccg * dccg,const struct dtbclk_dto_params * params)205 static void dccg32_set_dtbclk_dto(
206 struct dccg *dccg,
207 const struct dtbclk_dto_params *params)
208 {
209 struct dcn_dccg *dccg_dcn = TO_DCN_DCCG(dccg);
210 /* DTO Output Rate / Pixel Rate = 1/4 */
211 int req_dtbclk_khz = params->pixclk_khz / 4;
212
213 if (params->ref_dtbclk_khz && req_dtbclk_khz) {
214 uint32_t modulo, phase;
215
216 // phase / modulo = dtbclk / dtbclk ref
217 modulo = params->ref_dtbclk_khz * 1000;
218 phase = req_dtbclk_khz * 1000;
219
220 REG_WRITE(DTBCLK_DTO_MODULO[params->otg_inst], modulo);
221 REG_WRITE(DTBCLK_DTO_PHASE[params->otg_inst], phase);
222
223 REG_UPDATE(OTG_PIXEL_RATE_CNTL[params->otg_inst],
224 DTBCLK_DTO_ENABLE[params->otg_inst], 1);
225
226 REG_WAIT(OTG_PIXEL_RATE_CNTL[params->otg_inst],
227 DTBCLKDTO_ENABLE_STATUS[params->otg_inst], 1,
228 1, 100);
229
230 /* program OTG_PIXEL_RATE_DIV for DIVK1 and DIVK2 fields */
231 dccg32_set_pixel_rate_div(dccg, params->otg_inst, PIXEL_RATE_DIV_BY_1, PIXEL_RATE_DIV_BY_1);
232
233 /* The recommended programming sequence to enable DTBCLK DTO to generate
234 * valid pixel HPO DPSTREAM ENCODER, specifies that DTO source select should
235 * be set only after DTO is enabled
236 */
237 REG_UPDATE(OTG_PIXEL_RATE_CNTL[params->otg_inst],
238 PIPE_DTO_SRC_SEL[params->otg_inst], 2);
239 } else {
240 REG_UPDATE_2(OTG_PIXEL_RATE_CNTL[params->otg_inst],
241 DTBCLK_DTO_ENABLE[params->otg_inst], 0,
242 PIPE_DTO_SRC_SEL[params->otg_inst], params->is_hdmi ? 0 : 1);
243 REG_WRITE(DTBCLK_DTO_MODULO[params->otg_inst], 0);
244 REG_WRITE(DTBCLK_DTO_PHASE[params->otg_inst], 0);
245 }
246 }
247
dccg32_set_valid_pixel_rate(struct dccg * dccg,int ref_dtbclk_khz,int otg_inst,int pixclk_khz)248 static void dccg32_set_valid_pixel_rate(
249 struct dccg *dccg,
250 int ref_dtbclk_khz,
251 int otg_inst,
252 int pixclk_khz)
253 {
254 struct dtbclk_dto_params dto_params = {0};
255
256 dto_params.ref_dtbclk_khz = ref_dtbclk_khz;
257 dto_params.otg_inst = otg_inst;
258 dto_params.pixclk_khz = pixclk_khz;
259 dto_params.is_hdmi = true;
260
261 dccg32_set_dtbclk_dto(dccg, &dto_params);
262 }
263
dccg32_get_dccg_ref_freq(struct dccg * dccg,unsigned int xtalin_freq_inKhz,unsigned int * dccg_ref_freq_inKhz)264 static void dccg32_get_dccg_ref_freq(struct dccg *dccg,
265 unsigned int xtalin_freq_inKhz,
266 unsigned int *dccg_ref_freq_inKhz)
267 {
268 /*
269 * Assume refclk is sourced from xtalin
270 * expect 100MHz
271 */
272 *dccg_ref_freq_inKhz = xtalin_freq_inKhz;
273 return;
274 }
275
dccg32_set_dpstreamclk(struct dccg * dccg,enum streamclk_source src,int otg_inst,int dp_hpo_inst)276 static void dccg32_set_dpstreamclk(
277 struct dccg *dccg,
278 enum streamclk_source src,
279 int otg_inst,
280 int dp_hpo_inst)
281 {
282 struct dcn_dccg *dccg_dcn = TO_DCN_DCCG(dccg);
283
284 /* set the dtbclk_p source */
285 /* always program refclk as DTBCLK. No use-case expected to require DPREFCLK as refclk */
286 dccg32_set_dtbclk_p_src(dccg, DTBCLK0, otg_inst);
287
288 /* enabled to select one of the DTBCLKs for pipe */
289 switch (dp_hpo_inst) {
290 case 0:
291 REG_UPDATE_2(DPSTREAMCLK_CNTL,
292 DPSTREAMCLK0_EN,
293 (src == REFCLK) ? 0 : 1, DPSTREAMCLK0_SRC_SEL, otg_inst);
294 break;
295 case 1:
296 REG_UPDATE_2(DPSTREAMCLK_CNTL, DPSTREAMCLK1_EN,
297 (src == REFCLK) ? 0 : 1, DPSTREAMCLK1_SRC_SEL, otg_inst);
298 break;
299 case 2:
300 REG_UPDATE_2(DPSTREAMCLK_CNTL, DPSTREAMCLK2_EN,
301 (src == REFCLK) ? 0 : 1, DPSTREAMCLK2_SRC_SEL, otg_inst);
302 break;
303 case 3:
304 REG_UPDATE_2(DPSTREAMCLK_CNTL, DPSTREAMCLK3_EN,
305 (src == REFCLK) ? 0 : 1, DPSTREAMCLK3_SRC_SEL, otg_inst);
306 break;
307 default:
308 BREAK_TO_DEBUGGER();
309 return;
310 }
311 }
312
dccg32_otg_add_pixel(struct dccg * dccg,uint32_t otg_inst)313 static void dccg32_otg_add_pixel(struct dccg *dccg,
314 uint32_t otg_inst)
315 {
316 struct dcn_dccg *dccg_dcn = TO_DCN_DCCG(dccg);
317
318 REG_UPDATE(OTG_PIXEL_RATE_CNTL[otg_inst],
319 OTG_ADD_PIXEL[otg_inst], 1);
320 }
321
dccg32_otg_drop_pixel(struct dccg * dccg,uint32_t otg_inst)322 static void dccg32_otg_drop_pixel(struct dccg *dccg,
323 uint32_t otg_inst)
324 {
325 struct dcn_dccg *dccg_dcn = TO_DCN_DCCG(dccg);
326
327 REG_UPDATE(OTG_PIXEL_RATE_CNTL[otg_inst],
328 OTG_DROP_PIXEL[otg_inst], 1);
329 }
330
331 static const struct dccg_funcs dccg32_funcs = {
332 .update_dpp_dto = dccg2_update_dpp_dto,
333 .get_dccg_ref_freq = dccg32_get_dccg_ref_freq,
334 .dccg_init = dccg31_init,
335 .set_dpstreamclk = dccg32_set_dpstreamclk,
336 .enable_symclk32_se = dccg31_enable_symclk32_se,
337 .disable_symclk32_se = dccg31_disable_symclk32_se,
338 .enable_symclk32_le = dccg31_enable_symclk32_le,
339 .disable_symclk32_le = dccg31_disable_symclk32_le,
340 .set_physymclk = dccg31_set_physymclk,
341 .set_dtbclk_dto = dccg32_set_dtbclk_dto,
342 .set_valid_pixel_rate = dccg32_set_valid_pixel_rate,
343 .set_fifo_errdet_ovr_en = dccg2_set_fifo_errdet_ovr_en,
344 .set_audio_dtbclk_dto = dccg31_set_audio_dtbclk_dto,
345 .otg_add_pixel = dccg32_otg_add_pixel,
346 .otg_drop_pixel = dccg32_otg_drop_pixel,
347 .set_pixel_rate_div = dccg32_set_pixel_rate_div,
348 .get_pixel_rate_div = dccg32_get_pixel_rate_div,
349 .trigger_dio_fifo_resync = dccg32_trigger_dio_fifo_resync,
350 .set_dtbclk_p_src = dccg32_set_dtbclk_p_src,
351 .refclk_setup = dccg2_refclk_setup, /* Deprecated - for backward compatibility only */
352 .allow_clock_gating = dccg2_allow_clock_gating,
353 .enable_memory_low_power = dccg2_enable_memory_low_power,
354 .is_s0i3_golden_init_wa_done = dccg2_is_s0i3_golden_init_wa_done /* Deprecated - for backward compatibility only */
355 };
356
dccg32_create(struct dc_context * ctx,const struct dccg_registers * regs,const struct dccg_shift * dccg_shift,const struct dccg_mask * dccg_mask)357 struct dccg *dccg32_create(
358 struct dc_context *ctx,
359 const struct dccg_registers *regs,
360 const struct dccg_shift *dccg_shift,
361 const struct dccg_mask *dccg_mask)
362 {
363 struct dcn_dccg *dccg_dcn = kzalloc_obj(*dccg_dcn);
364 struct dccg *base;
365
366 if (dccg_dcn == NULL) {
367 BREAK_TO_DEBUGGER();
368 return NULL;
369 }
370
371 base = &dccg_dcn->base;
372 base->ctx = ctx;
373 base->funcs = &dccg32_funcs;
374
375 dccg_dcn->regs = regs;
376 dccg_dcn->dccg_shift = dccg_shift;
377 dccg_dcn->dccg_mask = dccg_mask;
378
379 return &dccg_dcn->base;
380 }
381