xref: /linux/drivers/gpu/drm/amd/display/dc/dccg/dcn201/dcn201_dccg.c (revision bf4afc53b77aeaa48b5409da5c8da6bb4eff7f43)
1 /*
2  * Copyright 2018 Advanced Micro Devices, Inc.
3  *
4  * Permission is hereby granted, free of charge, to any person obtaining a
5  * copy of this software and associated documentation files (the "Software"),
6  * to deal in the Software without restriction, including without limitation
7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8  * and/or sell copies of the Software, and to permit persons to whom the
9  * Software is furnished to do so, subject to the following conditions:
10  *
11  * The above copyright notice and this permission notice shall be included in
12  * all copies or substantial portions of the Software.
13  *
14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20  * OTHER DEALINGS IN THE SOFTWARE.
21  *
22  * Authors: AMD
23  *
24  */
25 
26 #include "dcn201_dccg.h"
27 #include "dcn20/dcn20_dccg.h"
28 
29 #include "reg_helper.h"
30 #include "core_types.h"
31 
32 #define TO_DCN_DCCG(dccg)\
33 	container_of(dccg, struct dcn_dccg, base)
34 
35 #define REG(reg) \
36 	(dccg_dcn->regs->reg)
37 
38 #undef FN
39 #define FN(reg_name, field_name) \
40 	dccg_dcn->dccg_shift->field_name, dccg_dcn->dccg_mask->field_name
41 
42 #define CTX \
43 	dccg_dcn->base.ctx
44 
45 #define DC_LOGGER \
46 	dccg->ctx->logger
47 
dccg201_update_dpp_dto(struct dccg * dccg,int dpp_inst,int req_dppclk)48 static void dccg201_update_dpp_dto(struct dccg *dccg, int dpp_inst,
49 				   int req_dppclk)
50 {
51 	/* vbios handles it */
52 }
53 
54 static const struct dccg_funcs dccg201_funcs = {
55 	.update_dpp_dto = dccg201_update_dpp_dto,
56 	.get_dccg_ref_freq = dccg2_get_dccg_ref_freq,
57 	.set_fifo_errdet_ovr_en = dccg2_set_fifo_errdet_ovr_en,
58 	.otg_add_pixel = dccg2_otg_add_pixel,
59 	.otg_drop_pixel = dccg2_otg_drop_pixel,
60 	.dccg_init = dccg2_init,
61 	.refclk_setup = dccg2_refclk_setup, /* Deprecated - for backward compatibility only */
62 	.allow_clock_gating = dccg2_allow_clock_gating,
63 	.enable_memory_low_power = dccg2_enable_memory_low_power,
64 	.is_s0i3_golden_init_wa_done = dccg2_is_s0i3_golden_init_wa_done /* Deprecated - for backward compatibility only */
65 };
66 
dccg201_create(struct dc_context * ctx,const struct dccg_registers * regs,const struct dccg_shift * dccg_shift,const struct dccg_mask * dccg_mask)67 struct dccg *dccg201_create(
68 	struct dc_context *ctx,
69 	const struct dccg_registers *regs,
70 	const struct dccg_shift *dccg_shift,
71 	const struct dccg_mask *dccg_mask)
72 {
73 	struct dcn_dccg *dccg_dcn = kzalloc_obj(*dccg_dcn);
74 	struct dccg *base;
75 
76 	if (dccg_dcn == NULL) {
77 		BREAK_TO_DEBUGGER();
78 		return NULL;
79 	}
80 
81 	base = &dccg_dcn->base;
82 	base->ctx = ctx;
83 	base->funcs = &dccg201_funcs;
84 
85 	dccg_dcn->regs = regs;
86 	dccg_dcn->dccg_shift = dccg_shift;
87 	dccg_dcn->dccg_mask = dccg_mask;
88 
89 	return &dccg_dcn->base;
90 }
91