1 /*
2  * Copyright (C) 2008
3  * Guennadi Liakhovetski, DENX Software Engineering, <lg@denx.de>
4  *
5  * Copyright 2004-2007 Freescale Semiconductor, Inc. All Rights Reserved.
6  *
7  * This program is free software; you can redistribute it and/or modify
8  * it under the terms of the GNU General Public License version 2 as
9  * published by the Free Software Foundation.
10  */
11 
12 #include <linux/module.h>
13 #include <linux/kernel.h>
14 #include <linux/platform_device.h>
15 #include <linux/sched.h>
16 #include <linux/errno.h>
17 #include <linux/string.h>
18 #include <linux/interrupt.h>
19 #include <linux/slab.h>
20 #include <linux/fb.h>
21 #include <linux/delay.h>
22 #include <linux/init.h>
23 #include <linux/ioport.h>
24 #include <linux/dma-mapping.h>
25 #include <linux/dmaengine.h>
26 #include <linux/console.h>
27 #include <linux/clk.h>
28 #include <linux/mutex.h>
29 
30 #include <mach/dma.h>
31 #include <mach/hardware.h>
32 #include <mach/ipu.h>
33 #include <mach/mx3fb.h>
34 
35 #include <asm/io.h>
36 #include <asm/uaccess.h>
37 
38 #define MX3FB_NAME		"mx3_sdc_fb"
39 
40 #define MX3FB_REG_OFFSET	0xB4
41 
42 /* SDC Registers */
43 #define SDC_COM_CONF		(0xB4 - MX3FB_REG_OFFSET)
44 #define SDC_GW_CTRL		(0xB8 - MX3FB_REG_OFFSET)
45 #define SDC_FG_POS		(0xBC - MX3FB_REG_OFFSET)
46 #define SDC_BG_POS		(0xC0 - MX3FB_REG_OFFSET)
47 #define SDC_CUR_POS		(0xC4 - MX3FB_REG_OFFSET)
48 #define SDC_PWM_CTRL		(0xC8 - MX3FB_REG_OFFSET)
49 #define SDC_CUR_MAP		(0xCC - MX3FB_REG_OFFSET)
50 #define SDC_HOR_CONF		(0xD0 - MX3FB_REG_OFFSET)
51 #define SDC_VER_CONF		(0xD4 - MX3FB_REG_OFFSET)
52 #define SDC_SHARP_CONF_1	(0xD8 - MX3FB_REG_OFFSET)
53 #define SDC_SHARP_CONF_2	(0xDC - MX3FB_REG_OFFSET)
54 
55 /* Register bits */
56 #define SDC_COM_TFT_COLOR	0x00000001UL
57 #define SDC_COM_FG_EN		0x00000010UL
58 #define SDC_COM_GWSEL		0x00000020UL
59 #define SDC_COM_GLB_A		0x00000040UL
60 #define SDC_COM_KEY_COLOR_G	0x00000080UL
61 #define SDC_COM_BG_EN		0x00000200UL
62 #define SDC_COM_SHARP		0x00001000UL
63 
64 #define SDC_V_SYNC_WIDTH_L	0x00000001UL
65 
66 /* Display Interface registers */
67 #define DI_DISP_IF_CONF		(0x0124 - MX3FB_REG_OFFSET)
68 #define DI_DISP_SIG_POL		(0x0128 - MX3FB_REG_OFFSET)
69 #define DI_SER_DISP1_CONF	(0x012C - MX3FB_REG_OFFSET)
70 #define DI_SER_DISP2_CONF	(0x0130 - MX3FB_REG_OFFSET)
71 #define DI_HSP_CLK_PER		(0x0134 - MX3FB_REG_OFFSET)
72 #define DI_DISP0_TIME_CONF_1	(0x0138 - MX3FB_REG_OFFSET)
73 #define DI_DISP0_TIME_CONF_2	(0x013C - MX3FB_REG_OFFSET)
74 #define DI_DISP0_TIME_CONF_3	(0x0140 - MX3FB_REG_OFFSET)
75 #define DI_DISP1_TIME_CONF_1	(0x0144 - MX3FB_REG_OFFSET)
76 #define DI_DISP1_TIME_CONF_2	(0x0148 - MX3FB_REG_OFFSET)
77 #define DI_DISP1_TIME_CONF_3	(0x014C - MX3FB_REG_OFFSET)
78 #define DI_DISP2_TIME_CONF_1	(0x0150 - MX3FB_REG_OFFSET)
79 #define DI_DISP2_TIME_CONF_2	(0x0154 - MX3FB_REG_OFFSET)
80 #define DI_DISP2_TIME_CONF_3	(0x0158 - MX3FB_REG_OFFSET)
81 #define DI_DISP3_TIME_CONF	(0x015C - MX3FB_REG_OFFSET)
82 #define DI_DISP0_DB0_MAP	(0x0160 - MX3FB_REG_OFFSET)
83 #define DI_DISP0_DB1_MAP	(0x0164 - MX3FB_REG_OFFSET)
84 #define DI_DISP0_DB2_MAP	(0x0168 - MX3FB_REG_OFFSET)
85 #define DI_DISP0_CB0_MAP	(0x016C - MX3FB_REG_OFFSET)
86 #define DI_DISP0_CB1_MAP	(0x0170 - MX3FB_REG_OFFSET)
87 #define DI_DISP0_CB2_MAP	(0x0174 - MX3FB_REG_OFFSET)
88 #define DI_DISP1_DB0_MAP	(0x0178 - MX3FB_REG_OFFSET)
89 #define DI_DISP1_DB1_MAP	(0x017C - MX3FB_REG_OFFSET)
90 #define DI_DISP1_DB2_MAP	(0x0180 - MX3FB_REG_OFFSET)
91 #define DI_DISP1_CB0_MAP	(0x0184 - MX3FB_REG_OFFSET)
92 #define DI_DISP1_CB1_MAP	(0x0188 - MX3FB_REG_OFFSET)
93 #define DI_DISP1_CB2_MAP	(0x018C - MX3FB_REG_OFFSET)
94 #define DI_DISP2_DB0_MAP	(0x0190 - MX3FB_REG_OFFSET)
95 #define DI_DISP2_DB1_MAP	(0x0194 - MX3FB_REG_OFFSET)
96 #define DI_DISP2_DB2_MAP	(0x0198 - MX3FB_REG_OFFSET)
97 #define DI_DISP2_CB0_MAP	(0x019C - MX3FB_REG_OFFSET)
98 #define DI_DISP2_CB1_MAP	(0x01A0 - MX3FB_REG_OFFSET)
99 #define DI_DISP2_CB2_MAP	(0x01A4 - MX3FB_REG_OFFSET)
100 #define DI_DISP3_B0_MAP		(0x01A8 - MX3FB_REG_OFFSET)
101 #define DI_DISP3_B1_MAP		(0x01AC - MX3FB_REG_OFFSET)
102 #define DI_DISP3_B2_MAP		(0x01B0 - MX3FB_REG_OFFSET)
103 #define DI_DISP_ACC_CC		(0x01B4 - MX3FB_REG_OFFSET)
104 #define DI_DISP_LLA_CONF	(0x01B8 - MX3FB_REG_OFFSET)
105 #define DI_DISP_LLA_DATA	(0x01BC - MX3FB_REG_OFFSET)
106 
107 /* DI_DISP_SIG_POL bits */
108 #define DI_D3_VSYNC_POL_SHIFT		28
109 #define DI_D3_HSYNC_POL_SHIFT		27
110 #define DI_D3_DRDY_SHARP_POL_SHIFT	26
111 #define DI_D3_CLK_POL_SHIFT		25
112 #define DI_D3_DATA_POL_SHIFT		24
113 
114 /* DI_DISP_IF_CONF bits */
115 #define DI_D3_CLK_IDLE_SHIFT		26
116 #define DI_D3_CLK_SEL_SHIFT		25
117 #define DI_D3_DATAMSK_SHIFT		24
118 
119 enum ipu_panel {
120 	IPU_PANEL_SHARP_TFT,
121 	IPU_PANEL_TFT,
122 };
123 
124 struct ipu_di_signal_cfg {
125 	unsigned datamask_en:1;
126 	unsigned clksel_en:1;
127 	unsigned clkidle_en:1;
128 	unsigned data_pol:1;	/* true = inverted */
129 	unsigned clk_pol:1;	/* true = rising edge */
130 	unsigned enable_pol:1;
131 	unsigned Hsync_pol:1;	/* true = active high */
132 	unsigned Vsync_pol:1;
133 };
134 
135 static const struct fb_videomode mx3fb_modedb[] = {
136 	{
137 		/* 240x320 @ 60 Hz */
138 		.name		= "Sharp-QVGA",
139 		.refresh	= 60,
140 		.xres		= 240,
141 		.yres		= 320,
142 		.pixclock	= 185925,
143 		.left_margin	= 9,
144 		.right_margin	= 16,
145 		.upper_margin	= 7,
146 		.lower_margin	= 9,
147 		.hsync_len	= 1,
148 		.vsync_len	= 1,
149 		.sync		= FB_SYNC_HOR_HIGH_ACT | FB_SYNC_SHARP_MODE |
150 				  FB_SYNC_CLK_INVERT | FB_SYNC_DATA_INVERT |
151 				  FB_SYNC_CLK_IDLE_EN,
152 		.vmode		= FB_VMODE_NONINTERLACED,
153 		.flag		= 0,
154 	}, {
155 		/* 240x33 @ 60 Hz */
156 		.name		= "Sharp-CLI",
157 		.refresh	= 60,
158 		.xres		= 240,
159 		.yres		= 33,
160 		.pixclock	= 185925,
161 		.left_margin	= 9,
162 		.right_margin	= 16,
163 		.upper_margin	= 7,
164 		.lower_margin	= 9 + 287,
165 		.hsync_len	= 1,
166 		.vsync_len	= 1,
167 		.sync		= FB_SYNC_HOR_HIGH_ACT | FB_SYNC_SHARP_MODE |
168 				  FB_SYNC_CLK_INVERT | FB_SYNC_DATA_INVERT |
169 				  FB_SYNC_CLK_IDLE_EN,
170 		.vmode		= FB_VMODE_NONINTERLACED,
171 		.flag		= 0,
172 	}, {
173 		/* 640x480 @ 60 Hz */
174 		.name		= "NEC-VGA",
175 		.refresh	= 60,
176 		.xres		= 640,
177 		.yres		= 480,
178 		.pixclock	= 38255,
179 		.left_margin	= 144,
180 		.right_margin	= 0,
181 		.upper_margin	= 34,
182 		.lower_margin	= 40,
183 		.hsync_len	= 1,
184 		.vsync_len	= 1,
185 		.sync		= FB_SYNC_VERT_HIGH_ACT | FB_SYNC_OE_ACT_HIGH,
186 		.vmode		= FB_VMODE_NONINTERLACED,
187 		.flag		= 0,
188 	}, {
189 		/* NTSC TV output */
190 		.name		= "TV-NTSC",
191 		.refresh	= 60,
192 		.xres		= 640,
193 		.yres		= 480,
194 		.pixclock	= 37538,
195 		.left_margin	= 38,
196 		.right_margin	= 858 - 640 - 38 - 3,
197 		.upper_margin	= 36,
198 		.lower_margin	= 518 - 480 - 36 - 1,
199 		.hsync_len	= 3,
200 		.vsync_len	= 1,
201 		.sync		= 0,
202 		.vmode		= FB_VMODE_NONINTERLACED,
203 		.flag		= 0,
204 	}, {
205 		/* PAL TV output */
206 		.name		= "TV-PAL",
207 		.refresh	= 50,
208 		.xres		= 640,
209 		.yres		= 480,
210 		.pixclock	= 37538,
211 		.left_margin	= 38,
212 		.right_margin	= 960 - 640 - 38 - 32,
213 		.upper_margin	= 32,
214 		.lower_margin	= 555 - 480 - 32 - 3,
215 		.hsync_len	= 32,
216 		.vsync_len	= 3,
217 		.sync		= 0,
218 		.vmode		= FB_VMODE_NONINTERLACED,
219 		.flag		= 0,
220 	}, {
221 		/* TV output VGA mode, 640x480 @ 65 Hz */
222 		.name		= "TV-VGA",
223 		.refresh	= 60,
224 		.xres		= 640,
225 		.yres		= 480,
226 		.pixclock	= 40574,
227 		.left_margin	= 35,
228 		.right_margin	= 45,
229 		.upper_margin	= 9,
230 		.lower_margin	= 1,
231 		.hsync_len	= 46,
232 		.vsync_len	= 5,
233 		.sync		= 0,
234 		.vmode		= FB_VMODE_NONINTERLACED,
235 		.flag		= 0,
236 	},
237 };
238 
239 struct mx3fb_data {
240 	struct fb_info		*fbi;
241 	int			backlight_level;
242 	void __iomem		*reg_base;
243 	spinlock_t		lock;
244 	struct device		*dev;
245 
246 	uint32_t		h_start_width;
247 	uint32_t		v_start_width;
248 	enum disp_data_mapping	disp_data_fmt;
249 };
250 
251 struct dma_chan_request {
252 	struct mx3fb_data	*mx3fb;
253 	enum ipu_channel	id;
254 };
255 
256 /* MX3 specific framebuffer information. */
257 struct mx3fb_info {
258 	int				blank;
259 	enum ipu_channel		ipu_ch;
260 	uint32_t			cur_ipu_buf;
261 
262 	u32				pseudo_palette[16];
263 
264 	struct completion		flip_cmpl;
265 	struct mutex			mutex;	/* Protects fb-ops */
266 	struct mx3fb_data		*mx3fb;
267 	struct idmac_channel		*idmac_channel;
268 	struct dma_async_tx_descriptor	*txd;
269 	dma_cookie_t			cookie;
270 	struct scatterlist		sg[2];
271 
272 	u32				sync;	/* preserve var->sync flags */
273 };
274 
275 static void mx3fb_dma_done(void *);
276 
277 /* Used fb-mode and bpp. Can be set on kernel command line, therefore file-static. */
278 static const char *fb_mode;
279 static unsigned long default_bpp = 16;
280 
mx3fb_read_reg(struct mx3fb_data * mx3fb,unsigned long reg)281 static u32 mx3fb_read_reg(struct mx3fb_data *mx3fb, unsigned long reg)
282 {
283 	return __raw_readl(mx3fb->reg_base + reg);
284 }
285 
mx3fb_write_reg(struct mx3fb_data * mx3fb,u32 value,unsigned long reg)286 static void mx3fb_write_reg(struct mx3fb_data *mx3fb, u32 value, unsigned long reg)
287 {
288 	__raw_writel(value, mx3fb->reg_base + reg);
289 }
290 
291 struct di_mapping {
292 	uint32_t b0, b1, b2;
293 };
294 
295 static const struct di_mapping di_mappings[] = {
296 	[IPU_DISP_DATA_MAPPING_RGB666] = { 0x0005000f, 0x000b000f, 0x0011000f },
297 	[IPU_DISP_DATA_MAPPING_RGB565] = { 0x0004003f, 0x000a000f, 0x000f003f },
298 	[IPU_DISP_DATA_MAPPING_RGB888] = { 0x00070000, 0x000f0000, 0x00170000 },
299 };
300 
sdc_fb_init(struct mx3fb_info * fbi)301 static void sdc_fb_init(struct mx3fb_info *fbi)
302 {
303 	struct mx3fb_data *mx3fb = fbi->mx3fb;
304 	uint32_t reg;
305 
306 	reg = mx3fb_read_reg(mx3fb, SDC_COM_CONF);
307 
308 	mx3fb_write_reg(mx3fb, reg | SDC_COM_BG_EN, SDC_COM_CONF);
309 }
310 
311 /* Returns enabled flag before uninit */
sdc_fb_uninit(struct mx3fb_info * fbi)312 static uint32_t sdc_fb_uninit(struct mx3fb_info *fbi)
313 {
314 	struct mx3fb_data *mx3fb = fbi->mx3fb;
315 	uint32_t reg;
316 
317 	reg = mx3fb_read_reg(mx3fb, SDC_COM_CONF);
318 
319 	mx3fb_write_reg(mx3fb, reg & ~SDC_COM_BG_EN, SDC_COM_CONF);
320 
321 	return reg & SDC_COM_BG_EN;
322 }
323 
sdc_enable_channel(struct mx3fb_info * mx3_fbi)324 static void sdc_enable_channel(struct mx3fb_info *mx3_fbi)
325 {
326 	struct mx3fb_data *mx3fb = mx3_fbi->mx3fb;
327 	struct idmac_channel *ichan = mx3_fbi->idmac_channel;
328 	struct dma_chan *dma_chan = &ichan->dma_chan;
329 	unsigned long flags;
330 	dma_cookie_t cookie;
331 
332 	if (mx3_fbi->txd)
333 		dev_dbg(mx3fb->dev, "mx3fbi %p, desc %p, sg %p\n", mx3_fbi,
334 			to_tx_desc(mx3_fbi->txd), to_tx_desc(mx3_fbi->txd)->sg);
335 	else
336 		dev_dbg(mx3fb->dev, "mx3fbi %p, txd = NULL\n", mx3_fbi);
337 
338 	/* This enables the channel */
339 	if (mx3_fbi->cookie < 0) {
340 		mx3_fbi->txd = dma_chan->device->device_prep_slave_sg(dma_chan,
341 		      &mx3_fbi->sg[0], 1, DMA_MEM_TO_DEV, DMA_PREP_INTERRUPT);
342 		if (!mx3_fbi->txd) {
343 			dev_err(mx3fb->dev, "Cannot allocate descriptor on %d\n",
344 				dma_chan->chan_id);
345 			return;
346 		}
347 
348 		mx3_fbi->txd->callback_param	= mx3_fbi->txd;
349 		mx3_fbi->txd->callback		= mx3fb_dma_done;
350 
351 		cookie = mx3_fbi->txd->tx_submit(mx3_fbi->txd);
352 		dev_dbg(mx3fb->dev, "%d: Submit %p #%d [%c]\n", __LINE__,
353 		       mx3_fbi->txd, cookie, list_empty(&ichan->queue) ? '-' : '+');
354 	} else {
355 		if (!mx3_fbi->txd || !mx3_fbi->txd->tx_submit) {
356 			dev_err(mx3fb->dev, "Cannot enable channel %d\n",
357 				dma_chan->chan_id);
358 			return;
359 		}
360 
361 		/* Just re-activate the same buffer */
362 		dma_async_issue_pending(dma_chan);
363 		cookie = mx3_fbi->cookie;
364 		dev_dbg(mx3fb->dev, "%d: Re-submit %p #%d [%c]\n", __LINE__,
365 		       mx3_fbi->txd, cookie, list_empty(&ichan->queue) ? '-' : '+');
366 	}
367 
368 	if (cookie >= 0) {
369 		spin_lock_irqsave(&mx3fb->lock, flags);
370 		sdc_fb_init(mx3_fbi);
371 		mx3_fbi->cookie = cookie;
372 		spin_unlock_irqrestore(&mx3fb->lock, flags);
373 	}
374 
375 	/*
376 	 * Attention! Without this msleep the channel keeps generating
377 	 * interrupts. Next sdc_set_brightness() is going to be called
378 	 * from mx3fb_blank().
379 	 */
380 	msleep(2);
381 }
382 
sdc_disable_channel(struct mx3fb_info * mx3_fbi)383 static void sdc_disable_channel(struct mx3fb_info *mx3_fbi)
384 {
385 	struct mx3fb_data *mx3fb = mx3_fbi->mx3fb;
386 	uint32_t enabled;
387 	unsigned long flags;
388 
389 	if (mx3_fbi->txd == NULL)
390 		return;
391 
392 	spin_lock_irqsave(&mx3fb->lock, flags);
393 
394 	enabled = sdc_fb_uninit(mx3_fbi);
395 
396 	spin_unlock_irqrestore(&mx3fb->lock, flags);
397 
398 	mx3_fbi->txd->chan->device->device_control(mx3_fbi->txd->chan,
399 						   DMA_TERMINATE_ALL, 0);
400 	mx3_fbi->txd = NULL;
401 	mx3_fbi->cookie = -EINVAL;
402 }
403 
404 /**
405  * sdc_set_window_pos() - set window position of the respective plane.
406  * @mx3fb:	mx3fb context.
407  * @channel:	IPU DMAC channel ID.
408  * @x_pos:	X coordinate relative to the top left corner to place window at.
409  * @y_pos:	Y coordinate relative to the top left corner to place window at.
410  * @return:	0 on success or negative error code on failure.
411  */
sdc_set_window_pos(struct mx3fb_data * mx3fb,enum ipu_channel channel,int16_t x_pos,int16_t y_pos)412 static int sdc_set_window_pos(struct mx3fb_data *mx3fb, enum ipu_channel channel,
413 			      int16_t x_pos, int16_t y_pos)
414 {
415 	if (channel != IDMAC_SDC_0)
416 		return -EINVAL;
417 
418 	x_pos += mx3fb->h_start_width;
419 	y_pos += mx3fb->v_start_width;
420 
421 	mx3fb_write_reg(mx3fb, (x_pos << 16) | y_pos, SDC_BG_POS);
422 	return 0;
423 }
424 
425 /**
426  * sdc_init_panel() - initialize a synchronous LCD panel.
427  * @mx3fb:		mx3fb context.
428  * @panel:		panel type.
429  * @pixel_clk:		desired pixel clock frequency in Hz.
430  * @width:		width of panel in pixels.
431  * @height:		height of panel in pixels.
432  * @h_start_width:	number of pixel clocks between the HSYNC signal pulse
433  *			and the start of valid data.
434  * @h_sync_width:	width of the HSYNC signal in units of pixel clocks.
435  * @h_end_width:	number of pixel clocks between the end of valid data
436  *			and the HSYNC signal for next line.
437  * @v_start_width:	number of lines between the VSYNC signal pulse and the
438  *			start of valid data.
439  * @v_sync_width:	width of the VSYNC signal in units of lines
440  * @v_end_width:	number of lines between the end of valid data and the
441  *			VSYNC signal for next frame.
442  * @sig:		bitfield of signal polarities for LCD interface.
443  * @return:		0 on success or negative error code on failure.
444  */
sdc_init_panel(struct mx3fb_data * mx3fb,enum ipu_panel panel,uint32_t pixel_clk,uint16_t width,uint16_t height,uint16_t h_start_width,uint16_t h_sync_width,uint16_t h_end_width,uint16_t v_start_width,uint16_t v_sync_width,uint16_t v_end_width,struct ipu_di_signal_cfg sig)445 static int sdc_init_panel(struct mx3fb_data *mx3fb, enum ipu_panel panel,
446 			  uint32_t pixel_clk,
447 			  uint16_t width, uint16_t height,
448 			  uint16_t h_start_width, uint16_t h_sync_width,
449 			  uint16_t h_end_width, uint16_t v_start_width,
450 			  uint16_t v_sync_width, uint16_t v_end_width,
451 			  struct ipu_di_signal_cfg sig)
452 {
453 	unsigned long lock_flags;
454 	uint32_t reg;
455 	uint32_t old_conf;
456 	uint32_t div;
457 	struct clk *ipu_clk;
458 	const struct di_mapping *map;
459 
460 	dev_dbg(mx3fb->dev, "panel size = %d x %d", width, height);
461 
462 	if (v_sync_width == 0 || h_sync_width == 0)
463 		return -EINVAL;
464 
465 	/* Init panel size and blanking periods */
466 	reg = ((uint32_t) (h_sync_width - 1) << 26) |
467 		((uint32_t) (width + h_start_width + h_end_width - 1) << 16);
468 	mx3fb_write_reg(mx3fb, reg, SDC_HOR_CONF);
469 
470 #ifdef DEBUG
471 	printk(KERN_CONT " hor_conf %x,", reg);
472 #endif
473 
474 	reg = ((uint32_t) (v_sync_width - 1) << 26) | SDC_V_SYNC_WIDTH_L |
475 	    ((uint32_t) (height + v_start_width + v_end_width - 1) << 16);
476 	mx3fb_write_reg(mx3fb, reg, SDC_VER_CONF);
477 
478 #ifdef DEBUG
479 	printk(KERN_CONT " ver_conf %x\n", reg);
480 #endif
481 
482 	mx3fb->h_start_width = h_start_width;
483 	mx3fb->v_start_width = v_start_width;
484 
485 	switch (panel) {
486 	case IPU_PANEL_SHARP_TFT:
487 		mx3fb_write_reg(mx3fb, 0x00FD0102L, SDC_SHARP_CONF_1);
488 		mx3fb_write_reg(mx3fb, 0x00F500F4L, SDC_SHARP_CONF_2);
489 		mx3fb_write_reg(mx3fb, SDC_COM_SHARP | SDC_COM_TFT_COLOR, SDC_COM_CONF);
490 		break;
491 	case IPU_PANEL_TFT:
492 		mx3fb_write_reg(mx3fb, SDC_COM_TFT_COLOR, SDC_COM_CONF);
493 		break;
494 	default:
495 		return -EINVAL;
496 	}
497 
498 	/* Init clocking */
499 
500 	/*
501 	 * Calculate divider: fractional part is 4 bits so simply multiple by
502 	 * 2^4 to get fractional part, as long as we stay under ~250MHz and on
503 	 * i.MX31 it (HSP_CLK) is <= 178MHz. Currently 128.267MHz
504 	 */
505 	ipu_clk = clk_get(mx3fb->dev, NULL);
506 	if (!IS_ERR(ipu_clk)) {
507 		div = clk_get_rate(ipu_clk) * 16 / pixel_clk;
508 		clk_put(ipu_clk);
509 	} else {
510 		div = 0;
511 	}
512 
513 	if (div < 0x40) {	/* Divider less than 4 */
514 		dev_dbg(mx3fb->dev,
515 			"InitPanel() - Pixel clock divider less than 4\n");
516 		div = 0x40;
517 	}
518 
519 	dev_dbg(mx3fb->dev, "pixel clk = %u, divider %u.%u\n",
520 		pixel_clk, div >> 4, (div & 7) * 125);
521 
522 	spin_lock_irqsave(&mx3fb->lock, lock_flags);
523 
524 	/*
525 	 * DISP3_IF_CLK_DOWN_WR is half the divider value and 2 fraction bits
526 	 * fewer. Subtract 1 extra from DISP3_IF_CLK_DOWN_WR based on timing
527 	 * debug. DISP3_IF_CLK_UP_WR is 0
528 	 */
529 	mx3fb_write_reg(mx3fb, (((div / 8) - 1) << 22) | div, DI_DISP3_TIME_CONF);
530 
531 	/* DI settings */
532 	old_conf = mx3fb_read_reg(mx3fb, DI_DISP_IF_CONF) & 0x78FFFFFF;
533 	old_conf |= sig.datamask_en << DI_D3_DATAMSK_SHIFT |
534 		sig.clksel_en << DI_D3_CLK_SEL_SHIFT |
535 		sig.clkidle_en << DI_D3_CLK_IDLE_SHIFT;
536 	mx3fb_write_reg(mx3fb, old_conf, DI_DISP_IF_CONF);
537 
538 	old_conf = mx3fb_read_reg(mx3fb, DI_DISP_SIG_POL) & 0xE0FFFFFF;
539 	old_conf |= sig.data_pol << DI_D3_DATA_POL_SHIFT |
540 		sig.clk_pol << DI_D3_CLK_POL_SHIFT |
541 		sig.enable_pol << DI_D3_DRDY_SHARP_POL_SHIFT |
542 		sig.Hsync_pol << DI_D3_HSYNC_POL_SHIFT |
543 		sig.Vsync_pol << DI_D3_VSYNC_POL_SHIFT;
544 	mx3fb_write_reg(mx3fb, old_conf, DI_DISP_SIG_POL);
545 
546 	map = &di_mappings[mx3fb->disp_data_fmt];
547 	mx3fb_write_reg(mx3fb, map->b0, DI_DISP3_B0_MAP);
548 	mx3fb_write_reg(mx3fb, map->b1, DI_DISP3_B1_MAP);
549 	mx3fb_write_reg(mx3fb, map->b2, DI_DISP3_B2_MAP);
550 
551 	spin_unlock_irqrestore(&mx3fb->lock, lock_flags);
552 
553 	dev_dbg(mx3fb->dev, "DI_DISP_IF_CONF = 0x%08X\n",
554 		mx3fb_read_reg(mx3fb, DI_DISP_IF_CONF));
555 	dev_dbg(mx3fb->dev, "DI_DISP_SIG_POL = 0x%08X\n",
556 		mx3fb_read_reg(mx3fb, DI_DISP_SIG_POL));
557 	dev_dbg(mx3fb->dev, "DI_DISP3_TIME_CONF = 0x%08X\n",
558 		mx3fb_read_reg(mx3fb, DI_DISP3_TIME_CONF));
559 
560 	return 0;
561 }
562 
563 /**
564  * sdc_set_color_key() - set the transparent color key for SDC graphic plane.
565  * @mx3fb:	mx3fb context.
566  * @channel:	IPU DMAC channel ID.
567  * @enable:	boolean to enable or disable color keyl.
568  * @color_key:	24-bit RGB color to use as transparent color key.
569  * @return:	0 on success or negative error code on failure.
570  */
sdc_set_color_key(struct mx3fb_data * mx3fb,enum ipu_channel channel,bool enable,uint32_t color_key)571 static int sdc_set_color_key(struct mx3fb_data *mx3fb, enum ipu_channel channel,
572 			     bool enable, uint32_t color_key)
573 {
574 	uint32_t reg, sdc_conf;
575 	unsigned long lock_flags;
576 
577 	spin_lock_irqsave(&mx3fb->lock, lock_flags);
578 
579 	sdc_conf = mx3fb_read_reg(mx3fb, SDC_COM_CONF);
580 	if (channel == IDMAC_SDC_0)
581 		sdc_conf &= ~SDC_COM_GWSEL;
582 	else
583 		sdc_conf |= SDC_COM_GWSEL;
584 
585 	if (enable) {
586 		reg = mx3fb_read_reg(mx3fb, SDC_GW_CTRL) & 0xFF000000L;
587 		mx3fb_write_reg(mx3fb, reg | (color_key & 0x00FFFFFFL),
588 			     SDC_GW_CTRL);
589 
590 		sdc_conf |= SDC_COM_KEY_COLOR_G;
591 	} else {
592 		sdc_conf &= ~SDC_COM_KEY_COLOR_G;
593 	}
594 	mx3fb_write_reg(mx3fb, sdc_conf, SDC_COM_CONF);
595 
596 	spin_unlock_irqrestore(&mx3fb->lock, lock_flags);
597 
598 	return 0;
599 }
600 
601 /**
602  * sdc_set_global_alpha() - set global alpha blending modes.
603  * @mx3fb:	mx3fb context.
604  * @enable:	boolean to enable or disable global alpha blending. If disabled,
605  *		per pixel blending is used.
606  * @alpha:	global alpha value.
607  * @return:	0 on success or negative error code on failure.
608  */
sdc_set_global_alpha(struct mx3fb_data * mx3fb,bool enable,uint8_t alpha)609 static int sdc_set_global_alpha(struct mx3fb_data *mx3fb, bool enable, uint8_t alpha)
610 {
611 	uint32_t reg;
612 	unsigned long lock_flags;
613 
614 	spin_lock_irqsave(&mx3fb->lock, lock_flags);
615 
616 	if (enable) {
617 		reg = mx3fb_read_reg(mx3fb, SDC_GW_CTRL) & 0x00FFFFFFL;
618 		mx3fb_write_reg(mx3fb, reg | ((uint32_t) alpha << 24), SDC_GW_CTRL);
619 
620 		reg = mx3fb_read_reg(mx3fb, SDC_COM_CONF);
621 		mx3fb_write_reg(mx3fb, reg | SDC_COM_GLB_A, SDC_COM_CONF);
622 	} else {
623 		reg = mx3fb_read_reg(mx3fb, SDC_COM_CONF);
624 		mx3fb_write_reg(mx3fb, reg & ~SDC_COM_GLB_A, SDC_COM_CONF);
625 	}
626 
627 	spin_unlock_irqrestore(&mx3fb->lock, lock_flags);
628 
629 	return 0;
630 }
631 
sdc_set_brightness(struct mx3fb_data * mx3fb,uint8_t value)632 static void sdc_set_brightness(struct mx3fb_data *mx3fb, uint8_t value)
633 {
634 	dev_dbg(mx3fb->dev, "%s: value = %d\n", __func__, value);
635 	/* This might be board-specific */
636 	mx3fb_write_reg(mx3fb, 0x03000000UL | value << 16, SDC_PWM_CTRL);
637 	return;
638 }
639 
bpp_to_pixfmt(int bpp)640 static uint32_t bpp_to_pixfmt(int bpp)
641 {
642 	uint32_t pixfmt = 0;
643 	switch (bpp) {
644 	case 24:
645 		pixfmt = IPU_PIX_FMT_BGR24;
646 		break;
647 	case 32:
648 		pixfmt = IPU_PIX_FMT_BGR32;
649 		break;
650 	case 16:
651 		pixfmt = IPU_PIX_FMT_RGB565;
652 		break;
653 	}
654 	return pixfmt;
655 }
656 
657 static int mx3fb_blank(int blank, struct fb_info *fbi);
658 static int mx3fb_map_video_memory(struct fb_info *fbi, unsigned int mem_len,
659 				  bool lock);
660 static int mx3fb_unmap_video_memory(struct fb_info *fbi);
661 
662 /**
663  * mx3fb_set_fix() - set fixed framebuffer parameters from variable settings.
664  * @info:	framebuffer information pointer
665  * @return:	0 on success or negative error code on failure.
666  */
mx3fb_set_fix(struct fb_info * fbi)667 static int mx3fb_set_fix(struct fb_info *fbi)
668 {
669 	struct fb_fix_screeninfo *fix = &fbi->fix;
670 	struct fb_var_screeninfo *var = &fbi->var;
671 
672 	strncpy(fix->id, "DISP3 BG", 8);
673 
674 	fix->line_length = var->xres_virtual * var->bits_per_pixel / 8;
675 
676 	fix->type = FB_TYPE_PACKED_PIXELS;
677 	fix->accel = FB_ACCEL_NONE;
678 	fix->visual = FB_VISUAL_TRUECOLOR;
679 	fix->xpanstep = 1;
680 	fix->ypanstep = 1;
681 
682 	return 0;
683 }
684 
mx3fb_dma_done(void * arg)685 static void mx3fb_dma_done(void *arg)
686 {
687 	struct idmac_tx_desc *tx_desc = to_tx_desc(arg);
688 	struct dma_chan *chan = tx_desc->txd.chan;
689 	struct idmac_channel *ichannel = to_idmac_chan(chan);
690 	struct mx3fb_data *mx3fb = ichannel->client;
691 	struct mx3fb_info *mx3_fbi = mx3fb->fbi->par;
692 
693 	dev_dbg(mx3fb->dev, "irq %d callback\n", ichannel->eof_irq);
694 
695 	/* We only need one interrupt, it will be re-enabled as needed */
696 	disable_irq_nosync(ichannel->eof_irq);
697 
698 	complete(&mx3_fbi->flip_cmpl);
699 }
700 
__set_par(struct fb_info * fbi,bool lock)701 static int __set_par(struct fb_info *fbi, bool lock)
702 {
703 	u32 mem_len;
704 	struct ipu_di_signal_cfg sig_cfg;
705 	enum ipu_panel mode = IPU_PANEL_TFT;
706 	struct mx3fb_info *mx3_fbi = fbi->par;
707 	struct mx3fb_data *mx3fb = mx3_fbi->mx3fb;
708 	struct idmac_channel *ichan = mx3_fbi->idmac_channel;
709 	struct idmac_video_param *video = &ichan->params.video;
710 	struct scatterlist *sg = mx3_fbi->sg;
711 
712 	/* Total cleanup */
713 	if (mx3_fbi->txd)
714 		sdc_disable_channel(mx3_fbi);
715 
716 	mx3fb_set_fix(fbi);
717 
718 	mem_len = fbi->var.yres_virtual * fbi->fix.line_length;
719 	if (mem_len > fbi->fix.smem_len) {
720 		if (fbi->fix.smem_start)
721 			mx3fb_unmap_video_memory(fbi);
722 
723 		if (mx3fb_map_video_memory(fbi, mem_len, lock) < 0)
724 			return -ENOMEM;
725 	}
726 
727 	sg_init_table(&sg[0], 1);
728 	sg_init_table(&sg[1], 1);
729 
730 	sg_dma_address(&sg[0]) = fbi->fix.smem_start;
731 	sg_set_page(&sg[0], virt_to_page(fbi->screen_base),
732 		    fbi->fix.smem_len,
733 		    offset_in_page(fbi->screen_base));
734 
735 	if (mx3_fbi->ipu_ch == IDMAC_SDC_0) {
736 		memset(&sig_cfg, 0, sizeof(sig_cfg));
737 		if (fbi->var.sync & FB_SYNC_HOR_HIGH_ACT)
738 			sig_cfg.Hsync_pol = true;
739 		if (fbi->var.sync & FB_SYNC_VERT_HIGH_ACT)
740 			sig_cfg.Vsync_pol = true;
741 		if (fbi->var.sync & FB_SYNC_CLK_INVERT)
742 			sig_cfg.clk_pol = true;
743 		if (fbi->var.sync & FB_SYNC_DATA_INVERT)
744 			sig_cfg.data_pol = true;
745 		if (fbi->var.sync & FB_SYNC_OE_ACT_HIGH)
746 			sig_cfg.enable_pol = true;
747 		if (fbi->var.sync & FB_SYNC_CLK_IDLE_EN)
748 			sig_cfg.clkidle_en = true;
749 		if (fbi->var.sync & FB_SYNC_CLK_SEL_EN)
750 			sig_cfg.clksel_en = true;
751 		if (fbi->var.sync & FB_SYNC_SHARP_MODE)
752 			mode = IPU_PANEL_SHARP_TFT;
753 
754 		dev_dbg(fbi->device, "pixclock = %ul Hz\n",
755 			(u32) (PICOS2KHZ(fbi->var.pixclock) * 1000UL));
756 
757 		if (sdc_init_panel(mx3fb, mode,
758 				   (PICOS2KHZ(fbi->var.pixclock)) * 1000UL,
759 				   fbi->var.xres, fbi->var.yres,
760 				   fbi->var.left_margin,
761 				   fbi->var.hsync_len,
762 				   fbi->var.right_margin +
763 				   fbi->var.hsync_len,
764 				   fbi->var.upper_margin,
765 				   fbi->var.vsync_len,
766 				   fbi->var.lower_margin +
767 				   fbi->var.vsync_len, sig_cfg) != 0) {
768 			dev_err(fbi->device,
769 				"mx3fb: Error initializing panel.\n");
770 			return -EINVAL;
771 		}
772 	}
773 
774 	sdc_set_window_pos(mx3fb, mx3_fbi->ipu_ch, 0, 0);
775 
776 	mx3_fbi->cur_ipu_buf	= 0;
777 
778 	video->out_pixel_fmt	= bpp_to_pixfmt(fbi->var.bits_per_pixel);
779 	video->out_width	= fbi->var.xres;
780 	video->out_height	= fbi->var.yres;
781 	video->out_stride	= fbi->var.xres_virtual;
782 
783 	if (mx3_fbi->blank == FB_BLANK_UNBLANK)
784 		sdc_enable_channel(mx3_fbi);
785 
786 	return 0;
787 }
788 
789 /**
790  * mx3fb_set_par() - set framebuffer parameters and change the operating mode.
791  * @fbi:	framebuffer information pointer.
792  * @return:	0 on success or negative error code on failure.
793  */
mx3fb_set_par(struct fb_info * fbi)794 static int mx3fb_set_par(struct fb_info *fbi)
795 {
796 	struct mx3fb_info *mx3_fbi = fbi->par;
797 	struct mx3fb_data *mx3fb = mx3_fbi->mx3fb;
798 	struct idmac_channel *ichan = mx3_fbi->idmac_channel;
799 	int ret;
800 
801 	dev_dbg(mx3fb->dev, "%s [%c]\n", __func__, list_empty(&ichan->queue) ? '-' : '+');
802 
803 	mutex_lock(&mx3_fbi->mutex);
804 
805 	ret = __set_par(fbi, true);
806 
807 	mutex_unlock(&mx3_fbi->mutex);
808 
809 	return ret;
810 }
811 
812 /**
813  * mx3fb_check_var() - check and adjust framebuffer variable parameters.
814  * @var:	framebuffer variable parameters
815  * @fbi:	framebuffer information pointer
816  */
mx3fb_check_var(struct fb_var_screeninfo * var,struct fb_info * fbi)817 static int mx3fb_check_var(struct fb_var_screeninfo *var, struct fb_info *fbi)
818 {
819 	struct mx3fb_info *mx3_fbi = fbi->par;
820 	u32 vtotal;
821 	u32 htotal;
822 
823 	dev_dbg(fbi->device, "%s\n", __func__);
824 
825 	if (var->xres_virtual < var->xres)
826 		var->xres_virtual = var->xres;
827 	if (var->yres_virtual < var->yres)
828 		var->yres_virtual = var->yres;
829 
830 	if ((var->bits_per_pixel != 32) && (var->bits_per_pixel != 24) &&
831 	    (var->bits_per_pixel != 16))
832 		var->bits_per_pixel = default_bpp;
833 
834 	switch (var->bits_per_pixel) {
835 	case 16:
836 		var->red.length = 5;
837 		var->red.offset = 11;
838 		var->red.msb_right = 0;
839 
840 		var->green.length = 6;
841 		var->green.offset = 5;
842 		var->green.msb_right = 0;
843 
844 		var->blue.length = 5;
845 		var->blue.offset = 0;
846 		var->blue.msb_right = 0;
847 
848 		var->transp.length = 0;
849 		var->transp.offset = 0;
850 		var->transp.msb_right = 0;
851 		break;
852 	case 24:
853 		var->red.length = 8;
854 		var->red.offset = 16;
855 		var->red.msb_right = 0;
856 
857 		var->green.length = 8;
858 		var->green.offset = 8;
859 		var->green.msb_right = 0;
860 
861 		var->blue.length = 8;
862 		var->blue.offset = 0;
863 		var->blue.msb_right = 0;
864 
865 		var->transp.length = 0;
866 		var->transp.offset = 0;
867 		var->transp.msb_right = 0;
868 		break;
869 	case 32:
870 		var->red.length = 8;
871 		var->red.offset = 16;
872 		var->red.msb_right = 0;
873 
874 		var->green.length = 8;
875 		var->green.offset = 8;
876 		var->green.msb_right = 0;
877 
878 		var->blue.length = 8;
879 		var->blue.offset = 0;
880 		var->blue.msb_right = 0;
881 
882 		var->transp.length = 8;
883 		var->transp.offset = 24;
884 		var->transp.msb_right = 0;
885 		break;
886 	}
887 
888 	if (var->pixclock < 1000) {
889 		htotal = var->xres + var->right_margin + var->hsync_len +
890 		    var->left_margin;
891 		vtotal = var->yres + var->lower_margin + var->vsync_len +
892 		    var->upper_margin;
893 		var->pixclock = (vtotal * htotal * 6UL) / 100UL;
894 		var->pixclock = KHZ2PICOS(var->pixclock);
895 		dev_dbg(fbi->device, "pixclock set for 60Hz refresh = %u ps\n",
896 			var->pixclock);
897 	}
898 
899 	var->height = -1;
900 	var->width = -1;
901 	var->grayscale = 0;
902 
903 	/* Preserve sync flags */
904 	var->sync |= mx3_fbi->sync;
905 	mx3_fbi->sync |= var->sync;
906 
907 	return 0;
908 }
909 
chan_to_field(unsigned int chan,struct fb_bitfield * bf)910 static u32 chan_to_field(unsigned int chan, struct fb_bitfield *bf)
911 {
912 	chan &= 0xffff;
913 	chan >>= 16 - bf->length;
914 	return chan << bf->offset;
915 }
916 
mx3fb_setcolreg(unsigned int regno,unsigned int red,unsigned int green,unsigned int blue,unsigned int trans,struct fb_info * fbi)917 static int mx3fb_setcolreg(unsigned int regno, unsigned int red,
918 			   unsigned int green, unsigned int blue,
919 			   unsigned int trans, struct fb_info *fbi)
920 {
921 	struct mx3fb_info *mx3_fbi = fbi->par;
922 	u32 val;
923 	int ret = 1;
924 
925 	dev_dbg(fbi->device, "%s, regno = %u\n", __func__, regno);
926 
927 	mutex_lock(&mx3_fbi->mutex);
928 	/*
929 	 * If greyscale is true, then we convert the RGB value
930 	 * to greyscale no matter what visual we are using.
931 	 */
932 	if (fbi->var.grayscale)
933 		red = green = blue = (19595 * red + 38470 * green +
934 				      7471 * blue) >> 16;
935 	switch (fbi->fix.visual) {
936 	case FB_VISUAL_TRUECOLOR:
937 		/*
938 		 * 16-bit True Colour.  We encode the RGB value
939 		 * according to the RGB bitfield information.
940 		 */
941 		if (regno < 16) {
942 			u32 *pal = fbi->pseudo_palette;
943 
944 			val = chan_to_field(red, &fbi->var.red);
945 			val |= chan_to_field(green, &fbi->var.green);
946 			val |= chan_to_field(blue, &fbi->var.blue);
947 
948 			pal[regno] = val;
949 
950 			ret = 0;
951 		}
952 		break;
953 
954 	case FB_VISUAL_STATIC_PSEUDOCOLOR:
955 	case FB_VISUAL_PSEUDOCOLOR:
956 		break;
957 	}
958 	mutex_unlock(&mx3_fbi->mutex);
959 
960 	return ret;
961 }
962 
__blank(int blank,struct fb_info * fbi)963 static void __blank(int blank, struct fb_info *fbi)
964 {
965 	struct mx3fb_info *mx3_fbi = fbi->par;
966 	struct mx3fb_data *mx3fb = mx3_fbi->mx3fb;
967 	int was_blank = mx3_fbi->blank;
968 
969 	mx3_fbi->blank = blank;
970 
971 	/* Attention!
972 	 * Do not call sdc_disable_channel() for a channel that is disabled
973 	 * already! This will result in a kernel NULL pointer dereference
974 	 * (mx3_fbi->txd is NULL). Hide the fact, that all blank modes are
975 	 * handled equally by this driver.
976 	 */
977 	if (blank > FB_BLANK_UNBLANK && was_blank > FB_BLANK_UNBLANK)
978 		return;
979 
980 	switch (blank) {
981 	case FB_BLANK_POWERDOWN:
982 	case FB_BLANK_VSYNC_SUSPEND:
983 	case FB_BLANK_HSYNC_SUSPEND:
984 	case FB_BLANK_NORMAL:
985 		sdc_set_brightness(mx3fb, 0);
986 		memset((char *)fbi->screen_base, 0, fbi->fix.smem_len);
987 		/* Give LCD time to update - enough for 50 and 60 Hz */
988 		msleep(25);
989 		sdc_disable_channel(mx3_fbi);
990 		break;
991 	case FB_BLANK_UNBLANK:
992 		sdc_enable_channel(mx3_fbi);
993 		sdc_set_brightness(mx3fb, mx3fb->backlight_level);
994 		break;
995 	}
996 }
997 
998 /**
999  * mx3fb_blank() - blank the display.
1000  */
mx3fb_blank(int blank,struct fb_info * fbi)1001 static int mx3fb_blank(int blank, struct fb_info *fbi)
1002 {
1003 	struct mx3fb_info *mx3_fbi = fbi->par;
1004 
1005 	dev_dbg(fbi->device, "%s, blank = %d, base %p, len %u\n", __func__,
1006 		blank, fbi->screen_base, fbi->fix.smem_len);
1007 
1008 	if (mx3_fbi->blank == blank)
1009 		return 0;
1010 
1011 	mutex_lock(&mx3_fbi->mutex);
1012 	__blank(blank, fbi);
1013 	mutex_unlock(&mx3_fbi->mutex);
1014 
1015 	return 0;
1016 }
1017 
1018 /**
1019  * mx3fb_pan_display() - pan or wrap the display
1020  * @var:	variable screen buffer information.
1021  * @info:	framebuffer information pointer.
1022  *
1023  * We look only at xoffset, yoffset and the FB_VMODE_YWRAP flag
1024  */
mx3fb_pan_display(struct fb_var_screeninfo * var,struct fb_info * fbi)1025 static int mx3fb_pan_display(struct fb_var_screeninfo *var,
1026 			     struct fb_info *fbi)
1027 {
1028 	struct mx3fb_info *mx3_fbi = fbi->par;
1029 	u32 y_bottom;
1030 	unsigned long base;
1031 	off_t offset;
1032 	dma_cookie_t cookie;
1033 	struct scatterlist *sg = mx3_fbi->sg;
1034 	struct dma_chan *dma_chan = &mx3_fbi->idmac_channel->dma_chan;
1035 	struct dma_async_tx_descriptor *txd;
1036 	int ret;
1037 
1038 	dev_dbg(fbi->device, "%s [%c]\n", __func__,
1039 		list_empty(&mx3_fbi->idmac_channel->queue) ? '-' : '+');
1040 
1041 	if (var->xoffset > 0) {
1042 		dev_dbg(fbi->device, "x panning not supported\n");
1043 		return -EINVAL;
1044 	}
1045 
1046 	if (fbi->var.xoffset == var->xoffset &&
1047 	    fbi->var.yoffset == var->yoffset)
1048 		return 0;	/* No change, do nothing */
1049 
1050 	y_bottom = var->yoffset;
1051 
1052 	if (!(var->vmode & FB_VMODE_YWRAP))
1053 		y_bottom += fbi->var.yres;
1054 
1055 	if (y_bottom > fbi->var.yres_virtual)
1056 		return -EINVAL;
1057 
1058 	mutex_lock(&mx3_fbi->mutex);
1059 
1060 	offset = var->yoffset * fbi->fix.line_length
1061 	       + var->xoffset * (fbi->var.bits_per_pixel / 8);
1062 	base = fbi->fix.smem_start + offset;
1063 
1064 	dev_dbg(fbi->device, "Updating SDC BG buf %d address=0x%08lX\n",
1065 		mx3_fbi->cur_ipu_buf, base);
1066 
1067 	/*
1068 	 * We enable the End of Frame interrupt, which will free a tx-descriptor,
1069 	 * which we will need for the next device_prep_slave_sg(). The
1070 	 * IRQ-handler will disable the IRQ again.
1071 	 */
1072 	init_completion(&mx3_fbi->flip_cmpl);
1073 	enable_irq(mx3_fbi->idmac_channel->eof_irq);
1074 
1075 	ret = wait_for_completion_timeout(&mx3_fbi->flip_cmpl, HZ / 10);
1076 	if (ret <= 0) {
1077 		mutex_unlock(&mx3_fbi->mutex);
1078 		dev_info(fbi->device, "Panning failed due to %s\n", ret < 0 ?
1079 			 "user interrupt" : "timeout");
1080 		disable_irq(mx3_fbi->idmac_channel->eof_irq);
1081 		return ret ? : -ETIMEDOUT;
1082 	}
1083 
1084 	mx3_fbi->cur_ipu_buf = !mx3_fbi->cur_ipu_buf;
1085 
1086 	sg_dma_address(&sg[mx3_fbi->cur_ipu_buf]) = base;
1087 	sg_set_page(&sg[mx3_fbi->cur_ipu_buf],
1088 		    virt_to_page(fbi->screen_base + offset), fbi->fix.smem_len,
1089 		    offset_in_page(fbi->screen_base + offset));
1090 
1091 	if (mx3_fbi->txd)
1092 		async_tx_ack(mx3_fbi->txd);
1093 
1094 	txd = dma_chan->device->device_prep_slave_sg(dma_chan, sg +
1095 		mx3_fbi->cur_ipu_buf, 1, DMA_MEM_TO_DEV, DMA_PREP_INTERRUPT);
1096 	if (!txd) {
1097 		dev_err(fbi->device,
1098 			"Error preparing a DMA transaction descriptor.\n");
1099 		mutex_unlock(&mx3_fbi->mutex);
1100 		return -EIO;
1101 	}
1102 
1103 	txd->callback_param	= txd;
1104 	txd->callback		= mx3fb_dma_done;
1105 
1106 	/*
1107 	 * Emulate original mx3fb behaviour: each new call to idmac_tx_submit()
1108 	 * should switch to another buffer
1109 	 */
1110 	cookie = txd->tx_submit(txd);
1111 	dev_dbg(fbi->device, "%d: Submit %p #%d\n", __LINE__, txd, cookie);
1112 	if (cookie < 0) {
1113 		dev_err(fbi->device,
1114 			"Error updating SDC buf %d to address=0x%08lX\n",
1115 			mx3_fbi->cur_ipu_buf, base);
1116 		mutex_unlock(&mx3_fbi->mutex);
1117 		return -EIO;
1118 	}
1119 
1120 	mx3_fbi->txd = txd;
1121 
1122 	fbi->var.xoffset = var->xoffset;
1123 	fbi->var.yoffset = var->yoffset;
1124 
1125 	if (var->vmode & FB_VMODE_YWRAP)
1126 		fbi->var.vmode |= FB_VMODE_YWRAP;
1127 	else
1128 		fbi->var.vmode &= ~FB_VMODE_YWRAP;
1129 
1130 	mutex_unlock(&mx3_fbi->mutex);
1131 
1132 	dev_dbg(fbi->device, "Update complete\n");
1133 
1134 	return 0;
1135 }
1136 
1137 /*
1138  * This structure contains the pointers to the control functions that are
1139  * invoked by the core framebuffer driver to perform operations like
1140  * blitting, rectangle filling, copy regions and cursor definition.
1141  */
1142 static struct fb_ops mx3fb_ops = {
1143 	.owner = THIS_MODULE,
1144 	.fb_set_par = mx3fb_set_par,
1145 	.fb_check_var = mx3fb_check_var,
1146 	.fb_setcolreg = mx3fb_setcolreg,
1147 	.fb_pan_display = mx3fb_pan_display,
1148 	.fb_fillrect = cfb_fillrect,
1149 	.fb_copyarea = cfb_copyarea,
1150 	.fb_imageblit = cfb_imageblit,
1151 	.fb_blank = mx3fb_blank,
1152 };
1153 
1154 #ifdef CONFIG_PM
1155 /*
1156  * Power management hooks.      Note that we won't be called from IRQ context,
1157  * unlike the blank functions above, so we may sleep.
1158  */
1159 
1160 /*
1161  * Suspends the framebuffer and blanks the screen. Power management support
1162  */
mx3fb_suspend(struct platform_device * pdev,pm_message_t state)1163 static int mx3fb_suspend(struct platform_device *pdev, pm_message_t state)
1164 {
1165 	struct mx3fb_data *mx3fb = platform_get_drvdata(pdev);
1166 	struct mx3fb_info *mx3_fbi = mx3fb->fbi->par;
1167 
1168 	console_lock();
1169 	fb_set_suspend(mx3fb->fbi, 1);
1170 	console_unlock();
1171 
1172 	if (mx3_fbi->blank == FB_BLANK_UNBLANK) {
1173 		sdc_disable_channel(mx3_fbi);
1174 		sdc_set_brightness(mx3fb, 0);
1175 
1176 	}
1177 	return 0;
1178 }
1179 
1180 /*
1181  * Resumes the framebuffer and unblanks the screen. Power management support
1182  */
mx3fb_resume(struct platform_device * pdev)1183 static int mx3fb_resume(struct platform_device *pdev)
1184 {
1185 	struct mx3fb_data *mx3fb = platform_get_drvdata(pdev);
1186 	struct mx3fb_info *mx3_fbi = mx3fb->fbi->par;
1187 
1188 	if (mx3_fbi->blank == FB_BLANK_UNBLANK) {
1189 		sdc_enable_channel(mx3_fbi);
1190 		sdc_set_brightness(mx3fb, mx3fb->backlight_level);
1191 	}
1192 
1193 	console_lock();
1194 	fb_set_suspend(mx3fb->fbi, 0);
1195 	console_unlock();
1196 
1197 	return 0;
1198 }
1199 #else
1200 #define mx3fb_suspend   NULL
1201 #define mx3fb_resume    NULL
1202 #endif
1203 
1204 /*
1205  * Main framebuffer functions
1206  */
1207 
1208 /**
1209  * mx3fb_map_video_memory() - allocates the DRAM memory for the frame buffer.
1210  * @fbi:	framebuffer information pointer
1211  * @mem_len:	length of mapped memory
1212  * @lock:	do not lock during initialisation
1213  * @return:	Error code indicating success or failure
1214  *
1215  * This buffer is remapped into a non-cached, non-buffered, memory region to
1216  * allow palette and pixel writes to occur without flushing the cache. Once this
1217  * area is remapped, all virtual memory access to the video memory should occur
1218  * at the new region.
1219  */
mx3fb_map_video_memory(struct fb_info * fbi,unsigned int mem_len,bool lock)1220 static int mx3fb_map_video_memory(struct fb_info *fbi, unsigned int mem_len,
1221 				  bool lock)
1222 {
1223 	int retval = 0;
1224 	dma_addr_t addr;
1225 
1226 	fbi->screen_base = dma_alloc_writecombine(fbi->device,
1227 						  mem_len,
1228 						  &addr, GFP_DMA);
1229 
1230 	if (!fbi->screen_base) {
1231 		dev_err(fbi->device, "Cannot allocate %u bytes framebuffer memory\n",
1232 			mem_len);
1233 		retval = -EBUSY;
1234 		goto err0;
1235 	}
1236 
1237 	if (lock)
1238 		mutex_lock(&fbi->mm_lock);
1239 	fbi->fix.smem_start = addr;
1240 	fbi->fix.smem_len = mem_len;
1241 	if (lock)
1242 		mutex_unlock(&fbi->mm_lock);
1243 
1244 	dev_dbg(fbi->device, "allocated fb @ p=0x%08x, v=0x%p, size=%d.\n",
1245 		(uint32_t) fbi->fix.smem_start, fbi->screen_base, fbi->fix.smem_len);
1246 
1247 	fbi->screen_size = fbi->fix.smem_len;
1248 
1249 	/* Clear the screen */
1250 	memset((char *)fbi->screen_base, 0, fbi->fix.smem_len);
1251 
1252 	return 0;
1253 
1254 err0:
1255 	fbi->fix.smem_len = 0;
1256 	fbi->fix.smem_start = 0;
1257 	fbi->screen_base = NULL;
1258 	return retval;
1259 }
1260 
1261 /**
1262  * mx3fb_unmap_video_memory() - de-allocate frame buffer memory.
1263  * @fbi:	framebuffer information pointer
1264  * @return:	error code indicating success or failure
1265  */
mx3fb_unmap_video_memory(struct fb_info * fbi)1266 static int mx3fb_unmap_video_memory(struct fb_info *fbi)
1267 {
1268 	dma_free_writecombine(fbi->device, fbi->fix.smem_len,
1269 			      fbi->screen_base, fbi->fix.smem_start);
1270 
1271 	fbi->screen_base = 0;
1272 	mutex_lock(&fbi->mm_lock);
1273 	fbi->fix.smem_start = 0;
1274 	fbi->fix.smem_len = 0;
1275 	mutex_unlock(&fbi->mm_lock);
1276 	return 0;
1277 }
1278 
1279 /**
1280  * mx3fb_init_fbinfo() - initialize framebuffer information object.
1281  * @return:	initialized framebuffer structure.
1282  */
mx3fb_init_fbinfo(struct device * dev,struct fb_ops * ops)1283 static struct fb_info *mx3fb_init_fbinfo(struct device *dev, struct fb_ops *ops)
1284 {
1285 	struct fb_info *fbi;
1286 	struct mx3fb_info *mx3fbi;
1287 	int ret;
1288 
1289 	/* Allocate sufficient memory for the fb structure */
1290 	fbi = framebuffer_alloc(sizeof(struct mx3fb_info), dev);
1291 	if (!fbi)
1292 		return NULL;
1293 
1294 	mx3fbi			= fbi->par;
1295 	mx3fbi->cookie		= -EINVAL;
1296 	mx3fbi->cur_ipu_buf	= 0;
1297 
1298 	fbi->var.activate	= FB_ACTIVATE_NOW;
1299 
1300 	fbi->fbops		= ops;
1301 	fbi->flags		= FBINFO_FLAG_DEFAULT;
1302 	fbi->pseudo_palette	= mx3fbi->pseudo_palette;
1303 
1304 	mutex_init(&mx3fbi->mutex);
1305 
1306 	/* Allocate colormap */
1307 	ret = fb_alloc_cmap(&fbi->cmap, 16, 0);
1308 	if (ret < 0) {
1309 		framebuffer_release(fbi);
1310 		return NULL;
1311 	}
1312 
1313 	return fbi;
1314 }
1315 
init_fb_chan(struct mx3fb_data * mx3fb,struct idmac_channel * ichan)1316 static int init_fb_chan(struct mx3fb_data *mx3fb, struct idmac_channel *ichan)
1317 {
1318 	struct device *dev = mx3fb->dev;
1319 	struct mx3fb_platform_data *mx3fb_pdata = dev->platform_data;
1320 	const char *name = mx3fb_pdata->name;
1321 	unsigned int irq;
1322 	struct fb_info *fbi;
1323 	struct mx3fb_info *mx3fbi;
1324 	const struct fb_videomode *mode;
1325 	int ret, num_modes;
1326 
1327 	if (mx3fb_pdata->disp_data_fmt >= ARRAY_SIZE(di_mappings)) {
1328 		dev_err(dev, "Illegal display data format %d\n",
1329 				mx3fb_pdata->disp_data_fmt);
1330 		return -EINVAL;
1331 	}
1332 
1333 	ichan->client = mx3fb;
1334 	irq = ichan->eof_irq;
1335 
1336 	if (ichan->dma_chan.chan_id != IDMAC_SDC_0)
1337 		return -EINVAL;
1338 
1339 	fbi = mx3fb_init_fbinfo(dev, &mx3fb_ops);
1340 	if (!fbi)
1341 		return -ENOMEM;
1342 
1343 	if (!fb_mode)
1344 		fb_mode = name;
1345 
1346 	if (!fb_mode) {
1347 		ret = -EINVAL;
1348 		goto emode;
1349 	}
1350 
1351 	if (mx3fb_pdata->mode && mx3fb_pdata->num_modes) {
1352 		mode = mx3fb_pdata->mode;
1353 		num_modes = mx3fb_pdata->num_modes;
1354 	} else {
1355 		mode = mx3fb_modedb;
1356 		num_modes = ARRAY_SIZE(mx3fb_modedb);
1357 	}
1358 
1359 	if (!fb_find_mode(&fbi->var, fbi, fb_mode, mode,
1360 			  num_modes, NULL, default_bpp)) {
1361 		ret = -EBUSY;
1362 		goto emode;
1363 	}
1364 
1365 	fb_videomode_to_modelist(mode, num_modes, &fbi->modelist);
1366 
1367 	/* Default Y virtual size is 2x panel size */
1368 	fbi->var.yres_virtual = fbi->var.yres * 2;
1369 
1370 	mx3fb->fbi = fbi;
1371 
1372 	/* set Display Interface clock period */
1373 	mx3fb_write_reg(mx3fb, 0x00100010L, DI_HSP_CLK_PER);
1374 	/* Might need to trigger HSP clock change - see 44.3.3.8.5 */
1375 
1376 	sdc_set_brightness(mx3fb, 255);
1377 	sdc_set_global_alpha(mx3fb, true, 0xFF);
1378 	sdc_set_color_key(mx3fb, IDMAC_SDC_0, false, 0);
1379 
1380 	mx3fbi			= fbi->par;
1381 	mx3fbi->idmac_channel	= ichan;
1382 	mx3fbi->ipu_ch		= ichan->dma_chan.chan_id;
1383 	mx3fbi->mx3fb		= mx3fb;
1384 	mx3fbi->blank		= FB_BLANK_NORMAL;
1385 
1386 	mx3fb->disp_data_fmt	= mx3fb_pdata->disp_data_fmt;
1387 
1388 	init_completion(&mx3fbi->flip_cmpl);
1389 	disable_irq(ichan->eof_irq);
1390 	dev_dbg(mx3fb->dev, "disabling irq %d\n", ichan->eof_irq);
1391 	ret = __set_par(fbi, false);
1392 	if (ret < 0)
1393 		goto esetpar;
1394 
1395 	__blank(FB_BLANK_UNBLANK, fbi);
1396 
1397 	dev_info(dev, "registered, using mode %s\n", fb_mode);
1398 
1399 	ret = register_framebuffer(fbi);
1400 	if (ret < 0)
1401 		goto erfb;
1402 
1403 	return 0;
1404 
1405 erfb:
1406 esetpar:
1407 emode:
1408 	fb_dealloc_cmap(&fbi->cmap);
1409 	framebuffer_release(fbi);
1410 
1411 	return ret;
1412 }
1413 
chan_filter(struct dma_chan * chan,void * arg)1414 static bool chan_filter(struct dma_chan *chan, void *arg)
1415 {
1416 	struct dma_chan_request *rq = arg;
1417 	struct device *dev;
1418 	struct mx3fb_platform_data *mx3fb_pdata;
1419 
1420 	if (!imx_dma_is_ipu(chan))
1421 		return false;
1422 
1423 	if (!rq)
1424 		return false;
1425 
1426 	dev = rq->mx3fb->dev;
1427 	mx3fb_pdata = dev->platform_data;
1428 
1429 	return rq->id == chan->chan_id &&
1430 		mx3fb_pdata->dma_dev == chan->device->dev;
1431 }
1432 
release_fbi(struct fb_info * fbi)1433 static void release_fbi(struct fb_info *fbi)
1434 {
1435 	mx3fb_unmap_video_memory(fbi);
1436 
1437 	fb_dealloc_cmap(&fbi->cmap);
1438 
1439 	unregister_framebuffer(fbi);
1440 	framebuffer_release(fbi);
1441 }
1442 
mx3fb_probe(struct platform_device * pdev)1443 static int mx3fb_probe(struct platform_device *pdev)
1444 {
1445 	struct device *dev = &pdev->dev;
1446 	int ret;
1447 	struct resource *sdc_reg;
1448 	struct mx3fb_data *mx3fb;
1449 	dma_cap_mask_t mask;
1450 	struct dma_chan *chan;
1451 	struct dma_chan_request rq;
1452 
1453 	/*
1454 	 * Display Interface (DI) and Synchronous Display Controller (SDC)
1455 	 * registers
1456 	 */
1457 	sdc_reg = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1458 	if (!sdc_reg)
1459 		return -EINVAL;
1460 
1461 	mx3fb = kzalloc(sizeof(*mx3fb), GFP_KERNEL);
1462 	if (!mx3fb)
1463 		return -ENOMEM;
1464 
1465 	spin_lock_init(&mx3fb->lock);
1466 
1467 	mx3fb->reg_base = ioremap(sdc_reg->start, resource_size(sdc_reg));
1468 	if (!mx3fb->reg_base) {
1469 		ret = -ENOMEM;
1470 		goto eremap;
1471 	}
1472 
1473 	pr_debug("Remapped %pR at %p\n", sdc_reg, mx3fb->reg_base);
1474 
1475 	/* IDMAC interface */
1476 	dmaengine_get();
1477 
1478 	mx3fb->dev = dev;
1479 	platform_set_drvdata(pdev, mx3fb);
1480 
1481 	rq.mx3fb = mx3fb;
1482 
1483 	dma_cap_zero(mask);
1484 	dma_cap_set(DMA_SLAVE, mask);
1485 	dma_cap_set(DMA_PRIVATE, mask);
1486 	rq.id = IDMAC_SDC_0;
1487 	chan = dma_request_channel(mask, chan_filter, &rq);
1488 	if (!chan) {
1489 		ret = -EBUSY;
1490 		goto ersdc0;
1491 	}
1492 
1493 	mx3fb->backlight_level = 255;
1494 
1495 	ret = init_fb_chan(mx3fb, to_idmac_chan(chan));
1496 	if (ret < 0)
1497 		goto eisdc0;
1498 
1499 	return 0;
1500 
1501 eisdc0:
1502 	dma_release_channel(chan);
1503 ersdc0:
1504 	dmaengine_put();
1505 	iounmap(mx3fb->reg_base);
1506 eremap:
1507 	kfree(mx3fb);
1508 	dev_err(dev, "mx3fb: failed to register fb\n");
1509 	return ret;
1510 }
1511 
mx3fb_remove(struct platform_device * dev)1512 static int mx3fb_remove(struct platform_device *dev)
1513 {
1514 	struct mx3fb_data *mx3fb = platform_get_drvdata(dev);
1515 	struct fb_info *fbi = mx3fb->fbi;
1516 	struct mx3fb_info *mx3_fbi = fbi->par;
1517 	struct dma_chan *chan;
1518 
1519 	chan = &mx3_fbi->idmac_channel->dma_chan;
1520 	release_fbi(fbi);
1521 
1522 	dma_release_channel(chan);
1523 	dmaengine_put();
1524 
1525 	iounmap(mx3fb->reg_base);
1526 	kfree(mx3fb);
1527 	return 0;
1528 }
1529 
1530 static struct platform_driver mx3fb_driver = {
1531 	.driver = {
1532 		   .name = MX3FB_NAME,
1533 	},
1534 	.probe = mx3fb_probe,
1535 	.remove = mx3fb_remove,
1536 	.suspend = mx3fb_suspend,
1537 	.resume = mx3fb_resume,
1538 };
1539 
1540 /*
1541  * Parse user specified options (`video=mx3fb:')
1542  * example:
1543  * 	video=mx3fb:bpp=16
1544  */
mx3fb_setup(void)1545 static int __init mx3fb_setup(void)
1546 {
1547 #ifndef MODULE
1548 	char *opt, *options = NULL;
1549 
1550 	if (fb_get_options("mx3fb", &options))
1551 		return -ENODEV;
1552 
1553 	if (!options || !*options)
1554 		return 0;
1555 
1556 	while ((opt = strsep(&options, ",")) != NULL) {
1557 		if (!*opt)
1558 			continue;
1559 		if (!strncmp(opt, "bpp=", 4))
1560 			default_bpp = simple_strtoul(opt + 4, NULL, 0);
1561 		else
1562 			fb_mode = opt;
1563 	}
1564 #endif
1565 
1566 	return 0;
1567 }
1568 
mx3fb_init(void)1569 static int __init mx3fb_init(void)
1570 {
1571 	int ret = mx3fb_setup();
1572 
1573 	if (ret < 0)
1574 		return ret;
1575 
1576 	ret = platform_driver_register(&mx3fb_driver);
1577 	return ret;
1578 }
1579 
mx3fb_exit(void)1580 static void __exit mx3fb_exit(void)
1581 {
1582 	platform_driver_unregister(&mx3fb_driver);
1583 }
1584 
1585 module_init(mx3fb_init);
1586 module_exit(mx3fb_exit);
1587 
1588 MODULE_AUTHOR("Freescale Semiconductor, Inc.");
1589 MODULE_DESCRIPTION("MX3 framebuffer driver");
1590 MODULE_ALIAS("platform:" MX3FB_NAME);
1591 MODULE_LICENSE("GPL v2");
1592