1 /* SPDX-License-Identifier: MIT */
2 /* Copyright 2025 Advanced Micro Devices, Inc. */
3
4 #include "dm_services.h"
5 #include "include/logger_interface.h"
6 #include "../dce110/irq_service_dce110.h"
7
8 #include "dcn/dcn_3_6_0_offset.h"
9 #include "dcn/dcn_3_6_0_sh_mask.h"
10
11 #include "irq_service_dcn36.h"
12
13 #include "ivsrcid/dcn/irqsrcs_dcn_1_0.h"
14
to_dal_irq_source_dcn36(struct irq_service * irq_service,uint32_t src_id,uint32_t ext_id)15 static enum dc_irq_source to_dal_irq_source_dcn36(
16 struct irq_service *irq_service,
17 uint32_t src_id,
18 uint32_t ext_id)
19 {
20 switch (src_id) {
21 case DCN_1_0__SRCID__DC_D1_OTG_VSTARTUP:
22 return DC_IRQ_SOURCE_VBLANK1;
23 case DCN_1_0__SRCID__DC_D2_OTG_VSTARTUP:
24 return DC_IRQ_SOURCE_VBLANK2;
25 case DCN_1_0__SRCID__DC_D3_OTG_VSTARTUP:
26 return DC_IRQ_SOURCE_VBLANK3;
27 case DCN_1_0__SRCID__DC_D4_OTG_VSTARTUP:
28 return DC_IRQ_SOURCE_VBLANK4;
29 case DCN_1_0__SRCID__DC_D5_OTG_VSTARTUP:
30 return DC_IRQ_SOURCE_VBLANK5;
31 case DCN_1_0__SRCID__DC_D6_OTG_VSTARTUP:
32 return DC_IRQ_SOURCE_VBLANK6;
33 case DCN_1_0__SRCID__OTG1_VERTICAL_INTERRUPT0_CONTROL:
34 return DC_IRQ_SOURCE_DC1_VLINE0;
35 case DCN_1_0__SRCID__OTG2_VERTICAL_INTERRUPT0_CONTROL:
36 return DC_IRQ_SOURCE_DC2_VLINE0;
37 case DCN_1_0__SRCID__OTG3_VERTICAL_INTERRUPT0_CONTROL:
38 return DC_IRQ_SOURCE_DC3_VLINE0;
39 case DCN_1_0__SRCID__OTG4_VERTICAL_INTERRUPT0_CONTROL:
40 return DC_IRQ_SOURCE_DC4_VLINE0;
41 case DCN_1_0__SRCID__OTG5_VERTICAL_INTERRUPT0_CONTROL:
42 return DC_IRQ_SOURCE_DC5_VLINE0;
43 case DCN_1_0__SRCID__OTG6_VERTICAL_INTERRUPT0_CONTROL:
44 return DC_IRQ_SOURCE_DC6_VLINE0;
45 case DCN_1_0__SRCID__HUBP0_FLIP_INTERRUPT:
46 return DC_IRQ_SOURCE_PFLIP1;
47 case DCN_1_0__SRCID__HUBP1_FLIP_INTERRUPT:
48 return DC_IRQ_SOURCE_PFLIP2;
49 case DCN_1_0__SRCID__HUBP2_FLIP_INTERRUPT:
50 return DC_IRQ_SOURCE_PFLIP3;
51 case DCN_1_0__SRCID__HUBP3_FLIP_INTERRUPT:
52 return DC_IRQ_SOURCE_PFLIP4;
53 case DCN_1_0__SRCID__HUBP4_FLIP_INTERRUPT:
54 return DC_IRQ_SOURCE_PFLIP5;
55 case DCN_1_0__SRCID__HUBP5_FLIP_INTERRUPT:
56 return DC_IRQ_SOURCE_PFLIP6;
57 case DCN_1_0__SRCID__OTG0_IHC_V_UPDATE_NO_LOCK_INTERRUPT:
58 return DC_IRQ_SOURCE_VUPDATE1;
59 case DCN_1_0__SRCID__OTG1_IHC_V_UPDATE_NO_LOCK_INTERRUPT:
60 return DC_IRQ_SOURCE_VUPDATE2;
61 case DCN_1_0__SRCID__OTG2_IHC_V_UPDATE_NO_LOCK_INTERRUPT:
62 return DC_IRQ_SOURCE_VUPDATE3;
63 case DCN_1_0__SRCID__OTG3_IHC_V_UPDATE_NO_LOCK_INTERRUPT:
64 return DC_IRQ_SOURCE_VUPDATE4;
65 case DCN_1_0__SRCID__OTG4_IHC_V_UPDATE_NO_LOCK_INTERRUPT:
66 return DC_IRQ_SOURCE_VUPDATE5;
67 case DCN_1_0__SRCID__OTG5_IHC_V_UPDATE_NO_LOCK_INTERRUPT:
68 return DC_IRQ_SOURCE_VUPDATE6;
69 case DCN_1_0__SRCID__DMCUB_OUTBOX_LOW_PRIORITY_READY_INT:
70 return DC_IRQ_SOURCE_DMCUB_OUTBOX;
71 case DCN_1_0__SRCID__DC_HPD1_INT:
72 /* generic src_id for all HPD and HPDRX interrupts */
73 switch (ext_id) {
74 case DCN_1_0__CTXID__DC_HPD1_INT:
75 return DC_IRQ_SOURCE_HPD1;
76 case DCN_1_0__CTXID__DC_HPD2_INT:
77 return DC_IRQ_SOURCE_HPD2;
78 case DCN_1_0__CTXID__DC_HPD3_INT:
79 return DC_IRQ_SOURCE_HPD3;
80 case DCN_1_0__CTXID__DC_HPD4_INT:
81 return DC_IRQ_SOURCE_HPD4;
82 case DCN_1_0__CTXID__DC_HPD5_INT:
83 return DC_IRQ_SOURCE_HPD5;
84 case DCN_1_0__CTXID__DC_HPD6_INT:
85 return DC_IRQ_SOURCE_HPD6;
86 case DCN_1_0__CTXID__DC_HPD1_RX_INT:
87 return DC_IRQ_SOURCE_HPD1RX;
88 case DCN_1_0__CTXID__DC_HPD2_RX_INT:
89 return DC_IRQ_SOURCE_HPD2RX;
90 case DCN_1_0__CTXID__DC_HPD3_RX_INT:
91 return DC_IRQ_SOURCE_HPD3RX;
92 case DCN_1_0__CTXID__DC_HPD4_RX_INT:
93 return DC_IRQ_SOURCE_HPD4RX;
94 case DCN_1_0__CTXID__DC_HPD5_RX_INT:
95 return DC_IRQ_SOURCE_HPD5RX;
96 case DCN_1_0__CTXID__DC_HPD6_RX_INT:
97 return DC_IRQ_SOURCE_HPD6RX;
98 default:
99 return DC_IRQ_SOURCE_INVALID;
100 }
101 break;
102
103 default:
104 return DC_IRQ_SOURCE_INVALID;
105 }
106 }
107
hpd_ack(struct irq_service * irq_service,const struct irq_source_info * info)108 static bool hpd_ack(
109 struct irq_service *irq_service,
110 const struct irq_source_info *info)
111 {
112 uint32_t addr = info->status_reg;
113 uint32_t value = dm_read_reg(irq_service->ctx, addr);
114 uint32_t current_status =
115 get_reg_field_value(
116 value,
117 HPD0_DC_HPD_INT_STATUS,
118 DC_HPD_SENSE_DELAYED);
119
120 dal_irq_service_ack_generic(irq_service, info);
121
122 value = dm_read_reg(irq_service->ctx, info->enable_reg);
123
124 set_reg_field_value(
125 value,
126 current_status ? 0 : 1,
127 HPD0_DC_HPD_INT_CONTROL,
128 DC_HPD_INT_POLARITY);
129
130 dm_write_reg(irq_service->ctx, info->enable_reg, value);
131
132 return true;
133 }
134
135 static struct irq_source_info_funcs hpd_irq_info_funcs = {
136 .set = NULL,
137 .ack = hpd_ack
138 };
139
140 static struct irq_source_info_funcs hpd_rx_irq_info_funcs = {
141 .set = NULL,
142 .ack = NULL
143 };
144
145 static struct irq_source_info_funcs pflip_irq_info_funcs = {
146 .set = NULL,
147 .ack = NULL
148 };
149
150 static struct irq_source_info_funcs vupdate_no_lock_irq_info_funcs = {
151 .set = NULL,
152 .ack = NULL
153 };
154
155 static struct irq_source_info_funcs vblank_irq_info_funcs = {
156 .set = NULL,
157 .ack = NULL
158 };
159
160 static struct irq_source_info_funcs outbox_irq_info_funcs = {
161 .set = NULL,
162 .ack = NULL
163 };
164
165 static struct irq_source_info_funcs vline0_irq_info_funcs = {
166 .set = NULL,
167 .ack = NULL
168 };
169
170 #undef BASE_INNER
171 #define BASE_INNER(seg) ctx->dcn_reg_offsets[seg]
172
173 /* compile time expand base address. */
174 #define BASE(seg) \
175 BASE_INNER(seg)
176
177 #define SRI(reg_name, block, id)\
178 BASE(reg ## block ## id ## _ ## reg_name ## _BASE_IDX) + \
179 reg ## block ## id ## _ ## reg_name
180
181 #define SRI_DMUB(reg_name)\
182 BASE(reg ## reg_name ## _BASE_IDX) + \
183 reg ## reg_name
184
185 #define IRQ_REG_ENTRY(base, block, reg_num, reg1, mask1, reg2, mask2)\
186 REG_STRUCT[base + reg_num].enable_reg = SRI(reg1, block, reg_num),\
187 REG_STRUCT[base + reg_num].enable_mask = \
188 block ## reg_num ## _ ## reg1 ## __ ## mask1 ## _MASK,\
189 REG_STRUCT[base + reg_num].enable_value[0] = \
190 block ## reg_num ## _ ## reg1 ## __ ## mask1 ## _MASK,\
191 REG_STRUCT[base + reg_num].enable_value[1] = \
192 ~block ## reg_num ## _ ## reg1 ## __ ## mask1 ## _MASK, \
193 REG_STRUCT[base + reg_num].ack_reg = SRI(reg2, block, reg_num),\
194 REG_STRUCT[base + reg_num].ack_mask = \
195 block ## reg_num ## _ ## reg2 ## __ ## mask2 ## _MASK,\
196 REG_STRUCT[base + reg_num].ack_value = \
197 block ## reg_num ## _ ## reg2 ## __ ## mask2 ## _MASK \
198
199 #define IRQ_REG_ENTRY_DMUB(base, reg1, mask1, reg2, mask2)\
200 REG_STRUCT[base].enable_reg = SRI_DMUB(reg1),\
201 REG_STRUCT[base].enable_mask = \
202 reg1 ## __ ## mask1 ## _MASK,\
203 REG_STRUCT[base].enable_value[0] = \
204 reg1 ## __ ## mask1 ## _MASK,\
205 REG_STRUCT[base].enable_value[1] = \
206 ~reg1 ## __ ## mask1 ## _MASK, \
207 REG_STRUCT[base].ack_reg = SRI_DMUB(reg2),\
208 REG_STRUCT[base].ack_mask = \
209 reg2 ## __ ## mask2 ## _MASK,\
210 REG_STRUCT[base].ack_value = \
211 reg2 ## __ ## mask2 ## _MASK \
212
213 #define hpd_int_entry(reg_num)\
214 IRQ_REG_ENTRY(DC_IRQ_SOURCE_HPD1, HPD, reg_num,\
215 DC_HPD_INT_CONTROL, DC_HPD_INT_EN,\
216 DC_HPD_INT_CONTROL, DC_HPD_INT_ACK),\
217 REG_STRUCT[DC_IRQ_SOURCE_HPD1 + reg_num].funcs = &hpd_irq_info_funcs;\
218 REG_STRUCT[DC_IRQ_SOURCE_HPD1 + reg_num].status_reg = SRI(DC_HPD_INT_STATUS, HPD, reg_num);\
219
220 #define hpd_rx_int_entry(reg_num)\
221 IRQ_REG_ENTRY(DC_IRQ_SOURCE_HPD1RX, HPD, reg_num,\
222 DC_HPD_INT_CONTROL, DC_HPD_RX_INT_EN,\
223 DC_HPD_INT_CONTROL, DC_HPD_RX_INT_ACK),\
224 REG_STRUCT[DC_IRQ_SOURCE_HPD1RX + reg_num].status_reg = SRI(DC_HPD_INT_STATUS, HPD, reg_num);\
225 REG_STRUCT[DC_IRQ_SOURCE_HPD1RX + reg_num].funcs = &hpd_rx_irq_info_funcs;\
226
227 #define pflip_int_entry(reg_num)\
228 IRQ_REG_ENTRY(DC_IRQ_SOURCE_PFLIP1, HUBPREQ, reg_num,\
229 DCSURF_SURFACE_FLIP_INTERRUPT, SURFACE_FLIP_INT_MASK,\
230 DCSURF_SURFACE_FLIP_INTERRUPT, SURFACE_FLIP_CLEAR),\
231 REG_STRUCT[DC_IRQ_SOURCE_PFLIP1 + reg_num].funcs = &pflip_irq_info_funcs\
232
233 /* vupdate_no_lock_int_entry maps to DC_IRQ_SOURCE_VUPDATEx, to match semantic
234 * of DCE's DC_IRQ_SOURCE_VUPDATEx.
235 */
236 #define vupdate_no_lock_int_entry(reg_num)\
237 IRQ_REG_ENTRY(DC_IRQ_SOURCE_VUPDATE1, OTG, reg_num,\
238 OTG_GLOBAL_SYNC_STATUS, VUPDATE_NO_LOCK_INT_EN,\
239 OTG_GLOBAL_SYNC_STATUS, VUPDATE_NO_LOCK_EVENT_CLEAR),\
240 REG_STRUCT[DC_IRQ_SOURCE_VUPDATE1 + reg_num].funcs = &vupdate_no_lock_irq_info_funcs\
241
242 #define vblank_int_entry(reg_num)\
243 IRQ_REG_ENTRY(DC_IRQ_SOURCE_VBLANK1, OTG, reg_num,\
244 OTG_GLOBAL_SYNC_STATUS, VSTARTUP_INT_EN,\
245 OTG_GLOBAL_SYNC_STATUS, VSTARTUP_EVENT_CLEAR),\
246 REG_STRUCT[DC_IRQ_SOURCE_VBLANK1 + reg_num].funcs = &vblank_irq_info_funcs\
247
248 #define vline0_int_entry(reg_num)\
249 IRQ_REG_ENTRY(DC_IRQ_SOURCE_DC1_VLINE0, OTG, reg_num,\
250 OTG_VERTICAL_INTERRUPT0_CONTROL, OTG_VERTICAL_INTERRUPT0_INT_ENABLE,\
251 OTG_VERTICAL_INTERRUPT0_CONTROL, OTG_VERTICAL_INTERRUPT0_CLEAR),\
252 REG_STRUCT[DC_IRQ_SOURCE_DC1_VLINE0 + reg_num].funcs = &vline0_irq_info_funcs\
253
254 #define dmub_outbox_int_entry()\
255 IRQ_REG_ENTRY_DMUB(DC_IRQ_SOURCE_DMCUB_OUTBOX, \
256 DMCUB_INTERRUPT_ENABLE, DMCUB_OUTBOX1_READY_INT_EN,\
257 DMCUB_INTERRUPT_ACK, DMCUB_OUTBOX1_READY_INT_ACK),\
258 REG_STRUCT[DC_IRQ_SOURCE_DMCUB_OUTBOX].funcs = &outbox_irq_info_funcs
259
260 #define dummy_irq_entry(irqno) \
261 REG_STRUCT[irqno].funcs = &dummy_irq_info_funcs\
262
263 #define i2c_int_entry(reg_num) \
264 dummy_irq_entry(DC_IRQ_SOURCE_I2C_DDC ## reg_num)
265
266 #define dp_sink_int_entry(reg_num) \
267 dummy_irq_entry(DC_IRQ_SOURCE_DPSINK ## reg_num)
268
269 #define gpio_pad_int_entry(reg_num) \
270 dummy_irq_entry(DC_IRQ_SOURCE_GPIOPAD ## reg_num)
271
272 #define dc_underflow_int_entry(reg_num) \
273 dummy_irq_entry(DC_IRQ_SOURCE_DC ## reg_num ## UNDERFLOW)
274
275 static struct irq_source_info_funcs dummy_irq_info_funcs = {
276 .set = dal_irq_service_dummy_set,
277 .ack = dal_irq_service_dummy_ack
278 };
279
280 #define dcn36_irq_init_part_1() {\
281 dummy_irq_entry(DC_IRQ_SOURCE_INVALID); \
282 hpd_int_entry(0); \
283 hpd_int_entry(1); \
284 hpd_int_entry(2); \
285 hpd_int_entry(3); \
286 hpd_int_entry(4); \
287 hpd_rx_int_entry(0); \
288 hpd_rx_int_entry(1); \
289 hpd_rx_int_entry(2); \
290 hpd_rx_int_entry(3); \
291 hpd_rx_int_entry(4); \
292 i2c_int_entry(1); \
293 i2c_int_entry(2); \
294 i2c_int_entry(3); \
295 i2c_int_entry(4); \
296 i2c_int_entry(5); \
297 i2c_int_entry(6); \
298 dp_sink_int_entry(1); \
299 dp_sink_int_entry(2); \
300 dp_sink_int_entry(3); \
301 dp_sink_int_entry(4); \
302 dp_sink_int_entry(5); \
303 dp_sink_int_entry(6); \
304 dummy_irq_entry(DC_IRQ_SOURCE_TIMER); \
305 pflip_int_entry(0); \
306 pflip_int_entry(1); \
307 pflip_int_entry(2); \
308 pflip_int_entry(3); \
309 dummy_irq_entry(DC_IRQ_SOURCE_PFLIP5); \
310 dummy_irq_entry(DC_IRQ_SOURCE_PFLIP6); \
311 dummy_irq_entry(DC_IRQ_SOURCE_PFLIP_UNDERLAY0); \
312 gpio_pad_int_entry(0); \
313 gpio_pad_int_entry(1); \
314 gpio_pad_int_entry(2); \
315 gpio_pad_int_entry(3); \
316 gpio_pad_int_entry(4); \
317 gpio_pad_int_entry(5); \
318 gpio_pad_int_entry(6); \
319 gpio_pad_int_entry(7); \
320 gpio_pad_int_entry(8); \
321 gpio_pad_int_entry(9); \
322 gpio_pad_int_entry(10); \
323 gpio_pad_int_entry(11); \
324 gpio_pad_int_entry(12); \
325 gpio_pad_int_entry(13); \
326 gpio_pad_int_entry(14); \
327 gpio_pad_int_entry(15); \
328 gpio_pad_int_entry(16); \
329 gpio_pad_int_entry(17); \
330 gpio_pad_int_entry(18); \
331 gpio_pad_int_entry(19); \
332 gpio_pad_int_entry(20); \
333 gpio_pad_int_entry(21); \
334 gpio_pad_int_entry(22); \
335 gpio_pad_int_entry(23); \
336 gpio_pad_int_entry(24); \
337 gpio_pad_int_entry(25); \
338 gpio_pad_int_entry(26); \
339 gpio_pad_int_entry(27); \
340 gpio_pad_int_entry(28); \
341 gpio_pad_int_entry(29); \
342 gpio_pad_int_entry(30); \
343 dc_underflow_int_entry(1); \
344 dc_underflow_int_entry(2); \
345 dc_underflow_int_entry(3); \
346 dc_underflow_int_entry(4); \
347 dc_underflow_int_entry(5); \
348 dc_underflow_int_entry(6); \
349 dummy_irq_entry(DC_IRQ_SOURCE_DMCU_SCP); \
350 dummy_irq_entry(DC_IRQ_SOURCE_VBIOS_SW); \
351 }
352
353 #define dcn36_irq_init_part_2() {\
354 vupdate_no_lock_int_entry(0); \
355 vupdate_no_lock_int_entry(1); \
356 vupdate_no_lock_int_entry(2); \
357 vupdate_no_lock_int_entry(3); \
358 vblank_int_entry(0); \
359 vblank_int_entry(1); \
360 vblank_int_entry(2); \
361 vblank_int_entry(3); \
362 vline0_int_entry(0); \
363 vline0_int_entry(1); \
364 vline0_int_entry(2); \
365 vline0_int_entry(3); \
366 dummy_irq_entry(DC_IRQ_SOURCE_DC5_VLINE1); \
367 dummy_irq_entry(DC_IRQ_SOURCE_DC6_VLINE1); \
368 dmub_outbox_int_entry(); \
369 }
370
371 #define dcn36_irq_init() {\
372 dcn36_irq_init_part_1(); \
373 dcn36_irq_init_part_2(); \
374 }
375
376 static struct irq_source_info irq_source_info_dcn36[DAL_IRQ_SOURCES_NUMBER] = {0};
377
378 static struct irq_service_funcs irq_service_funcs_dcn36 = {
379 .to_dal_irq_source = to_dal_irq_source_dcn36
380 };
381
dcn36_irq_construct(struct irq_service * irq_service,struct irq_service_init_data * init_data)382 static void dcn36_irq_construct(
383 struct irq_service *irq_service,
384 struct irq_service_init_data *init_data)
385 {
386 struct dc_context *ctx = init_data->ctx;
387
388 #define REG_STRUCT irq_source_info_dcn36
389 dcn36_irq_init();
390
391 dal_irq_service_construct(irq_service, init_data);
392
393 irq_service->info = irq_source_info_dcn36;
394 irq_service->funcs = &irq_service_funcs_dcn36;
395 }
396
dal_irq_service_dcn36_create(struct irq_service_init_data * init_data)397 struct irq_service *dal_irq_service_dcn36_create(
398 struct irq_service_init_data *init_data)
399 {
400 struct irq_service *irq_service = kzalloc(sizeof(*irq_service),
401 GFP_KERNEL);
402
403 if (!irq_service)
404 return NULL;
405
406 dcn36_irq_construct(irq_service, init_data);
407 return irq_service;
408 }
409