1 /* SPDX-License-Identifier: GPL-2.0 */
2 /*
3 * S390 version
4 * Copyright IBM Corp. 1999
5 * Author(s): Hartmut Penner (hp@de.ibm.com),
6 * Martin Schwidefsky (schwidefsky@de.ibm.com)
7 *
8 * Derived from "include/asm-i386/processor.h"
9 * Copyright (C) 1994, Linus Torvalds
10 */
11
12 #ifndef __ASM_S390_PROCESSOR_H
13 #define __ASM_S390_PROCESSOR_H
14
15 #include <linux/bits.h>
16
17 #define CIF_NOHZ_DELAY 2 /* delay HZ disable for a tick */
18 #define CIF_FPU 3 /* restore FPU registers */
19 #define CIF_ENABLED_WAIT 5 /* in enabled wait state */
20 #define CIF_MCCK_GUEST 6 /* machine check happening in guest */
21 #define CIF_DEDICATED_CPU 7 /* this CPU is dedicated */
22
23 #define _CIF_NOHZ_DELAY BIT(CIF_NOHZ_DELAY)
24 #define _CIF_FPU BIT(CIF_FPU)
25 #define _CIF_ENABLED_WAIT BIT(CIF_ENABLED_WAIT)
26 #define _CIF_MCCK_GUEST BIT(CIF_MCCK_GUEST)
27 #define _CIF_DEDICATED_CPU BIT(CIF_DEDICATED_CPU)
28
29 #define RESTART_FLAG_CTLREGS _AC(1 << 0, U)
30
31 #ifndef __ASSEMBLY__
32
33 #include <linux/cpumask.h>
34 #include <linux/linkage.h>
35 #include <linux/irqflags.h>
36 #include <asm/cpu.h>
37 #include <asm/page.h>
38 #include <asm/ptrace.h>
39 #include <asm/setup.h>
40 #include <asm/runtime_instr.h>
41 #include <asm/fpu/types.h>
42 #include <asm/fpu/internal.h>
43 #include <asm/irqflags.h>
44
45 typedef long (*sys_call_ptr_t)(struct pt_regs *regs);
46
set_cpu_flag(int flag)47 static __always_inline void set_cpu_flag(int flag)
48 {
49 S390_lowcore.cpu_flags |= (1UL << flag);
50 }
51
clear_cpu_flag(int flag)52 static __always_inline void clear_cpu_flag(int flag)
53 {
54 S390_lowcore.cpu_flags &= ~(1UL << flag);
55 }
56
test_cpu_flag(int flag)57 static __always_inline bool test_cpu_flag(int flag)
58 {
59 return S390_lowcore.cpu_flags & (1UL << flag);
60 }
61
test_and_set_cpu_flag(int flag)62 static __always_inline bool test_and_set_cpu_flag(int flag)
63 {
64 if (test_cpu_flag(flag))
65 return true;
66 set_cpu_flag(flag);
67 return false;
68 }
69
test_and_clear_cpu_flag(int flag)70 static __always_inline bool test_and_clear_cpu_flag(int flag)
71 {
72 if (!test_cpu_flag(flag))
73 return false;
74 clear_cpu_flag(flag);
75 return true;
76 }
77
78 /*
79 * Test CIF flag of another CPU. The caller needs to ensure that
80 * CPU hotplug can not happen, e.g. by disabling preemption.
81 */
test_cpu_flag_of(int flag,int cpu)82 static __always_inline bool test_cpu_flag_of(int flag, int cpu)
83 {
84 struct lowcore *lc = lowcore_ptr[cpu];
85
86 return lc->cpu_flags & (1UL << flag);
87 }
88
89 #define arch_needs_cpu() test_cpu_flag(CIF_NOHZ_DELAY)
90
get_cpu_id(struct cpuid * ptr)91 static inline void get_cpu_id(struct cpuid *ptr)
92 {
93 asm volatile("stidp %0" : "=Q" (*ptr));
94 }
95
96 void s390_adjust_jiffies(void);
97 void s390_update_cpu_mhz(void);
98 void cpu_detect_mhz_feature(void);
99
100 extern const struct seq_operations cpuinfo_op;
101 extern void execve_tail(void);
102 unsigned long vdso_size(void);
103
104 /*
105 * User space process size: 2GB for 31 bit, 4TB or 8PT for 64 bit.
106 */
107
108 #define TASK_SIZE (test_thread_flag(TIF_31BIT) ? \
109 _REGION3_SIZE : TASK_SIZE_MAX)
110 #define TASK_UNMAPPED_BASE (test_thread_flag(TIF_31BIT) ? \
111 (_REGION3_SIZE >> 1) : (_REGION2_SIZE >> 1))
112 #define TASK_SIZE_MAX (-PAGE_SIZE)
113
114 #define VDSO_BASE (STACK_TOP + PAGE_SIZE)
115 #define VDSO_LIMIT (test_thread_flag(TIF_31BIT) ? _REGION3_SIZE : _REGION2_SIZE)
116 #define STACK_TOP (VDSO_LIMIT - vdso_size() - PAGE_SIZE)
117 #define STACK_TOP_MAX (_REGION2_SIZE - vdso_size() - PAGE_SIZE)
118
119 #define HAVE_ARCH_PICK_MMAP_LAYOUT
120
121 #define __stackleak_poison __stackleak_poison
__stackleak_poison(unsigned long erase_low,unsigned long erase_high,unsigned long poison)122 static __always_inline void __stackleak_poison(unsigned long erase_low,
123 unsigned long erase_high,
124 unsigned long poison)
125 {
126 unsigned long tmp, count;
127
128 count = erase_high - erase_low;
129 if (!count)
130 return;
131 asm volatile(
132 " cghi %[count],8\n"
133 " je 2f\n"
134 " aghi %[count],-(8+1)\n"
135 " srlg %[tmp],%[count],8\n"
136 " ltgr %[tmp],%[tmp]\n"
137 " jz 1f\n"
138 "0: stg %[poison],0(%[addr])\n"
139 " mvc 8(256-8,%[addr]),0(%[addr])\n"
140 " la %[addr],256(%[addr])\n"
141 " brctg %[tmp],0b\n"
142 "1: stg %[poison],0(%[addr])\n"
143 " larl %[tmp],3f\n"
144 " ex %[count],0(%[tmp])\n"
145 " j 4f\n"
146 "2: stg %[poison],0(%[addr])\n"
147 " j 4f\n"
148 "3: mvc 8(1,%[addr]),0(%[addr])\n"
149 "4:\n"
150 : [addr] "+&a" (erase_low), [count] "+&d" (count), [tmp] "=&a" (tmp)
151 : [poison] "d" (poison)
152 : "memory", "cc"
153 );
154 }
155
156 /*
157 * Thread structure
158 */
159 struct thread_struct {
160 unsigned int acrs[NUM_ACRS];
161 unsigned long ksp; /* kernel stack pointer */
162 unsigned long user_timer; /* task cputime in user space */
163 unsigned long guest_timer; /* task cputime in kvm guest */
164 unsigned long system_timer; /* task cputime in kernel space */
165 unsigned long hardirq_timer; /* task cputime in hardirq context */
166 unsigned long softirq_timer; /* task cputime in softirq context */
167 const sys_call_ptr_t *sys_call_table; /* system call table address */
168 unsigned long gmap_addr; /* address of last gmap fault. */
169 unsigned int gmap_write_flag; /* gmap fault write indication */
170 unsigned int gmap_int_code; /* int code of last gmap fault */
171 unsigned int gmap_pfault; /* signal of a pending guest pfault */
172
173 /* Per-thread information related to debugging */
174 struct per_regs per_user; /* User specified PER registers */
175 struct per_event per_event; /* Cause of the last PER trap */
176 unsigned long per_flags; /* Flags to control debug behavior */
177 unsigned int system_call; /* system call number in signal */
178 unsigned long last_break; /* last breaking-event-address. */
179 /* pfault_wait is used to block the process on a pfault event */
180 unsigned long pfault_wait;
181 struct list_head list;
182 /* cpu runtime instrumentation */
183 struct runtime_instr_cb *ri_cb;
184 struct gs_cb *gs_cb; /* Current guarded storage cb */
185 struct gs_cb *gs_bc_cb; /* Broadcast guarded storage cb */
186 struct pgm_tdb trap_tdb; /* Transaction abort diagnose block */
187 struct fpu fpu; /* FP and VX register save area */
188 };
189
190 /* Flag to disable transactions. */
191 #define PER_FLAG_NO_TE 1UL
192 /* Flag to enable random transaction aborts. */
193 #define PER_FLAG_TE_ABORT_RAND 2UL
194 /* Flag to specify random transaction abort mode:
195 * - abort each transaction at a random instruction before TEND if set.
196 * - abort random transactions at a random instruction if cleared.
197 */
198 #define PER_FLAG_TE_ABORT_RAND_TEND 4UL
199
200 typedef struct thread_struct thread_struct;
201
202 #define ARCH_MIN_TASKALIGN 8
203
204 #define INIT_THREAD { \
205 .ksp = sizeof(init_stack) + (unsigned long) &init_stack, \
206 .fpu.regs = (void *) init_task.thread.fpu.fprs, \
207 .last_break = 1, \
208 }
209
210 /*
211 * Do necessary setup to start up a new thread.
212 */
213 #define start_thread(regs, new_psw, new_stackp) do { \
214 regs->psw.mask = PSW_USER_BITS | PSW_MASK_EA | PSW_MASK_BA; \
215 regs->psw.addr = new_psw; \
216 regs->gprs[15] = new_stackp; \
217 execve_tail(); \
218 } while (0)
219
220 #define start_thread31(regs, new_psw, new_stackp) do { \
221 regs->psw.mask = PSW_USER_BITS | PSW_MASK_BA; \
222 regs->psw.addr = new_psw; \
223 regs->gprs[15] = new_stackp; \
224 execve_tail(); \
225 } while (0)
226
227 struct task_struct;
228 struct mm_struct;
229 struct seq_file;
230 struct pt_regs;
231
232 void show_registers(struct pt_regs *regs);
233 void show_cacheinfo(struct seq_file *m);
234
235 /* Free guarded storage control block */
236 void guarded_storage_release(struct task_struct *tsk);
237 void gs_load_bc_cb(struct pt_regs *regs);
238
239 unsigned long __get_wchan(struct task_struct *p);
240 #define task_pt_regs(tsk) ((struct pt_regs *) \
241 (task_stack_page(tsk) + THREAD_SIZE) - 1)
242 #define KSTK_EIP(tsk) (task_pt_regs(tsk)->psw.addr)
243 #define KSTK_ESP(tsk) (task_pt_regs(tsk)->gprs[15])
244
245 /* Has task runtime instrumentation enabled ? */
246 #define is_ri_task(tsk) (!!(tsk)->thread.ri_cb)
247
248 /* avoid using global register due to gcc bug in versions < 8.4 */
249 #define current_stack_pointer (__current_stack_pointer())
250
__current_stack_pointer(void)251 static __always_inline unsigned long __current_stack_pointer(void)
252 {
253 unsigned long sp;
254
255 asm volatile("lgr %0,15" : "=d" (sp));
256 return sp;
257 }
258
on_thread_stack(void)259 static __always_inline bool on_thread_stack(void)
260 {
261 unsigned long ksp = S390_lowcore.kernel_stack;
262
263 return !((ksp ^ current_stack_pointer) & ~(THREAD_SIZE - 1));
264 }
265
stap(void)266 static __always_inline unsigned short stap(void)
267 {
268 unsigned short cpu_address;
269
270 asm volatile("stap %0" : "=Q" (cpu_address));
271 return cpu_address;
272 }
273
274 #define cpu_relax() barrier()
275
276 #define ECAG_CACHE_ATTRIBUTE 0
277 #define ECAG_CPU_ATTRIBUTE 1
278
__ecag(unsigned int asi,unsigned char parm)279 static inline unsigned long __ecag(unsigned int asi, unsigned char parm)
280 {
281 unsigned long val;
282
283 asm volatile("ecag %0,0,0(%1)" : "=d" (val) : "a" (asi << 8 | parm));
284 return val;
285 }
286
psw_set_key(unsigned int key)287 static inline void psw_set_key(unsigned int key)
288 {
289 asm volatile("spka 0(%0)" : : "d" (key));
290 }
291
292 /*
293 * Set PSW to specified value.
294 */
__load_psw(psw_t psw)295 static inline void __load_psw(psw_t psw)
296 {
297 asm volatile("lpswe %0" : : "Q" (psw) : "cc");
298 }
299
300 /*
301 * Set PSW mask to specified value, while leaving the
302 * PSW addr pointing to the next instruction.
303 */
__load_psw_mask(unsigned long mask)304 static __always_inline void __load_psw_mask(unsigned long mask)
305 {
306 unsigned long addr;
307 psw_t psw;
308
309 psw.mask = mask;
310
311 asm volatile(
312 " larl %0,1f\n"
313 " stg %0,%1\n"
314 " lpswe %2\n"
315 "1:"
316 : "=&d" (addr), "=Q" (psw.addr) : "Q" (psw) : "memory", "cc");
317 }
318
319 /*
320 * Extract current PSW mask
321 */
__extract_psw(void)322 static inline unsigned long __extract_psw(void)
323 {
324 unsigned int reg1, reg2;
325
326 asm volatile("epsw %0,%1" : "=d" (reg1), "=a" (reg2));
327 return (((unsigned long) reg1) << 32) | ((unsigned long) reg2);
328 }
329
__local_mcck_save(void)330 static inline unsigned long __local_mcck_save(void)
331 {
332 unsigned long mask = __extract_psw();
333
334 __load_psw_mask(mask & ~PSW_MASK_MCHECK);
335 return mask & PSW_MASK_MCHECK;
336 }
337
338 #define local_mcck_save(mflags) \
339 do { \
340 typecheck(unsigned long, mflags); \
341 mflags = __local_mcck_save(); \
342 } while (0)
343
local_mcck_restore(unsigned long mflags)344 static inline void local_mcck_restore(unsigned long mflags)
345 {
346 unsigned long mask = __extract_psw();
347
348 mask &= ~PSW_MASK_MCHECK;
349 __load_psw_mask(mask | mflags);
350 }
351
local_mcck_disable(void)352 static inline void local_mcck_disable(void)
353 {
354 __local_mcck_save();
355 }
356
local_mcck_enable(void)357 static inline void local_mcck_enable(void)
358 {
359 __load_psw_mask(__extract_psw() | PSW_MASK_MCHECK);
360 }
361
362 /*
363 * Rewind PSW instruction address by specified number of bytes.
364 */
__rewind_psw(psw_t psw,unsigned long ilc)365 static inline unsigned long __rewind_psw(psw_t psw, unsigned long ilc)
366 {
367 unsigned long mask;
368
369 mask = (psw.mask & PSW_MASK_EA) ? -1UL :
370 (psw.mask & PSW_MASK_BA) ? (1UL << 31) - 1 :
371 (1UL << 24) - 1;
372 return (psw.addr - ilc) & mask;
373 }
374
375 /*
376 * Function to drop a processor into disabled wait state
377 */
disabled_wait(void)378 static __always_inline void __noreturn disabled_wait(void)
379 {
380 psw_t psw;
381
382 psw.mask = PSW_MASK_BASE | PSW_MASK_WAIT | PSW_MASK_BA | PSW_MASK_EA;
383 psw.addr = _THIS_IP_;
384 __load_psw(psw);
385 while (1);
386 }
387
388 #define ARCH_LOW_ADDRESS_LIMIT 0x7fffffffUL
389
regs_irqs_disabled(struct pt_regs * regs)390 static __always_inline bool regs_irqs_disabled(struct pt_regs *regs)
391 {
392 return arch_irqs_disabled_flags(regs->psw.mask);
393 }
394
395 #endif /* __ASSEMBLY__ */
396
397 #endif /* __ASM_S390_PROCESSOR_H */
398