1 // SPDX-License-Identifier: GPL-2.0-only
2 /*
3 * EMIF driver
4 *
5 * Copyright (C) 2012 Texas Instruments, Inc.
6 *
7 * Aneesh V <aneesh@ti.com>
8 * Santosh Shilimkar <santosh.shilimkar@ti.com>
9 */
10 #include <linux/cleanup.h>
11 #include <linux/err.h>
12 #include <linux/kernel.h>
13 #include <linux/reboot.h>
14 #include <linux/platform_data/emif_plat.h>
15 #include <linux/io.h>
16 #include <linux/device.h>
17 #include <linux/platform_device.h>
18 #include <linux/interrupt.h>
19 #include <linux/slab.h>
20 #include <linux/of.h>
21 #include <linux/debugfs.h>
22 #include <linux/seq_file.h>
23 #include <linux/module.h>
24 #include <linux/list.h>
25 #include <linux/spinlock.h>
26 #include <linux/pm.h>
27
28 #include "emif.h"
29 #include "jedec_ddr.h"
30 #include "of_memory.h"
31
32 /**
33 * struct emif_data - Per device static data for driver's use
34 * @duplicate: Whether the DDR devices attached to this EMIF
35 * instance are exactly same as that on EMIF1. In
36 * this case we can save some memory and processing
37 * @temperature_level: Maximum temperature of LPDDR2 devices attached
38 * to this EMIF - read from MR4 register. If there
39 * are two devices attached to this EMIF, this
40 * value is the maximum of the two temperature
41 * levels.
42 * @lpmode: Chosen low power mode
43 * @node: node in the device list
44 * @base: base address of memory-mapped IO registers.
45 * @dev: device pointer.
46 * @regs_cache: An array of 'struct emif_regs' that stores
47 * calculated register values for different
48 * frequencies, to avoid re-calculating them on
49 * each DVFS transition.
50 * @curr_regs: The set of register values used in the last
51 * frequency change (i.e. corresponding to the
52 * frequency in effect at the moment)
53 * @plat_data: Pointer to saved platform data.
54 * @debugfs_root: dentry to the root folder for EMIF in debugfs
55 * @np_ddr: Pointer to ddr device tree node
56 */
57 struct emif_data {
58 u8 duplicate;
59 u8 temperature_level;
60 u8 lpmode;
61 struct list_head node;
62 void __iomem *base;
63 struct device *dev;
64 struct emif_regs *regs_cache[EMIF_MAX_NUM_FREQUENCIES];
65 struct emif_regs *curr_regs;
66 struct emif_platform_data *plat_data;
67 struct dentry *debugfs_root;
68 struct device_node *np_ddr;
69 };
70
71 static struct emif_data *emif1;
72 static DEFINE_SPINLOCK(emif_lock);
73 static LIST_HEAD(device_list);
74
do_emif_regdump_show(struct seq_file * s,struct emif_data * emif,struct emif_regs * regs)75 static void do_emif_regdump_show(struct seq_file *s, struct emif_data *emif,
76 struct emif_regs *regs)
77 {
78 u32 type = emif->plat_data->device_info->type;
79 u32 ip_rev = emif->plat_data->ip_rev;
80
81 seq_printf(s, "EMIF register cache dump for %dMHz\n",
82 regs->freq/1000000);
83
84 seq_printf(s, "ref_ctrl_shdw\t: 0x%08x\n", regs->ref_ctrl_shdw);
85 seq_printf(s, "sdram_tim1_shdw\t: 0x%08x\n", regs->sdram_tim1_shdw);
86 seq_printf(s, "sdram_tim2_shdw\t: 0x%08x\n", regs->sdram_tim2_shdw);
87 seq_printf(s, "sdram_tim3_shdw\t: 0x%08x\n", regs->sdram_tim3_shdw);
88
89 if (ip_rev == EMIF_4D) {
90 seq_printf(s, "read_idle_ctrl_shdw_normal\t: 0x%08x\n",
91 regs->read_idle_ctrl_shdw_normal);
92 seq_printf(s, "read_idle_ctrl_shdw_volt_ramp\t: 0x%08x\n",
93 regs->read_idle_ctrl_shdw_volt_ramp);
94 } else if (ip_rev == EMIF_4D5) {
95 seq_printf(s, "dll_calib_ctrl_shdw_normal\t: 0x%08x\n",
96 regs->dll_calib_ctrl_shdw_normal);
97 seq_printf(s, "dll_calib_ctrl_shdw_volt_ramp\t: 0x%08x\n",
98 regs->dll_calib_ctrl_shdw_volt_ramp);
99 }
100
101 if (type == DDR_TYPE_LPDDR2_S2 || type == DDR_TYPE_LPDDR2_S4) {
102 seq_printf(s, "ref_ctrl_shdw_derated\t: 0x%08x\n",
103 regs->ref_ctrl_shdw_derated);
104 seq_printf(s, "sdram_tim1_shdw_derated\t: 0x%08x\n",
105 regs->sdram_tim1_shdw_derated);
106 seq_printf(s, "sdram_tim3_shdw_derated\t: 0x%08x\n",
107 regs->sdram_tim3_shdw_derated);
108 }
109 }
110
emif_regdump_show(struct seq_file * s,void * unused)111 static int emif_regdump_show(struct seq_file *s, void *unused)
112 {
113 struct emif_data *emif = s->private;
114 struct emif_regs **regs_cache;
115 int i;
116
117 if (emif->duplicate)
118 regs_cache = emif1->regs_cache;
119 else
120 regs_cache = emif->regs_cache;
121
122 for (i = 0; i < EMIF_MAX_NUM_FREQUENCIES && regs_cache[i]; i++) {
123 do_emif_regdump_show(s, emif, regs_cache[i]);
124 seq_putc(s, '\n');
125 }
126
127 return 0;
128 }
129
130 DEFINE_SHOW_ATTRIBUTE(emif_regdump);
131
emif_mr4_show(struct seq_file * s,void * unused)132 static int emif_mr4_show(struct seq_file *s, void *unused)
133 {
134 struct emif_data *emif = s->private;
135
136 seq_printf(s, "MR4=%d\n", emif->temperature_level);
137 return 0;
138 }
139
140 DEFINE_SHOW_ATTRIBUTE(emif_mr4);
141
emif_debugfs_init(struct emif_data * emif)142 static void emif_debugfs_init(struct emif_data *emif)
143 {
144 if (IS_ENABLED(CONFIG_DEBUG_FS)) {
145 emif->debugfs_root = debugfs_create_dir(dev_name(emif->dev), NULL);
146 debugfs_create_file("regcache_dump", S_IRUGO, emif->debugfs_root, emif,
147 &emif_regdump_fops);
148 debugfs_create_file("mr4", S_IRUGO, emif->debugfs_root, emif,
149 &emif_mr4_fops);
150 }
151 }
152
emif_debugfs_exit(struct emif_data * emif)153 static void emif_debugfs_exit(struct emif_data *emif)
154 {
155 if (IS_ENABLED(CONFIG_DEBUG_FS)) {
156 debugfs_remove_recursive(emif->debugfs_root);
157 emif->debugfs_root = NULL;
158 }
159 }
160
161 /*
162 * Get bus width used by EMIF. Note that this may be different from the
163 * bus width of the DDR devices used. For instance two 16-bit DDR devices
164 * may be connected to a given CS of EMIF. In this case bus width as far
165 * as EMIF is concerned is 32, where as the DDR bus width is 16 bits.
166 */
get_emif_bus_width(struct emif_data * emif)167 static u32 get_emif_bus_width(struct emif_data *emif)
168 {
169 u32 width;
170 void __iomem *base = emif->base;
171
172 width = (readl(base + EMIF_SDRAM_CONFIG) & NARROW_MODE_MASK)
173 >> NARROW_MODE_SHIFT;
174 width = width == 0 ? 32 : 16;
175
176 return width;
177 }
178
set_lpmode(struct emif_data * emif,u8 lpmode)179 static void set_lpmode(struct emif_data *emif, u8 lpmode)
180 {
181 u32 temp;
182 void __iomem *base = emif->base;
183
184 /*
185 * Workaround for errata i743 - LPDDR2 Power-Down State is Not
186 * Efficient
187 *
188 * i743 DESCRIPTION:
189 * The EMIF supports power-down state for low power. The EMIF
190 * automatically puts the SDRAM into power-down after the memory is
191 * not accessed for a defined number of cycles and the
192 * EMIF_PWR_MGMT_CTRL[10:8] REG_LP_MODE bit field is set to 0x4.
193 * As the EMIF supports automatic output impedance calibration, a ZQ
194 * calibration long command is issued every time it exits active
195 * power-down and precharge power-down modes. The EMIF waits and
196 * blocks any other command during this calibration.
197 * The EMIF does not allow selective disabling of ZQ calibration upon
198 * exit of power-down mode. Due to very short periods of power-down
199 * cycles, ZQ calibration overhead creates bandwidth issues and
200 * increases overall system power consumption. On the other hand,
201 * issuing ZQ calibration long commands when exiting self-refresh is
202 * still required.
203 *
204 * WORKAROUND
205 * Because there is no power consumption benefit of the power-down due
206 * to the calibration and there is a performance risk, the guideline
207 * is to not allow power-down state and, therefore, to not have set
208 * the EMIF_PWR_MGMT_CTRL[10:8] REG_LP_MODE bit field to 0x4.
209 */
210 if ((emif->plat_data->ip_rev == EMIF_4D) &&
211 (lpmode == EMIF_LP_MODE_PWR_DN)) {
212 WARN_ONCE(1,
213 "REG_LP_MODE = LP_MODE_PWR_DN(4) is prohibited by erratum i743 switch to LP_MODE_SELF_REFRESH(2)\n");
214 /* rollback LP_MODE to Self-refresh mode */
215 lpmode = EMIF_LP_MODE_SELF_REFRESH;
216 }
217
218 temp = readl(base + EMIF_POWER_MANAGEMENT_CONTROL);
219 temp &= ~LP_MODE_MASK;
220 temp |= (lpmode << LP_MODE_SHIFT);
221 writel(temp, base + EMIF_POWER_MANAGEMENT_CONTROL);
222 }
223
do_freq_update(void)224 static void do_freq_update(void)
225 {
226 struct emif_data *emif;
227
228 /*
229 * Workaround for errata i728: Disable LPMODE during FREQ_UPDATE
230 *
231 * i728 DESCRIPTION:
232 * The EMIF automatically puts the SDRAM into self-refresh mode
233 * after the EMIF has not performed accesses during
234 * EMIF_PWR_MGMT_CTRL[7:4] REG_SR_TIM number of DDR clock cycles
235 * and the EMIF_PWR_MGMT_CTRL[10:8] REG_LP_MODE bit field is set
236 * to 0x2. If during a small window the following three events
237 * occur:
238 * - The SR_TIMING counter expires
239 * - And frequency change is requested
240 * - And OCP access is requested
241 * Then it causes instable clock on the DDR interface.
242 *
243 * WORKAROUND
244 * To avoid the occurrence of the three events, the workaround
245 * is to disable the self-refresh when requesting a frequency
246 * change. Before requesting a frequency change the software must
247 * program EMIF_PWR_MGMT_CTRL[10:8] REG_LP_MODE to 0x0. When the
248 * frequency change has been done, the software can reprogram
249 * EMIF_PWR_MGMT_CTRL[10:8] REG_LP_MODE to 0x2
250 */
251 list_for_each_entry(emif, &device_list, node) {
252 if (emif->lpmode == EMIF_LP_MODE_SELF_REFRESH)
253 set_lpmode(emif, EMIF_LP_MODE_DISABLE);
254 }
255
256 /*
257 * TODO: Do FREQ_UPDATE here when an API
258 * is available for this as part of the new
259 * clock framework
260 */
261
262 list_for_each_entry(emif, &device_list, node) {
263 if (emif->lpmode == EMIF_LP_MODE_SELF_REFRESH)
264 set_lpmode(emif, EMIF_LP_MODE_SELF_REFRESH);
265 }
266 }
267
268 /* Find addressing table entry based on the device's type and density */
get_addressing_table(const struct ddr_device_info * device_info)269 static const struct lpddr2_addressing *get_addressing_table(
270 const struct ddr_device_info *device_info)
271 {
272 u32 index, type, density;
273
274 type = device_info->type;
275 density = device_info->density;
276
277 switch (type) {
278 case DDR_TYPE_LPDDR2_S4:
279 index = density - 1;
280 break;
281 case DDR_TYPE_LPDDR2_S2:
282 switch (density) {
283 case DDR_DENSITY_1Gb:
284 case DDR_DENSITY_2Gb:
285 index = density + 3;
286 break;
287 default:
288 index = density - 1;
289 }
290 break;
291 default:
292 return NULL;
293 }
294
295 return &lpddr2_jedec_addressing_table[index];
296 }
297
get_zq_config_reg(const struct lpddr2_addressing * addressing,bool cs1_used,bool cal_resistors_per_cs)298 static u32 get_zq_config_reg(const struct lpddr2_addressing *addressing,
299 bool cs1_used, bool cal_resistors_per_cs)
300 {
301 u32 zq = 0, val = 0;
302
303 val = EMIF_ZQCS_INTERVAL_US * 1000 / addressing->tREFI_ns;
304 zq |= val << ZQ_REFINTERVAL_SHIFT;
305
306 val = DIV_ROUND_UP(T_ZQCL_DEFAULT_NS, T_ZQCS_DEFAULT_NS) - 1;
307 zq |= val << ZQ_ZQCL_MULT_SHIFT;
308
309 val = DIV_ROUND_UP(T_ZQINIT_DEFAULT_NS, T_ZQCL_DEFAULT_NS) - 1;
310 zq |= val << ZQ_ZQINIT_MULT_SHIFT;
311
312 zq |= ZQ_SFEXITEN_ENABLE << ZQ_SFEXITEN_SHIFT;
313
314 if (cal_resistors_per_cs)
315 zq |= ZQ_DUALCALEN_ENABLE << ZQ_DUALCALEN_SHIFT;
316 else
317 zq |= ZQ_DUALCALEN_DISABLE << ZQ_DUALCALEN_SHIFT;
318
319 zq |= ZQ_CS0EN_MASK; /* CS0 is used for sure */
320
321 val = cs1_used ? 1 : 0;
322 zq |= val << ZQ_CS1EN_SHIFT;
323
324 return zq;
325 }
326
get_temp_alert_config(const struct lpddr2_addressing * addressing,const struct emif_custom_configs * custom_configs,bool cs1_used,u32 sdram_io_width,u32 emif_bus_width)327 static u32 get_temp_alert_config(const struct lpddr2_addressing *addressing,
328 const struct emif_custom_configs *custom_configs, bool cs1_used,
329 u32 sdram_io_width, u32 emif_bus_width)
330 {
331 u32 alert = 0, interval, devcnt;
332
333 if (custom_configs && (custom_configs->mask &
334 EMIF_CUSTOM_CONFIG_TEMP_ALERT_POLL_INTERVAL))
335 interval = custom_configs->temp_alert_poll_interval_ms;
336 else
337 interval = TEMP_ALERT_POLL_INTERVAL_DEFAULT_MS;
338
339 interval *= 1000000; /* Convert to ns */
340 interval /= addressing->tREFI_ns; /* Convert to refresh cycles */
341 alert |= (interval << TA_REFINTERVAL_SHIFT);
342
343 /*
344 * sdram_io_width is in 'log2(x) - 1' form. Convert emif_bus_width
345 * also to this form and subtract to get TA_DEVCNT, which is
346 * in log2(x) form.
347 */
348 emif_bus_width = __fls(emif_bus_width) - 1;
349 devcnt = emif_bus_width - sdram_io_width;
350 alert |= devcnt << TA_DEVCNT_SHIFT;
351
352 /* DEVWDT is in 'log2(x) - 3' form */
353 alert |= (sdram_io_width - 2) << TA_DEVWDT_SHIFT;
354
355 alert |= 1 << TA_SFEXITEN_SHIFT;
356 alert |= 1 << TA_CS0EN_SHIFT;
357 alert |= (cs1_used ? 1 : 0) << TA_CS1EN_SHIFT;
358
359 return alert;
360 }
361
get_pwr_mgmt_ctrl(u32 freq,struct emif_data * emif,u32 ip_rev)362 static u32 get_pwr_mgmt_ctrl(u32 freq, struct emif_data *emif, u32 ip_rev)
363 {
364 u32 pwr_mgmt_ctrl = 0, timeout;
365 u32 lpmode = EMIF_LP_MODE_SELF_REFRESH;
366 u32 timeout_perf = EMIF_LP_MODE_TIMEOUT_PERFORMANCE;
367 u32 timeout_pwr = EMIF_LP_MODE_TIMEOUT_POWER;
368 u32 freq_threshold = EMIF_LP_MODE_FREQ_THRESHOLD;
369 u32 mask;
370 u8 shift;
371
372 struct emif_custom_configs *cust_cfgs = emif->plat_data->custom_configs;
373
374 if (cust_cfgs && (cust_cfgs->mask & EMIF_CUSTOM_CONFIG_LPMODE)) {
375 lpmode = cust_cfgs->lpmode;
376 timeout_perf = cust_cfgs->lpmode_timeout_performance;
377 timeout_pwr = cust_cfgs->lpmode_timeout_power;
378 freq_threshold = cust_cfgs->lpmode_freq_threshold;
379 }
380
381 /* Timeout based on DDR frequency */
382 timeout = freq >= freq_threshold ? timeout_perf : timeout_pwr;
383
384 /*
385 * The value to be set in register is "log2(timeout) - 3"
386 * if timeout < 16 load 0 in register
387 * if timeout is not a power of 2, round to next highest power of 2
388 */
389 if (timeout < 16) {
390 timeout = 0;
391 } else {
392 if (timeout & (timeout - 1))
393 timeout <<= 1;
394 timeout = __fls(timeout) - 3;
395 }
396
397 switch (lpmode) {
398 case EMIF_LP_MODE_CLOCK_STOP:
399 shift = CS_TIM_SHIFT;
400 mask = CS_TIM_MASK;
401 break;
402 case EMIF_LP_MODE_SELF_REFRESH:
403 /* Workaround for errata i735 */
404 if (timeout < 6)
405 timeout = 6;
406
407 shift = SR_TIM_SHIFT;
408 mask = SR_TIM_MASK;
409 break;
410 case EMIF_LP_MODE_PWR_DN:
411 shift = PD_TIM_SHIFT;
412 mask = PD_TIM_MASK;
413 break;
414 case EMIF_LP_MODE_DISABLE:
415 default:
416 mask = 0;
417 shift = 0;
418 break;
419 }
420 /* Round to maximum in case of overflow, BUT warn! */
421 if (lpmode != EMIF_LP_MODE_DISABLE && timeout > mask >> shift) {
422 pr_err("TIMEOUT Overflow - lpmode=%d perf=%d pwr=%d freq=%d\n",
423 lpmode,
424 timeout_perf,
425 timeout_pwr,
426 freq_threshold);
427 WARN(1, "timeout=0x%02x greater than 0x%02x. Using max\n",
428 timeout, mask >> shift);
429 timeout = mask >> shift;
430 }
431
432 /* Setup required timing */
433 pwr_mgmt_ctrl = (timeout << shift) & mask;
434 /* setup a default mask for rest of the modes */
435 pwr_mgmt_ctrl |= (SR_TIM_MASK | CS_TIM_MASK | PD_TIM_MASK) &
436 ~mask;
437
438 /* No CS_TIM in EMIF_4D5 */
439 if (ip_rev == EMIF_4D5)
440 pwr_mgmt_ctrl &= ~CS_TIM_MASK;
441
442 pwr_mgmt_ctrl |= lpmode << LP_MODE_SHIFT;
443
444 return pwr_mgmt_ctrl;
445 }
446
447 /*
448 * Get the temperature level of the EMIF instance:
449 * Reads the MR4 register of attached SDRAM parts to find out the temperature
450 * level. If there are two parts attached(one on each CS), then the temperature
451 * level for the EMIF instance is the higher of the two temperatures.
452 */
get_temperature_level(struct emif_data * emif)453 static void get_temperature_level(struct emif_data *emif)
454 {
455 u32 temp, temperature_level;
456 void __iomem *base;
457
458 base = emif->base;
459
460 /* Read mode register 4 */
461 writel(DDR_MR4, base + EMIF_LPDDR2_MODE_REG_CONFIG);
462 temperature_level = readl(base + EMIF_LPDDR2_MODE_REG_DATA);
463 temperature_level = (temperature_level & MR4_SDRAM_REF_RATE_MASK) >>
464 MR4_SDRAM_REF_RATE_SHIFT;
465
466 if (emif->plat_data->device_info->cs1_used) {
467 writel(DDR_MR4 | CS_MASK, base + EMIF_LPDDR2_MODE_REG_CONFIG);
468 temp = readl(base + EMIF_LPDDR2_MODE_REG_DATA);
469 temp = (temp & MR4_SDRAM_REF_RATE_MASK)
470 >> MR4_SDRAM_REF_RATE_SHIFT;
471 temperature_level = max(temp, temperature_level);
472 }
473
474 /* treat everything less than nominal(3) in MR4 as nominal */
475 if (unlikely(temperature_level < SDRAM_TEMP_NOMINAL))
476 temperature_level = SDRAM_TEMP_NOMINAL;
477
478 /* if we get reserved value in MR4 persist with the existing value */
479 if (likely(temperature_level != SDRAM_TEMP_RESERVED_4))
480 emif->temperature_level = temperature_level;
481 }
482
483 /*
484 * setup_temperature_sensitive_regs() - set the timings for temperature
485 * sensitive registers. This happens once at initialisation time based
486 * on the temperature at boot time and subsequently based on the temperature
487 * alert interrupt. Temperature alert can happen when the temperature
488 * increases or drops. So this function can have the effect of either
489 * derating the timings or going back to nominal values.
490 */
setup_temperature_sensitive_regs(struct emif_data * emif,struct emif_regs * regs)491 static void setup_temperature_sensitive_regs(struct emif_data *emif,
492 struct emif_regs *regs)
493 {
494 u32 tim1, tim3, ref_ctrl, type;
495 void __iomem *base = emif->base;
496 u32 temperature;
497
498 type = emif->plat_data->device_info->type;
499
500 tim1 = regs->sdram_tim1_shdw;
501 tim3 = regs->sdram_tim3_shdw;
502 ref_ctrl = regs->ref_ctrl_shdw;
503
504 /* No de-rating for non-lpddr2 devices */
505 if (type != DDR_TYPE_LPDDR2_S2 && type != DDR_TYPE_LPDDR2_S4)
506 goto out;
507
508 temperature = emif->temperature_level;
509 if (temperature == SDRAM_TEMP_HIGH_DERATE_REFRESH) {
510 ref_ctrl = regs->ref_ctrl_shdw_derated;
511 } else if (temperature == SDRAM_TEMP_HIGH_DERATE_REFRESH_AND_TIMINGS) {
512 tim1 = regs->sdram_tim1_shdw_derated;
513 tim3 = regs->sdram_tim3_shdw_derated;
514 ref_ctrl = regs->ref_ctrl_shdw_derated;
515 }
516
517 out:
518 writel(tim1, base + EMIF_SDRAM_TIMING_1_SHDW);
519 writel(tim3, base + EMIF_SDRAM_TIMING_3_SHDW);
520 writel(ref_ctrl, base + EMIF_SDRAM_REFRESH_CTRL_SHDW);
521 }
522
handle_temp_alert(void __iomem * base,struct emif_data * emif)523 static irqreturn_t handle_temp_alert(void __iomem *base, struct emif_data *emif)
524 {
525 u32 old_temp_level;
526 irqreturn_t ret;
527 struct emif_custom_configs *custom_configs;
528
529 guard(spinlock_irqsave)(&emif_lock);
530 old_temp_level = emif->temperature_level;
531 get_temperature_level(emif);
532
533 if (unlikely(emif->temperature_level == old_temp_level)) {
534 return IRQ_HANDLED;
535 } else if (!emif->curr_regs) {
536 dev_err(emif->dev, "temperature alert before registers are calculated, not de-rating timings\n");
537 return IRQ_HANDLED;
538 }
539
540 custom_configs = emif->plat_data->custom_configs;
541
542 /*
543 * IF we detect higher than "nominal rating" from DDR sensor
544 * on an unsupported DDR part, shutdown system
545 */
546 if (custom_configs && !(custom_configs->mask &
547 EMIF_CUSTOM_CONFIG_EXTENDED_TEMP_PART)) {
548 if (emif->temperature_level >= SDRAM_TEMP_HIGH_DERATE_REFRESH) {
549 dev_err(emif->dev,
550 "%s:NOT Extended temperature capable memory. Converting MR4=0x%02x as shutdown event\n",
551 __func__, emif->temperature_level);
552 /*
553 * Temperature far too high - do kernel_power_off()
554 * from thread context
555 */
556 emif->temperature_level = SDRAM_TEMP_VERY_HIGH_SHUTDOWN;
557 return IRQ_WAKE_THREAD;
558 }
559 }
560
561 if (emif->temperature_level < old_temp_level ||
562 emif->temperature_level == SDRAM_TEMP_VERY_HIGH_SHUTDOWN) {
563 /*
564 * Temperature coming down - defer handling to thread OR
565 * Temperature far too high - do kernel_power_off() from
566 * thread context
567 */
568 ret = IRQ_WAKE_THREAD;
569 } else {
570 /* Temperature is going up - handle immediately */
571 setup_temperature_sensitive_regs(emif, emif->curr_regs);
572 do_freq_update();
573 ret = IRQ_HANDLED;
574 }
575
576 return ret;
577 }
578
emif_interrupt_handler(int irq,void * dev_id)579 static irqreturn_t emif_interrupt_handler(int irq, void *dev_id)
580 {
581 u32 interrupts;
582 struct emif_data *emif = dev_id;
583 void __iomem *base = emif->base;
584 struct device *dev = emif->dev;
585 irqreturn_t ret = IRQ_HANDLED;
586
587 /* Save the status and clear it */
588 interrupts = readl(base + EMIF_SYSTEM_OCP_INTERRUPT_STATUS);
589 writel(interrupts, base + EMIF_SYSTEM_OCP_INTERRUPT_STATUS);
590
591 /*
592 * Handle temperature alert
593 * Temperature alert should be same for all ports
594 * So, it's enough to process it only for one of the ports
595 */
596 if (interrupts & TA_SYS_MASK)
597 ret = handle_temp_alert(base, emif);
598
599 if (interrupts & ERR_SYS_MASK)
600 dev_err(dev, "Access error from SYS port - %x\n", interrupts);
601
602 if (emif->plat_data->hw_caps & EMIF_HW_CAPS_LL_INTERFACE) {
603 /* Save the status and clear it */
604 interrupts = readl(base + EMIF_LL_OCP_INTERRUPT_STATUS);
605 writel(interrupts, base + EMIF_LL_OCP_INTERRUPT_STATUS);
606
607 if (interrupts & ERR_LL_MASK)
608 dev_err(dev, "Access error from LL port - %x\n",
609 interrupts);
610 }
611
612 return ret;
613 }
614
emif_threaded_isr(int irq,void * dev_id)615 static irqreturn_t emif_threaded_isr(int irq, void *dev_id)
616 {
617 struct emif_data *emif = dev_id;
618 unsigned long irq_state;
619
620 if (emif->temperature_level == SDRAM_TEMP_VERY_HIGH_SHUTDOWN) {
621 dev_emerg(emif->dev, "SDRAM temperature exceeds operating limit.. Needs shut down!!!\n");
622
623 /* If we have Power OFF ability, use it, else try restarting */
624 if (kernel_can_power_off()) {
625 kernel_power_off();
626 } else {
627 WARN(1, "FIXME: NO pm_power_off!!! trying restart\n");
628 kernel_restart("SDRAM Over-temp Emergency restart");
629 }
630 return IRQ_HANDLED;
631 }
632
633 spin_lock_irqsave(&emif_lock, irq_state);
634
635 if (emif->curr_regs) {
636 setup_temperature_sensitive_regs(emif, emif->curr_regs);
637 do_freq_update();
638 } else {
639 dev_err(emif->dev, "temperature alert before registers are calculated, not de-rating timings\n");
640 }
641
642 spin_unlock_irqrestore(&emif_lock, irq_state);
643
644 return IRQ_HANDLED;
645 }
646
clear_all_interrupts(struct emif_data * emif)647 static void clear_all_interrupts(struct emif_data *emif)
648 {
649 void __iomem *base = emif->base;
650
651 writel(readl(base + EMIF_SYSTEM_OCP_INTERRUPT_STATUS),
652 base + EMIF_SYSTEM_OCP_INTERRUPT_STATUS);
653 if (emif->plat_data->hw_caps & EMIF_HW_CAPS_LL_INTERFACE)
654 writel(readl(base + EMIF_LL_OCP_INTERRUPT_STATUS),
655 base + EMIF_LL_OCP_INTERRUPT_STATUS);
656 }
657
disable_and_clear_all_interrupts(struct emif_data * emif)658 static void disable_and_clear_all_interrupts(struct emif_data *emif)
659 {
660 void __iomem *base = emif->base;
661
662 /* Disable all interrupts */
663 writel(readl(base + EMIF_SYSTEM_OCP_INTERRUPT_ENABLE_SET),
664 base + EMIF_SYSTEM_OCP_INTERRUPT_ENABLE_CLEAR);
665 if (emif->plat_data->hw_caps & EMIF_HW_CAPS_LL_INTERFACE)
666 writel(readl(base + EMIF_LL_OCP_INTERRUPT_ENABLE_SET),
667 base + EMIF_LL_OCP_INTERRUPT_ENABLE_CLEAR);
668
669 /* Clear all interrupts */
670 clear_all_interrupts(emif);
671 }
672
setup_interrupts(struct emif_data * emif,u32 irq)673 static int setup_interrupts(struct emif_data *emif, u32 irq)
674 {
675 u32 interrupts, type;
676 void __iomem *base = emif->base;
677
678 type = emif->plat_data->device_info->type;
679
680 clear_all_interrupts(emif);
681
682 /* Enable interrupts for SYS interface */
683 interrupts = EN_ERR_SYS_MASK;
684 if (type == DDR_TYPE_LPDDR2_S2 || type == DDR_TYPE_LPDDR2_S4)
685 interrupts |= EN_TA_SYS_MASK;
686 writel(interrupts, base + EMIF_SYSTEM_OCP_INTERRUPT_ENABLE_SET);
687
688 /* Enable interrupts for LL interface */
689 if (emif->plat_data->hw_caps & EMIF_HW_CAPS_LL_INTERFACE) {
690 /* TA need not be enabled for LL */
691 interrupts = EN_ERR_LL_MASK;
692 writel(interrupts, base + EMIF_LL_OCP_INTERRUPT_ENABLE_SET);
693 }
694
695 /* setup IRQ handlers */
696 return devm_request_threaded_irq(emif->dev, irq,
697 emif_interrupt_handler,
698 emif_threaded_isr,
699 0, dev_name(emif->dev),
700 emif);
701
702 }
703
emif_onetime_settings(struct emif_data * emif)704 static void emif_onetime_settings(struct emif_data *emif)
705 {
706 u32 pwr_mgmt_ctrl, zq, temp_alert_cfg;
707 void __iomem *base = emif->base;
708 const struct lpddr2_addressing *addressing;
709 const struct ddr_device_info *device_info;
710
711 device_info = emif->plat_data->device_info;
712 addressing = get_addressing_table(device_info);
713
714 /*
715 * Init power management settings
716 * We don't know the frequency yet. Use a high frequency
717 * value for a conservative timeout setting
718 */
719 pwr_mgmt_ctrl = get_pwr_mgmt_ctrl(1000000000, emif,
720 emif->plat_data->ip_rev);
721 emif->lpmode = (pwr_mgmt_ctrl & LP_MODE_MASK) >> LP_MODE_SHIFT;
722 writel(pwr_mgmt_ctrl, base + EMIF_POWER_MANAGEMENT_CONTROL);
723
724 /* Init ZQ calibration settings */
725 zq = get_zq_config_reg(addressing, device_info->cs1_used,
726 device_info->cal_resistors_per_cs);
727 writel(zq, base + EMIF_SDRAM_OUTPUT_IMPEDANCE_CALIBRATION_CONFIG);
728
729 /* Check temperature level temperature level*/
730 get_temperature_level(emif);
731 if (emif->temperature_level == SDRAM_TEMP_VERY_HIGH_SHUTDOWN)
732 dev_emerg(emif->dev, "SDRAM temperature exceeds operating limit.. Needs shut down!!!\n");
733
734 /* Init temperature polling */
735 temp_alert_cfg = get_temp_alert_config(addressing,
736 emif->plat_data->custom_configs, device_info->cs1_used,
737 device_info->io_width, get_emif_bus_width(emif));
738 writel(temp_alert_cfg, base + EMIF_TEMPERATURE_ALERT_CONFIG);
739
740 /*
741 * Program external PHY control registers that are not frequency
742 * dependent
743 */
744 if (emif->plat_data->phy_type != EMIF_PHY_TYPE_INTELLIPHY)
745 return;
746 writel(EMIF_EXT_PHY_CTRL_1_VAL, base + EMIF_EXT_PHY_CTRL_1_SHDW);
747 writel(EMIF_EXT_PHY_CTRL_5_VAL, base + EMIF_EXT_PHY_CTRL_5_SHDW);
748 writel(EMIF_EXT_PHY_CTRL_6_VAL, base + EMIF_EXT_PHY_CTRL_6_SHDW);
749 writel(EMIF_EXT_PHY_CTRL_7_VAL, base + EMIF_EXT_PHY_CTRL_7_SHDW);
750 writel(EMIF_EXT_PHY_CTRL_8_VAL, base + EMIF_EXT_PHY_CTRL_8_SHDW);
751 writel(EMIF_EXT_PHY_CTRL_9_VAL, base + EMIF_EXT_PHY_CTRL_9_SHDW);
752 writel(EMIF_EXT_PHY_CTRL_10_VAL, base + EMIF_EXT_PHY_CTRL_10_SHDW);
753 writel(EMIF_EXT_PHY_CTRL_11_VAL, base + EMIF_EXT_PHY_CTRL_11_SHDW);
754 writel(EMIF_EXT_PHY_CTRL_12_VAL, base + EMIF_EXT_PHY_CTRL_12_SHDW);
755 writel(EMIF_EXT_PHY_CTRL_13_VAL, base + EMIF_EXT_PHY_CTRL_13_SHDW);
756 writel(EMIF_EXT_PHY_CTRL_14_VAL, base + EMIF_EXT_PHY_CTRL_14_SHDW);
757 writel(EMIF_EXT_PHY_CTRL_15_VAL, base + EMIF_EXT_PHY_CTRL_15_SHDW);
758 writel(EMIF_EXT_PHY_CTRL_16_VAL, base + EMIF_EXT_PHY_CTRL_16_SHDW);
759 writel(EMIF_EXT_PHY_CTRL_17_VAL, base + EMIF_EXT_PHY_CTRL_17_SHDW);
760 writel(EMIF_EXT_PHY_CTRL_18_VAL, base + EMIF_EXT_PHY_CTRL_18_SHDW);
761 writel(EMIF_EXT_PHY_CTRL_19_VAL, base + EMIF_EXT_PHY_CTRL_19_SHDW);
762 writel(EMIF_EXT_PHY_CTRL_20_VAL, base + EMIF_EXT_PHY_CTRL_20_SHDW);
763 writel(EMIF_EXT_PHY_CTRL_21_VAL, base + EMIF_EXT_PHY_CTRL_21_SHDW);
764 writel(EMIF_EXT_PHY_CTRL_22_VAL, base + EMIF_EXT_PHY_CTRL_22_SHDW);
765 writel(EMIF_EXT_PHY_CTRL_23_VAL, base + EMIF_EXT_PHY_CTRL_23_SHDW);
766 writel(EMIF_EXT_PHY_CTRL_24_VAL, base + EMIF_EXT_PHY_CTRL_24_SHDW);
767 }
768
get_default_timings(struct emif_data * emif)769 static void get_default_timings(struct emif_data *emif)
770 {
771 struct emif_platform_data *pd = emif->plat_data;
772
773 pd->timings = lpddr2_jedec_timings;
774 pd->timings_arr_size = ARRAY_SIZE(lpddr2_jedec_timings);
775
776 dev_warn(emif->dev, "%s: using default timings\n", __func__);
777 }
778
is_dev_data_valid(u32 type,u32 density,u32 io_width,u32 phy_type,u32 ip_rev,struct device * dev)779 static int is_dev_data_valid(u32 type, u32 density, u32 io_width, u32 phy_type,
780 u32 ip_rev, struct device *dev)
781 {
782 int valid;
783
784 valid = (type == DDR_TYPE_LPDDR2_S4 ||
785 type == DDR_TYPE_LPDDR2_S2)
786 && (density >= DDR_DENSITY_64Mb
787 && density <= DDR_DENSITY_8Gb)
788 && (io_width >= DDR_IO_WIDTH_8
789 && io_width <= DDR_IO_WIDTH_32);
790
791 /* Combinations of EMIF and PHY revisions that we support today */
792 switch (ip_rev) {
793 case EMIF_4D:
794 valid = valid && (phy_type == EMIF_PHY_TYPE_ATTILAPHY);
795 break;
796 case EMIF_4D5:
797 valid = valid && (phy_type == EMIF_PHY_TYPE_INTELLIPHY);
798 break;
799 default:
800 valid = 0;
801 }
802
803 if (!valid)
804 dev_err(dev, "%s: invalid DDR details\n", __func__);
805 return valid;
806 }
807
is_custom_config_valid(struct emif_custom_configs * cust_cfgs,struct device * dev)808 static int is_custom_config_valid(struct emif_custom_configs *cust_cfgs,
809 struct device *dev)
810 {
811 int valid = 1;
812
813 if ((cust_cfgs->mask & EMIF_CUSTOM_CONFIG_LPMODE) &&
814 (cust_cfgs->lpmode != EMIF_LP_MODE_DISABLE))
815 valid = cust_cfgs->lpmode_freq_threshold &&
816 cust_cfgs->lpmode_timeout_performance &&
817 cust_cfgs->lpmode_timeout_power;
818
819 if (cust_cfgs->mask & EMIF_CUSTOM_CONFIG_TEMP_ALERT_POLL_INTERVAL)
820 valid = valid && cust_cfgs->temp_alert_poll_interval_ms;
821
822 if (!valid)
823 dev_warn(dev, "%s: invalid custom configs\n", __func__);
824
825 return valid;
826 }
827
of_get_custom_configs(struct device_node * np_emif,struct emif_data * emif)828 static void of_get_custom_configs(struct device_node *np_emif,
829 struct emif_data *emif)
830 {
831 struct emif_custom_configs *cust_cfgs = NULL;
832 int len;
833 const __be32 *lpmode, *poll_intvl;
834
835 lpmode = of_get_property(np_emif, "low-power-mode", &len);
836 poll_intvl = of_get_property(np_emif, "temp-alert-poll-interval", &len);
837
838 if (lpmode || poll_intvl)
839 cust_cfgs = devm_kzalloc(emif->dev, sizeof(*cust_cfgs),
840 GFP_KERNEL);
841
842 if (!cust_cfgs)
843 return;
844
845 if (lpmode) {
846 cust_cfgs->mask |= EMIF_CUSTOM_CONFIG_LPMODE;
847 cust_cfgs->lpmode = be32_to_cpup(lpmode);
848 of_property_read_u32(np_emif,
849 "low-power-mode-timeout-performance",
850 &cust_cfgs->lpmode_timeout_performance);
851 of_property_read_u32(np_emif,
852 "low-power-mode-timeout-power",
853 &cust_cfgs->lpmode_timeout_power);
854 of_property_read_u32(np_emif,
855 "low-power-mode-freq-threshold",
856 &cust_cfgs->lpmode_freq_threshold);
857 }
858
859 if (poll_intvl) {
860 cust_cfgs->mask |=
861 EMIF_CUSTOM_CONFIG_TEMP_ALERT_POLL_INTERVAL;
862 cust_cfgs->temp_alert_poll_interval_ms =
863 be32_to_cpup(poll_intvl);
864 }
865
866 if (of_property_read_bool(np_emif, "extended-temp-part"))
867 cust_cfgs->mask |= EMIF_CUSTOM_CONFIG_EXTENDED_TEMP_PART;
868
869 if (!is_custom_config_valid(cust_cfgs, emif->dev)) {
870 devm_kfree(emif->dev, cust_cfgs);
871 return;
872 }
873
874 emif->plat_data->custom_configs = cust_cfgs;
875 }
876
of_get_ddr_info(struct device_node * np_emif,struct device_node * np_ddr,struct ddr_device_info * dev_info)877 static void of_get_ddr_info(struct device_node *np_emif,
878 struct device_node *np_ddr,
879 struct ddr_device_info *dev_info)
880 {
881 u32 density = 0, io_width = 0;
882
883 dev_info->cs1_used = of_property_read_bool(np_emif, "cs1-used");
884 dev_info->cal_resistors_per_cs = of_property_read_bool(np_emif, "cal-resistor-per-cs");
885
886 if (of_device_is_compatible(np_ddr, "jedec,lpddr2-s4"))
887 dev_info->type = DDR_TYPE_LPDDR2_S4;
888 else if (of_device_is_compatible(np_ddr, "jedec,lpddr2-s2"))
889 dev_info->type = DDR_TYPE_LPDDR2_S2;
890
891 of_property_read_u32(np_ddr, "density", &density);
892 of_property_read_u32(np_ddr, "io-width", &io_width);
893
894 /* Convert from density in Mb to the density encoding in jedc_ddr.h */
895 if (density & (density - 1))
896 dev_info->density = 0;
897 else
898 dev_info->density = __fls(density) - 5;
899
900 /* Convert from io_width in bits to io_width encoding in jedc_ddr.h */
901 if (io_width & (io_width - 1))
902 dev_info->io_width = 0;
903 else
904 dev_info->io_width = __fls(io_width) - 1;
905 }
906
of_get_memory_device_details(struct device_node * np_emif,struct device * dev)907 static struct emif_data *of_get_memory_device_details(
908 struct device_node *np_emif, struct device *dev)
909 {
910 struct emif_data *emif = NULL;
911 struct ddr_device_info *dev_info = NULL;
912 struct emif_platform_data *pd = NULL;
913 struct device_node *np_ddr;
914
915 np_ddr = of_parse_phandle(np_emif, "device-handle", 0);
916 if (!np_ddr)
917 goto error;
918 emif = devm_kzalloc(dev, sizeof(struct emif_data), GFP_KERNEL);
919 pd = devm_kzalloc(dev, sizeof(*pd), GFP_KERNEL);
920 dev_info = devm_kzalloc(dev, sizeof(*dev_info), GFP_KERNEL);
921
922 if (!emif || !pd || !dev_info) {
923 dev_err(dev, "%s: Out of memory!!\n",
924 __func__);
925 goto error;
926 }
927
928 emif->plat_data = pd;
929 pd->device_info = dev_info;
930 emif->dev = dev;
931 emif->np_ddr = np_ddr;
932 emif->temperature_level = SDRAM_TEMP_NOMINAL;
933
934 if (of_device_is_compatible(np_emif, "ti,emif-4d"))
935 emif->plat_data->ip_rev = EMIF_4D;
936 else if (of_device_is_compatible(np_emif, "ti,emif-4d5"))
937 emif->plat_data->ip_rev = EMIF_4D5;
938
939 of_property_read_u32(np_emif, "phy-type", &pd->phy_type);
940
941 if (of_property_read_bool(np_emif, "hw-caps-ll-interface"))
942 pd->hw_caps |= EMIF_HW_CAPS_LL_INTERFACE;
943
944 of_get_ddr_info(np_emif, np_ddr, dev_info);
945 if (!is_dev_data_valid(pd->device_info->type, pd->device_info->density,
946 pd->device_info->io_width, pd->phy_type, pd->ip_rev,
947 emif->dev)) {
948 dev_err(dev, "%s: invalid device data!!\n", __func__);
949 goto error;
950 }
951 /*
952 * For EMIF instances other than EMIF1 see if the devices connected
953 * are exactly same as on EMIF1(which is typically the case). If so,
954 * mark it as a duplicate of EMIF1. This will save some memory and
955 * computation.
956 */
957 if (emif1 && emif1->np_ddr == np_ddr) {
958 emif->duplicate = true;
959 goto out;
960 } else if (emif1) {
961 dev_warn(emif->dev, "%s: Non-symmetric DDR geometry\n",
962 __func__);
963 }
964
965 of_get_custom_configs(np_emif, emif);
966 emif->plat_data->timings = of_get_ddr_timings(np_ddr, emif->dev,
967 emif->plat_data->device_info->type,
968 &emif->plat_data->timings_arr_size);
969
970 emif->plat_data->min_tck = of_get_min_tck(np_ddr, emif->dev);
971 goto out;
972
973 error:
974 return NULL;
975 out:
976 return emif;
977 }
978
get_device_details(struct platform_device * pdev)979 static struct emif_data *get_device_details(
980 struct platform_device *pdev)
981 {
982 u32 size;
983 struct emif_data *emif = NULL;
984 struct ddr_device_info *dev_info;
985 struct emif_custom_configs *cust_cfgs;
986 struct emif_platform_data *pd;
987 struct device *dev;
988 void *temp;
989
990 pd = pdev->dev.platform_data;
991 dev = &pdev->dev;
992
993 if (!(pd && pd->device_info && is_dev_data_valid(pd->device_info->type,
994 pd->device_info->density, pd->device_info->io_width,
995 pd->phy_type, pd->ip_rev, dev))) {
996 dev_err(dev, "%s: invalid device data\n", __func__);
997 goto error;
998 }
999
1000 emif = devm_kzalloc(dev, sizeof(*emif), GFP_KERNEL);
1001 temp = devm_kzalloc(dev, sizeof(*pd), GFP_KERNEL);
1002 dev_info = devm_kzalloc(dev, sizeof(*dev_info), GFP_KERNEL);
1003
1004 if (!emif || !temp || !dev_info)
1005 goto error;
1006
1007 memcpy(temp, pd, sizeof(*pd));
1008 pd = temp;
1009 memcpy(dev_info, pd->device_info, sizeof(*dev_info));
1010
1011 pd->device_info = dev_info;
1012 emif->plat_data = pd;
1013 emif->dev = dev;
1014 emif->temperature_level = SDRAM_TEMP_NOMINAL;
1015
1016 /*
1017 * For EMIF instances other than EMIF1 see if the devices connected
1018 * are exactly same as on EMIF1(which is typically the case). If so,
1019 * mark it as a duplicate of EMIF1 and skip copying timings data.
1020 * This will save some memory and some computation later.
1021 */
1022 emif->duplicate = emif1 && (memcmp(dev_info,
1023 emif1->plat_data->device_info,
1024 sizeof(struct ddr_device_info)) == 0);
1025
1026 if (emif->duplicate) {
1027 pd->timings = NULL;
1028 pd->min_tck = NULL;
1029 goto out;
1030 } else if (emif1) {
1031 dev_warn(emif->dev, "%s: Non-symmetric DDR geometry\n",
1032 __func__);
1033 }
1034
1035 /*
1036 * Copy custom configs - ignore allocation error, if any, as
1037 * custom_configs is not very critical
1038 */
1039 cust_cfgs = pd->custom_configs;
1040 if (cust_cfgs && is_custom_config_valid(cust_cfgs, dev)) {
1041 temp = devm_kzalloc(dev, sizeof(*cust_cfgs), GFP_KERNEL);
1042 if (temp)
1043 memcpy(temp, cust_cfgs, sizeof(*cust_cfgs));
1044 pd->custom_configs = temp;
1045 }
1046
1047 /*
1048 * Copy timings and min-tck values from platform data. If it is not
1049 * available or if memory allocation fails, use JEDEC defaults
1050 */
1051 size = sizeof(struct lpddr2_timings) * pd->timings_arr_size;
1052 if (pd->timings) {
1053 temp = devm_kzalloc(dev, size, GFP_KERNEL);
1054 if (temp) {
1055 memcpy(temp, pd->timings, size);
1056 pd->timings = temp;
1057 } else {
1058 get_default_timings(emif);
1059 }
1060 } else {
1061 get_default_timings(emif);
1062 }
1063
1064 if (pd->min_tck) {
1065 temp = devm_kzalloc(dev, sizeof(*pd->min_tck), GFP_KERNEL);
1066 if (temp) {
1067 memcpy(temp, pd->min_tck, sizeof(*pd->min_tck));
1068 pd->min_tck = temp;
1069 } else {
1070 pd->min_tck = &lpddr2_jedec_min_tck;
1071 }
1072 } else {
1073 pd->min_tck = &lpddr2_jedec_min_tck;
1074 }
1075
1076 out:
1077 return emif;
1078
1079 error:
1080 return NULL;
1081 }
1082
emif_probe(struct platform_device * pdev)1083 static int emif_probe(struct platform_device *pdev)
1084 {
1085 struct emif_data *emif;
1086 int irq, ret;
1087
1088 if (pdev->dev.of_node)
1089 emif = of_get_memory_device_details(pdev->dev.of_node, &pdev->dev);
1090 else
1091 emif = get_device_details(pdev);
1092
1093 if (!emif) {
1094 pr_err("%s: error getting device data\n", __func__);
1095 goto error;
1096 }
1097
1098 list_add(&emif->node, &device_list);
1099
1100 /* Save pointers to each other in emif and device structures */
1101 emif->dev = &pdev->dev;
1102 platform_set_drvdata(pdev, emif);
1103
1104 emif->base = devm_platform_ioremap_resource(pdev, 0);
1105 if (IS_ERR(emif->base))
1106 goto error;
1107
1108 irq = platform_get_irq(pdev, 0);
1109 if (irq < 0)
1110 goto error;
1111
1112 emif_onetime_settings(emif);
1113 emif_debugfs_init(emif);
1114 disable_and_clear_all_interrupts(emif);
1115 ret = setup_interrupts(emif, irq);
1116 if (ret)
1117 goto error;
1118
1119 /* One-time actions taken on probing the first device */
1120 if (!emif1) {
1121 emif1 = emif;
1122
1123 /*
1124 * TODO: register notifiers for frequency and voltage
1125 * change here once the respective frameworks are
1126 * available
1127 */
1128 }
1129
1130 dev_info(&pdev->dev, "%s: device configured with addr = %p and IRQ%d\n",
1131 __func__, emif->base, irq);
1132
1133 return 0;
1134 error:
1135 return -ENODEV;
1136 }
1137
emif_remove(struct platform_device * pdev)1138 static void emif_remove(struct platform_device *pdev)
1139 {
1140 struct emif_data *emif = platform_get_drvdata(pdev);
1141
1142 emif_debugfs_exit(emif);
1143 }
1144
emif_shutdown(struct platform_device * pdev)1145 static void emif_shutdown(struct platform_device *pdev)
1146 {
1147 struct emif_data *emif = platform_get_drvdata(pdev);
1148
1149 disable_and_clear_all_interrupts(emif);
1150 }
1151
1152 #if defined(CONFIG_OF)
1153 static const struct of_device_id emif_of_match[] = {
1154 { .compatible = "ti,emif-4d" },
1155 { .compatible = "ti,emif-4d5" },
1156 {},
1157 };
1158 MODULE_DEVICE_TABLE(of, emif_of_match);
1159 #endif
1160
1161 static struct platform_driver emif_driver = {
1162 .probe = emif_probe,
1163 .remove = emif_remove,
1164 .shutdown = emif_shutdown,
1165 .driver = {
1166 .name = "emif",
1167 .of_match_table = of_match_ptr(emif_of_match),
1168 },
1169 };
1170
1171 module_platform_driver(emif_driver);
1172
1173 MODULE_DESCRIPTION("TI EMIF SDRAM Controller Driver");
1174 MODULE_LICENSE("GPL");
1175 MODULE_ALIAS("platform:emif");
1176 MODULE_AUTHOR("Texas Instruments Inc");
1177