1 /* SPDX-License-Identifier: GPL-2.0 */
2 /* Copyright(c) 2009-2012 Realtek Corporation.*/
3
4 #ifndef __RTL_WIFI_H__
5 #define __RTL_WIFI_H__
6
7 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
8
9 #include <linux/sched.h>
10 #include <linux/firmware.h>
11 #include <linux/etherdevice.h>
12 #include <linux/vmalloc.h>
13 #include <linux/usb.h>
14 #include <net/mac80211.h>
15 #include <linux/completion.h>
16 #include <linux/bitfield.h>
17 #include "debug.h"
18
19 #define MASKBYTE0 0xff
20 #define MASKBYTE1 0xff00
21 #define MASKBYTE2 0xff0000
22 #define MASKBYTE3 0xff000000
23 #define MASKH3BYTES 0xffffff00
24 #define MASKHWORD 0xffff0000
25 #define MASKLWORD 0x0000ffff
26 #define MASKDWORD 0xffffffff
27 #define MASK12BITS 0xfff
28 #define MASKH4BITS 0xf0000000
29 #define MASKOFDM_D 0xffc00000
30 #define MASKCCK 0x3f3f3f3f
31
32 #define MASK4BITS 0x0f
33 #define MASK20BITS 0xfffff
34 #define RFREG_OFFSET_MASK 0xfffff
35
36 #define MASKBYTE0 0xff
37 #define MASKBYTE1 0xff00
38 #define MASKBYTE2 0xff0000
39 #define MASKBYTE3 0xff000000
40 #define MASKHWORD 0xffff0000
41 #define MASKLWORD 0x0000ffff
42 #define MASKDWORD 0xffffffff
43 #define MASK12BITS 0xfff
44 #define MASKH4BITS 0xf0000000
45 #define MASKOFDM_D 0xffc00000
46 #define MASKCCK 0x3f3f3f3f
47
48 #define MASK4BITS 0x0f
49 #define MASK20BITS 0xfffff
50 #define RFREG_OFFSET_MASK 0xfffff
51
52 /* For dual MAC RTL8192DU */
53 #define MAC0_ACCESS_PHY1 0x4000
54 #define MAC1_ACCESS_PHY0 0x2000
55
56 #define RF_CHANGE_BY_INIT 0
57 #define RF_CHANGE_BY_IPS BIT(28)
58 #define RF_CHANGE_BY_PS BIT(29)
59 #define RF_CHANGE_BY_HW BIT(30)
60 #define RF_CHANGE_BY_SW BIT(31)
61
62 #define IQK_ADDA_REG_NUM 16
63 #define IQK_MAC_REG_NUM 4
64 #define IQK_THRESHOLD 8
65
66 #define MAX_KEY_LEN 61
67 #define KEY_BUF_SIZE 5
68
69 /* QoS related. */
70 /*aci: 0x00 Best Effort*/
71 /*aci: 0x01 Background*/
72 /*aci: 0x10 Video*/
73 /*aci: 0x11 Voice*/
74 /*Max: define total number.*/
75 #define AC0_BE 0
76 #define AC1_BK 1
77 #define AC2_VI 2
78 #define AC3_VO 3
79 #define AC_MAX 4
80 #define QOS_QUEUE_NUM 4
81 #define RTL_MAC80211_NUM_QUEUE 5
82 #define REALTEK_USB_VENQT_MAX_BUF_SIZE 254
83 #define RTL_USB_MAX_RX_COUNT 100
84 #define QBSS_LOAD_SIZE 5
85 #define MAX_WMMELE_LENGTH 64
86 #define ASPM_L1_LATENCY 7
87
88 #define TOTAL_CAM_ENTRY 32
89
90 /*slot time for 11g. */
91 #define RTL_SLOT_TIME_9 9
92 #define RTL_SLOT_TIME_20 20
93
94 /*related to tcp/ip. */
95 #define SNAP_SIZE 6
96 #define PROTOC_TYPE_SIZE 2
97
98 /*related with 802.11 frame*/
99 #define MAC80211_3ADDR_LEN 24
100 #define MAC80211_4ADDR_LEN 30
101
102 #define CHANNEL_MAX_NUMBER (14 + 24 + 21) /* 14 is the max channel no */
103 #define CHANNEL_MAX_NUMBER_2G 14
104 #define CHANNEL_MAX_NUMBER_5G 49 /* Please refer to
105 *"phy_GetChnlGroup8812A" and
106 * "Hal_ReadTxPowerInfo8812A"
107 */
108 #define CHANNEL_MAX_NUMBER_5G_80M 7
109 #define CHANNEL_GROUP_MAX (3 + 9) /* ch1~3, 4~9, 10~14 = three groups */
110 #define MAX_PG_GROUP 13
111 #define CHANNEL_GROUP_MAX_2G 3
112 #define CHANNEL_GROUP_IDX_5GL 3
113 #define CHANNEL_GROUP_IDX_5GM 6
114 #define CHANNEL_GROUP_IDX_5GH 9
115 #define CHANNEL_GROUP_MAX_5G 9
116 #define AVG_THERMAL_NUM 8
117 #define AVG_THERMAL_NUM_88E 4
118 #define AVG_THERMAL_NUM_8723BE 4
119 #define MAX_TID_COUNT 9
120
121 /* for early mode */
122 #define FCS_LEN 4
123 #define EM_HDR_LEN 8
124
125 enum rtl8192c_h2c_cmd {
126 H2C_AP_OFFLOAD = 0,
127 H2C_SETPWRMODE = 1,
128 H2C_JOINBSSRPT = 2,
129 H2C_RSVDPAGE = 3,
130 H2C_RSSI_REPORT = 5,
131 H2C_RA_MASK = 6,
132 H2C_MACID_PS_MODE = 7,
133 H2C_P2P_PS_OFFLOAD = 8,
134 H2C_MAC_MODE_SEL = 9,
135 H2C_PWRM = 15,
136 H2C_P2P_PS_CTW_CMD = 24,
137 MAX_H2CCMD
138 };
139
140 enum {
141 H2C_BT_PORT_ID = 0x71,
142 };
143
144 enum rtl_c2h_evt_v1 {
145 C2H_DBG = 0,
146 C2H_LB = 1,
147 C2H_TXBF = 2,
148 C2H_TX_REPORT = 3,
149 C2H_BT_INFO = 9,
150 C2H_BT_MP = 11,
151 C2H_RA_RPT = 12,
152
153 C2H_FW_SWCHNL = 0x10,
154 C2H_IQK_FINISH = 0x11,
155
156 C2H_EXT_V2 = 0xFF,
157 };
158
159 enum rtl_c2h_evt_v2 {
160 C2H_V2_CCX_RPT = 0x0F,
161 };
162
163 #define GET_C2H_CMD_ID(c2h) ({u8 *__c2h = c2h; __c2h[0]; })
164 #define GET_C2H_SEQ(c2h) ({u8 *__c2h = c2h; __c2h[1]; })
165 #define C2H_DATA_OFFSET 2
166 #define GET_C2H_DATA_PTR(c2h) ({u8 *__c2h = c2h; &__c2h[C2H_DATA_OFFSET]; })
167
168 #define GET_TX_REPORT_SN_V1(c2h) (c2h[6])
169 #define GET_TX_REPORT_ST_V1(c2h) (c2h[0] & 0xC0)
170 #define GET_TX_REPORT_RETRY_V1(c2h) (c2h[2] & 0x3F)
171 #define GET_TX_REPORT_SN_V2(c2h) (c2h[6])
172 #define GET_TX_REPORT_ST_V2(c2h) (c2h[7] & 0xC0)
173 #define GET_TX_REPORT_RETRY_V2(c2h) (c2h[8] & 0x3F)
174
175 #define MAX_TX_COUNT 4
176 #define MAX_REGULATION_NUM 4
177 #define MAX_RF_PATH_NUM 4
178 #define MAX_RATE_SECTION_NUM 6 /* = MAX_RATE_SECTION */
179 #define MAX_2_4G_BANDWIDTH_NUM 4
180 #define MAX_5G_BANDWIDTH_NUM 4
181 #define MAX_RF_PATH 4
182 #define MAX_CHNL_GROUP_24G 6
183 #define MAX_CHNL_GROUP_5G 14
184
185 #define TX_PWR_BY_RATE_NUM_BAND 2
186 #define TX_PWR_BY_RATE_NUM_RF 4
187 #define TX_PWR_BY_RATE_NUM_SECTION 12
188 #define TX_PWR_BY_RATE_NUM_RATE 84 /* >= TX_PWR_BY_RATE_NUM_SECTION */
189 #define MAX_BASE_NUM_IN_PHY_REG_PG_24G 6 /* MAX_RATE_SECTION */
190 #define MAX_BASE_NUM_IN_PHY_REG_PG_5G 5 /* MAX_RATE_SECTION -1 */
191
192 #define BUFDESC_SEG_NUM 1 /* 0:2 seg, 1: 4 seg, 2: 8 seg */
193
194 #define DEL_SW_IDX_SZ 30
195
196 /* For now, it's just for 8192ee
197 * but not OK yet, keep it 0
198 */
199 #define RTL8192EE_SEG_NUM BUFDESC_SEG_NUM
200
201 enum rf_tx_num {
202 RF_1TX = 0,
203 RF_2TX,
204 RF_MAX_TX_NUM,
205 RF_TX_NUM_NONIMPLEMENT,
206 };
207
208 #define PACKET_NORMAL 0
209 #define PACKET_DHCP 1
210 #define PACKET_ARP 2
211 #define PACKET_EAPOL 3
212
213 #define MAX_SUPPORT_WOL_PATTERN_NUM 16
214 #define RSVD_WOL_PATTERN_NUM 1
215 #define WKFMCAM_ADDR_NUM 6
216 #define WKFMCAM_SIZE 24
217
218 #define MAX_WOL_BIT_MASK_SIZE 16
219 /* MIN LEN keeps 13 here */
220 #define MIN_WOL_PATTERN_SIZE 13
221 #define MAX_WOL_PATTERN_SIZE 128
222
223 #define WAKE_ON_MAGIC_PACKET BIT(0)
224 #define WAKE_ON_PATTERN_MATCH BIT(1)
225
226 #define WOL_REASON_PTK_UPDATE BIT(0)
227 #define WOL_REASON_GTK_UPDATE BIT(1)
228 #define WOL_REASON_DISASSOC BIT(2)
229 #define WOL_REASON_DEAUTH BIT(3)
230 #define WOL_REASON_AP_LOST BIT(4)
231 #define WOL_REASON_MAGIC_PKT BIT(5)
232 #define WOL_REASON_UNICAST_PKT BIT(6)
233 #define WOL_REASON_PATTERN_PKT BIT(7)
234 #define WOL_REASON_RTD3_SSID_MATCH BIT(8)
235 #define WOL_REASON_REALWOW_V2_WAKEUPPKT BIT(9)
236 #define WOL_REASON_REALWOW_V2_ACKLOST BIT(10)
237
238 struct rtlwifi_firmware_header {
239 __le16 signature;
240 u8 category;
241 u8 function;
242 __le16 version;
243 u8 subversion;
244 u8 rsvd1;
245 u8 month;
246 u8 date;
247 u8 hour;
248 u8 minute;
249 __le16 ramcodesize;
250 __le16 rsvd2;
251 __le32 svnindex;
252 __le32 rsvd3;
253 __le32 rsvd4;
254 __le32 rsvd5;
255 };
256
257 struct txpower_info_2g {
258 u8 index_cck_base[MAX_RF_PATH][MAX_CHNL_GROUP_24G];
259 u8 index_bw40_base[MAX_RF_PATH][MAX_CHNL_GROUP_24G];
260 /*If only one tx, only BW20 and OFDM are used.*/
261 u8 cck_diff[MAX_RF_PATH][MAX_TX_COUNT];
262 u8 ofdm_diff[MAX_RF_PATH][MAX_TX_COUNT];
263 u8 bw20_diff[MAX_RF_PATH][MAX_TX_COUNT];
264 u8 bw40_diff[MAX_RF_PATH][MAX_TX_COUNT];
265 u8 bw80_diff[MAX_RF_PATH][MAX_TX_COUNT];
266 u8 bw160_diff[MAX_RF_PATH][MAX_TX_COUNT];
267 };
268
269 struct txpower_info_5g {
270 u8 index_bw40_base[MAX_RF_PATH][MAX_CHNL_GROUP_5G];
271 /*If only one tx, only BW20, OFDM, BW80 and BW160 are used.*/
272 u8 ofdm_diff[MAX_RF_PATH][MAX_TX_COUNT];
273 u8 bw20_diff[MAX_RF_PATH][MAX_TX_COUNT];
274 u8 bw40_diff[MAX_RF_PATH][MAX_TX_COUNT];
275 u8 bw80_diff[MAX_RF_PATH][MAX_TX_COUNT];
276 u8 bw160_diff[MAX_RF_PATH][MAX_TX_COUNT];
277 };
278
279 enum rate_section {
280 CCK = 0,
281 OFDM,
282 HT_MCS0_MCS7,
283 HT_MCS8_MCS15,
284 VHT_1SSMCS0_1SSMCS9,
285 VHT_2SSMCS0_2SSMCS9,
286 MAX_RATE_SECTION,
287 };
288
289 enum intf_type {
290 INTF_PCI = 0,
291 INTF_USB = 1,
292 };
293
294 enum radio_path {
295 RF90_PATH_A = 0,
296 RF90_PATH_B = 1,
297 RF90_PATH_C = 2,
298 RF90_PATH_D = 3,
299 };
300
301 enum radio_mask {
302 RF_MASK_A = BIT(0),
303 RF_MASK_B = BIT(1),
304 RF_MASK_C = BIT(2),
305 RF_MASK_D = BIT(3),
306 };
307
308 enum regulation_txpwr_lmt {
309 TXPWR_LMT_FCC = 0,
310 TXPWR_LMT_MKK = 1,
311 TXPWR_LMT_ETSI = 2,
312 TXPWR_LMT_WW = 3,
313
314 TXPWR_LMT_MAX_REGULATION_NUM = 4
315 };
316
317 enum rt_eeprom_type {
318 EEPROM_93C46,
319 EEPROM_93C56,
320 EEPROM_BOOT_EFUSE,
321 };
322
323 enum ttl_status {
324 RTL_STATUS_INTERFACE_START = 0,
325 };
326
327 enum hardware_type {
328 HARDWARE_TYPE_RTL8192E,
329 HARDWARE_TYPE_RTL8192U,
330 HARDWARE_TYPE_RTL8192SE,
331 HARDWARE_TYPE_RTL8192SU,
332 HARDWARE_TYPE_RTL8192CE,
333 HARDWARE_TYPE_RTL8192CU,
334 HARDWARE_TYPE_RTL8192DE,
335 HARDWARE_TYPE_RTL8192DU,
336 HARDWARE_TYPE_RTL8723AE,
337 HARDWARE_TYPE_RTL8723U,
338 HARDWARE_TYPE_RTL8188EE,
339 HARDWARE_TYPE_RTL8723BE,
340 HARDWARE_TYPE_RTL8192EE,
341 HARDWARE_TYPE_RTL8821AE,
342 HARDWARE_TYPE_RTL8812AE,
343 HARDWARE_TYPE_RTL8822BE,
344
345 /* keep it last */
346 HARDWARE_TYPE_NUM
347 };
348
349 #define RTL_HW_TYPE(rtlpriv) (rtl_hal((struct rtl_priv *)rtlpriv)->hw_type)
350 #define IS_NEW_GENERATION_IC(rtlpriv) \
351 (RTL_HW_TYPE(rtlpriv) >= HARDWARE_TYPE_RTL8192EE)
352 #define IS_HARDWARE_TYPE_8192CE(rtlpriv) \
353 (RTL_HW_TYPE(rtlpriv) == HARDWARE_TYPE_RTL8192CE)
354 #define IS_HARDWARE_TYPE_8812(rtlpriv) \
355 (RTL_HW_TYPE(rtlpriv) == HARDWARE_TYPE_RTL8812AE)
356 #define IS_HARDWARE_TYPE_8821(rtlpriv) \
357 (RTL_HW_TYPE(rtlpriv) == HARDWARE_TYPE_RTL8821AE)
358 #define IS_HARDWARE_TYPE_8723A(rtlpriv) \
359 (RTL_HW_TYPE(rtlpriv) == HARDWARE_TYPE_RTL8723AE)
360 #define IS_HARDWARE_TYPE_8723B(rtlpriv) \
361 (RTL_HW_TYPE(rtlpriv) == HARDWARE_TYPE_RTL8723BE)
362 #define IS_HARDWARE_TYPE_8192E(rtlpriv) \
363 (RTL_HW_TYPE(rtlpriv) == HARDWARE_TYPE_RTL8192EE)
364 #define IS_HARDWARE_TYPE_8822B(rtlpriv) \
365 (RTL_HW_TYPE(rtlpriv) == HARDWARE_TYPE_RTL8822BE)
366
367 #define RX_HAL_IS_CCK_RATE(rxmcs) \
368 ((rxmcs) == DESC_RATE1M || \
369 (rxmcs) == DESC_RATE2M || \
370 (rxmcs) == DESC_RATE5_5M || \
371 (rxmcs) == DESC_RATE11M)
372
373 enum scan_operation_backup_opt {
374 SCAN_OPT_BACKUP = 0,
375 SCAN_OPT_BACKUP_BAND0 = 0,
376 SCAN_OPT_BACKUP_BAND1,
377 SCAN_OPT_RESTORE,
378 SCAN_OPT_MAX
379 };
380
381 /*RF state.*/
382 enum rf_pwrstate {
383 ERFON,
384 ERFSLEEP,
385 ERFOFF
386 };
387
388 struct bb_reg_def {
389 u32 rfintfs;
390 u32 rfintfi;
391 u32 rfintfo;
392 u32 rfintfe;
393 u32 rf3wire_offset;
394 u32 rflssi_select;
395 u32 rftxgain_stage;
396 u32 rfhssi_para1;
397 u32 rfhssi_para2;
398 u32 rfsw_ctrl;
399 u32 rfagc_control1;
400 u32 rfagc_control2;
401 u32 rfrxiq_imbal;
402 u32 rfrx_afe;
403 u32 rftxiq_imbal;
404 u32 rftx_afe;
405 u32 rf_rb; /* rflssi_readback */
406 u32 rf_rbpi; /* rflssi_readbackpi */
407 };
408
409 enum io_type {
410 IO_CMD_PAUSE_DM_BY_SCAN = 0,
411 IO_CMD_PAUSE_BAND0_DM_BY_SCAN = 0,
412 IO_CMD_PAUSE_BAND1_DM_BY_SCAN = 1,
413 IO_CMD_RESUME_DM_BY_SCAN = 2,
414 };
415
416 enum hw_variables {
417 HW_VAR_ETHER_ADDR = 0x0,
418 HW_VAR_MULTICAST_REG = 0x1,
419 HW_VAR_BASIC_RATE = 0x2,
420 HW_VAR_BSSID = 0x3,
421 HW_VAR_MEDIA_STATUS = 0x4,
422 HW_VAR_SECURITY_CONF = 0x5,
423 HW_VAR_BEACON_INTERVAL = 0x6,
424 HW_VAR_ATIM_WINDOW = 0x7,
425 HW_VAR_LISTEN_INTERVAL = 0x8,
426 HW_VAR_CS_COUNTER = 0x9,
427 HW_VAR_DEFAULTKEY0 = 0xa,
428 HW_VAR_DEFAULTKEY1 = 0xb,
429 HW_VAR_DEFAULTKEY2 = 0xc,
430 HW_VAR_DEFAULTKEY3 = 0xd,
431 HW_VAR_SIFS = 0xe,
432 HW_VAR_R2T_SIFS = 0xf,
433 HW_VAR_DIFS = 0x10,
434 HW_VAR_EIFS = 0x11,
435 HW_VAR_SLOT_TIME = 0x12,
436 HW_VAR_ACK_PREAMBLE = 0x13,
437 HW_VAR_CW_CONFIG = 0x14,
438 HW_VAR_CW_VALUES = 0x15,
439 HW_VAR_RATE_FALLBACK_CONTROL = 0x16,
440 HW_VAR_CONTENTION_WINDOW = 0x17,
441 HW_VAR_RETRY_COUNT = 0x18,
442 HW_VAR_TR_SWITCH = 0x19,
443 HW_VAR_COMMAND = 0x1a,
444 HW_VAR_WPA_CONFIG = 0x1b,
445 HW_VAR_AMPDU_MIN_SPACE = 0x1c,
446 HW_VAR_SHORTGI_DENSITY = 0x1d,
447 HW_VAR_AMPDU_FACTOR = 0x1e,
448 HW_VAR_MCS_RATE_AVAILABLE = 0x1f,
449 HW_VAR_AC_PARAM = 0x20,
450 HW_VAR_ACM_CTRL = 0x21,
451 HW_VAR_DIS_REQ_QSIZE = 0x22,
452 HW_VAR_CCX_CHNL_LOAD = 0x23,
453 HW_VAR_CCX_NOISE_HISTOGRAM = 0x24,
454 HW_VAR_CCX_CLM_NHM = 0x25,
455 HW_VAR_TXOPLIMIT = 0x26,
456 HW_VAR_TURBO_MODE = 0x27,
457 HW_VAR_RF_STATE = 0x28,
458 HW_VAR_RF_OFF_BY_HW = 0x29,
459 HW_VAR_BUS_SPEED = 0x2a,
460 HW_VAR_SET_DEV_POWER = 0x2b,
461
462 HW_VAR_RCR = 0x2c,
463 HW_VAR_RATR_0 = 0x2d,
464 HW_VAR_RRSR = 0x2e,
465 HW_VAR_CPU_RST = 0x2f,
466 HW_VAR_CHECK_BSSID = 0x30,
467 HW_VAR_LBK_MODE = 0x31,
468 HW_VAR_AES_11N_FIX = 0x32,
469 HW_VAR_USB_RX_AGGR = 0x33,
470 HW_VAR_USER_CONTROL_TURBO_MODE = 0x34,
471 HW_VAR_RETRY_LIMIT = 0x35,
472 HW_VAR_INIT_TX_RATE = 0x36,
473 HW_VAR_TX_RATE_REG = 0x37,
474 HW_VAR_EFUSE_USAGE = 0x38,
475 HW_VAR_EFUSE_BYTES = 0x39,
476 HW_VAR_AUTOLOAD_STATUS = 0x3a,
477 HW_VAR_RF_2R_DISABLE = 0x3b,
478 HW_VAR_SET_RPWM = 0x3c,
479 HW_VAR_H2C_FW_PWRMODE = 0x3d,
480 HW_VAR_H2C_FW_JOINBSSRPT = 0x3e,
481 HW_VAR_H2C_FW_MEDIASTATUSRPT = 0x3f,
482 HW_VAR_H2C_FW_P2P_PS_OFFLOAD = 0x40,
483 HW_VAR_FW_PSMODE_STATUS = 0x41,
484 HW_VAR_INIT_RTS_RATE = 0x42,
485 HW_VAR_RESUME_CLK_ON = 0x43,
486 HW_VAR_FW_LPS_ACTION = 0x44,
487 HW_VAR_1X1_RECV_COMBINE = 0x45,
488 HW_VAR_STOP_SEND_BEACON = 0x46,
489 HW_VAR_TSF_TIMER = 0x47,
490 HW_VAR_IO_CMD = 0x48,
491
492 HW_VAR_RF_RECOVERY = 0x49,
493 HW_VAR_H2C_FW_UPDATE_GTK = 0x4a,
494 HW_VAR_WF_MASK = 0x4b,
495 HW_VAR_WF_CRC = 0x4c,
496 HW_VAR_WF_IS_MAC_ADDR = 0x4d,
497 HW_VAR_H2C_FW_OFFLOAD = 0x4e,
498 HW_VAR_RESET_WFCRC = 0x4f,
499
500 HW_VAR_HANDLE_FW_C2H = 0x50,
501 HW_VAR_DL_FW_RSVD_PAGE = 0x51,
502 HW_VAR_AID = 0x52,
503 HW_VAR_HW_SEQ_ENABLE = 0x53,
504 HW_VAR_CORRECT_TSF = 0x54,
505 HW_VAR_BCN_VALID = 0x55,
506 HW_VAR_FWLPS_RF_ON = 0x56,
507 HW_VAR_DUAL_TSF_RST = 0x57,
508 HW_VAR_SWITCH_EPHY_WOWLAN = 0x58,
509 HW_VAR_INT_MIGRATION = 0x59,
510 HW_VAR_INT_AC = 0x5a,
511 HW_VAR_RF_TIMING = 0x5b,
512
513 HAL_DEF_WOWLAN = 0x5c,
514 HW_VAR_MRC = 0x5d,
515 HW_VAR_KEEP_ALIVE = 0x5e,
516 HW_VAR_NAV_UPPER = 0x5f,
517
518 HW_VAR_MGT_FILTER = 0x60,
519 HW_VAR_CTRL_FILTER = 0x61,
520 HW_VAR_DATA_FILTER = 0x62,
521 };
522
523 enum rt_media_status {
524 RT_MEDIA_DISCONNECT = 0,
525 RT_MEDIA_CONNECT = 1
526 };
527
528 enum rt_oem_id {
529 RT_CID_DEFAULT = 0,
530 RT_CID_8187_ALPHA0 = 1,
531 RT_CID_8187_SERCOMM_PS = 2,
532 RT_CID_8187_HW_LED = 3,
533 RT_CID_8187_NETGEAR = 4,
534 RT_CID_WHQL = 5,
535 RT_CID_819X_CAMEO = 6,
536 RT_CID_819X_RUNTOP = 7,
537 RT_CID_819X_SENAO = 8,
538 RT_CID_TOSHIBA = 9,
539 RT_CID_819X_NETCORE = 10,
540 RT_CID_NETTRONIX = 11,
541 RT_CID_DLINK = 12,
542 RT_CID_PRONET = 13,
543 RT_CID_COREGA = 14,
544 RT_CID_819X_ALPHA = 15,
545 RT_CID_819X_SITECOM = 16,
546 RT_CID_CCX = 17,
547 RT_CID_819X_LENOVO = 18,
548 RT_CID_819X_QMI = 19,
549 RT_CID_819X_EDIMAX_BELKIN = 20,
550 RT_CID_819X_SERCOMM_BELKIN = 21,
551 RT_CID_819X_CAMEO1 = 22,
552 RT_CID_819X_MSI = 23,
553 RT_CID_819X_ACER = 24,
554 RT_CID_819X_HP = 27,
555 RT_CID_819X_CLEVO = 28,
556 RT_CID_819X_ARCADYAN_BELKIN = 29,
557 RT_CID_819X_SAMSUNG = 30,
558 RT_CID_819X_WNC_COREGA = 31,
559 RT_CID_819X_FOXCOON = 32,
560 RT_CID_819X_DELL = 33,
561 RT_CID_819X_PRONETS = 34,
562 RT_CID_819X_EDIMAX_ASUS = 35,
563 RT_CID_NETGEAR = 36,
564 RT_CID_PLANEX = 37,
565 RT_CID_CC_C = 38,
566 RT_CID_LENOVO_CHINA = 40,
567 };
568
569 enum hw_descs {
570 HW_DESC_OWN,
571 HW_DESC_RXOWN,
572 HW_DESC_TX_NEXTDESC_ADDR,
573 HW_DESC_TXBUFF_ADDR,
574 HW_DESC_RXBUFF_ADDR,
575 HW_DESC_RXPKT_LEN,
576 HW_DESC_RXERO,
577 HW_DESC_RX_PREPARE,
578 };
579
580 enum prime_sc {
581 PRIME_CHNL_OFFSET_DONT_CARE = 0,
582 PRIME_CHNL_OFFSET_LOWER = 1,
583 PRIME_CHNL_OFFSET_UPPER = 2,
584 };
585
586 enum rf_type {
587 RF_1T1R = 0,
588 RF_1T2R = 1,
589 RF_2T2R = 2,
590 RF_2T2R_GREEN = 3,
591 RF_2T3R = 4,
592 RF_2T4R = 5,
593 RF_3T3R = 6,
594 RF_3T4R = 7,
595 RF_4T4R = 8,
596 };
597
598 enum ht_channel_width {
599 HT_CHANNEL_WIDTH_20 = 0,
600 HT_CHANNEL_WIDTH_20_40 = 1,
601 HT_CHANNEL_WIDTH_80 = 2,
602 HT_CHANNEL_WIDTH_MAX,
603 };
604
605 /* Ref: 802.11i spec D10.0 7.3.2.25.1
606 * Cipher Suites Encryption Algorithms
607 */
608 enum rt_enc_alg {
609 NO_ENCRYPTION = 0,
610 WEP40_ENCRYPTION = 1,
611 TKIP_ENCRYPTION = 2,
612 RSERVED_ENCRYPTION = 3,
613 AESCCMP_ENCRYPTION = 4,
614 WEP104_ENCRYPTION = 5,
615 AESCMAC_ENCRYPTION = 6, /*IEEE802.11w */
616 };
617
618 enum rtl_hal_state {
619 _HAL_STATE_STOP = 0,
620 _HAL_STATE_START = 1,
621 };
622
623 enum rtl_desc_rate {
624 DESC_RATE1M = 0x00,
625 DESC_RATE2M = 0x01,
626 DESC_RATE5_5M = 0x02,
627 DESC_RATE11M = 0x03,
628
629 DESC_RATE6M = 0x04,
630 DESC_RATE9M = 0x05,
631 DESC_RATE12M = 0x06,
632 DESC_RATE18M = 0x07,
633 DESC_RATE24M = 0x08,
634 DESC_RATE36M = 0x09,
635 DESC_RATE48M = 0x0a,
636 DESC_RATE54M = 0x0b,
637
638 DESC_RATEMCS0 = 0x0c,
639 DESC_RATEMCS1 = 0x0d,
640 DESC_RATEMCS2 = 0x0e,
641 DESC_RATEMCS3 = 0x0f,
642 DESC_RATEMCS4 = 0x10,
643 DESC_RATEMCS5 = 0x11,
644 DESC_RATEMCS6 = 0x12,
645 DESC_RATEMCS7 = 0x13,
646 DESC_RATEMCS8 = 0x14,
647 DESC_RATEMCS9 = 0x15,
648 DESC_RATEMCS10 = 0x16,
649 DESC_RATEMCS11 = 0x17,
650 DESC_RATEMCS12 = 0x18,
651 DESC_RATEMCS13 = 0x19,
652 DESC_RATEMCS14 = 0x1a,
653 DESC_RATEMCS15 = 0x1b,
654 DESC_RATEMCS15_SG = 0x1c,
655 DESC_RATEMCS32 = 0x20,
656
657 DESC_RATEVHT1SS_MCS0 = 0x2c,
658 DESC_RATEVHT1SS_MCS1 = 0x2d,
659 DESC_RATEVHT1SS_MCS2 = 0x2e,
660 DESC_RATEVHT1SS_MCS3 = 0x2f,
661 DESC_RATEVHT1SS_MCS4 = 0x30,
662 DESC_RATEVHT1SS_MCS5 = 0x31,
663 DESC_RATEVHT1SS_MCS6 = 0x32,
664 DESC_RATEVHT1SS_MCS7 = 0x33,
665 DESC_RATEVHT1SS_MCS8 = 0x34,
666 DESC_RATEVHT1SS_MCS9 = 0x35,
667 DESC_RATEVHT2SS_MCS0 = 0x36,
668 DESC_RATEVHT2SS_MCS1 = 0x37,
669 DESC_RATEVHT2SS_MCS2 = 0x38,
670 DESC_RATEVHT2SS_MCS3 = 0x39,
671 DESC_RATEVHT2SS_MCS4 = 0x3a,
672 DESC_RATEVHT2SS_MCS5 = 0x3b,
673 DESC_RATEVHT2SS_MCS6 = 0x3c,
674 DESC_RATEVHT2SS_MCS7 = 0x3d,
675 DESC_RATEVHT2SS_MCS8 = 0x3e,
676 DESC_RATEVHT2SS_MCS9 = 0x3f,
677 };
678
679 enum rtl_var_map {
680 /*reg map */
681 SYS_ISO_CTRL = 0,
682 SYS_FUNC_EN,
683 SYS_CLK,
684 MAC_RCR_AM,
685 MAC_RCR_AB,
686 MAC_RCR_ACRC32,
687 MAC_RCR_ACF,
688 MAC_RCR_AAP,
689 MAC_HIMR,
690 MAC_HIMRE,
691 MAC_HSISR,
692
693 /*efuse map */
694 EFUSE_TEST,
695 EFUSE_CTRL,
696 EFUSE_CLK,
697 EFUSE_CLK_CTRL,
698 EFUSE_PWC_EV12V,
699 EFUSE_FEN_ELDR,
700 EFUSE_LOADER_CLK_EN,
701 EFUSE_ANA8M,
702 EFUSE_HWSET_MAX_SIZE,
703 EFUSE_MAX_SECTION_MAP,
704 EFUSE_REAL_CONTENT_SIZE,
705 EFUSE_OOB_PROTECT_BYTES_LEN,
706 EFUSE_ACCESS,
707
708 /*CAM map */
709 RWCAM,
710 WCAMI,
711 RCAMO,
712 CAMDBG,
713 SECR,
714 SEC_CAM_NONE,
715 SEC_CAM_WEP40,
716 SEC_CAM_TKIP,
717 SEC_CAM_AES,
718 SEC_CAM_WEP104,
719
720 /*IMR map */
721 RTL_IMR_BCNDMAINT6, /*Beacon DMA Interrupt 6 */
722 RTL_IMR_BCNDMAINT5, /*Beacon DMA Interrupt 5 */
723 RTL_IMR_BCNDMAINT4, /*Beacon DMA Interrupt 4 */
724 RTL_IMR_BCNDMAINT3, /*Beacon DMA Interrupt 3 */
725 RTL_IMR_BCNDMAINT2, /*Beacon DMA Interrupt 2 */
726 RTL_IMR_BCNDMAINT1, /*Beacon DMA Interrupt 1 */
727 RTL_IMR_BCNDOK8, /*Beacon Queue DMA OK Interrup 8 */
728 RTL_IMR_BCNDOK7, /*Beacon Queue DMA OK Interrup 7 */
729 RTL_IMR_BCNDOK6, /*Beacon Queue DMA OK Interrup 6 */
730 RTL_IMR_BCNDOK5, /*Beacon Queue DMA OK Interrup 5 */
731 RTL_IMR_BCNDOK4, /*Beacon Queue DMA OK Interrup 4 */
732 RTL_IMR_BCNDOK3, /*Beacon Queue DMA OK Interrup 3 */
733 RTL_IMR_BCNDOK2, /*Beacon Queue DMA OK Interrup 2 */
734 RTL_IMR_BCNDOK1, /*Beacon Queue DMA OK Interrup 1 */
735 RTL_IMR_TIMEOUT2, /*Timeout interrupt 2 */
736 RTL_IMR_TIMEOUT1, /*Timeout interrupt 1 */
737 RTL_IMR_TXFOVW, /*Transmit FIFO Overflow */
738 RTL_IMR_PSTIMEOUT, /*Power save time out interrupt */
739 RTL_IMR_BCNINT, /*Beacon DMA Interrupt 0 */
740 RTL_IMR_RXFOVW, /*Receive FIFO Overflow */
741 RTL_IMR_RDU, /*Receive Descriptor Unavailable */
742 RTL_IMR_ATIMEND, /*For 92C,ATIM Window End Interrupt */
743 RTL_IMR_H2CDOK, /*H2C Queue DMA OK Interrupt */
744 RTL_IMR_BDOK, /*Beacon Queue DMA OK Interrup */
745 RTL_IMR_HIGHDOK, /*High Queue DMA OK Interrupt */
746 RTL_IMR_COMDOK, /*Command Queue DMA OK Interrupt*/
747 RTL_IMR_TBDOK, /*Transmit Beacon OK interrup */
748 RTL_IMR_MGNTDOK, /*Management Queue DMA OK Interrupt */
749 RTL_IMR_TBDER, /*For 92C,Transmit Beacon Error Interrupt */
750 RTL_IMR_BKDOK, /*AC_BK DMA OK Interrupt */
751 RTL_IMR_BEDOK, /*AC_BE DMA OK Interrupt */
752 RTL_IMR_VIDOK, /*AC_VI DMA OK Interrupt */
753 RTL_IMR_VODOK, /*AC_VO DMA Interrupt */
754 RTL_IMR_ROK, /*Receive DMA OK Interrupt */
755 RTL_IMR_HSISR_IND, /*HSISR Interrupt*/
756 RTL_IBSS_INT_MASKS, /*(RTL_IMR_BCNINT | RTL_IMR_TBDOK |
757 * RTL_IMR_TBDER)
758 */
759 RTL_IMR_C2HCMD, /*fw interrupt*/
760
761 /*CCK Rates, TxHT = 0 */
762 RTL_RC_CCK_RATE1M,
763 RTL_RC_CCK_RATE2M,
764 RTL_RC_CCK_RATE5_5M,
765 RTL_RC_CCK_RATE11M,
766
767 /*OFDM Rates, TxHT = 0 */
768 RTL_RC_OFDM_RATE6M,
769 RTL_RC_OFDM_RATE9M,
770 RTL_RC_OFDM_RATE12M,
771 RTL_RC_OFDM_RATE18M,
772 RTL_RC_OFDM_RATE24M,
773 RTL_RC_OFDM_RATE36M,
774 RTL_RC_OFDM_RATE48M,
775 RTL_RC_OFDM_RATE54M,
776
777 RTL_RC_HT_RATEMCS7,
778 RTL_RC_HT_RATEMCS15,
779
780 RTL_RC_VHT_RATE_1SS_MCS7,
781 RTL_RC_VHT_RATE_1SS_MCS8,
782 RTL_RC_VHT_RATE_1SS_MCS9,
783 RTL_RC_VHT_RATE_2SS_MCS7,
784 RTL_RC_VHT_RATE_2SS_MCS8,
785 RTL_RC_VHT_RATE_2SS_MCS9,
786
787 /*keep it last */
788 RTL_VAR_MAP_MAX,
789 };
790
791 /*Firmware PS mode for control LPS.*/
792 enum _fw_ps_mode {
793 FW_PS_ACTIVE_MODE = 0,
794 FW_PS_MIN_MODE = 1,
795 FW_PS_MAX_MODE = 2,
796 FW_PS_DTIM_MODE = 3,
797 FW_PS_VOIP_MODE = 4,
798 FW_PS_UAPSD_WMM_MODE = 5,
799 FW_PS_UAPSD_MODE = 6,
800 FW_PS_IBSS_MODE = 7,
801 FW_PS_WWLAN_MODE = 8,
802 FW_PS_PM_RADIO_OFF = 9,
803 FW_PS_PM_CARD_DISABLE = 10,
804 };
805
806 enum rt_psmode {
807 EACTIVE, /*Active/Continuous access. */
808 EMAXPS, /*Max power save mode. */
809 EFASTPS, /*Fast power save mode. */
810 EAUTOPS, /*Auto power save mode. */
811 };
812
813 /*LED related.*/
814 enum led_ctl_mode {
815 LED_CTL_POWER_ON = 1,
816 LED_CTL_LINK = 2,
817 LED_CTL_NO_LINK = 3,
818 LED_CTL_TX = 4,
819 LED_CTL_RX = 5,
820 LED_CTL_SITE_SURVEY = 6,
821 LED_CTL_POWER_OFF = 7,
822 LED_CTL_START_TO_LINK = 8,
823 LED_CTL_START_WPS = 9,
824 LED_CTL_STOP_WPS = 10,
825 };
826
827 enum rtl_led_pin {
828 LED_PIN_GPIO0,
829 LED_PIN_LED0,
830 LED_PIN_LED1,
831 LED_PIN_LED2
832 };
833
834 /*QoS related.*/
835 /*acm implementation method.*/
836 enum acm_method {
837 EACMWAY0_SWANDHW = 0,
838 EACMWAY1_HW = 1,
839 EACMWAY2_SW = 2,
840 };
841
842 enum macphy_mode {
843 SINGLEMAC_SINGLEPHY = 0,
844 DUALMAC_DUALPHY,
845 DUALMAC_SINGLEPHY,
846 };
847
848 enum band_type {
849 BAND_ON_2_4G = 0,
850 BAND_ON_5G,
851 BAND_ON_BOTH,
852 BANDMAX
853 };
854
855 /* aci/aifsn Field.
856 * Ref: WMM spec 2.2.2: WME Parameter Element, p.12.
857 */
858 union aci_aifsn {
859 u8 char_data;
860
861 struct {
862 u8 aifsn:4;
863 u8 acm:1;
864 u8 aci:2;
865 u8 reserved:1;
866 } f; /* Field */
867 };
868
869 /*mlme related.*/
870 enum wireless_mode {
871 WIRELESS_MODE_UNKNOWN = 0x00,
872 WIRELESS_MODE_A = 0x01,
873 WIRELESS_MODE_B = 0x02,
874 WIRELESS_MODE_G = 0x04,
875 WIRELESS_MODE_AUTO = 0x08,
876 WIRELESS_MODE_N_24G = 0x10,
877 WIRELESS_MODE_N_5G = 0x20,
878 WIRELESS_MODE_AC_5G = 0x40,
879 WIRELESS_MODE_AC_24G = 0x80,
880 WIRELESS_MODE_AC_ONLY = 0x100,
881 WIRELESS_MODE_MAX = 0x800
882 };
883
884 #define IS_WIRELESS_MODE_A(wirelessmode) \
885 (wirelessmode == WIRELESS_MODE_A)
886 #define IS_WIRELESS_MODE_B(wirelessmode) \
887 (wirelessmode == WIRELESS_MODE_B)
888 #define IS_WIRELESS_MODE_G(wirelessmode) \
889 (wirelessmode == WIRELESS_MODE_G)
890 #define IS_WIRELESS_MODE_N_24G(wirelessmode) \
891 (wirelessmode == WIRELESS_MODE_N_24G)
892 #define IS_WIRELESS_MODE_N_5G(wirelessmode) \
893 (wirelessmode == WIRELESS_MODE_N_5G)
894
895 enum ratr_table_mode {
896 RATR_INX_WIRELESS_NGB = 0,
897 RATR_INX_WIRELESS_NG = 1,
898 RATR_INX_WIRELESS_NB = 2,
899 RATR_INX_WIRELESS_N = 3,
900 RATR_INX_WIRELESS_GB = 4,
901 RATR_INX_WIRELESS_G = 5,
902 RATR_INX_WIRELESS_B = 6,
903 RATR_INX_WIRELESS_MC = 7,
904 RATR_INX_WIRELESS_A = 8,
905 RATR_INX_WIRELESS_AC_5N = 8,
906 RATR_INX_WIRELESS_AC_24N = 9,
907 };
908
909 enum ratr_table_mode_new {
910 RATEID_IDX_BGN_40M_2SS = 0,
911 RATEID_IDX_BGN_40M_1SS = 1,
912 RATEID_IDX_BGN_20M_2SS_BN = 2,
913 RATEID_IDX_BGN_20M_1SS_BN = 3,
914 RATEID_IDX_GN_N2SS = 4,
915 RATEID_IDX_GN_N1SS = 5,
916 RATEID_IDX_BG = 6,
917 RATEID_IDX_G = 7,
918 RATEID_IDX_B = 8,
919 RATEID_IDX_VHT_2SS = 9,
920 RATEID_IDX_VHT_1SS = 10,
921 RATEID_IDX_MIX1 = 11,
922 RATEID_IDX_MIX2 = 12,
923 RATEID_IDX_VHT_3SS = 13,
924 RATEID_IDX_BGN_3SS = 14,
925 };
926
927 enum rtl_link_state {
928 MAC80211_NOLINK = 0,
929 MAC80211_LINKING = 1,
930 MAC80211_LINKED = 2,
931 MAC80211_LINKED_SCANNING = 3,
932 };
933
934 enum act_category {
935 ACT_CAT_QOS = 1,
936 ACT_CAT_DLS = 2,
937 ACT_CAT_BA = 3,
938 ACT_CAT_HT = 7,
939 ACT_CAT_WMM = 17,
940 };
941
942 enum ba_action {
943 ACT_ADDBAREQ = 0,
944 ACT_ADDBARSP = 1,
945 ACT_DELBA = 2,
946 };
947
948 enum rt_polarity_ctl {
949 RT_POLARITY_LOW_ACT = 0,
950 RT_POLARITY_HIGH_ACT = 1,
951 };
952
953 /* After 8188E, we use V2 reason define. 88C/8723A use V1 reason. */
954 enum fw_wow_reason_v2 {
955 FW_WOW_V2_PTK_UPDATE_EVENT = 0x01,
956 FW_WOW_V2_GTK_UPDATE_EVENT = 0x02,
957 FW_WOW_V2_DISASSOC_EVENT = 0x04,
958 FW_WOW_V2_DEAUTH_EVENT = 0x08,
959 FW_WOW_V2_FW_DISCONNECT_EVENT = 0x10,
960 FW_WOW_V2_MAGIC_PKT_EVENT = 0x21,
961 FW_WOW_V2_UNICAST_PKT_EVENT = 0x22,
962 FW_WOW_V2_PATTERN_PKT_EVENT = 0x23,
963 FW_WOW_V2_RTD3_SSID_MATCH_EVENT = 0x24,
964 FW_WOW_V2_REALWOW_V2_WAKEUPPKT = 0x30,
965 FW_WOW_V2_REALWOW_V2_ACKLOST = 0x31,
966 FW_WOW_V2_REASON_MAX = 0xff,
967 };
968
969 enum wolpattern_type {
970 UNICAST_PATTERN = 0,
971 MULTICAST_PATTERN = 1,
972 BROADCAST_PATTERN = 2,
973 DONT_CARE_DA = 3,
974 UNKNOWN_TYPE = 4,
975 };
976
977 enum package_type {
978 PACKAGE_DEFAULT,
979 PACKAGE_QFN68,
980 PACKAGE_TFBGA90,
981 PACKAGE_TFBGA80,
982 PACKAGE_TFBGA79
983 };
984
985 enum rtl_spec_ver {
986 RTL_SPEC_NEW_RATEID = BIT(0), /* use ratr_table_mode_new */
987 RTL_SPEC_SUPPORT_VHT = BIT(1), /* support VHT */
988 RTL_SPEC_EXT_C2H = BIT(2), /* extend FW C2H (e.g. TX REPORT) */
989 };
990
991 enum dm_info_query {
992 DM_INFO_FA_OFDM,
993 DM_INFO_FA_CCK,
994 DM_INFO_FA_TOTAL,
995 DM_INFO_CCA_OFDM,
996 DM_INFO_CCA_CCK,
997 DM_INFO_CCA_ALL,
998 DM_INFO_CRC32_OK_VHT,
999 DM_INFO_CRC32_OK_HT,
1000 DM_INFO_CRC32_OK_LEGACY,
1001 DM_INFO_CRC32_OK_CCK,
1002 DM_INFO_CRC32_ERROR_VHT,
1003 DM_INFO_CRC32_ERROR_HT,
1004 DM_INFO_CRC32_ERROR_LEGACY,
1005 DM_INFO_CRC32_ERROR_CCK,
1006 DM_INFO_EDCCA_FLAG,
1007 DM_INFO_OFDM_ENABLE,
1008 DM_INFO_CCK_ENABLE,
1009 DM_INFO_CRC32_OK_HT_AGG,
1010 DM_INFO_CRC32_ERROR_HT_AGG,
1011 DM_INFO_DBG_PORT_0,
1012 DM_INFO_CURR_IGI,
1013 DM_INFO_RSSI_MIN,
1014 DM_INFO_RSSI_MAX,
1015 DM_INFO_CLM_RATIO,
1016 DM_INFO_NHM_RATIO,
1017 DM_INFO_IQK_ALL,
1018 DM_INFO_IQK_OK,
1019 DM_INFO_IQK_NG,
1020 DM_INFO_SIZE,
1021 };
1022
1023 enum rx_packet_type {
1024 NORMAL_RX,
1025 TX_REPORT1,
1026 TX_REPORT2,
1027 HIS_REPORT,
1028 C2H_PACKET,
1029 };
1030
1031 struct rtlwifi_tx_info {
1032 int sn;
1033 unsigned long send_time;
1034 };
1035
rtl_tx_skb_cb_info(struct sk_buff * skb)1036 static inline struct rtlwifi_tx_info *rtl_tx_skb_cb_info(struct sk_buff *skb)
1037 {
1038 struct ieee80211_tx_info *info = IEEE80211_SKB_CB(skb);
1039
1040 BUILD_BUG_ON(sizeof(struct rtlwifi_tx_info) >
1041 sizeof(info->status.status_driver_data));
1042
1043 return (struct rtlwifi_tx_info *)(info->status.status_driver_data);
1044 }
1045
1046 struct octet_string {
1047 u8 *octet;
1048 u16 length;
1049 };
1050
1051 struct rtl_led_ctl {
1052 bool led_opendrain;
1053 enum rtl_led_pin sw_led0;
1054 enum rtl_led_pin sw_led1;
1055 };
1056
1057 struct rtl_qos_parameters {
1058 __le16 cw_min;
1059 __le16 cw_max;
1060 u8 aifs;
1061 u8 flag;
1062 __le16 tx_op;
1063 } __packed;
1064
1065 struct rt_smooth_data {
1066 u32 elements[100]; /*array to store values */
1067 u32 index; /*index to current array to store */
1068 u32 total_num; /*num of valid elements */
1069 u32 total_val; /*sum of valid elements */
1070 };
1071
1072 struct false_alarm_statistics {
1073 u32 cnt_parity_fail;
1074 u32 cnt_rate_illegal;
1075 u32 cnt_crc8_fail;
1076 u32 cnt_mcs_fail;
1077 u32 cnt_fast_fsync_fail;
1078 u32 cnt_sb_search_fail;
1079 u32 cnt_ofdm_fail;
1080 u32 cnt_cck_fail;
1081 u32 cnt_all;
1082 u32 cnt_ofdm_cca;
1083 u32 cnt_cck_cca;
1084 u32 cnt_cca_all;
1085 u32 cnt_bw_usc;
1086 u32 cnt_bw_lsc;
1087 };
1088
1089 struct init_gain {
1090 u8 xaagccore1;
1091 u8 xbagccore1;
1092 u8 xcagccore1;
1093 u8 xdagccore1;
1094 u8 cca;
1095
1096 };
1097
1098 struct wireless_stats {
1099 u64 txbytesunicast;
1100 u64 txbytesmulticast;
1101 u64 txbytesbroadcast;
1102 u64 rxbytesunicast;
1103
1104 u64 txbytesunicast_inperiod;
1105 u64 rxbytesunicast_inperiod;
1106 u32 txbytesunicast_inperiod_tp;
1107 u32 rxbytesunicast_inperiod_tp;
1108 u64 txbytesunicast_last;
1109 u64 rxbytesunicast_last;
1110
1111 long rx_snr_db[4];
1112 /*Correct smoothed ss in Dbm, only used
1113 * in driver to report real power now.
1114 */
1115 long recv_signal_power;
1116 long signal_quality;
1117 long last_sigstrength_inpercent;
1118
1119 u32 rssi_calculate_cnt;
1120 u32 pwdb_all_cnt;
1121
1122 /* Transformed, in dbm. Beautified signal
1123 * strength for UI, not correct.
1124 */
1125 long signal_strength;
1126
1127 u8 rx_rssi_percentage[4];
1128 u8 rx_evm_dbm[4];
1129 u8 rx_evm_percentage[2];
1130
1131 u16 rx_cfo_short[4];
1132 u16 rx_cfo_tail[4];
1133
1134 struct rt_smooth_data ui_rssi;
1135 struct rt_smooth_data ui_link_quality;
1136 };
1137
1138 struct rate_adaptive {
1139 u8 rate_adaptive_disabled;
1140 u8 ratr_state;
1141 u16 reserve;
1142
1143 u32 high_rssi_thresh_for_ra;
1144 u32 high2low_rssi_thresh_for_ra;
1145 u8 low2high_rssi_thresh_for_ra40m;
1146 u32 low_rssi_thresh_for_ra40m;
1147 u8 low2high_rssi_thresh_for_ra20m;
1148 u32 low_rssi_thresh_for_ra20m;
1149 u32 upper_rssi_threshold_ratr;
1150 u32 middleupper_rssi_threshold_ratr;
1151 u32 middle_rssi_threshold_ratr;
1152 u32 middlelow_rssi_threshold_ratr;
1153 u32 low_rssi_threshold_ratr;
1154 u32 ultralow_rssi_threshold_ratr;
1155 u32 low_rssi_threshold_ratr_40m;
1156 u32 low_rssi_threshold_ratr_20m;
1157 u8 ping_rssi_enable;
1158 u32 ping_rssi_ratr;
1159 u32 ping_rssi_thresh_for_ra;
1160 u32 last_ratr;
1161 u8 pre_ratr_state;
1162 u8 ldpc_thres;
1163 bool use_ldpc;
1164 bool lower_rts_rate;
1165 bool is_special_data;
1166 };
1167
1168 struct regd_pair_mapping {
1169 u16 reg_dmnenum;
1170 u16 reg_5ghz_ctl;
1171 u16 reg_2ghz_ctl;
1172 };
1173
1174 struct dynamic_primary_cca {
1175 u8 pricca_flag;
1176 u8 intf_flag;
1177 u8 intf_type;
1178 u8 dup_rts_flag;
1179 u8 monitor_flag;
1180 u8 ch_offset;
1181 u8 mf_state;
1182 };
1183
1184 struct rtl_regulatory {
1185 s8 alpha2[2];
1186 u16 country_code;
1187 u16 max_power_level;
1188 u32 tp_scale;
1189 u16 current_rd;
1190 u16 current_rd_ext;
1191 int16_t power_limit;
1192 struct regd_pair_mapping *regpair;
1193 };
1194
1195 struct rtl_rfkill {
1196 bool rfkill_state; /*0 is off, 1 is on */
1197 };
1198
1199 /*for P2P PS**/
1200 #define P2P_MAX_NOA_NUM 2
1201
1202 enum p2p_role {
1203 P2P_ROLE_DISABLE = 0,
1204 P2P_ROLE_DEVICE = 1,
1205 P2P_ROLE_CLIENT = 2,
1206 P2P_ROLE_GO = 3
1207 };
1208
1209 enum p2p_ps_state {
1210 P2P_PS_DISABLE = 0,
1211 P2P_PS_ENABLE = 1,
1212 P2P_PS_SCAN = 2,
1213 P2P_PS_SCAN_DONE = 3,
1214 P2P_PS_ALLSTASLEEP = 4, /* for P2P GO */
1215 };
1216
1217 enum p2p_ps_mode {
1218 P2P_PS_NONE = 0,
1219 P2P_PS_CTWINDOW = 1,
1220 P2P_PS_NOA = 2,
1221 P2P_PS_MIX = 3, /* CTWindow and NoA */
1222 };
1223
1224 struct rtl_p2p_ps_info {
1225 enum p2p_ps_mode p2p_ps_mode; /* indicate p2p ps mode */
1226 enum p2p_ps_state p2p_ps_state; /* indicate p2p ps state */
1227 u8 noa_index; /* Identifies instance of Notice of Absence timing. */
1228 /* Client traffic window. A period of time in TU after TBTT. */
1229 u8 ctwindow;
1230 u8 opp_ps; /* opportunistic power save. */
1231 u8 noa_num; /* number of NoA descriptor in P2P IE. */
1232 /* Count for owner, Type of client. */
1233 u8 noa_count_type[P2P_MAX_NOA_NUM];
1234 /* Max duration for owner, preferred or min acceptable duration
1235 * for client.
1236 */
1237 u32 noa_duration[P2P_MAX_NOA_NUM];
1238 /* Length of interval for owner, preferred or max acceptable intervali
1239 * of client.
1240 */
1241 u32 noa_interval[P2P_MAX_NOA_NUM];
1242 /* schedule in terms of the lower 4 bytes of the TSF timer. */
1243 u32 noa_start_time[P2P_MAX_NOA_NUM];
1244 };
1245
1246 struct p2p_ps_offload_t {
1247 u8 offload_en:1;
1248 u8 role:1; /* 1: Owner, 0: Client */
1249 u8 ctwindow_en:1;
1250 u8 noa0_en:1;
1251 u8 noa1_en:1;
1252 u8 allstasleep:1;
1253 u8 discovery:1;
1254 u8 reserved:1;
1255 };
1256
1257 #define IQK_MATRIX_REG_NUM 8
1258 #define IQK_MATRIX_SETTINGS_NUM (1 + 24 + 21)
1259
1260 struct iqk_matrix_regs {
1261 bool iqk_done;
1262 long value[1][IQK_MATRIX_REG_NUM];
1263 };
1264
1265 struct phy_parameters {
1266 u16 length;
1267 u32 *pdata;
1268 };
1269
1270 enum hw_param_tab_index {
1271 PHY_REG_2T,
1272 PHY_REG_1T,
1273 PHY_REG_PG,
1274 RADIOA_2T,
1275 RADIOB_2T,
1276 RADIOA_1T,
1277 RADIOB_1T,
1278 MAC_REG,
1279 AGCTAB_2T,
1280 AGCTAB_1T,
1281 MAX_TAB
1282 };
1283
1284 struct rtl_phy {
1285 struct bb_reg_def phyreg_def[4]; /*Radio A/B/C/D */
1286 struct init_gain initgain_backup;
1287 enum io_type current_io_type;
1288
1289 u8 rf_mode;
1290 u8 rf_type;
1291 u8 current_chan_bw;
1292 u8 set_bwmode_inprogress;
1293 u8 sw_chnl_inprogress;
1294 u8 sw_chnl_stage;
1295 u8 sw_chnl_step;
1296 u8 current_channel;
1297 u8 set_io_inprogress;
1298 u8 lck_inprogress;
1299
1300 /* record for power tracking */
1301 s32 reg_e94;
1302 s32 reg_e9c;
1303 s32 reg_ea4;
1304 s32 reg_eac;
1305 s32 reg_eb4;
1306 s32 reg_ebc;
1307 s32 reg_ec4;
1308 s32 reg_ecc;
1309 u32 reg_c04, reg_c08, reg_874;
1310 u32 adda_backup[16];
1311 u32 iqk_mac_backup[IQK_MAC_REG_NUM];
1312 u32 iqk_bb_backup[10];
1313 bool iqk_initialized;
1314
1315 bool rfpath_rx_enable[MAX_RF_PATH];
1316 u8 reg_837;
1317 /* Dual mac */
1318 bool need_iqk;
1319 struct iqk_matrix_regs iqk_matrix[IQK_MATRIX_SETTINGS_NUM];
1320
1321 bool rfpi_enable;
1322
1323 u8 pwrgroup_cnt;
1324 u8 cck_high_power;
1325 /* this is for 88E & 8723A */
1326 u32 mcs_txpwrlevel_origoffset[MAX_PG_GROUP][16];
1327 /* MAX_PG_GROUP groups of pwr diff by rates */
1328 u32 mcs_offset[MAX_PG_GROUP][16];
1329 u32 tx_power_by_rate_offset[TX_PWR_BY_RATE_NUM_BAND]
1330 [TX_PWR_BY_RATE_NUM_RF]
1331 [TX_PWR_BY_RATE_NUM_RF]
1332 [TX_PWR_BY_RATE_NUM_RATE];
1333 u8 txpwr_by_rate_base_24g[TX_PWR_BY_RATE_NUM_RF]
1334 [TX_PWR_BY_RATE_NUM_RF]
1335 [MAX_BASE_NUM_IN_PHY_REG_PG_24G];
1336 u8 txpwr_by_rate_base_5g[TX_PWR_BY_RATE_NUM_RF]
1337 [TX_PWR_BY_RATE_NUM_RF]
1338 [MAX_BASE_NUM_IN_PHY_REG_PG_5G];
1339 u8 default_initialgain[4];
1340
1341 /* the current Tx power level */
1342 u8 cur_cck_txpwridx;
1343 u8 cur_ofdm24g_txpwridx;
1344 u8 cur_bw20_txpwridx;
1345 u8 cur_bw40_txpwridx;
1346
1347 s8 txpwr_limit_2_4g[MAX_REGULATION_NUM]
1348 [MAX_2_4G_BANDWIDTH_NUM]
1349 [MAX_RATE_SECTION_NUM]
1350 [CHANNEL_MAX_NUMBER_2G]
1351 [MAX_RF_PATH_NUM];
1352 s8 txpwr_limit_5g[MAX_REGULATION_NUM]
1353 [MAX_5G_BANDWIDTH_NUM]
1354 [MAX_RATE_SECTION_NUM]
1355 [CHANNEL_MAX_NUMBER_5G]
1356 [MAX_RF_PATH_NUM];
1357
1358 u32 rfreg_chnlval[2];
1359 u32 reg_rf3c[2]; /* pathA / pathB */
1360
1361 u32 backup_rf_0x1a;/*92ee*/
1362 /* bfsync */
1363 u8 framesync;
1364 u32 framesync_c34;
1365
1366 u8 num_total_rfpath;
1367 struct phy_parameters hwparam_tables[MAX_TAB];
1368 u16 rf_pathmap;
1369
1370 enum rt_polarity_ctl polarity_ctl;
1371 };
1372
1373 #define MAX_TID_COUNT 9
1374 #define RTL_AGG_STOP 0
1375 #define RTL_AGG_PROGRESS 1
1376 #define RTL_AGG_START 2
1377 #define RTL_AGG_OPERATIONAL 3
1378 #define RTL_RX_AGG_START 1
1379 #define RTL_RX_AGG_STOP 0
1380 #define RTL_AGG_EMPTYING_HW_QUEUE_ADDBA 2
1381 #define RTL_AGG_EMPTYING_HW_QUEUE_DELBA 3
1382
1383 struct rtl_ht_agg {
1384 u16 txq_id;
1385 u16 wait_for_ba;
1386 u16 start_idx;
1387 u64 bitmap;
1388 u32 rate_n_flags;
1389 u8 agg_state;
1390 u8 rx_agg_state;
1391 };
1392
1393 struct rssi_sta {
1394 long undec_sm_pwdb;
1395 long undec_sm_cck;
1396 };
1397
1398 struct rtl_tid_data {
1399 struct rtl_ht_agg agg;
1400 };
1401
1402 struct rtl_sta_info {
1403 struct list_head list;
1404 struct rtl_tid_data tids[MAX_TID_COUNT];
1405 /* just used for ap adhoc or mesh*/
1406 struct rssi_sta rssi_stat;
1407 u8 rssi_level;
1408 u16 wireless_mode;
1409 u8 ratr_index;
1410 u8 mimo_ps;
1411 u8 mac_addr[ETH_ALEN];
1412 } __packed;
1413
1414 struct rtl_priv;
1415 struct rtl_io {
1416 struct device *dev;
1417 struct mutex bb_mutex;
1418
1419 /*PCI MEM map */
1420 unsigned long pci_mem_end; /*shared mem end */
1421 unsigned long pci_mem_start; /*shared mem start */
1422
1423 /*PCI IO map */
1424 unsigned long pci_base_addr; /*device I/O address */
1425
1426 void (*write8)(struct rtl_priv *rtlpriv, u32 addr, u8 val);
1427 void (*write16)(struct rtl_priv *rtlpriv, u32 addr, u16 val);
1428 void (*write32)(struct rtl_priv *rtlpriv, u32 addr, u32 val);
1429 void (*write_chunk)(struct rtl_priv *rtlpriv, u32 addr, u32 length,
1430 u8 *data);
1431
1432 u8 (*read8)(struct rtl_priv *rtlpriv, u32 addr);
1433 u16 (*read16)(struct rtl_priv *rtlpriv, u32 addr);
1434 u32 (*read32)(struct rtl_priv *rtlpriv, u32 addr);
1435
1436 };
1437
1438 struct rtl_mac {
1439 u8 mac_addr[ETH_ALEN];
1440 u8 mac80211_registered;
1441 u8 beacon_enabled;
1442
1443 u32 tx_ss_num;
1444 u32 rx_ss_num;
1445
1446 struct ieee80211_supported_band bands[NUM_NL80211_BANDS];
1447 struct ieee80211_hw *hw;
1448 struct ieee80211_vif *vif;
1449 enum nl80211_iftype opmode;
1450
1451 /*Probe Beacon management */
1452 enum rtl_link_state link_state;
1453
1454 int n_channels;
1455 int n_bitrates;
1456
1457 bool offchan_delay;
1458 u8 p2p; /*using p2p role*/
1459 bool p2p_in_use;
1460
1461 /*filters */
1462 u32 rx_conf;
1463 u16 rx_mgt_filter;
1464 u16 rx_ctrl_filter;
1465 u16 rx_data_filter;
1466
1467 bool act_scanning;
1468 u8 cnt_after_linked;
1469 bool skip_scan;
1470
1471 /* early mode */
1472 /* skb wait queue */
1473 struct sk_buff_head skb_waitq[MAX_TID_COUNT];
1474
1475 u8 ht_stbc_cap;
1476 u8 ht_cur_stbc;
1477
1478 /*vht support*/
1479 u8 vht_enable;
1480 u8 bw_80;
1481 u8 vht_cur_ldpc;
1482 u8 vht_cur_stbc;
1483 u8 vht_stbc_cap;
1484 u8 vht_ldpc_cap;
1485
1486 /*RDG*/
1487 bool rdg_en;
1488
1489 /*AP*/
1490 u8 bssid[ETH_ALEN] __aligned(2);
1491 u32 vendor;
1492 u8 mcs[16]; /* 16 bytes mcs for HT rates. */
1493 u32 basic_rates; /* b/g rates */
1494 u8 ht_enable;
1495 u8 sgi_40;
1496 u8 sgi_20;
1497 u8 bw_40;
1498 u16 mode; /* wireless mode */
1499 u8 slot_time;
1500 u8 short_preamble;
1501 u8 use_cts_protect;
1502 u8 cur_40_prime_sc;
1503 u8 cur_40_prime_sc_bk;
1504 u8 cur_80_prime_sc;
1505 u64 tsf;
1506 u8 retry_short;
1507 u8 retry_long;
1508 u16 assoc_id;
1509 bool hiddenssid;
1510
1511 /*IBSS*/
1512 int beacon_interval;
1513
1514 /*AMPDU*/
1515 u8 min_space_cfg; /*For Min spacing configurations */
1516 u8 max_mss_density;
1517 u8 current_ampdu_factor;
1518 u8 current_ampdu_density;
1519
1520 /*QOS & EDCA */
1521 struct ieee80211_tx_queue_params edca_param[RTL_MAC80211_NUM_QUEUE];
1522 struct rtl_qos_parameters ac[AC_MAX];
1523
1524 /* counters */
1525 u64 last_txok_cnt;
1526 u64 last_rxok_cnt;
1527 u32 last_bt_edca_ul;
1528 u32 last_bt_edca_dl;
1529 };
1530
1531 struct btdm_8723 {
1532 bool all_off;
1533 bool agc_table_en;
1534 bool adc_back_off_on;
1535 bool b2_ant_hid_en;
1536 bool low_penalty_rate_adaptive;
1537 bool rf_rx_lpf_shrink;
1538 bool reject_aggre_pkt;
1539 bool tra_tdma_on;
1540 u8 tra_tdma_nav;
1541 u8 tra_tdma_ant;
1542 bool tdma_on;
1543 u8 tdma_ant;
1544 u8 tdma_nav;
1545 u8 tdma_dac_swing;
1546 u8 fw_dac_swing_lvl;
1547 bool ps_tdma_on;
1548 u8 ps_tdma_byte[5];
1549 bool pta_on;
1550 u32 val_0x6c0;
1551 u32 val_0x6c8;
1552 u32 val_0x6cc;
1553 bool sw_dac_swing_on;
1554 u32 sw_dac_swing_lvl;
1555 u32 wlan_act_hi;
1556 u32 wlan_act_lo;
1557 u32 bt_retry_index;
1558 bool dec_bt_pwr;
1559 bool ignore_wlan_act;
1560 };
1561
1562 struct bt_coexist_8723 {
1563 u32 high_priority_tx;
1564 u32 high_priority_rx;
1565 u32 low_priority_tx;
1566 u32 low_priority_rx;
1567 u8 c2h_bt_info;
1568 bool c2h_bt_info_req_sent;
1569 bool c2h_bt_inquiry_page;
1570 unsigned long bt_inq_page_start_time;
1571 u8 bt_retry_cnt;
1572 u8 c2h_bt_info_original;
1573 u8 bt_inquiry_page_cnt;
1574 struct btdm_8723 btdm;
1575 };
1576
1577 struct rtl_hal {
1578 struct ieee80211_hw *hw;
1579 bool driver_is_goingto_unload;
1580 bool up_first_time;
1581 bool first_init;
1582 bool being_init_adapter;
1583 bool mac_func_enable;
1584 bool pre_edcca_enable;
1585 struct bt_coexist_8723 hal_coex_8723;
1586
1587 enum intf_type interface;
1588 u16 hw_type; /*92c or 92d or 92s and so on */
1589 u8 ic_class;
1590 u8 oem_id;
1591 u32 version; /*version of chip */
1592 u8 state; /*stop 0, start 1 */
1593 u8 board_type;
1594 u8 package_type;
1595
1596 u8 pa_type_2g;
1597 u8 pa_type_5g;
1598 u8 lna_type_2g;
1599 u8 lna_type_5g;
1600 u8 external_pa_2g;
1601 u8 external_lna_2g;
1602 u8 external_pa_5g;
1603 u8 external_lna_5g;
1604 u8 type_glna;
1605 u8 type_gpa;
1606 u8 type_alna;
1607 u8 type_apa;
1608 u8 rfe_type;
1609
1610 /*firmware */
1611 u32 fwsize;
1612 u8 *pfirmware;
1613 u16 fw_version;
1614 u16 fw_subversion;
1615 bool h2c_setinprogress;
1616 u8 last_hmeboxnum;
1617 bool fw_ready;
1618 /*Reserve page start offset except beacon in TxQ. */
1619 u8 fw_rsvdpage_startoffset;
1620 u8 h2c_txcmd_seq;
1621 u8 current_ra_rate;
1622
1623 /* FW Cmd IO related */
1624 u16 fwcmd_iomap;
1625 u32 fwcmd_ioparam;
1626 bool set_fwcmd_inprogress;
1627 u8 current_fwcmd_io;
1628
1629 struct p2p_ps_offload_t p2p_ps_offload;
1630 bool fw_clk_change_in_progress;
1631 bool allow_sw_to_change_hwclc;
1632 u8 fw_ps_state;
1633
1634 /*AMPDU init min space*/
1635 u8 minspace_cfg; /*For Min spacing configurations */
1636
1637 /* Dual mac */
1638 enum macphy_mode macphymode;
1639 enum band_type current_bandtype; /* 0:2.4G, 1:5G */
1640 enum band_type current_bandtypebackup;
1641 enum band_type bandset;
1642 /* dual MAC 0--Mac0 1--Mac1 */
1643 u32 interfaceindex;
1644 /* just for DualMac S3S4 */
1645 u8 macphyctl_reg;
1646 bool earlymode_enable;
1647 u8 max_earlymode_num;
1648 /* Dual mac*/
1649 bool during_mac0init_radiob;
1650 bool during_mac1init_radioa;
1651 bool reloadtxpowerindex;
1652 /* True if IMR or IQK have done
1653 * for 2.4G in scan progress
1654 */
1655 bool load_imrandiqk_setting_for2g;
1656
1657 bool disable_amsdu_8k;
1658 bool master_of_dmsp;
1659 bool slave_of_dmsp;
1660
1661 /*for wowlan*/
1662 bool enter_pnp_sleep;
1663 bool wake_from_pnp_sleep;
1664 time64_t last_suspend_sec;
1665 u32 wowlan_fwsize;
1666 u8 *wowlan_firmware;
1667
1668 u8 hw_rof_enable; /*Enable GPIO[9] as WL RF HW PDn source*/
1669
1670 bool real_wow_v2_enable;
1671 bool re_init_llt_table;
1672 };
1673
1674 struct rtl_security {
1675 /*default 0 */
1676 bool use_sw_sec;
1677
1678 bool being_setkey;
1679 bool use_defaultkey;
1680 /*Encryption Algorithm for Unicast Packet */
1681 enum rt_enc_alg pairwise_enc_algorithm;
1682 /*Encryption Algorithm for Brocast/Multicast */
1683 enum rt_enc_alg group_enc_algorithm;
1684 /*Cam Entry Bitmap */
1685 u32 hwsec_cam_bitmap;
1686 u8 hwsec_cam_sta_addr[TOTAL_CAM_ENTRY][ETH_ALEN];
1687 /*local Key buffer, indx 0 is for
1688 * pairwise key 1-4 is for agoup key.
1689 */
1690 u8 key_buf[KEY_BUF_SIZE][MAX_KEY_LEN];
1691 u8 key_len[KEY_BUF_SIZE];
1692
1693 /*The pointer of Pairwise Key,
1694 * it always points to KeyBuf[4]
1695 */
1696 u8 *pairwise_key;
1697 };
1698
1699 #define ASSOCIATE_ENTRY_NUM 33
1700
1701 struct fast_ant_training {
1702 u8 bssid[6];
1703 u8 antsel_rx_keep_0;
1704 u8 antsel_rx_keep_1;
1705 u8 antsel_rx_keep_2;
1706 u32 ant_sum[7];
1707 u32 ant_cnt[7];
1708 u32 ant_ave[7];
1709 u8 fat_state;
1710 u32 train_idx;
1711 u8 antsel_a[ASSOCIATE_ENTRY_NUM];
1712 u8 antsel_b[ASSOCIATE_ENTRY_NUM];
1713 u8 antsel_c[ASSOCIATE_ENTRY_NUM];
1714 u32 main_ant_sum[ASSOCIATE_ENTRY_NUM];
1715 u32 aux_ant_sum[ASSOCIATE_ENTRY_NUM];
1716 u32 main_ant_cnt[ASSOCIATE_ENTRY_NUM];
1717 u32 aux_ant_cnt[ASSOCIATE_ENTRY_NUM];
1718 u8 rx_idle_ant;
1719 bool becomelinked;
1720 };
1721
1722 struct dm_phy_dbg_info {
1723 s8 rx_snrdb[4];
1724 u64 num_qry_phy_status;
1725 u64 num_qry_phy_status_cck;
1726 u64 num_qry_phy_status_ofdm;
1727 u16 num_qry_beacon_pkt;
1728 u16 num_non_be_pkt;
1729 s32 rx_evm[4];
1730 };
1731
1732 struct rtl_dm {
1733 /*PHY status for Dynamic Management */
1734 long entry_min_undec_sm_pwdb;
1735 long undec_sm_cck;
1736 long undec_sm_pwdb; /*out dm */
1737 long entry_max_undec_sm_pwdb;
1738 s32 ofdm_pkt_cnt;
1739 bool dm_initialgain_enable;
1740 bool dynamic_txpower_enable;
1741 bool current_turbo_edca;
1742 bool is_any_nonbepkts; /*out dm */
1743 bool is_cur_rdlstate;
1744 bool txpower_trackinginit;
1745 bool disable_framebursting;
1746 bool cck_inch14;
1747 bool txpower_tracking;
1748 bool useramask;
1749 bool rfpath_rxenable[4];
1750 bool inform_fw_driverctrldm;
1751 bool current_mrc_switch;
1752 u8 txpowercount;
1753 u8 powerindex_backup[6];
1754
1755 u8 thermalvalue_rxgain;
1756 u8 thermalvalue_iqk;
1757 u8 thermalvalue_lck;
1758 u8 thermalvalue;
1759 u8 last_dtp_lvl;
1760 u8 thermalvalue_avg[AVG_THERMAL_NUM];
1761 u8 thermalvalue_avg_index;
1762 u8 tm_trigger;
1763 bool done_txpower;
1764 u8 dynamic_txhighpower_lvl; /*Tx high power level */
1765 u8 dm_flag; /*Indicate each dynamic mechanism's status. */
1766 u8 dm_flag_tmp;
1767 u8 dm_type;
1768 u8 dm_rssi_sel;
1769 u8 txpower_track_control;
1770 bool interrupt_migration;
1771 bool disable_tx_int;
1772 s8 ofdm_index[MAX_RF_PATH];
1773 u8 default_ofdm_index;
1774 u8 default_cck_index;
1775 s8 cck_index;
1776 s8 delta_power_index[MAX_RF_PATH];
1777 s8 delta_power_index_last[MAX_RF_PATH];
1778 s8 power_index_offset[MAX_RF_PATH];
1779 s8 absolute_ofdm_swing_idx[MAX_RF_PATH];
1780 s8 remnant_ofdm_swing_idx[MAX_RF_PATH];
1781 s8 remnant_cck_idx;
1782 bool modify_txagc_flag_path_a;
1783 bool modify_txagc_flag_path_b;
1784
1785 bool one_entry_only;
1786 struct dm_phy_dbg_info dbginfo;
1787
1788 /* Dynamic ATC switch */
1789 bool atc_status;
1790 bool large_cfo_hit;
1791 bool is_freeze;
1792 int cfo_tail[2];
1793 int cfo_ave_pre;
1794 int crystal_cap;
1795 u8 cfo_threshold;
1796 u32 packet_count;
1797 u32 packet_count_pre;
1798 u8 tx_rate;
1799
1800 /*88e tx power tracking*/
1801 u8 swing_idx_ofdm[MAX_RF_PATH];
1802 u8 swing_idx_ofdm_cur;
1803 u8 swing_idx_ofdm_base[MAX_RF_PATH];
1804 bool swing_flag_ofdm;
1805 u8 swing_idx_cck;
1806 u8 swing_idx_cck_cur;
1807 u8 swing_idx_cck_base;
1808 bool swing_flag_cck;
1809
1810 s8 swing_diff_2g;
1811 s8 swing_diff_5g;
1812
1813 /* DMSP */
1814 bool supp_phymode_switch;
1815
1816 /* DulMac */
1817 struct fast_ant_training fat_table;
1818
1819 u8 resp_tx_path;
1820 u8 path_sel;
1821 u32 patha_sum;
1822 u32 pathb_sum;
1823 u32 patha_cnt;
1824 u32 pathb_cnt;
1825
1826 u8 pre_channel;
1827 u8 *p_channel;
1828 u8 linked_interval;
1829
1830 u64 last_tx_ok_cnt;
1831 u64 last_rx_ok_cnt;
1832 };
1833
1834 #define EFUSE_MAX_LOGICAL_SIZE 512
1835
1836 struct rtl_efuse {
1837 const struct rtl_efuse_ops *efuse_ops;
1838 bool autoload_ok;
1839 bool bootfromefuse;
1840 u16 max_physical_size;
1841
1842 u8 efuse_map[2][EFUSE_MAX_LOGICAL_SIZE];
1843 u16 efuse_usedbytes;
1844 u8 efuse_usedpercentage;
1845
1846 u8 autoload_failflag;
1847 u8 autoload_status;
1848
1849 short epromtype;
1850 u16 eeprom_vid;
1851 u16 eeprom_did;
1852 u16 eeprom_svid;
1853 u16 eeprom_smid;
1854 u8 eeprom_oemid;
1855 u16 eeprom_channelplan;
1856 u8 eeprom_version;
1857 u8 board_type;
1858 u8 external_pa;
1859
1860 u8 dev_addr[6];
1861 u8 wowlan_enable;
1862 u8 antenna_div_cfg;
1863 u8 antenna_div_type;
1864
1865 bool txpwr_fromeprom;
1866 u8 eeprom_crystalcap;
1867 u8 eeprom_tssi[2];
1868 u8 eeprom_tssi_5g[3][2]; /* for 5GL/5GM/5GH band. */
1869 u8 eeprom_pwrlimit_ht20[CHANNEL_GROUP_MAX];
1870 u8 eeprom_pwrlimit_ht40[CHANNEL_GROUP_MAX];
1871 u8 eeprom_chnlarea_txpwr_cck[MAX_RF_PATH][CHANNEL_GROUP_MAX_2G];
1872 u8 eeprom_chnlarea_txpwr_ht40_1s[MAX_RF_PATH][CHANNEL_GROUP_MAX];
1873 u8 eprom_chnl_txpwr_ht40_2sdf[MAX_RF_PATH][CHANNEL_GROUP_MAX];
1874
1875 u8 internal_pa_5g[2]; /* pathA / pathB */
1876 u8 eeprom_c9;
1877 u8 eeprom_cc;
1878
1879 /*For power group */
1880 u8 eeprom_pwrgroup[2][3];
1881 u8 pwrgroup_ht20[2][CHANNEL_MAX_NUMBER];
1882 u8 pwrgroup_ht40[2][CHANNEL_MAX_NUMBER];
1883
1884 u8 txpwrlevel_cck[MAX_RF_PATH][CHANNEL_MAX_NUMBER_2G];
1885 /*For HT 40MHZ pwr */
1886 u8 txpwrlevel_ht40_1s[MAX_RF_PATH][CHANNEL_MAX_NUMBER];
1887 /*For HT 40MHZ pwr */
1888 u8 txpwrlevel_ht40_2s[MAX_RF_PATH][CHANNEL_MAX_NUMBER];
1889
1890 /*--------------------------------------------------------*
1891 * 8192CE\8192SE\8192DE\8723AE use the following 4 arrays,
1892 * other ICs (8188EE\8723BE\8192EE\8812AE...)
1893 * define new arrays in Windows code.
1894 * BUT, in linux code, we use the same array for all ICs.
1895 *
1896 * The Correspondance relation between two arrays is:
1897 * txpwr_cckdiff[][] == CCK_24G_Diff[][]
1898 * txpwr_ht20diff[][] == BW20_24G_Diff[][]
1899 * txpwr_ht40diff[][] == BW40_24G_Diff[][]
1900 * txpwr_legacyhtdiff[][] == OFDM_24G_Diff[][]
1901 *
1902 * Sizes of these arrays are decided by the larger ones.
1903 */
1904 s8 txpwr_cckdiff[MAX_RF_PATH][CHANNEL_MAX_NUMBER];
1905 s8 txpwr_ht20diff[MAX_RF_PATH][CHANNEL_MAX_NUMBER];
1906 s8 txpwr_ht40diff[MAX_RF_PATH][CHANNEL_MAX_NUMBER];
1907 s8 txpwr_legacyhtdiff[MAX_RF_PATH][CHANNEL_MAX_NUMBER];
1908
1909 u8 txpwr_5g_bw40base[MAX_RF_PATH][CHANNEL_MAX_NUMBER];
1910 u8 txpwr_5g_bw80base[MAX_RF_PATH][CHANNEL_MAX_NUMBER_5G_80M];
1911 s8 txpwr_5g_ofdmdiff[MAX_RF_PATH][MAX_TX_COUNT];
1912 s8 txpwr_5g_bw20diff[MAX_RF_PATH][MAX_TX_COUNT];
1913 s8 txpwr_5g_bw40diff[MAX_RF_PATH][MAX_TX_COUNT];
1914 s8 txpwr_5g_bw80diff[MAX_RF_PATH][MAX_TX_COUNT];
1915
1916 u8 txpwr_safetyflag; /* Band edge enable flag */
1917 u16 eeprom_txpowerdiff;
1918 u8 antenna_txpwdiff[3];
1919
1920 u8 eeprom_regulatory;
1921 u8 eeprom_thermalmeter;
1922 u8 thermalmeter[2]; /*ThermalMeter, index 0 for RFIC0, 1 for RFIC1 */
1923 u16 tssi_13dbm;
1924 u8 crystalcap; /* CrystalCap. */
1925 u8 delta_iqk;
1926 u8 delta_lck;
1927
1928 u8 legacy_ht_txpowerdiff; /*Legacy to HT rate power diff */
1929 bool apk_thermalmeterignore;
1930
1931 bool b1x1_recvcombine;
1932 bool b1ss_support;
1933
1934 /*channel plan */
1935 u8 channel_plan;
1936 };
1937
1938 struct rtl_efuse_ops {
1939 int (*efuse_onebyte_read)(struct ieee80211_hw *hw, u16 addr, u8 *data);
1940 void (*efuse_logical_map_read)(struct ieee80211_hw *hw, u8 type,
1941 u16 offset, u32 *value);
1942 };
1943
1944 struct rtl_tx_report {
1945 atomic_t sn;
1946 u16 last_sent_sn;
1947 unsigned long last_sent_time;
1948 u16 last_recv_sn;
1949 struct sk_buff_head queue;
1950 };
1951
1952 struct rtl_ps_ctl {
1953 bool pwrdomain_protect;
1954 bool in_powersavemode;
1955 bool rfchange_inprogress;
1956 bool swrf_processing;
1957 bool hwradiooff;
1958 /* just for PCIE ASPM
1959 * If it supports ASPM, Offset[560h] = 0x40,
1960 * otherwise Offset[560h] = 0x00.
1961 */
1962 bool support_aspm;
1963 bool support_backdoor;
1964
1965 /*for LPS */
1966 enum rt_psmode dot11_psmode; /*Power save mode configured. */
1967 bool swctrl_lps;
1968 bool leisure_ps;
1969 bool fwctrl_lps;
1970 u8 fwctrl_psmode;
1971 /*For Fw control LPS mode */
1972 u8 reg_fwctrl_lps;
1973 /*Record Fw PS mode status. */
1974 bool fw_current_inpsmode;
1975 u8 reg_max_lps_awakeintvl;
1976 bool report_linked;
1977 bool low_power_enable;/*for 32k*/
1978
1979 /*for IPS */
1980 bool inactiveps;
1981
1982 u32 rfoff_reason;
1983
1984 /*RF OFF Level */
1985 u32 cur_ps_level;
1986 u32 reg_rfps_level;
1987
1988 bool pwrdown_mode;
1989
1990 enum rf_pwrstate inactive_pwrstate;
1991 enum rf_pwrstate rfpwr_state; /*cur power state */
1992
1993 /* for SW LPS*/
1994 bool sw_ps_enabled;
1995 bool state_inap;
1996 bool multi_buffered;
1997 u16 nullfunc_seq;
1998 unsigned int dtim_counter;
1999 unsigned long last_sleep_jiffies;
2000 unsigned long last_awake_jiffies;
2001 unsigned long last_delaylps_stamp_jiffies;
2002 unsigned long last_dtim;
2003 unsigned long last_beacon;
2004
2005 /*For P2P PS */
2006 struct rtl_p2p_ps_info p2p_ps_info;
2007 u8 pwr_mode;
2008 u8 smart_ps;
2009
2010 /* wake up on line */
2011 u8 wo_wlan_mode;
2012 u8 arp_offload_enable;
2013 u8 gtk_offload_enable;
2014 /* Used for WOL, indicates the reason for waking event.*/
2015 u32 wakeup_reason;
2016 };
2017
2018 struct rtl_stats {
2019 u8 psaddr[ETH_ALEN];
2020 u32 mac_time[2];
2021 s8 rssi;
2022 u8 signal;
2023 u8 noise;
2024 u8 rate; /* hw desc rate */
2025 u8 received_channel;
2026 u8 control;
2027 u8 mask;
2028 u8 freq;
2029 u16 len;
2030 u64 tsf;
2031 u32 beacon_time;
2032 u8 nic_type;
2033 u16 length;
2034 u8 signalquality; /*in 0-100 index. */
2035 /* Real power in dBm for this packet,
2036 * no beautification and aggregation.
2037 */
2038 s32 recvsignalpower;
2039 s8 rxpower; /*in dBm Translate from PWdB */
2040 u8 signalstrength; /*in 0-100 index. */
2041 u16 hwerror:1;
2042 u16 crc:1;
2043 u16 icv:1;
2044 u16 shortpreamble:1;
2045 u16 antenna:1;
2046 u16 decrypted:1;
2047 u16 wakeup:1;
2048 u32 timestamp_low;
2049 u32 timestamp_high;
2050 bool shift;
2051
2052 u8 rx_drvinfo_size;
2053 u8 rx_bufshift;
2054 bool isampdu;
2055 bool isfirst_ampdu;
2056 bool rx_is40mhzpacket;
2057 u8 rx_packet_bw;
2058 u32 rx_pwdb_all;
2059 u8 rx_mimo_signalstrength[4]; /*in 0~100 index */
2060 s8 rx_mimo_signalquality[4];
2061 u8 rx_mimo_evm_dbm[4];
2062 u16 cfo_short[4]; /* per-path's Cfo_short */
2063 u16 cfo_tail[4];
2064
2065 s8 rx_mimo_sig_qual[4];
2066 u8 rx_pwr[4]; /* per-path's pwdb */
2067 u8 rx_snr[4]; /* per-path's SNR */
2068 u8 bandwidth;
2069 u8 bt_coex_pwr_adjust;
2070 bool packet_matchbssid;
2071 bool is_cck;
2072 bool is_ht;
2073 bool packet_toself;
2074 bool packet_beacon; /*for rssi */
2075 s8 cck_adc_pwdb[4]; /*for rx path selection */
2076
2077 bool is_vht;
2078 bool is_short_gi;
2079 u8 vht_nss;
2080
2081 u8 packet_report_type;
2082
2083 u32 macid;
2084 u32 bt_rx_rssi_percentage;
2085 u32 macid_valid_entry[2];
2086 };
2087
2088 struct rt_link_detect {
2089 /* count for roaming */
2090 u32 bcn_rx_inperiod;
2091 u32 roam_times;
2092
2093 u32 num_tx_in4period[4];
2094 u32 num_rx_in4period[4];
2095
2096 u32 num_tx_inperiod;
2097 u32 num_rx_inperiod;
2098
2099 bool busytraffic;
2100 bool tx_busy_traffic;
2101 bool rx_busy_traffic;
2102 bool higher_busytraffic;
2103 bool higher_busyrxtraffic;
2104
2105 u32 tidtx_in4period[MAX_TID_COUNT][4];
2106 u32 tidtx_inperiod[MAX_TID_COUNT];
2107 bool higher_busytxtraffic[MAX_TID_COUNT];
2108 };
2109
2110 struct rtl_tcb_desc {
2111 u8 packet_bw:2;
2112 u8 multicast:1;
2113 u8 broadcast:1;
2114
2115 u8 rts_stbc:1;
2116 u8 rts_enable:1;
2117 u8 cts_enable:1;
2118 u8 rts_use_shortpreamble:1;
2119 u8 rts_use_shortgi:1;
2120 u8 rts_sc:1;
2121 u8 rts_bw:1;
2122 u8 rts_rate;
2123
2124 u8 use_shortgi:1;
2125 u8 use_shortpreamble:1;
2126 u8 use_driver_rate:1;
2127 u8 disable_ratefallback:1;
2128
2129 u8 use_spe_rpt:1;
2130
2131 u8 ratr_index;
2132 u8 mac_id;
2133 u8 hw_rate;
2134
2135 u8 last_inipkt:1;
2136 u8 cmd_or_init:1;
2137 u8 queue_index;
2138
2139 /* early mode */
2140 u8 empkt_num;
2141 /* The max value by HW */
2142 u32 empkt_len[10];
2143 bool tx_enable_sw_calc_duration;
2144 };
2145
2146 struct rtl_wow_pattern {
2147 u8 type;
2148 u16 crc;
2149 u32 mask[4];
2150 };
2151
2152 /* struct to store contents of interrupt vectors */
2153 struct rtl_int {
2154 u32 inta;
2155 u32 intb;
2156 u32 intc;
2157 u32 intd;
2158 };
2159
2160 struct rtl_hal_ops {
2161 int (*init_sw_vars)(struct ieee80211_hw *hw);
2162 void (*deinit_sw_vars)(struct ieee80211_hw *hw);
2163 void (*read_chip_version)(struct ieee80211_hw *hw);
2164 void (*read_eeprom_info)(struct ieee80211_hw *hw);
2165 void (*interrupt_recognized)(struct ieee80211_hw *hw,
2166 struct rtl_int *intvec);
2167 int (*hw_init)(struct ieee80211_hw *hw);
2168 void (*hw_disable)(struct ieee80211_hw *hw);
2169 void (*hw_suspend)(struct ieee80211_hw *hw);
2170 void (*hw_resume)(struct ieee80211_hw *hw);
2171 void (*enable_interrupt)(struct ieee80211_hw *hw);
2172 void (*disable_interrupt)(struct ieee80211_hw *hw);
2173 int (*set_network_type)(struct ieee80211_hw *hw,
2174 enum nl80211_iftype type);
2175 void (*set_chk_bssid)(struct ieee80211_hw *hw,
2176 bool check_bssid);
2177 void (*set_bw_mode)(struct ieee80211_hw *hw,
2178 enum nl80211_channel_type ch_type);
2179 u8 (*switch_channel)(struct ieee80211_hw *hw);
2180 void (*set_qos)(struct ieee80211_hw *hw, int aci);
2181 void (*set_bcn_reg)(struct ieee80211_hw *hw);
2182 void (*set_bcn_intv)(struct ieee80211_hw *hw);
2183 void (*update_interrupt_mask)(struct ieee80211_hw *hw,
2184 u32 add_msr, u32 rm_msr);
2185 void (*get_hw_reg)(struct ieee80211_hw *hw, u8 variable, u8 *val);
2186 void (*set_hw_reg)(struct ieee80211_hw *hw, u8 variable, u8 *val);
2187 void (*update_rate_tbl)(struct ieee80211_hw *hw,
2188 struct ieee80211_sta *sta, u8 rssi_leve,
2189 bool update_bw);
2190 void (*update_rate_mask)(struct ieee80211_hw *hw, u8 rssi_level);
2191 u16 (*rx_desc_buff_remained_cnt)(struct ieee80211_hw *hw,
2192 u8 queue_index);
2193 void (*rx_check_dma_ok)(struct ieee80211_hw *hw, u8 *header_desc,
2194 u8 queue_index);
2195 void (*fill_tx_desc)(struct ieee80211_hw *hw,
2196 struct ieee80211_hdr *hdr, u8 *pdesc_tx,
2197 u8 *pbd_desc_tx,
2198 struct ieee80211_tx_info *info,
2199 struct ieee80211_sta *sta,
2200 struct sk_buff *skb, u8 hw_queue,
2201 struct rtl_tcb_desc *ptcb_desc);
2202 void (*fill_tx_cmddesc)(struct ieee80211_hw *hw, u8 *pdesc,
2203 struct sk_buff *skb);
2204 void (*fill_tx_special_desc)(struct ieee80211_hw *hw,
2205 u8 *pdesc, u8 *pbd_desc,
2206 struct sk_buff *skb, u8 hw_queue);
2207 bool (*query_rx_desc)(struct ieee80211_hw *hw,
2208 struct rtl_stats *stats,
2209 struct ieee80211_rx_status *rx_status,
2210 u8 *pdesc, struct sk_buff *skb);
2211 void (*set_channel_access)(struct ieee80211_hw *hw);
2212 bool (*radio_onoff_checking)(struct ieee80211_hw *hw, u8 *valid);
2213 void (*dm_watchdog)(struct ieee80211_hw *hw);
2214 void (*scan_operation_backup)(struct ieee80211_hw *hw, u8 operation);
2215 bool (*set_rf_power_state)(struct ieee80211_hw *hw,
2216 enum rf_pwrstate rfpwr_state);
2217 void (*led_control)(struct ieee80211_hw *hw,
2218 enum led_ctl_mode ledaction);
2219 void (*set_desc)(struct ieee80211_hw *hw, u8 *pdesc, bool istx,
2220 u8 desc_name, u8 *val);
2221 u64 (*get_desc)(struct ieee80211_hw *hw, u8 *pdesc, bool istx,
2222 u8 desc_name);
2223 bool (*is_tx_desc_closed)(struct ieee80211_hw *hw,
2224 u8 hw_queue, u16 index);
2225 void (*tx_polling)(struct ieee80211_hw *hw, u8 hw_queue);
2226 void (*enable_hw_sec)(struct ieee80211_hw *hw);
2227 void (*set_key)(struct ieee80211_hw *hw, u32 key_index,
2228 u8 *macaddr, bool is_group, u8 enc_algo,
2229 bool is_wepkey, bool clear_all);
2230 u32 (*get_bbreg)(struct ieee80211_hw *hw, u32 regaddr, u32 bitmask);
2231 void (*set_bbreg)(struct ieee80211_hw *hw, u32 regaddr, u32 bitmask,
2232 u32 data);
2233 u32 (*get_rfreg)(struct ieee80211_hw *hw, enum radio_path rfpath,
2234 u32 regaddr, u32 bitmask);
2235 void (*set_rfreg)(struct ieee80211_hw *hw, enum radio_path rfpath,
2236 u32 regaddr, u32 bitmask, u32 data);
2237 void (*linked_set_reg)(struct ieee80211_hw *hw);
2238 void (*dualmac_switch_to_dmdp)(struct ieee80211_hw *hw);
2239 bool (*phy_rf6052_config)(struct ieee80211_hw *hw);
2240 void (*phy_rf6052_set_cck_txpower)(struct ieee80211_hw *hw,
2241 u8 *powerlevel);
2242 void (*phy_rf6052_set_ofdm_txpower)(struct ieee80211_hw *hw,
2243 u8 *ppowerlevel, u8 channel);
2244 bool (*config_bb_with_headerfile)(struct ieee80211_hw *hw,
2245 u8 configtype);
2246 bool (*config_bb_with_pgheaderfile)(struct ieee80211_hw *hw,
2247 u8 configtype);
2248 void (*phy_lc_calibrate)(struct ieee80211_hw *hw, bool is2t);
2249 void (*phy_iq_calibrate)(struct ieee80211_hw *hw);
2250 void (*phy_set_bw_mode_callback)(struct ieee80211_hw *hw);
2251 void (*dm_dynamic_txpower)(struct ieee80211_hw *hw);
2252 void (*c2h_command_handle)(struct ieee80211_hw *hw);
2253 void (*bt_wifi_media_status_notify)(struct ieee80211_hw *hw,
2254 bool mstate);
2255 void (*bt_coex_off_before_lps)(struct ieee80211_hw *hw);
2256 void (*fill_h2c_cmd)(struct ieee80211_hw *hw, u8 element_id,
2257 u32 cmd_len, u8 *p_cmdbuffer);
2258 void (*set_default_port_id_cmd)(struct ieee80211_hw *hw);
2259 bool (*get_btc_status)(void);
2260 bool (*is_fw_header)(struct rtlwifi_firmware_header *hdr);
2261 void (*add_wowlan_pattern)(struct ieee80211_hw *hw,
2262 struct rtl_wow_pattern *rtl_pattern,
2263 u8 index);
2264 u16 (*get_available_desc)(struct ieee80211_hw *hw, u8 q_idx);
2265 void (*c2h_ra_report_handler)(struct ieee80211_hw *hw,
2266 u8 *cmd_buf, u8 cmd_len);
2267 };
2268
2269 struct rtl_intf_ops {
2270 /*com */
2271 int (*adapter_start)(struct ieee80211_hw *hw);
2272 void (*adapter_stop)(struct ieee80211_hw *hw);
2273
2274 int (*adapter_tx)(struct ieee80211_hw *hw,
2275 struct ieee80211_sta *sta,
2276 struct sk_buff *skb,
2277 struct rtl_tcb_desc *ptcb_desc);
2278 void (*flush)(struct ieee80211_hw *hw, u32 queues, bool drop);
2279 int (*reset_trx_ring)(struct ieee80211_hw *hw);
2280 bool (*waitq_insert)(struct ieee80211_hw *hw,
2281 struct ieee80211_sta *sta,
2282 struct sk_buff *skb);
2283
2284 /*pci */
2285 void (*disable_aspm)(struct ieee80211_hw *hw);
2286 void (*enable_aspm)(struct ieee80211_hw *hw);
2287
2288 /*usb */
2289 };
2290
2291 struct rtl_mod_params {
2292 /* default: 0,0 */
2293 u64 debug_mask;
2294 /* default: 0 = using hardware encryption */
2295 bool sw_crypto;
2296
2297 /* default: 0 = DBG_EMERG (0)*/
2298 int debug_level;
2299
2300 /* default: 1 = using no linked power save */
2301 bool inactiveps;
2302
2303 /* default: 1 = using linked sw power save */
2304 bool swctrl_lps;
2305
2306 /* default: 1 = using linked fw power save */
2307 bool fwctrl_lps;
2308
2309 /* default: 0 = not using MSI interrupts mode
2310 * submodules should set their own default value
2311 */
2312 bool msi_support;
2313
2314 /* default: 0 = dma 32 */
2315 bool dma64;
2316
2317 /* default: 1 = enable aspm */
2318 int aspm_support;
2319
2320 /* default 0: 1 means disable */
2321 bool disable_watchdog;
2322
2323 /* default 0: 1 means do not disable interrupts */
2324 bool int_clear;
2325
2326 /* select antenna */
2327 int ant_sel;
2328 };
2329
2330 struct rtl_hal_usbint_cfg {
2331 /* data - rx */
2332 u32 rx_urb_num;
2333 u32 rx_max_size;
2334
2335 /* op - rx */
2336 void (*usb_rx_hdl)(struct ieee80211_hw *, struct sk_buff *);
2337 void (*usb_rx_segregate_hdl)(struct ieee80211_hw *, struct sk_buff *,
2338 struct sk_buff_head *);
2339
2340 /* tx */
2341 void (*usb_tx_cleanup)(struct ieee80211_hw *, struct sk_buff *);
2342 int (*usb_tx_post_hdl)(struct ieee80211_hw *, struct urb *,
2343 struct sk_buff *);
2344 struct sk_buff *(*usb_tx_aggregate_hdl)(struct ieee80211_hw *,
2345 struct sk_buff_head *);
2346
2347 /* endpoint mapping */
2348 int (*usb_endpoint_mapping)(struct ieee80211_hw *hw);
2349 u16 (*usb_mq_to_hwq)(__le16 fc, u16 mac80211_queue_index);
2350 };
2351
2352 struct rtl_hal_cfg {
2353 u8 bar_id;
2354 bool write_readback;
2355 char *name;
2356 char *alt_fw_name;
2357 const struct rtl_hal_ops *ops;
2358 struct rtl_mod_params *mod_params;
2359 const struct rtl_hal_usbint_cfg *usb_interface_cfg;
2360 enum rtl_spec_ver spec_ver;
2361
2362 /*this map used for some registers or vars
2363 * defined int HAL but used in MAIN
2364 */
2365 u32 maps[RTL_VAR_MAP_MAX];
2366
2367 };
2368
2369 struct rtl_locks {
2370 /* mutex */
2371 struct mutex conf_mutex;
2372 struct mutex ips_mutex; /* mutex for enter/leave IPS */
2373 struct mutex lps_mutex; /* mutex for enter/leave LPS */
2374
2375 /*spin lock */
2376 spinlock_t irq_th_lock;
2377 spinlock_t h2c_lock;
2378 spinlock_t rf_ps_lock;
2379 spinlock_t rf_lock;
2380 spinlock_t waitq_lock;
2381 spinlock_t entry_list_lock;
2382 spinlock_t usb_lock;
2383 spinlock_t scan_list_lock; /* lock for the scan list */
2384
2385 /*FW clock change */
2386 spinlock_t fw_ps_lock;
2387
2388 /*Dual mac*/
2389 spinlock_t cck_and_rw_pagea_lock;
2390
2391 spinlock_t iqk_lock;
2392 };
2393
2394 struct rtl_works {
2395 struct ieee80211_hw *hw;
2396
2397 /*timer */
2398 struct timer_list watchdog_timer;
2399 struct timer_list fw_clockoff_timer;
2400 struct timer_list fast_antenna_training_timer;
2401 /*task */
2402 struct tasklet_struct irq_tasklet;
2403 struct tasklet_struct irq_prepare_bcn_tasklet;
2404
2405 /*work queue */
2406 struct workqueue_struct *rtl_wq;
2407 struct delayed_work watchdog_wq;
2408 struct delayed_work ips_nic_off_wq;
2409 struct delayed_work c2hcmd_wq;
2410
2411 /* For SW LPS */
2412 struct delayed_work ps_work;
2413 struct delayed_work ps_rfon_wq;
2414 struct delayed_work fwevt_wq;
2415
2416 struct work_struct lps_change_work;
2417 struct work_struct fill_h2c_cmd;
2418 struct work_struct update_beacon_work;
2419 };
2420
2421 struct rtl_debug {
2422 /* add for debug */
2423 struct dentry *debugfs_dir;
2424 char debugfs_name[20];
2425 };
2426
2427 #define MIMO_PS_STATIC 0
2428 #define MIMO_PS_DYNAMIC 1
2429 #define MIMO_PS_NOLIMIT 3
2430
2431 struct rtl_dmsp_ctl {
2432 bool activescan_for_slaveofdmsp;
2433 bool scan_for_anothermac_fordmsp;
2434 bool scan_for_itself_fordmsp;
2435 bool writedig_for_anothermacofdmsp;
2436 u32 curdigvalue_for_anothermacofdmsp;
2437 bool changecckpdstate_for_anothermacofdmsp;
2438 u8 curcckpdstate_for_anothermacofdmsp;
2439 bool changetxhighpowerlvl_for_anothermacofdmsp;
2440 u8 curtxhighlvl_for_anothermacofdmsp;
2441 long rssivalmin_for_anothermacofdmsp;
2442 };
2443
2444 struct ps_t {
2445 u8 pre_ccastate;
2446 u8 cur_ccasate;
2447 u8 pre_rfstate;
2448 u8 cur_rfstate;
2449 u8 initialize;
2450 long rssi_val_min;
2451 };
2452
2453 struct dig_t {
2454 u32 rssi_lowthresh;
2455 u32 rssi_highthresh;
2456 u32 fa_lowthresh;
2457 u32 fa_highthresh;
2458 long last_min_undec_pwdb_for_dm;
2459 long rssi_highpower_lowthresh;
2460 long rssi_highpower_highthresh;
2461 u32 recover_cnt;
2462 u32 pre_igvalue;
2463 u32 cur_igvalue;
2464 long rssi_val;
2465 u8 dig_enable_flag;
2466 u8 dig_ext_port_stage;
2467 u8 dig_algorithm;
2468 u8 dig_twoport_algorithm;
2469 u8 dig_dbgmode;
2470 u8 dig_slgorithm_switch;
2471 u8 cursta_cstate;
2472 u8 presta_cstate;
2473 u8 curmultista_cstate;
2474 u8 stop_dig;
2475 s8 back_val;
2476 s8 back_range_max;
2477 s8 back_range_min;
2478 u8 rx_gain_max;
2479 u8 rx_gain_min;
2480 u8 min_undec_pwdb_for_dm;
2481 u8 rssi_val_min;
2482 u8 pre_cck_cca_thres;
2483 u8 cur_cck_cca_thres;
2484 u8 pre_cck_pd_state;
2485 u8 cur_cck_pd_state;
2486 u8 pre_cck_fa_state;
2487 u8 cur_cck_fa_state;
2488 u8 pre_ccastate;
2489 u8 cur_ccasate;
2490 u8 large_fa_hit;
2491 u8 forbidden_igi;
2492 u8 dig_state;
2493 u8 dig_highpwrstate;
2494 u8 cur_sta_cstate;
2495 u8 pre_sta_cstate;
2496 u8 cur_ap_cstate;
2497 u8 pre_ap_cstate;
2498 u8 cur_pd_thstate;
2499 u8 pre_pd_thstate;
2500 u8 cur_cs_ratiostate;
2501 u8 pre_cs_ratiostate;
2502 u8 backoff_enable_flag;
2503 s8 backoffval_range_max;
2504 s8 backoffval_range_min;
2505 u8 dig_min_0;
2506 u8 dig_min_1;
2507 u8 bt30_cur_igi;
2508 bool media_connect_0;
2509 bool media_connect_1;
2510
2511 u32 antdiv_rssi_max;
2512 u32 rssi_max;
2513 };
2514
2515 #define IN_4WAY_TIMEOUT_TIME (30 * MSEC_PER_SEC) /* 30 seconds */
2516
2517 struct rtl_btc_info {
2518 u8 bt_type;
2519 u8 btcoexist;
2520 u8 ant_num;
2521 u8 single_ant_path;
2522
2523 u8 ap_num;
2524 bool in_4way;
2525 unsigned long in_4way_ts;
2526 };
2527
2528 struct bt_coexist_info {
2529 struct rtl_btc_ops *btc_ops;
2530 struct rtl_btc_info btc_info;
2531 /* btc context */
2532 void *btc_context;
2533 void *wifi_only_context;
2534 /* EEPROM BT info. */
2535 u8 eeprom_bt_coexist;
2536 u8 eeprom_bt_type;
2537 u8 eeprom_bt_ant_num;
2538 u8 eeprom_bt_ant_isol;
2539 u8 eeprom_bt_radio_shared;
2540
2541 u8 bt_coexistence;
2542 u8 bt_ant_num;
2543 u8 bt_coexist_type;
2544 u8 bt_state;
2545 u8 bt_cur_state; /* 0:on, 1:off */
2546 u8 bt_ant_isolation; /* 0:good, 1:bad */
2547 u8 bt_pape_ctrl; /* 0:SW, 1:SW/HW dynamic */
2548 u8 bt_service;
2549 u8 bt_radio_shared_type;
2550 u8 bt_rfreg_origin_1e;
2551 u8 bt_rfreg_origin_1f;
2552 u8 bt_rssi_state;
2553 u32 ratio_tx;
2554 u32 ratio_pri;
2555 u32 bt_edca_ul;
2556 u32 bt_edca_dl;
2557
2558 bool init_set;
2559 bool bt_busy_traffic;
2560 bool bt_traffic_mode_set;
2561 bool bt_non_traffic_mode_set;
2562
2563 bool fw_coexist_all_off;
2564 bool sw_coexist_all_off;
2565 bool hw_coexist_all_off;
2566 u32 cstate;
2567 u32 previous_state;
2568 u32 cstate_h;
2569 u32 previous_state_h;
2570
2571 u8 bt_pre_rssi_state;
2572 u8 bt_pre_rssi_state1;
2573
2574 u8 reg_bt_iso;
2575 u8 reg_bt_sco;
2576 bool balance_on;
2577 u8 bt_active_zero_cnt;
2578 bool cur_bt_disabled;
2579 bool pre_bt_disabled;
2580
2581 u8 bt_profile_case;
2582 u8 bt_profile_action;
2583 bool bt_busy;
2584 bool hold_for_bt_operation;
2585 u8 lps_counter;
2586 };
2587
2588 struct rtl_btc_ops {
2589 void (*btc_init_variables)(struct rtl_priv *rtlpriv);
2590 void (*btc_init_variables_wifi_only)(struct rtl_priv *rtlpriv);
2591 void (*btc_deinit_variables)(struct rtl_priv *rtlpriv);
2592 void (*btc_init_hal_vars)(struct rtl_priv *rtlpriv);
2593 void (*btc_power_on_setting)(struct rtl_priv *rtlpriv);
2594 void (*btc_init_hw_config)(struct rtl_priv *rtlpriv);
2595 void (*btc_init_hw_config_wifi_only)(struct rtl_priv *rtlpriv);
2596 void (*btc_ips_notify)(struct rtl_priv *rtlpriv, u8 type);
2597 void (*btc_lps_notify)(struct rtl_priv *rtlpriv, u8 type);
2598 void (*btc_scan_notify)(struct rtl_priv *rtlpriv, u8 scantype);
2599 void (*btc_scan_notify_wifi_only)(struct rtl_priv *rtlpriv,
2600 u8 scantype);
2601 void (*btc_connect_notify)(struct rtl_priv *rtlpriv, u8 action);
2602 void (*btc_mediastatus_notify)(struct rtl_priv *rtlpriv,
2603 enum rt_media_status mstatus);
2604 void (*btc_periodical)(struct rtl_priv *rtlpriv);
2605 void (*btc_halt_notify)(struct rtl_priv *rtlpriv);
2606 void (*btc_btinfo_notify)(struct rtl_priv *rtlpriv,
2607 u8 *tmp_buf, u8 length);
2608 void (*btc_btmpinfo_notify)(struct rtl_priv *rtlpriv,
2609 u8 *tmp_buf, u8 length);
2610 bool (*btc_is_limited_dig)(struct rtl_priv *rtlpriv);
2611 bool (*btc_is_disable_edca_turbo)(struct rtl_priv *rtlpriv);
2612 bool (*btc_is_bt_disabled)(struct rtl_priv *rtlpriv);
2613 void (*btc_special_packet_notify)(struct rtl_priv *rtlpriv,
2614 u8 pkt_type);
2615 void (*btc_switch_band_notify)(struct rtl_priv *rtlpriv, u8 type,
2616 bool scanning);
2617 void (*btc_switch_band_notify_wifi_only)(struct rtl_priv *rtlpriv,
2618 u8 type, bool scanning);
2619 void (*btc_display_bt_coex_info)(struct rtl_priv *rtlpriv,
2620 struct seq_file *m);
2621 void (*btc_record_pwr_mode)(struct rtl_priv *rtlpriv, u8 *buf, u8 len);
2622 u8 (*btc_get_lps_val)(struct rtl_priv *rtlpriv);
2623 u8 (*btc_get_rpwm_val)(struct rtl_priv *rtlpriv);
2624 bool (*btc_is_bt_ctrl_lps)(struct rtl_priv *rtlpriv);
2625 void (*btc_get_ampdu_cfg)(struct rtl_priv *rtlpriv, u8 *reject_agg,
2626 u8 *ctrl_agg_size, u8 *agg_size);
2627 bool (*btc_is_bt_lps_on)(struct rtl_priv *rtlpriv);
2628 };
2629
2630 struct proxim {
2631 bool proxim_on;
2632
2633 void *proximity_priv;
2634 int (*proxim_rx)(struct ieee80211_hw *hw, struct rtl_stats *status,
2635 struct sk_buff *skb);
2636 u8 (*proxim_get_var)(struct ieee80211_hw *hw, u8 type);
2637 };
2638
2639 struct rtl_c2hcmd {
2640 struct list_head list;
2641 u8 tag;
2642 u8 len;
2643 u8 *val;
2644 };
2645
2646 struct rtl_bssid_entry {
2647 struct list_head list;
2648 u8 bssid[ETH_ALEN];
2649 unsigned long age;
2650 };
2651
2652 struct rtl_scan_list {
2653 int num;
2654 struct list_head list; /* sort by age */
2655 };
2656
2657 struct rtl_priv {
2658 struct ieee80211_hw *hw;
2659 struct completion firmware_loading_complete;
2660 struct rtl_priv *buddy_priv;
2661 struct rtl_dmsp_ctl dmsp_ctl;
2662 struct rtl_locks locks;
2663 struct rtl_works works;
2664 struct rtl_mac mac80211;
2665 struct rtl_hal rtlhal;
2666 struct rtl_regulatory regd;
2667 struct rtl_rfkill rfkill;
2668 struct rtl_io io;
2669 struct rtl_phy phy;
2670 struct rtl_dm dm;
2671 struct rtl_security sec;
2672 struct rtl_efuse efuse;
2673 struct rtl_led_ctl ledctl;
2674 struct rtl_tx_report tx_report;
2675 struct rtl_scan_list scan_list;
2676
2677 struct rtl_ps_ctl psc;
2678 struct rate_adaptive ra;
2679 struct dynamic_primary_cca primarycca;
2680 struct wireless_stats stats;
2681 struct rt_link_detect link_info;
2682 struct false_alarm_statistics falsealm_cnt;
2683
2684 struct rtl_rate_priv *rate_priv;
2685
2686 /* sta entry list for ap adhoc or mesh */
2687 struct list_head entry_list;
2688
2689 /* c2hcmd list for kthread level access */
2690 struct sk_buff_head c2hcmd_queue;
2691
2692 struct rtl_debug dbg;
2693 int max_fw_size;
2694
2695 /* hal_cfg : for diff cards
2696 * intf_ops : for diff interrface usb/pcie
2697 */
2698 const struct rtl_hal_cfg *cfg;
2699 const struct rtl_intf_ops *intf_ops;
2700
2701 /* this var will be set by set_bit,
2702 * and was used to indicate status of
2703 * interface or hardware
2704 */
2705 unsigned long status;
2706
2707 /* tables for dm */
2708 struct dig_t dm_digtable;
2709 struct ps_t dm_pstable;
2710
2711 u32 reg_874;
2712 u32 reg_c70;
2713 u32 reg_85c;
2714 u32 reg_a74;
2715 bool reg_init; /* true if regs saved */
2716 bool bt_operation_on;
2717 __le32 *usb_data;
2718 int usb_data_index;
2719 bool initialized;
2720 bool enter_ps; /* true when entering PS */
2721 u8 rate_mask[5];
2722
2723 /* intel Proximity, should be alloc mem
2724 * in intel Proximity module and can only
2725 * be used in intel Proximity mode
2726 */
2727 struct proxim proximity;
2728
2729 /*for bt coexist use*/
2730 struct bt_coexist_info btcoexist;
2731
2732 /* separate 92ee from other ICs,
2733 * 92ee use new trx flow.
2734 */
2735 bool use_new_trx_flow;
2736
2737 /* For dual MAC RTL8192DU, things shared by the 2 USB interfaces */
2738 u32 *curveindex_2g;
2739 u32 *curveindex_5g;
2740 struct mutex *mutex_for_power_on_off; /* for power on/off */
2741 struct mutex *mutex_for_hw_init; /* for hardware init */
2742
2743 #ifdef CONFIG_PM
2744 struct wiphy_wowlan_support wowlan;
2745 #endif
2746 /* This must be the last item so
2747 * that it points to the data allocated
2748 * beyond this structure like:
2749 * rtl_pci_priv or rtl_usb_priv
2750 */
2751 u8 priv[] __aligned(sizeof(void *));
2752 };
2753
2754 #define rtl_priv(hw) (((struct rtl_priv *)(hw)->priv))
2755 #define rtl_mac(rtlpriv) (&((rtlpriv)->mac80211))
2756 #define rtl_hal(rtlpriv) (&((rtlpriv)->rtlhal))
2757 #define rtl_efuse(rtlpriv) (&((rtlpriv)->efuse))
2758 #define rtl_psc(rtlpriv) (&((rtlpriv)->psc))
2759
2760 /* Bluetooth Co-existence Related */
2761
2762 enum bt_ant_num {
2763 ANT_X2 = 0,
2764 ANT_X1 = 1,
2765 };
2766
2767 enum bt_ant_path {
2768 ANT_MAIN = 0,
2769 ANT_AUX = 1,
2770 };
2771
2772 enum bt_co_type {
2773 BT_2WIRE = 0,
2774 BT_ISSC_3WIRE = 1,
2775 BT_ACCEL = 2,
2776 BT_CSR_BC4 = 3,
2777 BT_CSR_BC8 = 4,
2778 BT_RTL8756 = 5,
2779 BT_RTL8723A = 6,
2780 BT_RTL8821A = 7,
2781 BT_RTL8723B = 8,
2782 BT_RTL8192E = 9,
2783 BT_RTL8812A = 11,
2784 };
2785
2786 enum bt_cur_state {
2787 BT_OFF = 0,
2788 BT_ON = 1,
2789 };
2790
2791 enum bt_service_type {
2792 BT_SCO = 0,
2793 BT_A2DP = 1,
2794 BT_HID = 2,
2795 BT_HID_IDLE = 3,
2796 BT_SCAN = 4,
2797 BT_IDLE = 5,
2798 BT_OTHER_ACTION = 6,
2799 BT_BUSY = 7,
2800 BT_OTHERBUSY = 8,
2801 BT_PAN = 9,
2802 };
2803
2804 enum bt_radio_shared {
2805 BT_RADIO_SHARED = 0,
2806 BT_RADIO_INDIVIDUAL = 1,
2807 };
2808
2809 /****************************************
2810 * mem access macro define start
2811 * Call endian free function when
2812 * 1. Read/write packet content.
2813 * 2. Before write integer to IO.
2814 * 3. After read integer from IO.
2815 ****************************************/
2816
2817 #define N_BYTE_ALIGMENT(__value, __aligment) ((__aligment == 1) ? \
2818 (__value) : (((__value + __aligment - 1) / __aligment) * __aligment))
2819
2820 /* mem access macro define end */
2821
2822 #define byte(x, n) ((x >> (8 * n)) & 0xff)
2823
2824 #define packet_get_type(_packet) (EF1BYTE((_packet).octet[0]) & 0xFC)
2825 #define RTL_WATCH_DOG_TIME 2000
2826 #define MSECS(t) msecs_to_jiffies(t)
2827 #define WLAN_FC_GET_VERS(fc) (le16_to_cpu(fc) & IEEE80211_FCTL_VERS)
2828 #define WLAN_FC_GET_TYPE(fc) (le16_to_cpu(fc) & IEEE80211_FCTL_FTYPE)
2829 #define WLAN_FC_GET_STYPE(fc) (le16_to_cpu(fc) & IEEE80211_FCTL_STYPE)
2830 #define WLAN_FC_MORE_DATA(fc) (le16_to_cpu(fc) & IEEE80211_FCTL_MOREDATA)
2831 #define rtl_dm(rtlpriv) (&((rtlpriv)->dm))
2832
2833 #define RT_RF_OFF_LEVL_ASPM BIT(0) /*PCI ASPM */
2834 #define RT_RF_OFF_LEVL_CLK_REQ BIT(1) /*PCI clock request */
2835 #define RT_RF_OFF_LEVL_PCI_D3 BIT(2) /*PCI D3 mode */
2836 /*NIC halt, re-initialize hw parameters*/
2837 #define RT_RF_OFF_LEVL_HALT_NIC BIT(3)
2838 #define RT_RF_OFF_LEVL_FREE_FW BIT(4) /*FW free, re-download the FW */
2839 #define RT_RF_OFF_LEVL_FW_32K BIT(5) /*FW in 32k */
2840 /*Always enable ASPM and Clock Req in initialization.*/
2841 #define RT_RF_PS_LEVEL_ALWAYS_ASPM BIT(6)
2842 /* no matter RFOFF or SLEEP we set PS_ASPM_LEVL*/
2843 #define RT_PS_LEVEL_ASPM BIT(7)
2844 /*When LPS is on, disable 2R if no packet is received or transmittd.*/
2845 #define RT_RF_LPS_DISALBE_2R BIT(30)
2846 #define RT_RF_LPS_LEVEL_ASPM BIT(31) /*LPS with ASPM */
2847 #define RT_IN_PS_LEVEL(ppsc, _ps_flg) \
2848 ((ppsc->cur_ps_level & _ps_flg) ? true : false)
2849 #define RT_CLEAR_PS_LEVEL(ppsc, _ps_flg) \
2850 (ppsc->cur_ps_level &= (~(_ps_flg)))
2851 #define RT_SET_PS_LEVEL(ppsc, _ps_flg) \
2852 (ppsc->cur_ps_level |= _ps_flg)
2853
2854 #define FILL_OCTET_STRING(_os, _octet, _len) \
2855 (_os).octet = (u8 *)(_octet); \
2856 (_os).length = (_len);
2857
2858 #define CP_MACADDR(des, src) \
2859 ((des)[0] = (src)[0], (des)[1] = (src)[1],\
2860 (des)[2] = (src)[2], (des)[3] = (src)[3],\
2861 (des)[4] = (src)[4], (des)[5] = (src)[5])
2862
2863 #define LDPC_HT_ENABLE_RX BIT(0)
2864 #define LDPC_HT_ENABLE_TX BIT(1)
2865 #define LDPC_HT_TEST_TX_ENABLE BIT(2)
2866 #define LDPC_HT_CAP_TX BIT(3)
2867
2868 #define STBC_HT_ENABLE_RX BIT(0)
2869 #define STBC_HT_ENABLE_TX BIT(1)
2870 #define STBC_HT_TEST_TX_ENABLE BIT(2)
2871 #define STBC_HT_CAP_TX BIT(3)
2872
2873 #define LDPC_VHT_ENABLE_RX BIT(0)
2874 #define LDPC_VHT_ENABLE_TX BIT(1)
2875 #define LDPC_VHT_TEST_TX_ENABLE BIT(2)
2876 #define LDPC_VHT_CAP_TX BIT(3)
2877
2878 #define STBC_VHT_ENABLE_RX BIT(0)
2879 #define STBC_VHT_ENABLE_TX BIT(1)
2880 #define STBC_VHT_TEST_TX_ENABLE BIT(2)
2881 #define STBC_VHT_CAP_TX BIT(3)
2882
2883 extern u8 channel5g[CHANNEL_MAX_NUMBER_5G];
2884
2885 extern u8 channel5g_80m[CHANNEL_MAX_NUMBER_5G_80M];
2886
rtl_read_byte(struct rtl_priv * rtlpriv,u32 addr)2887 static inline u8 rtl_read_byte(struct rtl_priv *rtlpriv, u32 addr)
2888 {
2889 return rtlpriv->io.read8(rtlpriv, addr);
2890 }
2891
rtl_read_word(struct rtl_priv * rtlpriv,u32 addr)2892 static inline u16 rtl_read_word(struct rtl_priv *rtlpriv, u32 addr)
2893 {
2894 return rtlpriv->io.read16(rtlpriv, addr);
2895 }
2896
rtl_read_dword(struct rtl_priv * rtlpriv,u32 addr)2897 static inline u32 rtl_read_dword(struct rtl_priv *rtlpriv, u32 addr)
2898 {
2899 return rtlpriv->io.read32(rtlpriv, addr);
2900 }
2901
rtl_write_byte(struct rtl_priv * rtlpriv,u32 addr,u8 val8)2902 static inline void rtl_write_byte(struct rtl_priv *rtlpriv, u32 addr, u8 val8)
2903 {
2904 rtlpriv->io.write8(rtlpriv, addr, val8);
2905
2906 if (rtlpriv->cfg->write_readback)
2907 rtlpriv->io.read8(rtlpriv, addr);
2908 }
2909
rtl_write_byte_with_val32(struct ieee80211_hw * hw,u32 addr,u32 val8)2910 static inline void rtl_write_byte_with_val32(struct ieee80211_hw *hw,
2911 u32 addr, u32 val8)
2912 {
2913 struct rtl_priv *rtlpriv = rtl_priv(hw);
2914
2915 rtl_write_byte(rtlpriv, addr, (u8)val8);
2916 }
2917
rtl_write_word(struct rtl_priv * rtlpriv,u32 addr,u16 val16)2918 static inline void rtl_write_word(struct rtl_priv *rtlpriv, u32 addr, u16 val16)
2919 {
2920 rtlpriv->io.write16(rtlpriv, addr, val16);
2921
2922 if (rtlpriv->cfg->write_readback)
2923 rtlpriv->io.read16(rtlpriv, addr);
2924 }
2925
rtl_write_dword(struct rtl_priv * rtlpriv,u32 addr,u32 val32)2926 static inline void rtl_write_dword(struct rtl_priv *rtlpriv,
2927 u32 addr, u32 val32)
2928 {
2929 rtlpriv->io.write32(rtlpriv, addr, val32);
2930
2931 if (rtlpriv->cfg->write_readback)
2932 rtlpriv->io.read32(rtlpriv, addr);
2933 }
2934
rtl_write_chunk(struct rtl_priv * rtlpriv,u32 addr,u32 length,u8 * data)2935 static inline void rtl_write_chunk(struct rtl_priv *rtlpriv,
2936 u32 addr, u32 length, u8 *data)
2937 {
2938 rtlpriv->io.write_chunk(rtlpriv, addr, length, data);
2939 }
2940
rtl_get_bbreg(struct ieee80211_hw * hw,u32 regaddr,u32 bitmask)2941 static inline u32 rtl_get_bbreg(struct ieee80211_hw *hw,
2942 u32 regaddr, u32 bitmask)
2943 {
2944 struct rtl_priv *rtlpriv = hw->priv;
2945
2946 return rtlpriv->cfg->ops->get_bbreg(hw, regaddr, bitmask);
2947 }
2948
rtl_set_bbreg(struct ieee80211_hw * hw,u32 regaddr,u32 bitmask,u32 data)2949 static inline void rtl_set_bbreg(struct ieee80211_hw *hw, u32 regaddr,
2950 u32 bitmask, u32 data)
2951 {
2952 struct rtl_priv *rtlpriv = hw->priv;
2953
2954 rtlpriv->cfg->ops->set_bbreg(hw, regaddr, bitmask, data);
2955 }
2956
rtl_set_bbreg_with_dwmask(struct ieee80211_hw * hw,u32 regaddr,u32 data)2957 static inline void rtl_set_bbreg_with_dwmask(struct ieee80211_hw *hw,
2958 u32 regaddr, u32 data)
2959 {
2960 rtl_set_bbreg(hw, regaddr, 0xffffffff, data);
2961 }
2962
rtl_get_rfreg(struct ieee80211_hw * hw,enum radio_path rfpath,u32 regaddr,u32 bitmask)2963 static inline u32 rtl_get_rfreg(struct ieee80211_hw *hw,
2964 enum radio_path rfpath, u32 regaddr,
2965 u32 bitmask)
2966 {
2967 struct rtl_priv *rtlpriv = hw->priv;
2968
2969 return rtlpriv->cfg->ops->get_rfreg(hw, rfpath, regaddr, bitmask);
2970 }
2971
rtl_set_rfreg(struct ieee80211_hw * hw,enum radio_path rfpath,u32 regaddr,u32 bitmask,u32 data)2972 static inline void rtl_set_rfreg(struct ieee80211_hw *hw,
2973 enum radio_path rfpath, u32 regaddr,
2974 u32 bitmask, u32 data)
2975 {
2976 struct rtl_priv *rtlpriv = hw->priv;
2977
2978 rtlpriv->cfg->ops->set_rfreg(hw, rfpath, regaddr, bitmask, data);
2979 }
2980
is_hal_stop(struct rtl_hal * rtlhal)2981 static inline bool is_hal_stop(struct rtl_hal *rtlhal)
2982 {
2983 return (_HAL_STATE_STOP == rtlhal->state);
2984 }
2985
set_hal_start(struct rtl_hal * rtlhal)2986 static inline void set_hal_start(struct rtl_hal *rtlhal)
2987 {
2988 rtlhal->state = _HAL_STATE_START;
2989 }
2990
set_hal_stop(struct rtl_hal * rtlhal)2991 static inline void set_hal_stop(struct rtl_hal *rtlhal)
2992 {
2993 rtlhal->state = _HAL_STATE_STOP;
2994 }
2995
get_rf_type(struct rtl_phy * rtlphy)2996 static inline u8 get_rf_type(struct rtl_phy *rtlphy)
2997 {
2998 return rtlphy->rf_type;
2999 }
3000
rtl_get_hdr(struct sk_buff * skb)3001 static inline struct ieee80211_hdr *rtl_get_hdr(struct sk_buff *skb)
3002 {
3003 return (struct ieee80211_hdr *)(skb->data);
3004 }
3005
rtl_get_fc(struct sk_buff * skb)3006 static inline __le16 rtl_get_fc(struct sk_buff *skb)
3007 {
3008 return rtl_get_hdr(skb)->frame_control;
3009 }
3010
rtl_get_tid(struct sk_buff * skb)3011 static inline u16 rtl_get_tid(struct sk_buff *skb)
3012 {
3013 return ieee80211_get_tid(rtl_get_hdr(skb));
3014 }
3015
get_sta(struct ieee80211_hw * hw,struct ieee80211_vif * vif,const u8 * bssid)3016 static inline struct ieee80211_sta *get_sta(struct ieee80211_hw *hw,
3017 struct ieee80211_vif *vif,
3018 const u8 *bssid)
3019 {
3020 return ieee80211_find_sta(vif, bssid);
3021 }
3022
rtl_find_sta(struct ieee80211_hw * hw,u8 * mac_addr)3023 static inline struct ieee80211_sta *rtl_find_sta(struct ieee80211_hw *hw,
3024 u8 *mac_addr)
3025 {
3026 struct rtl_mac *mac = rtl_mac(rtl_priv(hw));
3027
3028 return ieee80211_find_sta(mac->vif, mac_addr);
3029 }
3030
calculate_bit_shift(u32 bitmask)3031 static inline u32 calculate_bit_shift(u32 bitmask)
3032 {
3033 if (WARN_ON_ONCE(!bitmask))
3034 return 0;
3035
3036 return __ffs(bitmask);
3037 }
3038 #endif
3039