1 /* SPDX-License-Identifier: GPL-2.0 */
2 /* Marvell RVU Admin Function driver
3 *
4 * Copyright (C) 2018 Marvell.
5 *
6 */
7
8 #ifndef MBOX_H
9 #define MBOX_H
10
11 #include <linux/etherdevice.h>
12 #include <linux/sizes.h>
13
14 #include "rvu_struct.h"
15 #include "common.h"
16
17 #define MBOX_SIZE SZ_64K
18
19 /* AF/PF: PF initiated, PF/VF VF initiated */
20 #define MBOX_DOWN_RX_START 0
21 #define MBOX_DOWN_RX_SIZE (46 * SZ_1K)
22 #define MBOX_DOWN_TX_START (MBOX_DOWN_RX_START + MBOX_DOWN_RX_SIZE)
23 #define MBOX_DOWN_TX_SIZE (16 * SZ_1K)
24 /* AF/PF: AF initiated, PF/VF PF initiated */
25 #define MBOX_UP_RX_START (MBOX_DOWN_TX_START + MBOX_DOWN_TX_SIZE)
26 #define MBOX_UP_RX_SIZE SZ_1K
27 #define MBOX_UP_TX_START (MBOX_UP_RX_START + MBOX_UP_RX_SIZE)
28 #define MBOX_UP_TX_SIZE SZ_1K
29
30 #if MBOX_UP_TX_SIZE + MBOX_UP_TX_START != MBOX_SIZE
31 # error "incorrect mailbox area sizes"
32 #endif
33
34 #define INTR_MASK(pfvfs) ((pfvfs < 64) ? (BIT_ULL(pfvfs) - 1) : (~0ull))
35
36 #define MBOX_RSP_TIMEOUT 6000 /* Time(ms) to wait for mbox response */
37
38 #define MBOX_MSG_ALIGN 16 /* Align mbox msg start to 16bytes */
39
40 /* Mailbox directions */
41 #define MBOX_DIR_AFPF 0 /* AF replies to PF */
42 #define MBOX_DIR_PFAF 1 /* PF sends messages to AF */
43 #define MBOX_DIR_PFVF 2 /* PF replies to VF */
44 #define MBOX_DIR_VFPF 3 /* VF sends messages to PF */
45 #define MBOX_DIR_AFPF_UP 4 /* AF sends messages to PF */
46 #define MBOX_DIR_PFAF_UP 5 /* PF replies to AF */
47 #define MBOX_DIR_PFVF_UP 6 /* PF sends messages to VF */
48 #define MBOX_DIR_VFPF_UP 7 /* VF replies to PF */
49
50 struct otx2_mbox_dev {
51 void *mbase; /* This dev's mbox region */
52 void *hwbase;
53 spinlock_t mbox_lock;
54 u16 msg_size; /* Total msg size to be sent */
55 u16 rsp_size; /* Total rsp size to be sure the reply is ok */
56 u16 num_msgs; /* No of msgs sent or waiting for response */
57 u16 msgs_acked; /* No of msgs for which response is received */
58 };
59
60 struct otx2_mbox {
61 struct pci_dev *pdev;
62 void *hwbase; /* Mbox region advertised by HW */
63 void *reg_base;/* CSR base for this dev */
64 u64 trigger; /* Trigger mbox notification */
65 u16 tr_shift; /* Mbox trigger shift */
66 u64 rx_start; /* Offset of Rx region in mbox memory */
67 u64 tx_start; /* Offset of Tx region in mbox memory */
68 u16 rx_size; /* Size of Rx region */
69 u16 tx_size; /* Size of Tx region */
70 u16 ndevs; /* The number of peers */
71 struct otx2_mbox_dev *dev;
72 };
73
74 /* Header which precedes all mbox messages */
75 struct mbox_hdr {
76 u64 msg_size; /* Total msgs size embedded */
77 u16 num_msgs; /* No of msgs embedded */
78 };
79
80 /* Header which precedes every msg and is also part of it */
81 struct mbox_msghdr {
82 u16 pcifunc; /* Who's sending this msg */
83 u16 id; /* Mbox message ID */
84 #define OTX2_MBOX_REQ_SIG (0xdead)
85 #define OTX2_MBOX_RSP_SIG (0xbeef)
86 u16 sig; /* Signature, for validating corrupted msgs */
87 #define OTX2_MBOX_VERSION (0x000a)
88 u16 ver; /* Version of msg's structure for this ID */
89 u16 next_msgoff; /* Offset of next msg within mailbox region */
90 int rc; /* Msg process'ed response code */
91 };
92
93 void otx2_mbox_reset(struct otx2_mbox *mbox, int devid);
94 void __otx2_mbox_reset(struct otx2_mbox *mbox, int devid);
95 void otx2_mbox_destroy(struct otx2_mbox *mbox);
96 int otx2_mbox_init(struct otx2_mbox *mbox, void __force *hwbase,
97 struct pci_dev *pdev, void __force *reg_base,
98 int direction, int ndevs);
99
100 int otx2_mbox_regions_init(struct otx2_mbox *mbox, void __force **hwbase,
101 struct pci_dev *pdev, void __force *reg_base,
102 int direction, int ndevs, unsigned long *bmap);
103 void otx2_mbox_msg_send(struct otx2_mbox *mbox, int devid);
104 int otx2_mbox_wait_for_rsp(struct otx2_mbox *mbox, int devid);
105 int otx2_mbox_busy_poll_for_rsp(struct otx2_mbox *mbox, int devid);
106 struct mbox_msghdr *otx2_mbox_alloc_msg_rsp(struct otx2_mbox *mbox, int devid,
107 int size, int size_rsp);
108 struct mbox_msghdr *otx2_mbox_get_rsp(struct otx2_mbox *mbox, int devid,
109 struct mbox_msghdr *msg);
110 int otx2_mbox_check_rsp_msgs(struct otx2_mbox *mbox, int devid);
111 int otx2_reply_invalid_msg(struct otx2_mbox *mbox, int devid,
112 u16 pcifunc, u16 id);
113 bool otx2_mbox_nonempty(struct otx2_mbox *mbox, int devid);
114 const char *otx2_mbox_id2name(u16 id);
otx2_mbox_alloc_msg(struct otx2_mbox * mbox,int devid,int size)115 static inline struct mbox_msghdr *otx2_mbox_alloc_msg(struct otx2_mbox *mbox,
116 int devid, int size)
117 {
118 return otx2_mbox_alloc_msg_rsp(mbox, devid, size, 0);
119 }
120
121 /* Mailbox message types */
122 #define MBOX_MSG_MASK 0xFFFF
123 #define MBOX_MSG_INVALID 0xFFFE
124 #define MBOX_MSG_MAX 0xFFFF
125
126 #define MBOX_MESSAGES \
127 /* Generic mbox IDs (range 0x000 - 0x1FF) */ \
128 M(READY, 0x001, ready, msg_req, ready_msg_rsp) \
129 M(ATTACH_RESOURCES, 0x002, attach_resources, rsrc_attach, msg_rsp) \
130 M(DETACH_RESOURCES, 0x003, detach_resources, rsrc_detach, msg_rsp) \
131 M(FREE_RSRC_CNT, 0x004, free_rsrc_cnt, msg_req, free_rsrcs_rsp) \
132 M(MSIX_OFFSET, 0x005, msix_offset, msg_req, msix_offset_rsp) \
133 M(VF_FLR, 0x006, vf_flr, msg_req, msg_rsp) \
134 M(PTP_OP, 0x007, ptp_op, ptp_req, ptp_rsp) \
135 M(GET_HW_CAP, 0x008, get_hw_cap, msg_req, get_hw_cap_rsp) \
136 M(LMTST_TBL_SETUP, 0x00a, lmtst_tbl_setup, lmtst_tbl_setup_req, \
137 msg_rsp) \
138 M(SET_VF_PERM, 0x00b, set_vf_perm, set_vf_perm, msg_rsp) \
139 M(PTP_GET_CAP, 0x00c, ptp_get_cap, msg_req, ptp_get_cap_rsp) \
140 /* CGX mbox IDs (range 0x200 - 0x3FF) */ \
141 M(CGX_START_RXTX, 0x200, cgx_start_rxtx, msg_req, msg_rsp) \
142 M(CGX_STOP_RXTX, 0x201, cgx_stop_rxtx, msg_req, msg_rsp) \
143 M(CGX_STATS, 0x202, cgx_stats, msg_req, cgx_stats_rsp) \
144 M(CGX_MAC_ADDR_SET, 0x203, cgx_mac_addr_set, cgx_mac_addr_set_or_get, \
145 cgx_mac_addr_set_or_get) \
146 M(CGX_MAC_ADDR_GET, 0x204, cgx_mac_addr_get, cgx_mac_addr_set_or_get, \
147 cgx_mac_addr_set_or_get) \
148 M(CGX_PROMISC_ENABLE, 0x205, cgx_promisc_enable, msg_req, msg_rsp) \
149 M(CGX_PROMISC_DISABLE, 0x206, cgx_promisc_disable, msg_req, msg_rsp) \
150 M(CGX_START_LINKEVENTS, 0x207, cgx_start_linkevents, msg_req, msg_rsp) \
151 M(CGX_STOP_LINKEVENTS, 0x208, cgx_stop_linkevents, msg_req, msg_rsp) \
152 M(CGX_GET_LINKINFO, 0x209, cgx_get_linkinfo, msg_req, cgx_link_info_msg) \
153 M(CGX_INTLBK_ENABLE, 0x20A, cgx_intlbk_enable, msg_req, msg_rsp) \
154 M(CGX_INTLBK_DISABLE, 0x20B, cgx_intlbk_disable, msg_req, msg_rsp) \
155 M(CGX_PTP_RX_ENABLE, 0x20C, cgx_ptp_rx_enable, msg_req, msg_rsp) \
156 M(CGX_PTP_RX_DISABLE, 0x20D, cgx_ptp_rx_disable, msg_req, msg_rsp) \
157 M(CGX_CFG_PAUSE_FRM, 0x20E, cgx_cfg_pause_frm, cgx_pause_frm_cfg, \
158 cgx_pause_frm_cfg) \
159 M(CGX_FW_DATA_GET, 0x20F, cgx_get_aux_link_info, msg_req, cgx_fw_data) \
160 M(CGX_FEC_SET, 0x210, cgx_set_fec_param, fec_mode, fec_mode) \
161 M(CGX_MAC_ADDR_ADD, 0x211, cgx_mac_addr_add, cgx_mac_addr_add_req, \
162 cgx_mac_addr_add_rsp) \
163 M(CGX_MAC_ADDR_DEL, 0x212, cgx_mac_addr_del, cgx_mac_addr_del_req, \
164 msg_rsp) \
165 M(CGX_MAC_MAX_ENTRIES_GET, 0x213, cgx_mac_max_entries_get, msg_req, \
166 cgx_max_dmac_entries_get_rsp) \
167 M(CGX_FEC_STATS, 0x217, cgx_fec_stats, msg_req, cgx_fec_stats_rsp) \
168 M(CGX_SET_LINK_MODE, 0x218, cgx_set_link_mode, cgx_set_link_mode_req,\
169 cgx_set_link_mode_rsp) \
170 M(CGX_GET_PHY_FEC_STATS, 0x219, cgx_get_phy_fec_stats, msg_req, msg_rsp) \
171 M(CGX_FEATURES_GET, 0x21B, cgx_features_get, msg_req, \
172 cgx_features_info_msg) \
173 M(RPM_STATS, 0x21C, rpm_stats, msg_req, rpm_stats_rsp) \
174 M(CGX_MAC_ADDR_RESET, 0x21D, cgx_mac_addr_reset, cgx_mac_addr_reset_req, \
175 msg_rsp) \
176 M(CGX_MAC_ADDR_UPDATE, 0x21E, cgx_mac_addr_update, cgx_mac_addr_update_req, \
177 cgx_mac_addr_update_rsp) \
178 M(CGX_PRIO_FLOW_CTRL_CFG, 0x21F, cgx_prio_flow_ctrl_cfg, cgx_pfc_cfg, \
179 cgx_pfc_rsp) \
180 /* NPA mbox IDs (range 0x400 - 0x5FF) */ \
181 M(NPA_LF_ALLOC, 0x400, npa_lf_alloc, \
182 npa_lf_alloc_req, npa_lf_alloc_rsp) \
183 M(NPA_LF_FREE, 0x401, npa_lf_free, msg_req, msg_rsp) \
184 M(NPA_AQ_ENQ, 0x402, npa_aq_enq, npa_aq_enq_req, npa_aq_enq_rsp) \
185 M(NPA_HWCTX_DISABLE, 0x403, npa_hwctx_disable, hwctx_disable_req, msg_rsp)\
186 /* SSO/SSOW mbox IDs (range 0x600 - 0x7FF) */ \
187 /* TIM mbox IDs (range 0x800 - 0x9FF) */ \
188 /* CPT mbox IDs (range 0xA00 - 0xBFF) */ \
189 M(CPT_LF_ALLOC, 0xA00, cpt_lf_alloc, cpt_lf_alloc_req_msg, \
190 msg_rsp) \
191 M(CPT_LF_FREE, 0xA01, cpt_lf_free, msg_req, msg_rsp) \
192 M(CPT_RD_WR_REGISTER, 0xA02, cpt_rd_wr_register, cpt_rd_wr_reg_msg, \
193 cpt_rd_wr_reg_msg) \
194 M(CPT_INLINE_IPSEC_CFG, 0xA04, cpt_inline_ipsec_cfg, \
195 cpt_inline_ipsec_cfg_msg, msg_rsp) \
196 M(CPT_STATS, 0xA05, cpt_sts, cpt_sts_req, cpt_sts_rsp) \
197 M(CPT_RXC_TIME_CFG, 0xA06, cpt_rxc_time_cfg, cpt_rxc_time_cfg_req, \
198 msg_rsp) \
199 M(CPT_CTX_CACHE_SYNC, 0xA07, cpt_ctx_cache_sync, msg_req, msg_rsp) \
200 M(CPT_LF_RESET, 0xA08, cpt_lf_reset, cpt_lf_rst_req, msg_rsp) \
201 M(CPT_FLT_ENG_INFO, 0xA09, cpt_flt_eng_info, cpt_flt_eng_info_req, \
202 cpt_flt_eng_info_rsp) \
203 /* SDP mbox IDs (range 0x1000 - 0x11FF) */ \
204 M(SET_SDP_CHAN_INFO, 0x1000, set_sdp_chan_info, sdp_chan_info_msg, msg_rsp) \
205 M(GET_SDP_CHAN_INFO, 0x1001, get_sdp_chan_info, msg_req, sdp_get_chan_info_msg) \
206 /* NPC mbox IDs (range 0x6000 - 0x7FFF) */ \
207 M(NPC_MCAM_ALLOC_ENTRY, 0x6000, npc_mcam_alloc_entry, npc_mcam_alloc_entry_req,\
208 npc_mcam_alloc_entry_rsp) \
209 M(NPC_MCAM_FREE_ENTRY, 0x6001, npc_mcam_free_entry, \
210 npc_mcam_free_entry_req, msg_rsp) \
211 M(NPC_MCAM_WRITE_ENTRY, 0x6002, npc_mcam_write_entry, \
212 npc_mcam_write_entry_req, msg_rsp) \
213 M(NPC_MCAM_ENA_ENTRY, 0x6003, npc_mcam_ena_entry, \
214 npc_mcam_ena_dis_entry_req, msg_rsp) \
215 M(NPC_MCAM_DIS_ENTRY, 0x6004, npc_mcam_dis_entry, \
216 npc_mcam_ena_dis_entry_req, msg_rsp) \
217 M(NPC_MCAM_SHIFT_ENTRY, 0x6005, npc_mcam_shift_entry, npc_mcam_shift_entry_req,\
218 npc_mcam_shift_entry_rsp) \
219 M(NPC_MCAM_ALLOC_COUNTER, 0x6006, npc_mcam_alloc_counter, \
220 npc_mcam_alloc_counter_req, \
221 npc_mcam_alloc_counter_rsp) \
222 M(NPC_MCAM_FREE_COUNTER, 0x6007, npc_mcam_free_counter, \
223 npc_mcam_oper_counter_req, msg_rsp) \
224 M(NPC_MCAM_UNMAP_COUNTER, 0x6008, npc_mcam_unmap_counter, \
225 npc_mcam_unmap_counter_req, msg_rsp) \
226 M(NPC_MCAM_CLEAR_COUNTER, 0x6009, npc_mcam_clear_counter, \
227 npc_mcam_oper_counter_req, msg_rsp) \
228 M(NPC_MCAM_COUNTER_STATS, 0x600a, npc_mcam_counter_stats, \
229 npc_mcam_oper_counter_req, \
230 npc_mcam_oper_counter_rsp) \
231 M(NPC_MCAM_ALLOC_AND_WRITE_ENTRY, 0x600b, npc_mcam_alloc_and_write_entry, \
232 npc_mcam_alloc_and_write_entry_req, \
233 npc_mcam_alloc_and_write_entry_rsp) \
234 M(NPC_GET_KEX_CFG, 0x600c, npc_get_kex_cfg, \
235 msg_req, npc_get_kex_cfg_rsp) \
236 M(NPC_INSTALL_FLOW, 0x600d, npc_install_flow, \
237 npc_install_flow_req, npc_install_flow_rsp) \
238 M(NPC_DELETE_FLOW, 0x600e, npc_delete_flow, \
239 npc_delete_flow_req, npc_delete_flow_rsp) \
240 M(NPC_MCAM_READ_ENTRY, 0x600f, npc_mcam_read_entry, \
241 npc_mcam_read_entry_req, \
242 npc_mcam_read_entry_rsp) \
243 M(NPC_SET_PKIND, 0x6010, npc_set_pkind, \
244 npc_set_pkind, msg_rsp) \
245 M(NPC_MCAM_READ_BASE_RULE, 0x6011, npc_read_base_steer_rule, \
246 msg_req, npc_mcam_read_base_rule_rsp) \
247 M(NPC_MCAM_GET_STATS, 0x6012, npc_mcam_entry_stats, \
248 npc_mcam_get_stats_req, \
249 npc_mcam_get_stats_rsp) \
250 M(NPC_GET_FIELD_HASH_INFO, 0x6013, npc_get_field_hash_info, \
251 npc_get_field_hash_info_req, \
252 npc_get_field_hash_info_rsp) \
253 M(NPC_GET_FIELD_STATUS, 0x6014, npc_get_field_status, \
254 npc_get_field_status_req, \
255 npc_get_field_status_rsp) \
256 /* NIX mbox IDs (range 0x8000 - 0xFFFF) */ \
257 M(NIX_LF_ALLOC, 0x8000, nix_lf_alloc, \
258 nix_lf_alloc_req, nix_lf_alloc_rsp) \
259 M(NIX_LF_FREE, 0x8001, nix_lf_free, nix_lf_free_req, msg_rsp) \
260 M(NIX_AQ_ENQ, 0x8002, nix_aq_enq, nix_aq_enq_req, nix_aq_enq_rsp) \
261 M(NIX_HWCTX_DISABLE, 0x8003, nix_hwctx_disable, \
262 hwctx_disable_req, msg_rsp) \
263 M(NIX_TXSCH_ALLOC, 0x8004, nix_txsch_alloc, \
264 nix_txsch_alloc_req, nix_txsch_alloc_rsp) \
265 M(NIX_TXSCH_FREE, 0x8005, nix_txsch_free, nix_txsch_free_req, msg_rsp) \
266 M(NIX_TXSCHQ_CFG, 0x8006, nix_txschq_cfg, nix_txschq_config, \
267 nix_txschq_config) \
268 M(NIX_STATS_RST, 0x8007, nix_stats_rst, msg_req, msg_rsp) \
269 M(NIX_VTAG_CFG, 0x8008, nix_vtag_cfg, nix_vtag_config, \
270 nix_vtag_config_rsp) \
271 M(NIX_RSS_FLOWKEY_CFG, 0x8009, nix_rss_flowkey_cfg, \
272 nix_rss_flowkey_cfg, \
273 nix_rss_flowkey_cfg_rsp) \
274 M(NIX_SET_MAC_ADDR, 0x800a, nix_set_mac_addr, nix_set_mac_addr, msg_rsp) \
275 M(NIX_SET_RX_MODE, 0x800b, nix_set_rx_mode, nix_rx_mode, msg_rsp) \
276 M(NIX_SET_HW_FRS, 0x800c, nix_set_hw_frs, nix_frs_cfg, msg_rsp) \
277 M(NIX_LF_START_RX, 0x800d, nix_lf_start_rx, msg_req, msg_rsp) \
278 M(NIX_LF_STOP_RX, 0x800e, nix_lf_stop_rx, msg_req, msg_rsp) \
279 M(NIX_MARK_FORMAT_CFG, 0x800f, nix_mark_format_cfg, \
280 nix_mark_format_cfg, \
281 nix_mark_format_cfg_rsp) \
282 M(NIX_SET_RX_CFG, 0x8010, nix_set_rx_cfg, nix_rx_cfg, msg_rsp) \
283 M(NIX_LSO_FORMAT_CFG, 0x8011, nix_lso_format_cfg, \
284 nix_lso_format_cfg, \
285 nix_lso_format_cfg_rsp) \
286 M(NIX_LF_PTP_TX_ENABLE, 0x8013, nix_lf_ptp_tx_enable, msg_req, msg_rsp) \
287 M(NIX_LF_PTP_TX_DISABLE, 0x8014, nix_lf_ptp_tx_disable, msg_req, msg_rsp) \
288 M(NIX_BP_ENABLE, 0x8016, nix_bp_enable, nix_bp_cfg_req, \
289 nix_bp_cfg_rsp) \
290 M(NIX_BP_DISABLE, 0x8017, nix_bp_disable, nix_bp_cfg_req, msg_rsp) \
291 M(NIX_GET_MAC_ADDR, 0x8018, nix_get_mac_addr, msg_req, nix_get_mac_addr_rsp) \
292 M(NIX_INLINE_IPSEC_CFG, 0x8019, nix_inline_ipsec_cfg, \
293 nix_inline_ipsec_cfg, msg_rsp) \
294 M(NIX_INLINE_IPSEC_LF_CFG, 0x801a, nix_inline_ipsec_lf_cfg, \
295 nix_inline_ipsec_lf_cfg, msg_rsp) \
296 M(NIX_CN10K_AQ_ENQ, 0x801b, nix_cn10k_aq_enq, nix_cn10k_aq_enq_req, \
297 nix_cn10k_aq_enq_rsp) \
298 M(NIX_GET_HW_INFO, 0x801c, nix_get_hw_info, msg_req, nix_hw_info) \
299 M(NIX_BANDPROF_ALLOC, 0x801d, nix_bandprof_alloc, nix_bandprof_alloc_req, \
300 nix_bandprof_alloc_rsp) \
301 M(NIX_BANDPROF_FREE, 0x801e, nix_bandprof_free, nix_bandprof_free_req, \
302 msg_rsp) \
303 M(NIX_BANDPROF_GET_HWINFO, 0x801f, nix_bandprof_get_hwinfo, msg_req, \
304 nix_bandprof_get_hwinfo_rsp) \
305 M(NIX_READ_INLINE_IPSEC_CFG, 0x8023, nix_read_inline_ipsec_cfg, \
306 msg_req, nix_inline_ipsec_cfg) \
307 M(NIX_MCAST_GRP_CREATE, 0x802b, nix_mcast_grp_create, nix_mcast_grp_create_req, \
308 nix_mcast_grp_create_rsp) \
309 M(NIX_MCAST_GRP_DESTROY, 0x802c, nix_mcast_grp_destroy, nix_mcast_grp_destroy_req, \
310 msg_rsp) \
311 M(NIX_MCAST_GRP_UPDATE, 0x802d, nix_mcast_grp_update, \
312 nix_mcast_grp_update_req, \
313 nix_mcast_grp_update_rsp) \
314 /* MCS mbox IDs (range 0xA000 - 0xBFFF) */ \
315 M(MCS_ALLOC_RESOURCES, 0xa000, mcs_alloc_resources, mcs_alloc_rsrc_req, \
316 mcs_alloc_rsrc_rsp) \
317 M(MCS_FREE_RESOURCES, 0xa001, mcs_free_resources, mcs_free_rsrc_req, msg_rsp) \
318 M(MCS_FLOWID_ENTRY_WRITE, 0xa002, mcs_flowid_entry_write, mcs_flowid_entry_write_req, \
319 msg_rsp) \
320 M(MCS_SECY_PLCY_WRITE, 0xa003, mcs_secy_plcy_write, mcs_secy_plcy_write_req, \
321 msg_rsp) \
322 M(MCS_RX_SC_CAM_WRITE, 0xa004, mcs_rx_sc_cam_write, mcs_rx_sc_cam_write_req, \
323 msg_rsp) \
324 M(MCS_SA_PLCY_WRITE, 0xa005, mcs_sa_plcy_write, mcs_sa_plcy_write_req, \
325 msg_rsp) \
326 M(MCS_TX_SC_SA_MAP_WRITE, 0xa006, mcs_tx_sc_sa_map_write, mcs_tx_sc_sa_map, \
327 msg_rsp) \
328 M(MCS_RX_SC_SA_MAP_WRITE, 0xa007, mcs_rx_sc_sa_map_write, mcs_rx_sc_sa_map, \
329 msg_rsp) \
330 M(MCS_FLOWID_ENA_ENTRY, 0xa008, mcs_flowid_ena_entry, mcs_flowid_ena_dis_entry, \
331 msg_rsp) \
332 M(MCS_PN_TABLE_WRITE, 0xa009, mcs_pn_table_write, mcs_pn_table_write_req, \
333 msg_rsp) \
334 M(MCS_SET_ACTIVE_LMAC, 0xa00a, mcs_set_active_lmac, mcs_set_active_lmac, \
335 msg_rsp) \
336 M(MCS_GET_HW_INFO, 0xa00b, mcs_get_hw_info, msg_req, mcs_hw_info) \
337 M(MCS_GET_FLOWID_STATS, 0xa00c, mcs_get_flowid_stats, mcs_stats_req, \
338 mcs_flowid_stats) \
339 M(MCS_GET_SECY_STATS, 0xa00d, mcs_get_secy_stats, mcs_stats_req, \
340 mcs_secy_stats) \
341 M(MCS_GET_SC_STATS, 0xa00e, mcs_get_sc_stats, mcs_stats_req, mcs_sc_stats) \
342 M(MCS_GET_SA_STATS, 0xa00f, mcs_get_sa_stats, mcs_stats_req, mcs_sa_stats) \
343 M(MCS_GET_PORT_STATS, 0xa010, mcs_get_port_stats, mcs_stats_req, \
344 mcs_port_stats) \
345 M(MCS_CLEAR_STATS, 0xa011, mcs_clear_stats, mcs_clear_stats, msg_rsp) \
346 M(MCS_INTR_CFG, 0xa012, mcs_intr_cfg, mcs_intr_cfg, msg_rsp) \
347 M(MCS_SET_LMAC_MODE, 0xa013, mcs_set_lmac_mode, mcs_set_lmac_mode, msg_rsp) \
348 M(MCS_SET_PN_THRESHOLD, 0xa014, mcs_set_pn_threshold, mcs_set_pn_threshold, \
349 msg_rsp) \
350 M(MCS_ALLOC_CTRL_PKT_RULE, 0xa015, mcs_alloc_ctrl_pkt_rule, \
351 mcs_alloc_ctrl_pkt_rule_req, \
352 mcs_alloc_ctrl_pkt_rule_rsp) \
353 M(MCS_FREE_CTRL_PKT_RULE, 0xa016, mcs_free_ctrl_pkt_rule, \
354 mcs_free_ctrl_pkt_rule_req, msg_rsp) \
355 M(MCS_CTRL_PKT_RULE_WRITE, 0xa017, mcs_ctrl_pkt_rule_write, \
356 mcs_ctrl_pkt_rule_write_req, msg_rsp) \
357 M(MCS_PORT_RESET, 0xa018, mcs_port_reset, mcs_port_reset_req, msg_rsp) \
358 M(MCS_PORT_CFG_SET, 0xa019, mcs_port_cfg_set, mcs_port_cfg_set_req, msg_rsp)\
359 M(MCS_PORT_CFG_GET, 0xa020, mcs_port_cfg_get, mcs_port_cfg_get_req, \
360 mcs_port_cfg_get_rsp) \
361 M(MCS_CUSTOM_TAG_CFG_GET, 0xa021, mcs_custom_tag_cfg_get, \
362 mcs_custom_tag_cfg_get_req, \
363 mcs_custom_tag_cfg_get_rsp)
364
365 /* Messages initiated by AF (range 0xC00 - 0xEFF) */
366 #define MBOX_UP_CGX_MESSAGES \
367 M(CGX_LINK_EVENT, 0xC00, cgx_link_event, cgx_link_info_msg, msg_rsp)
368
369 #define MBOX_UP_CPT_MESSAGES \
370 M(CPT_INST_LMTST, 0xD00, cpt_inst_lmtst, cpt_inst_lmtst_req, msg_rsp)
371
372 #define MBOX_UP_MCS_MESSAGES \
373 M(MCS_INTR_NOTIFY, 0xE00, mcs_intr_notify, mcs_intr_info, msg_rsp)
374
375 enum {
376 #define M(_name, _id, _1, _2, _3) MBOX_MSG_ ## _name = _id,
377 MBOX_MESSAGES
378 MBOX_UP_CGX_MESSAGES
379 MBOX_UP_CPT_MESSAGES
380 MBOX_UP_MCS_MESSAGES
381 #undef M
382 };
383
384 /* Mailbox message formats */
385
386 #define RVU_DEFAULT_PF_FUNC 0xFFFF
387
388 /* Generic request msg used for those mbox messages which
389 * don't send any data in the request.
390 */
391 struct msg_req {
392 struct mbox_msghdr hdr;
393 };
394
395 /* Generic response msg used an ack or response for those mbox
396 * messages which don't have a specific rsp msg format.
397 */
398 struct msg_rsp {
399 struct mbox_msghdr hdr;
400 };
401
402 /* RVU mailbox error codes
403 * Range 256 - 300.
404 */
405 enum rvu_af_status {
406 RVU_INVALID_VF_ID = -256,
407 };
408
409 struct ready_msg_rsp {
410 struct mbox_msghdr hdr;
411 u16 sclk_freq; /* SCLK frequency (in MHz) */
412 u16 rclk_freq; /* RCLK frequency (in MHz) */
413 };
414
415 /* Structure for requesting resource provisioning.
416 * 'modify' flag to be used when either requesting more
417 * or to detach partial of a certain resource type.
418 * Rest of the fields specify how many of what type to
419 * be attached.
420 * To request LFs from two blocks of same type this mailbox
421 * can be sent twice as below:
422 * struct rsrc_attach *attach;
423 * .. Allocate memory for message ..
424 * attach->cptlfs = 3; <3 LFs from CPT0>
425 * .. Send message ..
426 * .. Allocate memory for message ..
427 * attach->modify = 1;
428 * attach->cpt_blkaddr = BLKADDR_CPT1;
429 * attach->cptlfs = 2; <2 LFs from CPT1>
430 * .. Send message ..
431 */
432 struct rsrc_attach {
433 struct mbox_msghdr hdr;
434 u8 modify:1;
435 u8 npalf:1;
436 u8 nixlf:1;
437 u16 sso;
438 u16 ssow;
439 u16 timlfs;
440 u16 cptlfs;
441 int cpt_blkaddr; /* BLKADDR_CPT0/BLKADDR_CPT1 or 0 for BLKADDR_CPT0 */
442 };
443
444 /* Structure for relinquishing resources.
445 * 'partial' flag to be used when relinquishing all resources
446 * but only of a certain type. If not set, all resources of all
447 * types provisioned to the RVU function will be detached.
448 */
449 struct rsrc_detach {
450 struct mbox_msghdr hdr;
451 u8 partial:1;
452 u8 npalf:1;
453 u8 nixlf:1;
454 u8 sso:1;
455 u8 ssow:1;
456 u8 timlfs:1;
457 u8 cptlfs:1;
458 };
459
460 /* Number of resources available to the caller.
461 * In reply to MBOX_MSG_FREE_RSRC_CNT.
462 */
463 struct free_rsrcs_rsp {
464 struct mbox_msghdr hdr;
465 u16 schq[NIX_TXSCH_LVL_CNT];
466 u16 sso;
467 u16 tim;
468 u16 ssow;
469 u16 cpt;
470 u8 npa;
471 u8 nix;
472 u16 schq_nix1[NIX_TXSCH_LVL_CNT];
473 u8 nix1;
474 u8 cpt1;
475 u8 ree0;
476 u8 ree1;
477 };
478
479 #define MSIX_VECTOR_INVALID 0xFFFF
480 #define MAX_RVU_BLKLF_CNT 256
481
482 struct msix_offset_rsp {
483 struct mbox_msghdr hdr;
484 u16 npa_msixoff;
485 u16 nix_msixoff;
486 u16 sso;
487 u16 ssow;
488 u16 timlfs;
489 u16 cptlfs;
490 u16 sso_msixoff[MAX_RVU_BLKLF_CNT];
491 u16 ssow_msixoff[MAX_RVU_BLKLF_CNT];
492 u16 timlf_msixoff[MAX_RVU_BLKLF_CNT];
493 u16 cptlf_msixoff[MAX_RVU_BLKLF_CNT];
494 u16 cpt1_lfs;
495 u16 ree0_lfs;
496 u16 ree1_lfs;
497 u16 cpt1_lf_msixoff[MAX_RVU_BLKLF_CNT];
498 u16 ree0_lf_msixoff[MAX_RVU_BLKLF_CNT];
499 u16 ree1_lf_msixoff[MAX_RVU_BLKLF_CNT];
500 };
501
502 struct get_hw_cap_rsp {
503 struct mbox_msghdr hdr;
504 u8 nix_fixed_txschq_mapping; /* Schq mapping fixed or flexible */
505 u8 nix_shaping; /* Is shaping and coloring supported */
506 u8 npc_hash_extract; /* Is hash extract supported */
507 };
508
509 /* CGX mbox message formats */
510
511 struct cgx_stats_rsp {
512 struct mbox_msghdr hdr;
513 #define CGX_RX_STATS_COUNT 9
514 #define CGX_TX_STATS_COUNT 18
515 u64 rx_stats[CGX_RX_STATS_COUNT];
516 u64 tx_stats[CGX_TX_STATS_COUNT];
517 };
518
519 struct cgx_fec_stats_rsp {
520 struct mbox_msghdr hdr;
521 u64 fec_corr_blks;
522 u64 fec_uncorr_blks;
523 };
524 /* Structure for requesting the operation for
525 * setting/getting mac address in the CGX interface
526 */
527 struct cgx_mac_addr_set_or_get {
528 struct mbox_msghdr hdr;
529 u8 mac_addr[ETH_ALEN];
530 u32 index;
531 };
532
533 /* Structure for requesting the operation to
534 * add DMAC filter entry into CGX interface
535 */
536 struct cgx_mac_addr_add_req {
537 struct mbox_msghdr hdr;
538 u8 mac_addr[ETH_ALEN];
539 };
540
541 /* Structure for response against the operation to
542 * add DMAC filter entry into CGX interface
543 */
544 struct cgx_mac_addr_add_rsp {
545 struct mbox_msghdr hdr;
546 u32 index;
547 };
548
549 /* Structure for requesting the operation to
550 * delete DMAC filter entry from CGX interface
551 */
552 struct cgx_mac_addr_del_req {
553 struct mbox_msghdr hdr;
554 u32 index;
555 };
556
557 /* Structure for response against the operation to
558 * get maximum supported DMAC filter entries
559 */
560 struct cgx_max_dmac_entries_get_rsp {
561 struct mbox_msghdr hdr;
562 u32 max_dmac_filters;
563 };
564
565 struct cgx_link_user_info {
566 uint64_t link_up:1;
567 uint64_t full_duplex:1;
568 uint64_t lmac_type_id:4;
569 uint64_t speed:20; /* speed in Mbps */
570 uint64_t an:1; /* AN supported or not */
571 uint64_t fec:2; /* FEC type if enabled else 0 */
572 #define LMACTYPE_STR_LEN 16
573 char lmac_type[LMACTYPE_STR_LEN];
574 };
575
576 struct cgx_link_info_msg {
577 struct mbox_msghdr hdr;
578 struct cgx_link_user_info link_info;
579 };
580
581 struct cgx_pause_frm_cfg {
582 struct mbox_msghdr hdr;
583 u8 set;
584 /* set = 1 if the request is to config pause frames */
585 /* set = 0 if the request is to fetch pause frames config */
586 u8 rx_pause;
587 u8 tx_pause;
588 };
589
590 enum fec_type {
591 OTX2_FEC_NONE,
592 OTX2_FEC_BASER,
593 OTX2_FEC_RS,
594 OTX2_FEC_STATS_CNT = 2,
595 OTX2_FEC_OFF,
596 };
597
598 struct fec_mode {
599 struct mbox_msghdr hdr;
600 int fec;
601 };
602
603 struct sfp_eeprom_s {
604 #define SFP_EEPROM_SIZE 256
605 u16 sff_id;
606 u8 buf[SFP_EEPROM_SIZE];
607 u64 reserved;
608 };
609
610 struct phy_s {
611 struct {
612 u64 can_change_mod_type:1;
613 u64 mod_type:1;
614 u64 has_fec_stats:1;
615 } misc;
616 struct fec_stats_s {
617 u32 rsfec_corr_cws;
618 u32 rsfec_uncorr_cws;
619 u32 brfec_corr_blks;
620 u32 brfec_uncorr_blks;
621 } fec_stats;
622 };
623
624 struct cgx_lmac_fwdata_s {
625 u16 rw_valid;
626 u64 supported_fec;
627 u64 supported_an;
628 u64 supported_link_modes;
629 /* only applicable if AN is supported */
630 u64 advertised_fec;
631 u64 advertised_link_modes;
632 /* Only applicable if SFP/QSFP slot is present */
633 struct sfp_eeprom_s sfp_eeprom;
634 struct phy_s phy;
635 #define LMAC_FWDATA_RESERVED_MEM 1021
636 u64 reserved[LMAC_FWDATA_RESERVED_MEM];
637 };
638
639 struct cgx_fw_data {
640 struct mbox_msghdr hdr;
641 struct cgx_lmac_fwdata_s fwdata;
642 };
643
644 struct cgx_set_link_mode_args {
645 u32 speed;
646 u8 duplex;
647 u8 an;
648 u8 ports;
649 u64 mode;
650 };
651
652 struct cgx_set_link_mode_req {
653 #define AUTONEG_UNKNOWN 0xff
654 struct mbox_msghdr hdr;
655 struct cgx_set_link_mode_args args;
656 };
657
658 struct cgx_set_link_mode_rsp {
659 struct mbox_msghdr hdr;
660 int status;
661 };
662
663 struct cgx_mac_addr_reset_req {
664 struct mbox_msghdr hdr;
665 u32 index;
666 };
667
668 struct cgx_mac_addr_update_req {
669 struct mbox_msghdr hdr;
670 u8 mac_addr[ETH_ALEN];
671 u32 index;
672 };
673
674 struct cgx_mac_addr_update_rsp {
675 struct mbox_msghdr hdr;
676 u32 index;
677 };
678
679 #define RVU_LMAC_FEAT_FC BIT_ULL(0) /* pause frames */
680 #define RVU_LMAC_FEAT_HIGIG2 BIT_ULL(1)
681 /* flow control from physical link higig2 messages */
682 #define RVU_LMAC_FEAT_PTP BIT_ULL(2) /* precison time protocol */
683 #define RVU_LMAC_FEAT_DMACF BIT_ULL(3) /* DMAC FILTER */
684 #define RVU_MAC_VERSION BIT_ULL(4)
685 #define RVU_MAC_CGX BIT_ULL(5)
686 #define RVU_MAC_RPM BIT_ULL(6)
687
688 struct cgx_features_info_msg {
689 struct mbox_msghdr hdr;
690 u64 lmac_features;
691 };
692
693 struct rpm_stats_rsp {
694 struct mbox_msghdr hdr;
695 #define RPM_RX_STATS_COUNT 43
696 #define RPM_TX_STATS_COUNT 34
697 u64 rx_stats[RPM_RX_STATS_COUNT];
698 u64 tx_stats[RPM_TX_STATS_COUNT];
699 };
700
701 struct cgx_pfc_cfg {
702 struct mbox_msghdr hdr;
703 u8 rx_pause;
704 u8 tx_pause;
705 u16 pfc_en; /* bitmap indicating pfc enabled traffic classes */
706 };
707
708 struct cgx_pfc_rsp {
709 struct mbox_msghdr hdr;
710 u8 rx_pause;
711 u8 tx_pause;
712 };
713
714 /* NPA mbox message formats */
715
716 struct npc_set_pkind {
717 struct mbox_msghdr hdr;
718 #define OTX2_PRIV_FLAGS_DEFAULT BIT_ULL(0)
719 #define OTX2_PRIV_FLAGS_CUSTOM BIT_ULL(63)
720 u64 mode;
721 #define PKIND_TX BIT_ULL(0)
722 #define PKIND_RX BIT_ULL(1)
723 u8 dir;
724 u8 pkind; /* valid only in case custom flag */
725 u8 var_len_off; /* Offset of custom header length field.
726 * Valid only for pkind NPC_RX_CUSTOM_PRE_L2_PKIND
727 */
728 u8 var_len_off_mask; /* Mask for length with in offset */
729 u8 shift_dir; /* shift direction to get length of the header at var_len_off */
730 };
731
732 /* NPA mbox message formats */
733
734 /* NPA mailbox error codes
735 * Range 301 - 400.
736 */
737 enum npa_af_status {
738 NPA_AF_ERR_PARAM = -301,
739 NPA_AF_ERR_AQ_FULL = -302,
740 NPA_AF_ERR_AQ_ENQUEUE = -303,
741 NPA_AF_ERR_AF_LF_INVALID = -304,
742 NPA_AF_ERR_AF_LF_ALLOC = -305,
743 NPA_AF_ERR_LF_RESET = -306,
744 };
745
746 /* For NPA LF context alloc and init */
747 struct npa_lf_alloc_req {
748 struct mbox_msghdr hdr;
749 int node;
750 int aura_sz; /* No of auras */
751 u32 nr_pools; /* No of pools */
752 u64 way_mask;
753 };
754
755 struct npa_lf_alloc_rsp {
756 struct mbox_msghdr hdr;
757 u32 stack_pg_ptrs; /* No of ptrs per stack page */
758 u32 stack_pg_bytes; /* Size of stack page */
759 u16 qints; /* NPA_AF_CONST::QINTS */
760 u8 cache_lines; /*BATCH ALLOC DMA */
761 };
762
763 /* NPA AQ enqueue msg */
764 struct npa_aq_enq_req {
765 struct mbox_msghdr hdr;
766 u32 aura_id;
767 u8 ctype;
768 u8 op;
769 union {
770 /* Valid when op == WRITE/INIT and ctype == AURA.
771 * LF fills the pool_id in aura.pool_addr. AF will translate
772 * the pool_id to pool context pointer.
773 */
774 struct npa_aura_s aura;
775 /* Valid when op == WRITE/INIT and ctype == POOL */
776 struct npa_pool_s pool;
777 };
778 /* Mask data when op == WRITE (1=write, 0=don't write) */
779 union {
780 /* Valid when op == WRITE and ctype == AURA */
781 struct npa_aura_s aura_mask;
782 /* Valid when op == WRITE and ctype == POOL */
783 struct npa_pool_s pool_mask;
784 };
785 };
786
787 struct npa_aq_enq_rsp {
788 struct mbox_msghdr hdr;
789 union {
790 /* Valid when op == READ and ctype == AURA */
791 struct npa_aura_s aura;
792 /* Valid when op == READ and ctype == POOL */
793 struct npa_pool_s pool;
794 };
795 };
796
797 /* Disable all contexts of type 'ctype' */
798 struct hwctx_disable_req {
799 struct mbox_msghdr hdr;
800 u8 ctype;
801 };
802
803 /* NIX mbox message formats */
804
805 /* NIX mailbox error codes
806 * Range 401 - 500.
807 */
808 enum nix_af_status {
809 NIX_AF_ERR_PARAM = -401,
810 NIX_AF_ERR_AQ_FULL = -402,
811 NIX_AF_ERR_AQ_ENQUEUE = -403,
812 NIX_AF_ERR_AF_LF_INVALID = -404,
813 NIX_AF_ERR_AF_LF_ALLOC = -405,
814 NIX_AF_ERR_TLX_ALLOC_FAIL = -406,
815 NIX_AF_ERR_TLX_INVALID = -407,
816 NIX_AF_ERR_RSS_SIZE_INVALID = -408,
817 NIX_AF_ERR_RSS_GRPS_INVALID = -409,
818 NIX_AF_ERR_FRS_INVALID = -410,
819 NIX_AF_ERR_RX_LINK_INVALID = -411,
820 NIX_AF_INVAL_TXSCHQ_CFG = -412,
821 NIX_AF_SMQ_FLUSH_FAILED = -413,
822 NIX_AF_ERR_LF_RESET = -414,
823 NIX_AF_ERR_RSS_NOSPC_FIELD = -415,
824 NIX_AF_ERR_RSS_NOSPC_ALGO = -416,
825 NIX_AF_ERR_MARK_CFG_FAIL = -417,
826 NIX_AF_ERR_LSO_CFG_FAIL = -418,
827 NIX_AF_INVAL_NPA_PF_FUNC = -419,
828 NIX_AF_INVAL_SSO_PF_FUNC = -420,
829 NIX_AF_ERR_TX_VTAG_NOSPC = -421,
830 NIX_AF_ERR_RX_VTAG_INUSE = -422,
831 NIX_AF_ERR_PTP_CONFIG_FAIL = -423,
832 NIX_AF_ERR_NPC_KEY_NOT_SUPP = -424,
833 NIX_AF_ERR_INVALID_NIXBLK = -425,
834 NIX_AF_ERR_INVALID_BANDPROF = -426,
835 NIX_AF_ERR_IPOLICER_NOTSUPP = -427,
836 NIX_AF_ERR_BANDPROF_INVAL_REQ = -428,
837 NIX_AF_ERR_CQ_CTX_WRITE_ERR = -429,
838 NIX_AF_ERR_AQ_CTX_RETRY_WRITE = -430,
839 NIX_AF_ERR_LINK_CREDITS = -431,
840 NIX_AF_ERR_INVALID_MCAST_GRP = -436,
841 NIX_AF_ERR_INVALID_MCAST_DEL_REQ = -437,
842 NIX_AF_ERR_NON_CONTIG_MCE_LIST = -438,
843 };
844
845 /* For NIX RX vtag action */
846 enum nix_rx_vtag0_type {
847 NIX_AF_LFX_RX_VTAG_TYPE0, /* reserved for rx vlan offload */
848 NIX_AF_LFX_RX_VTAG_TYPE1,
849 NIX_AF_LFX_RX_VTAG_TYPE2,
850 NIX_AF_LFX_RX_VTAG_TYPE3,
851 NIX_AF_LFX_RX_VTAG_TYPE4,
852 NIX_AF_LFX_RX_VTAG_TYPE5,
853 NIX_AF_LFX_RX_VTAG_TYPE6,
854 NIX_AF_LFX_RX_VTAG_TYPE7,
855 };
856
857 /* For NIX LF context alloc and init */
858 struct nix_lf_alloc_req {
859 struct mbox_msghdr hdr;
860 int node;
861 u32 rq_cnt; /* No of receive queues */
862 u32 sq_cnt; /* No of send queues */
863 u32 cq_cnt; /* No of completion queues */
864 u8 xqe_sz;
865 u16 rss_sz;
866 u8 rss_grps;
867 u16 npa_func;
868 u16 sso_func;
869 u64 rx_cfg; /* See NIX_AF_LF(0..127)_RX_CFG */
870 u64 way_mask;
871 #define NIX_LF_RSS_TAG_LSB_AS_ADDER BIT_ULL(0)
872 #define NIX_LF_LBK_BLK_SEL BIT_ULL(1)
873 u64 flags;
874 };
875
876 struct nix_lf_alloc_rsp {
877 struct mbox_msghdr hdr;
878 u16 sqb_size;
879 u16 rx_chan_base;
880 u16 tx_chan_base;
881 u8 rx_chan_cnt; /* total number of RX channels */
882 u8 tx_chan_cnt; /* total number of TX channels */
883 u8 lso_tsov4_idx;
884 u8 lso_tsov6_idx;
885 u8 mac_addr[ETH_ALEN];
886 u8 lf_rx_stats; /* NIX_AF_CONST1::LF_RX_STATS */
887 u8 lf_tx_stats; /* NIX_AF_CONST1::LF_TX_STATS */
888 u16 cints; /* NIX_AF_CONST2::CINTS */
889 u16 qints; /* NIX_AF_CONST2::QINTS */
890 u8 cgx_links; /* No. of CGX links present in HW */
891 u8 lbk_links; /* No. of LBK links present in HW */
892 u8 sdp_links; /* No. of SDP links present in HW */
893 u8 tx_link; /* Transmit channel link number */
894 };
895
896 struct nix_lf_free_req {
897 struct mbox_msghdr hdr;
898 #define NIX_LF_DISABLE_FLOWS BIT_ULL(0)
899 #define NIX_LF_DONT_FREE_TX_VTAG BIT_ULL(1)
900 u64 flags;
901 };
902
903 /* CN10K NIX AQ enqueue msg */
904 struct nix_cn10k_aq_enq_req {
905 struct mbox_msghdr hdr;
906 u32 qidx;
907 u8 ctype;
908 u8 op;
909 union {
910 struct nix_cn10k_rq_ctx_s rq;
911 struct nix_cn10k_sq_ctx_s sq;
912 struct nix_cq_ctx_s cq;
913 struct nix_rsse_s rss;
914 struct nix_rx_mce_s mce;
915 struct nix_bandprof_s prof;
916 };
917 union {
918 struct nix_cn10k_rq_ctx_s rq_mask;
919 struct nix_cn10k_sq_ctx_s sq_mask;
920 struct nix_cq_ctx_s cq_mask;
921 struct nix_rsse_s rss_mask;
922 struct nix_rx_mce_s mce_mask;
923 struct nix_bandprof_s prof_mask;
924 };
925 };
926
927 struct nix_cn10k_aq_enq_rsp {
928 struct mbox_msghdr hdr;
929 union {
930 struct nix_cn10k_rq_ctx_s rq;
931 struct nix_cn10k_sq_ctx_s sq;
932 struct nix_cq_ctx_s cq;
933 struct nix_rsse_s rss;
934 struct nix_rx_mce_s mce;
935 struct nix_bandprof_s prof;
936 };
937 };
938
939 /* NIX AQ enqueue msg */
940 struct nix_aq_enq_req {
941 struct mbox_msghdr hdr;
942 u32 qidx;
943 u8 ctype;
944 u8 op;
945 union {
946 struct nix_rq_ctx_s rq;
947 struct nix_sq_ctx_s sq;
948 struct nix_cq_ctx_s cq;
949 struct nix_rsse_s rss;
950 struct nix_rx_mce_s mce;
951 struct nix_bandprof_s prof;
952 };
953 union {
954 struct nix_rq_ctx_s rq_mask;
955 struct nix_sq_ctx_s sq_mask;
956 struct nix_cq_ctx_s cq_mask;
957 struct nix_rsse_s rss_mask;
958 struct nix_rx_mce_s mce_mask;
959 struct nix_bandprof_s prof_mask;
960 };
961 };
962
963 struct nix_aq_enq_rsp {
964 struct mbox_msghdr hdr;
965 union {
966 struct nix_rq_ctx_s rq;
967 struct nix_sq_ctx_s sq;
968 struct nix_cq_ctx_s cq;
969 struct nix_rsse_s rss;
970 struct nix_rx_mce_s mce;
971 struct nix_bandprof_s prof;
972 };
973 };
974
975 /* Tx scheduler/shaper mailbox messages */
976
977 #define MAX_TXSCHQ_PER_FUNC 128
978
979 struct nix_txsch_alloc_req {
980 struct mbox_msghdr hdr;
981 /* Scheduler queue count request at each level */
982 u16 schq_contig[NIX_TXSCH_LVL_CNT]; /* No of contiguous queues */
983 u16 schq[NIX_TXSCH_LVL_CNT]; /* No of non-contiguous queues */
984 };
985
986 struct nix_txsch_alloc_rsp {
987 struct mbox_msghdr hdr;
988 /* Scheduler queue count allocated at each level */
989 u16 schq_contig[NIX_TXSCH_LVL_CNT];
990 u16 schq[NIX_TXSCH_LVL_CNT];
991 /* Scheduler queue list allocated at each level */
992 u16 schq_contig_list[NIX_TXSCH_LVL_CNT][MAX_TXSCHQ_PER_FUNC];
993 u16 schq_list[NIX_TXSCH_LVL_CNT][MAX_TXSCHQ_PER_FUNC];
994 u8 aggr_level; /* Traffic aggregation scheduler level */
995 u8 aggr_lvl_rr_prio; /* Aggregation lvl's RR_PRIO config */
996 u8 link_cfg_lvl; /* LINKX_CFG CSRs mapped to TL3 or TL2's index ? */
997 };
998
999 struct nix_txsch_free_req {
1000 struct mbox_msghdr hdr;
1001 #define TXSCHQ_FREE_ALL BIT_ULL(0)
1002 u16 flags;
1003 /* Scheduler queue level to be freed */
1004 u16 schq_lvl;
1005 /* List of scheduler queues to be freed */
1006 u16 schq;
1007 };
1008
1009 struct nix_txschq_config {
1010 struct mbox_msghdr hdr;
1011 u8 lvl; /* SMQ/MDQ/TL4/TL3/TL2/TL1 */
1012 u8 read;
1013 #define TXSCHQ_IDX_SHIFT 16
1014 #define TXSCHQ_IDX_MASK (BIT_ULL(10) - 1)
1015 #define TXSCHQ_IDX(reg, shift) (((reg) >> (shift)) & TXSCHQ_IDX_MASK)
1016 u8 num_regs;
1017 #define MAX_REGS_PER_MBOX_MSG 20
1018 u64 reg[MAX_REGS_PER_MBOX_MSG];
1019 u64 regval[MAX_REGS_PER_MBOX_MSG];
1020 /* All 0's => overwrite with new value */
1021 u64 regval_mask[MAX_REGS_PER_MBOX_MSG];
1022 };
1023
1024 struct nix_vtag_config {
1025 struct mbox_msghdr hdr;
1026 /* '0' for 4 octet VTAG, '1' for 8 octet VTAG */
1027 u8 vtag_size;
1028 /* cfg_type is '0' for tx vlan cfg
1029 * cfg_type is '1' for rx vlan cfg
1030 */
1031 u8 cfg_type;
1032 union {
1033 /* valid when cfg_type is '0' */
1034 struct {
1035 u64 vtag0;
1036 u64 vtag1;
1037
1038 /* cfg_vtag0 & cfg_vtag1 fields are valid
1039 * when free_vtag0 & free_vtag1 are '0's.
1040 */
1041 /* cfg_vtag0 = 1 to configure vtag0 */
1042 u8 cfg_vtag0 :1;
1043 /* cfg_vtag1 = 1 to configure vtag1 */
1044 u8 cfg_vtag1 :1;
1045
1046 /* vtag0_idx & vtag1_idx are only valid when
1047 * both cfg_vtag0 & cfg_vtag1 are '0's,
1048 * these fields are used along with free_vtag0
1049 * & free_vtag1 to free the nix lf's tx_vlan
1050 * configuration.
1051 *
1052 * Denotes the indices of tx_vtag def registers
1053 * that needs to be cleared and freed.
1054 */
1055 int vtag0_idx;
1056 int vtag1_idx;
1057
1058 /* free_vtag0 & free_vtag1 fields are valid
1059 * when cfg_vtag0 & cfg_vtag1 are '0's.
1060 */
1061 /* free_vtag0 = 1 clears vtag0 configuration
1062 * vtag0_idx denotes the index to be cleared.
1063 */
1064 u8 free_vtag0 :1;
1065 /* free_vtag1 = 1 clears vtag1 configuration
1066 * vtag1_idx denotes the index to be cleared.
1067 */
1068 u8 free_vtag1 :1;
1069 } tx;
1070
1071 /* valid when cfg_type is '1' */
1072 struct {
1073 /* rx vtag type index, valid values are in 0..7 range */
1074 u8 vtag_type;
1075 /* rx vtag strip */
1076 u8 strip_vtag :1;
1077 /* rx vtag capture */
1078 u8 capture_vtag :1;
1079 } rx;
1080 };
1081 };
1082
1083 struct nix_vtag_config_rsp {
1084 struct mbox_msghdr hdr;
1085 int vtag0_idx;
1086 int vtag1_idx;
1087 /* Indices of tx_vtag def registers used to configure
1088 * tx vtag0 & vtag1 headers, these indices are valid
1089 * when nix_vtag_config mbox requested for vtag0 and/
1090 * or vtag1 configuration.
1091 */
1092 };
1093
1094 #define NIX_FLOW_KEY_TYPE_L3_L4_MASK (~(0xf << 28))
1095
1096 struct nix_rss_flowkey_cfg {
1097 struct mbox_msghdr hdr;
1098 int mcam_index; /* MCAM entry index to modify */
1099 #define NIX_FLOW_KEY_TYPE_PORT BIT(0)
1100 #define NIX_FLOW_KEY_TYPE_IPV4 BIT(1)
1101 #define NIX_FLOW_KEY_TYPE_IPV6 BIT(2)
1102 #define NIX_FLOW_KEY_TYPE_TCP BIT(3)
1103 #define NIX_FLOW_KEY_TYPE_UDP BIT(4)
1104 #define NIX_FLOW_KEY_TYPE_SCTP BIT(5)
1105 #define NIX_FLOW_KEY_TYPE_NVGRE BIT(6)
1106 #define NIX_FLOW_KEY_TYPE_VXLAN BIT(7)
1107 #define NIX_FLOW_KEY_TYPE_GENEVE BIT(8)
1108 #define NIX_FLOW_KEY_TYPE_ETH_DMAC BIT(9)
1109 #define NIX_FLOW_KEY_TYPE_IPV6_EXT BIT(10)
1110 #define NIX_FLOW_KEY_TYPE_GTPU BIT(11)
1111 #define NIX_FLOW_KEY_TYPE_INNR_IPV4 BIT(12)
1112 #define NIX_FLOW_KEY_TYPE_INNR_IPV6 BIT(13)
1113 #define NIX_FLOW_KEY_TYPE_INNR_TCP BIT(14)
1114 #define NIX_FLOW_KEY_TYPE_INNR_UDP BIT(15)
1115 #define NIX_FLOW_KEY_TYPE_INNR_SCTP BIT(16)
1116 #define NIX_FLOW_KEY_TYPE_INNR_ETH_DMAC BIT(17)
1117 #define NIX_FLOW_KEY_TYPE_VLAN BIT(20)
1118 #define NIX_FLOW_KEY_TYPE_IPV4_PROTO BIT(21)
1119 #define NIX_FLOW_KEY_TYPE_AH BIT(22)
1120 #define NIX_FLOW_KEY_TYPE_ESP BIT(23)
1121 #define NIX_FLOW_KEY_TYPE_L4_DST_ONLY BIT(28)
1122 #define NIX_FLOW_KEY_TYPE_L4_SRC_ONLY BIT(29)
1123 #define NIX_FLOW_KEY_TYPE_L3_DST_ONLY BIT(30)
1124 #define NIX_FLOW_KEY_TYPE_L3_SRC_ONLY BIT(31)
1125 u32 flowkey_cfg; /* Flowkey types selected */
1126 u8 group; /* RSS context or group */
1127 };
1128
1129 struct nix_rss_flowkey_cfg_rsp {
1130 struct mbox_msghdr hdr;
1131 u8 alg_idx; /* Selected algo index */
1132 };
1133
1134 struct nix_set_mac_addr {
1135 struct mbox_msghdr hdr;
1136 u8 mac_addr[ETH_ALEN]; /* MAC address to be set for this pcifunc */
1137 };
1138
1139 struct nix_get_mac_addr_rsp {
1140 struct mbox_msghdr hdr;
1141 u8 mac_addr[ETH_ALEN];
1142 };
1143
1144 struct nix_mark_format_cfg {
1145 struct mbox_msghdr hdr;
1146 u8 offset;
1147 u8 y_mask;
1148 u8 y_val;
1149 u8 r_mask;
1150 u8 r_val;
1151 };
1152
1153 struct nix_mark_format_cfg_rsp {
1154 struct mbox_msghdr hdr;
1155 u8 mark_format_idx;
1156 };
1157
1158 struct nix_rx_mode {
1159 struct mbox_msghdr hdr;
1160 #define NIX_RX_MODE_UCAST BIT(0)
1161 #define NIX_RX_MODE_PROMISC BIT(1)
1162 #define NIX_RX_MODE_ALLMULTI BIT(2)
1163 #define NIX_RX_MODE_USE_MCE BIT(3)
1164 u16 mode;
1165 };
1166
1167 struct nix_rx_cfg {
1168 struct mbox_msghdr hdr;
1169 #define NIX_RX_OL3_VERIFY BIT(0)
1170 #define NIX_RX_OL4_VERIFY BIT(1)
1171 #define NIX_RX_DROP_RE BIT(2)
1172 u8 len_verify; /* Outer L3/L4 len check */
1173 #define NIX_RX_CSUM_OL4_VERIFY BIT(0)
1174 u8 csum_verify; /* Outer L4 checksum verification */
1175 };
1176
1177 struct nix_frs_cfg {
1178 struct mbox_msghdr hdr;
1179 u8 update_smq; /* Update SMQ's min/max lens */
1180 u8 update_minlen; /* Set minlen also */
1181 u8 sdp_link; /* Set SDP RX link */
1182 u16 maxlen;
1183 u16 minlen;
1184 };
1185
1186 struct nix_lso_format_cfg {
1187 struct mbox_msghdr hdr;
1188 u64 field_mask;
1189 #define NIX_LSO_FIELD_MAX 8
1190 u64 fields[NIX_LSO_FIELD_MAX];
1191 };
1192
1193 struct nix_lso_format_cfg_rsp {
1194 struct mbox_msghdr hdr;
1195 u8 lso_format_idx;
1196 };
1197
1198 struct nix_bp_cfg_req {
1199 struct mbox_msghdr hdr;
1200 u16 chan_base; /* Starting channel number */
1201 u8 chan_cnt; /* Number of channels */
1202 u8 bpid_per_chan;
1203 /* bpid_per_chan = 0 assigns single bp id for range of channels */
1204 /* bpid_per_chan = 1 assigns separate bp id for each channel */
1205 };
1206
1207 /* PF can be mapped to either CGX or LBK interface,
1208 * so maximum 64 channels are possible.
1209 */
1210 #define NIX_MAX_BPID_CHAN 64
1211 struct nix_bp_cfg_rsp {
1212 struct mbox_msghdr hdr;
1213 u16 chan_bpid[NIX_MAX_BPID_CHAN]; /* Channel and bpid mapping */
1214 u8 chan_cnt; /* Number of channel for which bpids are assigned */
1215 };
1216
1217 struct nix_mcast_grp_create_req {
1218 struct mbox_msghdr hdr;
1219 #define NIX_MCAST_INGRESS 0
1220 #define NIX_MCAST_EGRESS 1
1221 u8 dir;
1222 u8 reserved[11];
1223 /* Reserving few bytes for future requirement */
1224 };
1225
1226 struct nix_mcast_grp_create_rsp {
1227 struct mbox_msghdr hdr;
1228 /* This mcast_grp_idx should be passed during MCAM
1229 * write entry for multicast. AF will identify the
1230 * corresponding multicast table index associated
1231 * with the group id and program the same to MCAM entry.
1232 * This group id is also needed during group delete
1233 * and update request.
1234 */
1235 u32 mcast_grp_idx;
1236 };
1237
1238 struct nix_mcast_grp_destroy_req {
1239 struct mbox_msghdr hdr;
1240 /* Group id returned by nix_mcast_grp_create_rsp */
1241 u32 mcast_grp_idx;
1242 /* If AF is requesting for destroy, then set
1243 * it to '1'. Otherwise keep it to '0'
1244 */
1245 u8 is_af;
1246 };
1247
1248 struct nix_mcast_grp_update_req {
1249 struct mbox_msghdr hdr;
1250 /* Group id returned by nix_mcast_grp_create_rsp */
1251 u32 mcast_grp_idx;
1252 /* Number of multicast/mirror entries requested */
1253 u32 num_mce_entry;
1254 #define NIX_MCE_ENTRY_MAX 64
1255 #define NIX_RX_RQ 0
1256 #define NIX_RX_RSS 1
1257 /* Receive queue or RSS index within pf_func */
1258 u32 rq_rss_index[NIX_MCE_ENTRY_MAX];
1259 /* pcifunc is required for both ingress and egress multicast */
1260 u16 pcifunc[NIX_MCE_ENTRY_MAX];
1261 /* channel is required for egress multicast */
1262 u16 channel[NIX_MCE_ENTRY_MAX];
1263 #define NIX_MCAST_OP_ADD_ENTRY 0
1264 #define NIX_MCAST_OP_DEL_ENTRY 1
1265 /* Destination type. 0:Receive queue, 1:RSS*/
1266 u8 dest_type[NIX_MCE_ENTRY_MAX];
1267 u8 op;
1268 /* If AF is requesting for update, then set
1269 * it to '1'. Otherwise keep it to '0'
1270 */
1271 u8 is_af;
1272 };
1273
1274 struct nix_mcast_grp_update_rsp {
1275 struct mbox_msghdr hdr;
1276 u32 mce_start_index;
1277 };
1278
1279 /* Global NIX inline IPSec configuration */
1280 struct nix_inline_ipsec_cfg {
1281 struct mbox_msghdr hdr;
1282 u32 cpt_credit;
1283 struct {
1284 u8 egrp;
1285 u16 opcode;
1286 u16 param1;
1287 u16 param2;
1288 } gen_cfg;
1289 struct {
1290 u16 cpt_pf_func;
1291 u8 cpt_slot;
1292 } inst_qsel;
1293 u8 enable;
1294 u16 bpid;
1295 u32 credit_th;
1296 };
1297
1298 /* Per NIX LF inline IPSec configuration */
1299 struct nix_inline_ipsec_lf_cfg {
1300 struct mbox_msghdr hdr;
1301 u64 sa_base_addr;
1302 struct {
1303 u32 tag_const;
1304 u16 lenm1_max;
1305 u8 sa_pow2_size;
1306 u8 tt;
1307 } ipsec_cfg0;
1308 struct {
1309 u32 sa_idx_max;
1310 u8 sa_idx_w;
1311 } ipsec_cfg1;
1312 u8 enable;
1313 };
1314
1315 struct nix_hw_info {
1316 struct mbox_msghdr hdr;
1317 u16 rsvs16;
1318 u16 max_mtu;
1319 u16 min_mtu;
1320 u32 rpm_dwrr_mtu;
1321 u32 sdp_dwrr_mtu;
1322 u32 lbk_dwrr_mtu;
1323 u32 rsvd32[1];
1324 u64 rsvd[15]; /* Add reserved fields for future expansion */
1325 };
1326
1327 struct nix_bandprof_alloc_req {
1328 struct mbox_msghdr hdr;
1329 /* Count of profiles needed per layer */
1330 u16 prof_count[BAND_PROF_NUM_LAYERS];
1331 };
1332
1333 struct nix_bandprof_alloc_rsp {
1334 struct mbox_msghdr hdr;
1335 u16 prof_count[BAND_PROF_NUM_LAYERS];
1336
1337 /* There is no need to allocate morethan 1 bandwidth profile
1338 * per RQ of a PF_FUNC's NIXLF. So limit the maximum
1339 * profiles to 64 per PF_FUNC.
1340 */
1341 #define MAX_BANDPROF_PER_PFFUNC 64
1342 u16 prof_idx[BAND_PROF_NUM_LAYERS][MAX_BANDPROF_PER_PFFUNC];
1343 };
1344
1345 struct nix_bandprof_free_req {
1346 struct mbox_msghdr hdr;
1347 u8 free_all;
1348 u16 prof_count[BAND_PROF_NUM_LAYERS];
1349 u16 prof_idx[BAND_PROF_NUM_LAYERS][MAX_BANDPROF_PER_PFFUNC];
1350 };
1351
1352 struct nix_bandprof_get_hwinfo_rsp {
1353 struct mbox_msghdr hdr;
1354 u16 prof_count[BAND_PROF_NUM_LAYERS];
1355 u32 policer_timeunit;
1356 };
1357
1358 /* NPC mbox message structs */
1359
1360 #define NPC_MCAM_ENTRY_INVALID 0xFFFF
1361 #define NPC_MCAM_INVALID_MAP 0xFFFF
1362
1363 /* NPC mailbox error codes
1364 * Range 701 - 800.
1365 */
1366 enum npc_af_status {
1367 NPC_MCAM_INVALID_REQ = -701,
1368 NPC_MCAM_ALLOC_DENIED = -702,
1369 NPC_MCAM_ALLOC_FAILED = -703,
1370 NPC_MCAM_PERM_DENIED = -704,
1371 NPC_FLOW_INTF_INVALID = -707,
1372 NPC_FLOW_CHAN_INVALID = -708,
1373 NPC_FLOW_NO_NIXLF = -709,
1374 NPC_FLOW_NOT_SUPPORTED = -710,
1375 NPC_FLOW_VF_PERM_DENIED = -711,
1376 NPC_FLOW_VF_NOT_INIT = -712,
1377 NPC_FLOW_VF_OVERLAP = -713,
1378 };
1379
1380 struct npc_mcam_alloc_entry_req {
1381 struct mbox_msghdr hdr;
1382 #define NPC_MAX_NONCONTIG_ENTRIES 256
1383 u8 contig; /* Contiguous entries ? */
1384 #define NPC_MCAM_ANY_PRIO 0
1385 #define NPC_MCAM_LOWER_PRIO 1
1386 #define NPC_MCAM_HIGHER_PRIO 2
1387 u8 priority; /* Lower or higher w.r.t ref_entry */
1388 u16 ref_entry;
1389 u16 count; /* Number of entries requested */
1390 };
1391
1392 struct npc_mcam_alloc_entry_rsp {
1393 struct mbox_msghdr hdr;
1394 u16 entry; /* Entry allocated or start index if contiguous.
1395 * Invalid incase of non-contiguous.
1396 */
1397 u16 count; /* Number of entries allocated */
1398 u16 free_count; /* Number of entries available */
1399 u16 entry_list[NPC_MAX_NONCONTIG_ENTRIES];
1400 };
1401
1402 struct npc_mcam_free_entry_req {
1403 struct mbox_msghdr hdr;
1404 u16 entry; /* Entry index to be freed */
1405 u8 all; /* If all entries allocated to this PFVF to be freed */
1406 };
1407
1408 struct mcam_entry {
1409 #define NPC_MAX_KWS_IN_KEY 7 /* Number of keywords in max keywidth */
1410 u64 kw[NPC_MAX_KWS_IN_KEY];
1411 u64 kw_mask[NPC_MAX_KWS_IN_KEY];
1412 u64 action;
1413 u64 vtag_action;
1414 };
1415
1416 struct npc_mcam_write_entry_req {
1417 struct mbox_msghdr hdr;
1418 struct mcam_entry entry_data;
1419 u16 entry; /* MCAM entry to write this match key */
1420 u16 cntr; /* Counter for this MCAM entry */
1421 u8 intf; /* Rx or Tx interface */
1422 u8 enable_entry;/* Enable this MCAM entry ? */
1423 u8 set_cntr; /* Set counter for this entry ? */
1424 };
1425
1426 /* Enable/Disable a given entry */
1427 struct npc_mcam_ena_dis_entry_req {
1428 struct mbox_msghdr hdr;
1429 u16 entry;
1430 };
1431
1432 struct npc_mcam_shift_entry_req {
1433 struct mbox_msghdr hdr;
1434 #define NPC_MCAM_MAX_SHIFTS 64
1435 u16 curr_entry[NPC_MCAM_MAX_SHIFTS];
1436 u16 new_entry[NPC_MCAM_MAX_SHIFTS];
1437 u16 shift_count; /* Number of entries to shift */
1438 };
1439
1440 struct npc_mcam_shift_entry_rsp {
1441 struct mbox_msghdr hdr;
1442 u16 failed_entry_idx; /* Index in 'curr_entry', not entry itself */
1443 };
1444
1445 struct npc_mcam_alloc_counter_req {
1446 struct mbox_msghdr hdr;
1447 u8 contig; /* Contiguous counters ? */
1448 #define NPC_MAX_NONCONTIG_COUNTERS 64
1449 u16 count; /* Number of counters requested */
1450 };
1451
1452 struct npc_mcam_alloc_counter_rsp {
1453 struct mbox_msghdr hdr;
1454 u16 cntr; /* Counter allocated or start index if contiguous.
1455 * Invalid incase of non-contiguous.
1456 */
1457 u16 count; /* Number of counters allocated */
1458 u16 cntr_list[NPC_MAX_NONCONTIG_COUNTERS];
1459 };
1460
1461 struct npc_mcam_oper_counter_req {
1462 struct mbox_msghdr hdr;
1463 u16 cntr; /* Free a counter or clear/fetch it's stats */
1464 };
1465
1466 struct npc_mcam_oper_counter_rsp {
1467 struct mbox_msghdr hdr;
1468 u64 stat; /* valid only while fetching counter's stats */
1469 };
1470
1471 struct npc_mcam_unmap_counter_req {
1472 struct mbox_msghdr hdr;
1473 u16 cntr;
1474 u16 entry; /* Entry and counter to be unmapped */
1475 u8 all; /* Unmap all entries using this counter ? */
1476 };
1477
1478 struct npc_mcam_alloc_and_write_entry_req {
1479 struct mbox_msghdr hdr;
1480 struct mcam_entry entry_data;
1481 u16 ref_entry;
1482 u8 priority; /* Lower or higher w.r.t ref_entry */
1483 u8 intf; /* Rx or Tx interface */
1484 u8 enable_entry;/* Enable this MCAM entry ? */
1485 u8 alloc_cntr; /* Allocate counter and map ? */
1486 };
1487
1488 struct npc_mcam_alloc_and_write_entry_rsp {
1489 struct mbox_msghdr hdr;
1490 u16 entry;
1491 u16 cntr;
1492 };
1493
1494 struct npc_get_kex_cfg_rsp {
1495 struct mbox_msghdr hdr;
1496 u64 rx_keyx_cfg; /* NPC_AF_INTF(0)_KEX_CFG */
1497 u64 tx_keyx_cfg; /* NPC_AF_INTF(1)_KEX_CFG */
1498 #define NPC_MAX_INTF 2
1499 #define NPC_MAX_LID 8
1500 #define NPC_MAX_LT 16
1501 #define NPC_MAX_LD 2
1502 #define NPC_MAX_LFL 16
1503 /* NPC_AF_KEX_LDATA(0..1)_FLAGS_CFG */
1504 u64 kex_ld_flags[NPC_MAX_LD];
1505 /* NPC_AF_INTF(0..1)_LID(0..7)_LT(0..15)_LD(0..1)_CFG */
1506 u64 intf_lid_lt_ld[NPC_MAX_INTF][NPC_MAX_LID][NPC_MAX_LT][NPC_MAX_LD];
1507 /* NPC_AF_INTF(0..1)_LDATA(0..1)_FLAGS(0..15)_CFG */
1508 u64 intf_ld_flags[NPC_MAX_INTF][NPC_MAX_LD][NPC_MAX_LFL];
1509 #define MKEX_NAME_LEN 128
1510 u8 mkex_pfl_name[MKEX_NAME_LEN];
1511 };
1512
1513 struct ptp_get_cap_rsp {
1514 struct mbox_msghdr hdr;
1515 #define PTP_CAP_HW_ATOMIC_UPDATE BIT_ULL(0)
1516 u64 cap;
1517 };
1518
1519 struct flow_msg {
1520 unsigned char dmac[6];
1521 unsigned char smac[6];
1522 __be16 etype;
1523 __be16 vlan_etype;
1524 __be16 vlan_tci;
1525 union {
1526 __be32 ip4src;
1527 __be32 ip6src[4];
1528 };
1529 union {
1530 __be32 ip4dst;
1531 __be32 ip6dst[4];
1532 };
1533 union {
1534 __be32 spi;
1535 };
1536
1537 u8 tos;
1538 u8 ip_ver;
1539 u8 ip_proto;
1540 u8 tc;
1541 __be16 sport;
1542 __be16 dport;
1543 union {
1544 u8 ip_flag;
1545 u8 next_header;
1546 };
1547 __be16 vlan_itci;
1548 #define OTX2_FLOWER_MASK_MPLS_LB GENMASK(31, 12)
1549 #define OTX2_FLOWER_MASK_MPLS_TC GENMASK(11, 9)
1550 #define OTX2_FLOWER_MASK_MPLS_BOS BIT(8)
1551 #define OTX2_FLOWER_MASK_MPLS_TTL GENMASK(7, 0)
1552 #define OTX2_FLOWER_MASK_MPLS_NON_TTL GENMASK(31, 8)
1553 u32 mpls_lse[4];
1554 u8 icmp_type;
1555 u8 icmp_code;
1556 };
1557
1558 struct npc_install_flow_req {
1559 struct mbox_msghdr hdr;
1560 struct flow_msg packet;
1561 struct flow_msg mask;
1562 u64 features;
1563 u16 entry;
1564 u16 channel;
1565 u16 chan_mask;
1566 u8 intf;
1567 u8 set_cntr; /* If counter is available set counter for this entry ? */
1568 u8 default_rule;
1569 u8 append; /* overwrite(0) or append(1) flow to default rule? */
1570 u16 vf;
1571 /* action */
1572 u32 index;
1573 u16 match_id;
1574 u8 flow_key_alg;
1575 u8 op;
1576 /* vtag rx action */
1577 u8 vtag0_type;
1578 u8 vtag0_valid;
1579 u8 vtag1_type;
1580 u8 vtag1_valid;
1581 /* vtag tx action */
1582 u16 vtag0_def;
1583 u8 vtag0_op;
1584 u16 vtag1_def;
1585 u8 vtag1_op;
1586 /* old counter value */
1587 u16 cntr_val;
1588 };
1589
1590 struct npc_install_flow_rsp {
1591 struct mbox_msghdr hdr;
1592 int counter; /* negative if no counter else counter number */
1593 };
1594
1595 struct npc_delete_flow_req {
1596 struct mbox_msghdr hdr;
1597 u16 entry;
1598 u16 start;/*Disable range of entries */
1599 u16 end;
1600 u8 all; /* PF + VFs */
1601 };
1602
1603 struct npc_delete_flow_rsp {
1604 struct mbox_msghdr hdr;
1605 u16 cntr_val;
1606 };
1607
1608 struct npc_mcam_read_entry_req {
1609 struct mbox_msghdr hdr;
1610 u16 entry; /* MCAM entry to read */
1611 };
1612
1613 struct npc_mcam_read_entry_rsp {
1614 struct mbox_msghdr hdr;
1615 struct mcam_entry entry_data;
1616 u8 intf;
1617 u8 enable;
1618 };
1619
1620 struct npc_mcam_read_base_rule_rsp {
1621 struct mbox_msghdr hdr;
1622 struct mcam_entry entry;
1623 };
1624
1625 struct npc_mcam_get_stats_req {
1626 struct mbox_msghdr hdr;
1627 u16 entry; /* mcam entry */
1628 };
1629
1630 struct npc_mcam_get_stats_rsp {
1631 struct mbox_msghdr hdr;
1632 u64 stat; /* counter stats */
1633 u8 stat_ena; /* enabled */
1634 };
1635
1636 struct npc_get_field_hash_info_req {
1637 struct mbox_msghdr hdr;
1638 u8 intf;
1639 };
1640
1641 struct npc_get_field_hash_info_rsp {
1642 struct mbox_msghdr hdr;
1643 u64 secret_key[3];
1644 #define NPC_MAX_HASH 2
1645 #define NPC_MAX_HASH_MASK 2
1646 /* NPC_AF_INTF(0..1)_HASH(0..1)_MASK(0..1) */
1647 u64 hash_mask[NPC_MAX_INTF][NPC_MAX_HASH][NPC_MAX_HASH_MASK];
1648 /* NPC_AF_INTF(0..1)_HASH(0..1)_RESULT_CTRL */
1649 u64 hash_ctrl[NPC_MAX_INTF][NPC_MAX_HASH];
1650 };
1651
1652 enum ptp_op {
1653 PTP_OP_ADJFINE = 0,
1654 PTP_OP_GET_CLOCK = 1,
1655 PTP_OP_GET_TSTMP = 2,
1656 PTP_OP_SET_THRESH = 3,
1657 PTP_OP_PPS_ON = 4,
1658 PTP_OP_ADJTIME = 5,
1659 PTP_OP_SET_CLOCK = 6,
1660 };
1661
1662 struct ptp_req {
1663 struct mbox_msghdr hdr;
1664 u8 op;
1665 s64 scaled_ppm;
1666 u64 thresh;
1667 u64 period;
1668 int pps_on;
1669 s64 delta;
1670 u64 clk;
1671 };
1672
1673 struct ptp_rsp {
1674 struct mbox_msghdr hdr;
1675 u64 clk;
1676 u64 tsc;
1677 };
1678
1679 struct npc_get_field_status_req {
1680 struct mbox_msghdr hdr;
1681 u8 intf;
1682 u8 field;
1683 };
1684
1685 struct npc_get_field_status_rsp {
1686 struct mbox_msghdr hdr;
1687 u8 enable;
1688 };
1689
1690 struct set_vf_perm {
1691 struct mbox_msghdr hdr;
1692 u16 vf;
1693 #define RESET_VF_PERM BIT_ULL(0)
1694 #define VF_TRUSTED BIT_ULL(1)
1695 u64 flags;
1696 };
1697
1698 struct lmtst_tbl_setup_req {
1699 struct mbox_msghdr hdr;
1700 u64 dis_sched_early_comp :1;
1701 u64 sch_ena :1;
1702 u64 dis_line_pref :1;
1703 u64 ssow_pf_func :13;
1704 u16 base_pcifunc;
1705 u8 use_local_lmt_region;
1706 u64 lmt_iova;
1707 u64 rsvd[4];
1708 };
1709
1710 /* CPT mailbox error codes
1711 * Range 901 - 1000.
1712 */
1713 enum cpt_af_status {
1714 CPT_AF_ERR_PARAM = -901,
1715 CPT_AF_ERR_GRP_INVALID = -902,
1716 CPT_AF_ERR_LF_INVALID = -903,
1717 CPT_AF_ERR_ACCESS_DENIED = -904,
1718 CPT_AF_ERR_SSO_PF_FUNC_INVALID = -905,
1719 CPT_AF_ERR_NIX_PF_FUNC_INVALID = -906,
1720 CPT_AF_ERR_INLINE_IPSEC_INB_ENA = -907,
1721 CPT_AF_ERR_INLINE_IPSEC_OUT_ENA = -908
1722 };
1723
1724 /* CPT mbox message formats */
1725 struct cpt_rd_wr_reg_msg {
1726 struct mbox_msghdr hdr;
1727 u64 reg_offset;
1728 u64 *ret_val;
1729 u64 val;
1730 u8 is_write;
1731 int blkaddr;
1732 };
1733
1734 struct cpt_lf_alloc_req_msg {
1735 struct mbox_msghdr hdr;
1736 u16 nix_pf_func;
1737 u16 sso_pf_func;
1738 u16 eng_grpmsk;
1739 int blkaddr;
1740 u8 ctx_ilen_valid : 1;
1741 u8 ctx_ilen : 7;
1742 };
1743
1744 #define CPT_INLINE_INBOUND 0
1745 #define CPT_INLINE_OUTBOUND 1
1746
1747 /* Mailbox message request format for CPT IPsec
1748 * inline inbound and outbound configuration.
1749 */
1750 struct cpt_inline_ipsec_cfg_msg {
1751 struct mbox_msghdr hdr;
1752 u8 enable;
1753 u8 slot;
1754 u8 dir;
1755 u8 sso_pf_func_ovrd;
1756 u16 sso_pf_func; /* inbound path SSO_PF_FUNC */
1757 u16 nix_pf_func; /* outbound path NIX_PF_FUNC */
1758 };
1759
1760 /* Mailbox message request and response format for CPT stats. */
1761 struct cpt_sts_req {
1762 struct mbox_msghdr hdr;
1763 u8 blkaddr;
1764 };
1765
1766 struct cpt_sts_rsp {
1767 struct mbox_msghdr hdr;
1768 u64 inst_req_pc;
1769 u64 inst_lat_pc;
1770 u64 rd_req_pc;
1771 u64 rd_lat_pc;
1772 u64 rd_uc_pc;
1773 u64 active_cycles_pc;
1774 u64 ctx_mis_pc;
1775 u64 ctx_hit_pc;
1776 u64 ctx_aop_pc;
1777 u64 ctx_aop_lat_pc;
1778 u64 ctx_ifetch_pc;
1779 u64 ctx_ifetch_lat_pc;
1780 u64 ctx_ffetch_pc;
1781 u64 ctx_ffetch_lat_pc;
1782 u64 ctx_wback_pc;
1783 u64 ctx_wback_lat_pc;
1784 u64 ctx_psh_pc;
1785 u64 ctx_psh_lat_pc;
1786 u64 ctx_err;
1787 u64 ctx_enc_id;
1788 u64 ctx_flush_timer;
1789 u64 rxc_time;
1790 u64 rxc_time_cfg;
1791 u64 rxc_active_sts;
1792 u64 rxc_zombie_sts;
1793 u64 busy_sts_ae;
1794 u64 free_sts_ae;
1795 u64 busy_sts_se;
1796 u64 free_sts_se;
1797 u64 busy_sts_ie;
1798 u64 free_sts_ie;
1799 u64 exe_err_info;
1800 u64 cptclk_cnt;
1801 u64 diag;
1802 u64 rxc_dfrg;
1803 u64 x2p_link_cfg0;
1804 u64 x2p_link_cfg1;
1805 };
1806
1807 /* Mailbox message request format to configure reassembly timeout. */
1808 struct cpt_rxc_time_cfg_req {
1809 struct mbox_msghdr hdr;
1810 int blkaddr;
1811 u32 step;
1812 u16 zombie_thres;
1813 u16 zombie_limit;
1814 u16 active_thres;
1815 u16 active_limit;
1816 };
1817
1818 /* Mailbox message request format to request for CPT_INST_S lmtst. */
1819 struct cpt_inst_lmtst_req {
1820 struct mbox_msghdr hdr;
1821 u64 inst[8];
1822 u64 rsvd;
1823 };
1824
1825 /* Mailbox message format to request for CPT LF reset */
1826 struct cpt_lf_rst_req {
1827 struct mbox_msghdr hdr;
1828 u32 slot;
1829 u32 rsvd;
1830 };
1831
1832 /* Mailbox message format to request for CPT faulted engines */
1833 struct cpt_flt_eng_info_req {
1834 struct mbox_msghdr hdr;
1835 int blkaddr;
1836 bool reset;
1837 u32 rsvd;
1838 };
1839
1840 struct cpt_flt_eng_info_rsp {
1841 struct mbox_msghdr hdr;
1842 u64 flt_eng_map[CPT_10K_AF_INT_VEC_RVU];
1843 u64 rcvrd_eng_map[CPT_10K_AF_INT_VEC_RVU];
1844 u64 rsvd;
1845 };
1846
1847 struct sdp_node_info {
1848 /* Node to which this PF belons to */
1849 u8 node_id;
1850 u8 max_vfs;
1851 u8 num_pf_rings;
1852 u8 pf_srn;
1853 #define SDP_MAX_VFS 128
1854 u8 vf_rings[SDP_MAX_VFS];
1855 };
1856
1857 struct sdp_chan_info_msg {
1858 struct mbox_msghdr hdr;
1859 struct sdp_node_info info;
1860 };
1861
1862 struct sdp_get_chan_info_msg {
1863 struct mbox_msghdr hdr;
1864 u16 chan_base;
1865 u16 num_chan;
1866 };
1867
1868 /* CGX mailbox error codes
1869 * Range 1101 - 1200.
1870 */
1871 enum cgx_af_status {
1872 LMAC_AF_ERR_INVALID_PARAM = -1101,
1873 LMAC_AF_ERR_PF_NOT_MAPPED = -1102,
1874 LMAC_AF_ERR_PERM_DENIED = -1103,
1875 LMAC_AF_ERR_PFC_ENADIS_PERM_DENIED = -1104,
1876 LMAC_AF_ERR_8023PAUSE_ENADIS_PERM_DENIED = -1105,
1877 LMAC_AF_ERR_CMD_TIMEOUT = -1106,
1878 LMAC_AF_ERR_FIRMWARE_DATA_NOT_MAPPED = -1107,
1879 LMAC_AF_ERR_EXACT_MATCH_TBL_ADD_FAILED = -1108,
1880 LMAC_AF_ERR_EXACT_MATCH_TBL_DEL_FAILED = -1109,
1881 LMAC_AF_ERR_EXACT_MATCH_TBL_LOOK_UP_FAILED = -1110,
1882 };
1883
1884 enum mcs_direction {
1885 MCS_RX,
1886 MCS_TX,
1887 };
1888
1889 enum mcs_rsrc_type {
1890 MCS_RSRC_TYPE_FLOWID,
1891 MCS_RSRC_TYPE_SECY,
1892 MCS_RSRC_TYPE_SC,
1893 MCS_RSRC_TYPE_SA,
1894 };
1895
1896 struct mcs_alloc_rsrc_req {
1897 struct mbox_msghdr hdr;
1898 u8 rsrc_type;
1899 u8 rsrc_cnt; /* Resources count */
1900 u8 mcs_id; /* MCS block ID */
1901 u8 dir; /* Macsec ingress or egress side */
1902 u8 all; /* Allocate all resource type one each */
1903 u64 rsvd;
1904 };
1905
1906 struct mcs_alloc_rsrc_rsp {
1907 struct mbox_msghdr hdr;
1908 u8 flow_ids[128]; /* Index of reserved entries */
1909 u8 secy_ids[128];
1910 u8 sc_ids[128];
1911 u8 sa_ids[256];
1912 u8 rsrc_type;
1913 u8 rsrc_cnt; /* No of entries reserved */
1914 u8 mcs_id;
1915 u8 dir;
1916 u8 all;
1917 u8 rsvd[256]; /* reserved fields for future expansion */
1918 };
1919
1920 struct mcs_free_rsrc_req {
1921 struct mbox_msghdr hdr;
1922 u8 rsrc_id; /* Index of the entry to be freed */
1923 u8 rsrc_type;
1924 u8 mcs_id;
1925 u8 dir;
1926 u8 all; /* Free all the cam resources */
1927 u64 rsvd;
1928 };
1929
1930 struct mcs_flowid_entry_write_req {
1931 struct mbox_msghdr hdr;
1932 u64 data[4];
1933 u64 mask[4];
1934 u64 sci; /* CNF10K-B for tx_secy_mem_map */
1935 u8 flow_id;
1936 u8 secy_id; /* secyid for which flowid is mapped */
1937 u8 sc_id; /* Valid if dir = MCS_TX, SC_CAM id mapped to flowid */
1938 u8 ena; /* Enable tcam entry */
1939 u8 ctrl_pkt;
1940 u8 mcs_id;
1941 u8 dir;
1942 u64 rsvd;
1943 };
1944
1945 struct mcs_secy_plcy_write_req {
1946 struct mbox_msghdr hdr;
1947 u64 plcy;
1948 u8 secy_id;
1949 u8 mcs_id;
1950 u8 dir;
1951 u64 rsvd;
1952 };
1953
1954 /* RX SC_CAM mapping */
1955 struct mcs_rx_sc_cam_write_req {
1956 struct mbox_msghdr hdr;
1957 u64 sci; /* SCI */
1958 u64 secy_id; /* secy index mapped to SC */
1959 u8 sc_id; /* SC CAM entry index */
1960 u8 mcs_id;
1961 u64 rsvd;
1962 };
1963
1964 struct mcs_sa_plcy_write_req {
1965 struct mbox_msghdr hdr;
1966 u64 plcy[2][9]; /* Support 2 SA policy */
1967 u8 sa_index[2];
1968 u8 sa_cnt;
1969 u8 mcs_id;
1970 u8 dir;
1971 u64 rsvd;
1972 };
1973
1974 struct mcs_tx_sc_sa_map {
1975 struct mbox_msghdr hdr;
1976 u8 sa_index0;
1977 u8 sa_index1;
1978 u8 rekey_ena;
1979 u8 sa_index0_vld;
1980 u8 sa_index1_vld;
1981 u8 tx_sa_active;
1982 u64 sectag_sci;
1983 u8 sc_id; /* used as index for SA_MEM_MAP */
1984 u8 mcs_id;
1985 u64 rsvd;
1986 };
1987
1988 struct mcs_rx_sc_sa_map {
1989 struct mbox_msghdr hdr;
1990 u8 sa_index;
1991 u8 sa_in_use;
1992 u8 sc_id;
1993 u8 an; /* value range 0-3, sc_id + an used as index SA_MEM_MAP */
1994 u8 mcs_id;
1995 u64 rsvd;
1996 };
1997
1998 struct mcs_flowid_ena_dis_entry {
1999 struct mbox_msghdr hdr;
2000 u8 flow_id;
2001 u8 ena;
2002 u8 mcs_id;
2003 u8 dir;
2004 u64 rsvd;
2005 };
2006
2007 struct mcs_pn_table_write_req {
2008 struct mbox_msghdr hdr;
2009 u64 next_pn;
2010 u8 pn_id;
2011 u8 mcs_id;
2012 u8 dir;
2013 u64 rsvd;
2014 };
2015
2016 struct mcs_hw_info {
2017 struct mbox_msghdr hdr;
2018 u8 num_mcs_blks; /* Number of MCS blocks */
2019 u8 tcam_entries; /* RX/TX Tcam entries per mcs block */
2020 u8 secy_entries; /* RX/TX SECY entries per mcs block */
2021 u8 sc_entries; /* RX/TX SC CAM entries per mcs block */
2022 u16 sa_entries; /* PN table entries = SA entries */
2023 u64 rsvd[16];
2024 };
2025
2026 struct mcs_set_active_lmac {
2027 struct mbox_msghdr hdr;
2028 u32 lmac_bmap; /* bitmap of active lmac per mcs block */
2029 u8 mcs_id;
2030 u16 chan_base; /* MCS channel base */
2031 u64 rsvd;
2032 };
2033
2034 struct mcs_set_lmac_mode {
2035 struct mbox_msghdr hdr;
2036 u8 mode; /* 1:Bypass 0:Operational */
2037 u8 lmac_id;
2038 u8 mcs_id;
2039 u64 rsvd;
2040 };
2041
2042 struct mcs_port_reset_req {
2043 struct mbox_msghdr hdr;
2044 u8 reset;
2045 u8 mcs_id;
2046 u8 port_id;
2047 u64 rsvd;
2048 };
2049
2050 struct mcs_port_cfg_set_req {
2051 struct mbox_msghdr hdr;
2052 u8 cstm_tag_rel_mode_sel;
2053 u8 custom_hdr_enb;
2054 u8 fifo_skid;
2055 u8 port_mode;
2056 u8 port_id;
2057 u8 mcs_id;
2058 u64 rsvd;
2059 };
2060
2061 struct mcs_port_cfg_get_req {
2062 struct mbox_msghdr hdr;
2063 u8 port_id;
2064 u8 mcs_id;
2065 u64 rsvd;
2066 };
2067
2068 struct mcs_port_cfg_get_rsp {
2069 struct mbox_msghdr hdr;
2070 u8 cstm_tag_rel_mode_sel;
2071 u8 custom_hdr_enb;
2072 u8 fifo_skid;
2073 u8 port_mode;
2074 u8 port_id;
2075 u8 mcs_id;
2076 u64 rsvd;
2077 };
2078
2079 struct mcs_custom_tag_cfg_get_req {
2080 struct mbox_msghdr hdr;
2081 u8 mcs_id;
2082 u8 dir;
2083 u64 rsvd;
2084 };
2085
2086 struct mcs_custom_tag_cfg_get_rsp {
2087 struct mbox_msghdr hdr;
2088 u16 cstm_etype[8];
2089 u8 cstm_indx[8];
2090 u8 cstm_etype_en;
2091 u8 mcs_id;
2092 u8 dir;
2093 u64 rsvd;
2094 };
2095
2096 /* MCS mailbox error codes
2097 * Range 1201 - 1300.
2098 */
2099 enum mcs_af_status {
2100 MCS_AF_ERR_INVALID_MCSID = -1201,
2101 MCS_AF_ERR_NOT_MAPPED = -1202,
2102 };
2103
2104 struct mcs_set_pn_threshold {
2105 struct mbox_msghdr hdr;
2106 u64 threshold;
2107 u8 xpn; /* '1' for setting xpn threshold */
2108 u8 mcs_id;
2109 u8 dir;
2110 u64 rsvd;
2111 };
2112
2113 enum mcs_ctrl_pkt_rulew_type {
2114 MCS_CTRL_PKT_RULE_TYPE_ETH,
2115 MCS_CTRL_PKT_RULE_TYPE_DA,
2116 MCS_CTRL_PKT_RULE_TYPE_RANGE,
2117 MCS_CTRL_PKT_RULE_TYPE_COMBO,
2118 MCS_CTRL_PKT_RULE_TYPE_MAC,
2119 };
2120
2121 struct mcs_alloc_ctrl_pkt_rule_req {
2122 struct mbox_msghdr hdr;
2123 u8 rule_type;
2124 u8 mcs_id; /* MCS block ID */
2125 u8 dir; /* Macsec ingress or egress side */
2126 u64 rsvd;
2127 };
2128
2129 struct mcs_alloc_ctrl_pkt_rule_rsp {
2130 struct mbox_msghdr hdr;
2131 u8 rule_idx;
2132 u8 rule_type;
2133 u8 mcs_id;
2134 u8 dir;
2135 u64 rsvd;
2136 };
2137
2138 struct mcs_free_ctrl_pkt_rule_req {
2139 struct mbox_msghdr hdr;
2140 u8 rule_idx;
2141 u8 rule_type;
2142 u8 mcs_id;
2143 u8 dir;
2144 u8 all;
2145 u64 rsvd;
2146 };
2147
2148 struct mcs_ctrl_pkt_rule_write_req {
2149 struct mbox_msghdr hdr;
2150 u64 data0;
2151 u64 data1;
2152 u64 data2;
2153 u8 rule_idx;
2154 u8 rule_type;
2155 u8 mcs_id;
2156 u8 dir;
2157 u64 rsvd;
2158 };
2159
2160 struct mcs_stats_req {
2161 struct mbox_msghdr hdr;
2162 u8 id;
2163 u8 mcs_id;
2164 u8 dir;
2165 u64 rsvd;
2166 };
2167
2168 struct mcs_flowid_stats {
2169 struct mbox_msghdr hdr;
2170 u64 tcam_hit_cnt;
2171 u64 rsvd;
2172 };
2173
2174 struct mcs_secy_stats {
2175 struct mbox_msghdr hdr;
2176 u64 ctl_pkt_bcast_cnt;
2177 u64 ctl_pkt_mcast_cnt;
2178 u64 ctl_pkt_ucast_cnt;
2179 u64 ctl_octet_cnt;
2180 u64 unctl_pkt_bcast_cnt;
2181 u64 unctl_pkt_mcast_cnt;
2182 u64 unctl_pkt_ucast_cnt;
2183 u64 unctl_octet_cnt;
2184 /* Valid only for RX */
2185 u64 octet_decrypted_cnt;
2186 u64 octet_validated_cnt;
2187 u64 pkt_port_disabled_cnt;
2188 u64 pkt_badtag_cnt;
2189 u64 pkt_nosa_cnt;
2190 u64 pkt_nosaerror_cnt;
2191 u64 pkt_tagged_ctl_cnt;
2192 u64 pkt_untaged_cnt;
2193 u64 pkt_ctl_cnt; /* CN10K-B */
2194 u64 pkt_notag_cnt; /* CNF10K-B */
2195 /* Valid only for TX */
2196 u64 octet_encrypted_cnt;
2197 u64 octet_protected_cnt;
2198 u64 pkt_noactivesa_cnt;
2199 u64 pkt_toolong_cnt;
2200 u64 pkt_untagged_cnt;
2201 u64 rsvd[4];
2202 };
2203
2204 struct mcs_port_stats {
2205 struct mbox_msghdr hdr;
2206 u64 tcam_miss_cnt;
2207 u64 parser_err_cnt;
2208 u64 preempt_err_cnt; /* CNF10K-B */
2209 u64 sectag_insert_err_cnt;
2210 u64 rsvd[4];
2211 };
2212
2213 /* Only for CN10K-B */
2214 struct mcs_sa_stats {
2215 struct mbox_msghdr hdr;
2216 /* RX */
2217 u64 pkt_invalid_cnt;
2218 u64 pkt_nosaerror_cnt;
2219 u64 pkt_notvalid_cnt;
2220 u64 pkt_ok_cnt;
2221 u64 pkt_nosa_cnt;
2222 /* TX */
2223 u64 pkt_encrypt_cnt;
2224 u64 pkt_protected_cnt;
2225 u64 rsvd[4];
2226 };
2227
2228 struct mcs_sc_stats {
2229 struct mbox_msghdr hdr;
2230 /* RX */
2231 u64 hit_cnt;
2232 u64 pkt_invalid_cnt;
2233 u64 pkt_late_cnt;
2234 u64 pkt_notvalid_cnt;
2235 u64 pkt_unchecked_cnt;
2236 u64 pkt_delay_cnt; /* CNF10K-B */
2237 u64 pkt_ok_cnt; /* CNF10K-B */
2238 u64 octet_decrypt_cnt; /* CN10K-B */
2239 u64 octet_validate_cnt; /* CN10K-B */
2240 /* TX */
2241 u64 pkt_encrypt_cnt;
2242 u64 pkt_protected_cnt;
2243 u64 octet_encrypt_cnt; /* CN10K-B */
2244 u64 octet_protected_cnt; /* CN10K-B */
2245 u64 rsvd[4];
2246 };
2247
2248 struct mcs_clear_stats {
2249 struct mbox_msghdr hdr;
2250 #define MCS_FLOWID_STATS 0
2251 #define MCS_SECY_STATS 1
2252 #define MCS_SC_STATS 2
2253 #define MCS_SA_STATS 3
2254 #define MCS_PORT_STATS 4
2255 u8 type; /* FLOWID, SECY, SC, SA, PORT */
2256 u8 id; /* type = PORT, If id = FF(invalid) port no is derived from pcifunc */
2257 u8 mcs_id;
2258 u8 dir;
2259 u8 all; /* All resources stats mapped to PF are cleared */
2260 };
2261
2262 struct mcs_intr_cfg {
2263 struct mbox_msghdr hdr;
2264 #define MCS_CPM_RX_SECTAG_V_EQ1_INT BIT_ULL(0)
2265 #define MCS_CPM_RX_SECTAG_E_EQ0_C_EQ1_INT BIT_ULL(1)
2266 #define MCS_CPM_RX_SECTAG_SL_GTE48_INT BIT_ULL(2)
2267 #define MCS_CPM_RX_SECTAG_ES_EQ1_SC_EQ1_INT BIT_ULL(3)
2268 #define MCS_CPM_RX_SECTAG_SC_EQ1_SCB_EQ1_INT BIT_ULL(4)
2269 #define MCS_CPM_RX_PACKET_XPN_EQ0_INT BIT_ULL(5)
2270 #define MCS_CPM_RX_PN_THRESH_REACHED_INT BIT_ULL(6)
2271 #define MCS_CPM_TX_PACKET_XPN_EQ0_INT BIT_ULL(7)
2272 #define MCS_CPM_TX_PN_THRESH_REACHED_INT BIT_ULL(8)
2273 #define MCS_CPM_TX_SA_NOT_VALID_INT BIT_ULL(9)
2274 #define MCS_BBE_RX_DFIFO_OVERFLOW_INT BIT_ULL(10)
2275 #define MCS_BBE_RX_PLFIFO_OVERFLOW_INT BIT_ULL(11)
2276 #define MCS_BBE_TX_DFIFO_OVERFLOW_INT BIT_ULL(12)
2277 #define MCS_BBE_TX_PLFIFO_OVERFLOW_INT BIT_ULL(13)
2278 #define MCS_PAB_RX_CHAN_OVERFLOW_INT BIT_ULL(14)
2279 #define MCS_PAB_TX_CHAN_OVERFLOW_INT BIT_ULL(15)
2280 u64 intr_mask; /* Interrupt enable mask */
2281 u8 mcs_id;
2282 u8 lmac_id;
2283 u64 rsvd;
2284 };
2285
2286 struct mcs_intr_info {
2287 struct mbox_msghdr hdr;
2288 u64 intr_mask;
2289 int sa_id;
2290 u8 mcs_id;
2291 u8 lmac_id;
2292 u64 rsvd;
2293 };
2294
2295 #endif /* MBOX_H */
2296