1 /* SPDX-License-Identifier: GPL-2.0-only */ 2 /* 3 * Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved. 4 * Copyright (c) 2015-2018, The Linux Foundation. All rights reserved. 5 */ 6 7 #ifndef _DPU_HW_MDSS_H 8 #define _DPU_HW_MDSS_H 9 10 #include <linux/kernel.h> 11 #include <linux/err.h> 12 13 #include "msm_drv.h" 14 15 #include "disp/mdp_format.h" 16 17 #define DPU_DBG_NAME "dpu" 18 19 #define DPU_NONE 0 20 21 #ifndef DPU_CSC_MATRIX_COEFF_SIZE 22 #define DPU_CSC_MATRIX_COEFF_SIZE 9 23 #endif 24 25 #ifndef DPU_CSC_CLAMP_SIZE 26 #define DPU_CSC_CLAMP_SIZE 6 27 #endif 28 29 #ifndef DPU_CSC_BIAS_SIZE 30 #define DPU_CSC_BIAS_SIZE 3 31 #endif 32 33 #ifndef DPU_MAX_PLANES 34 #define DPU_MAX_PLANES 4 35 #endif 36 37 #define PIPES_PER_STAGE 2 38 #ifndef DPU_MAX_DE_CURVES 39 #define DPU_MAX_DE_CURVES 3 40 #endif 41 42 #define DPU_BLEND_FG_ALPHA_FG_CONST (0 << 0) 43 #define DPU_BLEND_FG_ALPHA_BG_CONST (1 << 0) 44 #define DPU_BLEND_FG_ALPHA_FG_PIXEL (2 << 0) 45 #define DPU_BLEND_FG_ALPHA_BG_PIXEL (3 << 0) 46 #define DPU_BLEND_FG_INV_ALPHA (1 << 2) 47 #define DPU_BLEND_FG_MOD_ALPHA (1 << 3) 48 #define DPU_BLEND_FG_INV_MOD_ALPHA (1 << 4) 49 #define DPU_BLEND_FG_TRANSP_EN (1 << 5) 50 #define DPU_BLEND_BG_ALPHA_FG_CONST (0 << 8) 51 #define DPU_BLEND_BG_ALPHA_BG_CONST (1 << 8) 52 #define DPU_BLEND_BG_ALPHA_FG_PIXEL (2 << 8) 53 #define DPU_BLEND_BG_ALPHA_BG_PIXEL (3 << 8) 54 #define DPU_BLEND_BG_INV_ALPHA (1 << 10) 55 #define DPU_BLEND_BG_MOD_ALPHA (1 << 11) 56 #define DPU_BLEND_BG_INV_MOD_ALPHA (1 << 12) 57 #define DPU_BLEND_BG_TRANSP_EN (1 << 13) 58 59 enum dpu_vsync_source { 60 DPU_VSYNC_SOURCE_GPIO_0, 61 DPU_VSYNC_SOURCE_GPIO_1, 62 DPU_VSYNC_SOURCE_GPIO_2, 63 DPU_VSYNC_SOURCE_INTF_0 = 3, 64 DPU_VSYNC_SOURCE_INTF_1, 65 DPU_VSYNC_SOURCE_INTF_2, 66 DPU_VSYNC_SOURCE_INTF_3, 67 DPU_VSYNC_SOURCE_WD_TIMER_4 = 11, 68 DPU_VSYNC_SOURCE_WD_TIMER_3, 69 DPU_VSYNC_SOURCE_WD_TIMER_2, 70 DPU_VSYNC_SOURCE_WD_TIMER_1, 71 DPU_VSYNC_SOURCE_WD_TIMER_0, 72 }; 73 74 enum dpu_hw_blk_type { 75 DPU_HW_BLK_TOP = 0, 76 DPU_HW_BLK_SSPP, 77 DPU_HW_BLK_LM, 78 DPU_HW_BLK_CTL, 79 DPU_HW_BLK_PINGPONG, 80 DPU_HW_BLK_DCWB_PINGPONG, 81 DPU_HW_BLK_INTF, 82 DPU_HW_BLK_WB, 83 DPU_HW_BLK_DSPP, 84 DPU_HW_BLK_MERGE_3D, 85 DPU_HW_BLK_DSC, 86 DPU_HW_BLK_CDM, 87 DPU_HW_BLK_CWB, 88 DPU_HW_BLK_MAX, 89 }; 90 91 enum dpu_sspp { 92 SSPP_NONE, 93 SSPP_VIG0, 94 SSPP_VIG1, 95 SSPP_VIG2, 96 SSPP_VIG3, 97 SSPP_RGB0, 98 SSPP_RGB1, 99 SSPP_RGB2, 100 SSPP_RGB3, 101 SSPP_DMA0, 102 SSPP_DMA1, 103 SSPP_DMA2, 104 SSPP_DMA3, 105 SSPP_DMA4, 106 SSPP_DMA5, 107 SSPP_CURSOR0, 108 SSPP_CURSOR1, 109 SSPP_MAX 110 }; 111 112 enum dpu_sspp_type { 113 SSPP_TYPE_VIG, 114 SSPP_TYPE_RGB, 115 SSPP_TYPE_DMA, 116 SSPP_TYPE_CURSOR, 117 SSPP_TYPE_MAX 118 }; 119 120 enum dpu_lm { 121 LM_0 = 1, 122 LM_1, 123 LM_2, 124 LM_3, 125 LM_4, 126 LM_5, 127 LM_6, 128 LM_7, 129 LM_MAX 130 }; 131 132 enum dpu_stage { 133 DPU_STAGE_BASE = 0, 134 DPU_STAGE_0, 135 DPU_STAGE_1, 136 DPU_STAGE_2, 137 DPU_STAGE_3, 138 DPU_STAGE_4, 139 DPU_STAGE_5, 140 DPU_STAGE_6, 141 DPU_STAGE_7, 142 DPU_STAGE_8, 143 DPU_STAGE_9, 144 DPU_STAGE_10, 145 DPU_STAGE_MAX 146 }; 147 enum dpu_dspp { 148 DSPP_0 = 1, 149 DSPP_1, 150 DSPP_2, 151 DSPP_3, 152 DSPP_MAX 153 }; 154 155 enum dpu_ctl { 156 CTL_0 = 1, 157 CTL_1, 158 CTL_2, 159 CTL_3, 160 CTL_4, 161 CTL_5, 162 CTL_MAX 163 }; 164 165 enum dpu_dsc { 166 DSC_NONE = 0, 167 DSC_0, 168 DSC_1, 169 DSC_2, 170 DSC_3, 171 DSC_4, 172 DSC_5, 173 DSC_6, 174 DSC_7, 175 DSC_MAX 176 }; 177 178 enum dpu_cdm { 179 CDM_0 = 1, 180 CDM_MAX 181 }; 182 183 enum dpu_pingpong { 184 PINGPONG_NONE, 185 PINGPONG_0, 186 PINGPONG_1, 187 PINGPONG_2, 188 PINGPONG_3, 189 PINGPONG_4, 190 PINGPONG_5, 191 PINGPONG_6, 192 PINGPONG_7, 193 PINGPONG_CWB_0, 194 PINGPONG_CWB_1, 195 PINGPONG_CWB_2, 196 PINGPONG_CWB_3, 197 PINGPONG_S0, 198 PINGPONG_MAX 199 }; 200 201 enum dpu_merge_3d { 202 MERGE_3D_0 = 1, 203 MERGE_3D_1, 204 MERGE_3D_2, 205 MERGE_3D_3, 206 MERGE_3D_4, 207 MERGE_3D_5, 208 MERGE_3D_MAX 209 }; 210 211 enum dpu_intf { 212 INTF_0 = 1, 213 INTF_1, 214 INTF_2, 215 INTF_3, 216 INTF_4, 217 INTF_5, 218 INTF_6, 219 INTF_7, 220 INTF_8, 221 INTF_MAX 222 }; 223 224 /* 225 * Historically these values correspond to the values written to the 226 * DISP_INTF_SEL register, which had to programmed manually. On newer MDP 227 * generations this register is NOP, but we keep the values for historical 228 * reasons. 229 */ 230 enum dpu_intf_type { 231 INTF_NONE = 0x0, 232 INTF_DSI = 0x1, 233 INTF_HDMI = 0x3, 234 INTF_LCDC = 0x5, 235 /* old eDP found on 8x74 and 8x84 */ 236 INTF_EDP = 0x9, 237 /* both DP and eDP, handled by the new DP driver */ 238 INTF_DP = 0xa, 239 240 /* virtual interfaces */ 241 INTF_WB = 0x100, 242 }; 243 244 enum dpu_intf_mode { 245 INTF_MODE_NONE = 0, 246 INTF_MODE_CMD, 247 INTF_MODE_VIDEO, 248 INTF_MODE_WB_BLOCK, 249 INTF_MODE_WB_LINE, 250 INTF_MODE_MAX 251 }; 252 253 enum dpu_wb { 254 WB_0 = 1, 255 WB_1, 256 WB_2, 257 WB_3, 258 WB_MAX 259 }; 260 261 enum dpu_cwb { 262 CWB_0 = 0x1, 263 CWB_1, 264 CWB_2, 265 CWB_3, 266 CWB_MAX 267 }; 268 269 enum dpu_wd_timer { 270 WD_TIMER_0 = 0x1, 271 WD_TIMER_1, 272 WD_TIMER_2, 273 WD_TIMER_3, 274 WD_TIMER_4, 275 WD_TIMER_5, 276 WD_TIMER_MAX 277 }; 278 279 enum dpu_vbif { 280 VBIF_RT, 281 VBIF_NRT, 282 VBIF_MAX, 283 }; 284 285 /** 286 * enum dpu_3d_blend_mode 287 * Desribes how the 3d data is blended 288 * @BLEND_3D_NONE : 3d blending not enabled 289 * @BLEND_3D_FRAME_INT : Frame interleaving 290 * @BLEND_3D_H_ROW_INT : Horizontal row interleaving 291 * @BLEND_3D_V_ROW_INT : vertical row interleaving 292 * @BLEND_3D_COL_INT : column interleaving 293 * @BLEND_3D_MAX : 294 */ 295 enum dpu_3d_blend_mode { 296 BLEND_3D_NONE = 0, 297 BLEND_3D_FRAME_INT, 298 BLEND_3D_H_ROW_INT, 299 BLEND_3D_V_ROW_INT, 300 BLEND_3D_COL_INT, 301 BLEND_3D_MAX 302 }; 303 304 /** 305 * struct dpu_hw_fmt_layout - format information of the source pixel data 306 * @num_planes: number of planes (including meta data planes) 307 * @width: image width 308 * @height: image height 309 * @total_size: total size in bytes 310 * @plane_addr: address of each plane 311 * @plane_size: length of each plane 312 * @plane_pitch: pitch of each plane 313 */ 314 struct dpu_hw_fmt_layout { 315 uint32_t num_planes; 316 uint32_t width; 317 uint32_t height; 318 uint32_t total_size; 319 uint32_t plane_addr[DPU_MAX_PLANES]; 320 uint32_t plane_size[DPU_MAX_PLANES]; 321 uint32_t plane_pitch[DPU_MAX_PLANES]; 322 }; 323 324 struct dpu_csc_cfg { 325 /* matrix coefficients in S15.16 format */ 326 uint32_t csc_mv[DPU_CSC_MATRIX_COEFF_SIZE]; 327 uint32_t csc_pre_bv[DPU_CSC_BIAS_SIZE]; 328 uint32_t csc_post_bv[DPU_CSC_BIAS_SIZE]; 329 uint32_t csc_pre_lv[DPU_CSC_CLAMP_SIZE]; 330 uint32_t csc_post_lv[DPU_CSC_CLAMP_SIZE]; 331 }; 332 333 /** 334 * struct dpu_mdss_color - mdss color description 335 * color 0 : green 336 * color 1 : blue 337 * color 2 : red 338 * color 3 : alpha 339 */ 340 struct dpu_mdss_color { 341 u32 color_0; 342 u32 color_1; 343 u32 color_2; 344 u32 color_3; 345 }; 346 347 /* 348 * Define bit masks for h/w logging. 349 */ 350 #define DPU_DBG_MASK_NONE (1 << 0) 351 #define DPU_DBG_MASK_INTF (1 << 1) 352 #define DPU_DBG_MASK_LM (1 << 2) 353 #define DPU_DBG_MASK_CTL (1 << 3) 354 #define DPU_DBG_MASK_PINGPONG (1 << 4) 355 #define DPU_DBG_MASK_SSPP (1 << 5) 356 #define DPU_DBG_MASK_WB (1 << 6) 357 #define DPU_DBG_MASK_TOP (1 << 7) 358 #define DPU_DBG_MASK_VBIF (1 << 8) 359 #define DPU_DBG_MASK_ROT (1 << 9) 360 #define DPU_DBG_MASK_DSPP (1 << 10) 361 #define DPU_DBG_MASK_DSC (1 << 11) 362 #define DPU_DBG_MASK_CDM (1 << 12) 363 #define DPU_DBG_MASK_CWB (1 << 13) 364 365 /** 366 * struct dpu_hw_tear_check - Struct contains parameters to configure 367 * tear-effect module. This structure is used to configure tear-check 368 * logic present either in ping-pong or in interface module. 369 * @vsync_count: Ratio of MDP VSYNC clk freq(Hz) to refresh rate divided 370 * by no of lines 371 * @sync_cfg_height: Total vertical lines (display height - 1) 372 * @vsync_init_val: Init value to which the read pointer gets loaded at 373 * vsync edge 374 * @sync_threshold_start: Read pointer threshold start ROI for write operation 375 * @sync_threshold_continue: The minimum number of lines the write pointer 376 * needs to be above the read pointer 377 * @start_pos: The position from which the start_threshold value is added 378 * @rd_ptr_irq: The read pointer line at which interrupt has to be generated 379 * @hw_vsync_mode: Sync with external frame sync input 380 */ 381 struct dpu_hw_tear_check { 382 /* 383 * This is ratio of MDP VSYNC clk freq(Hz) to 384 * refresh rate divided by no of lines 385 */ 386 u32 vsync_count; 387 u32 sync_cfg_height; 388 u32 vsync_init_val; 389 u32 sync_threshold_start; 390 u32 sync_threshold_continue; 391 u32 start_pos; 392 u32 rd_ptr_irq; 393 u8 hw_vsync_mode; 394 }; 395 396 /** 397 * struct dpu_hw_pp_vsync_info - Struct contains parameters to configure 398 * read and write pointers for command mode panels 399 * @rd_ptr_init_val: Value of rd pointer at vsync edge 400 * @rd_ptr_frame_count: Num frames sent since enabling interface 401 * @rd_ptr_line_count: Current line on panel (rd ptr) 402 * @wr_ptr_line_count: Current line within pp fifo (wr ptr) 403 * @intf_frame_count: Frames read from intf 404 */ 405 struct dpu_hw_pp_vsync_info { 406 u32 rd_ptr_init_val; 407 u32 rd_ptr_frame_count; 408 u32 rd_ptr_line_count; 409 u32 wr_ptr_line_count; 410 u32 intf_frame_count; 411 }; 412 413 #endif /* _DPU_HW_MDSS_H */ 414